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1 ? fn9250.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006, 2008. all rights reserved all other trademarks mentioned are the property of their respective owners. isl8700, isl8701, isl8702 adjustable quad sequencer the isl8700, isl8701, isl8702 family of ics provide four delay adjustable sequenced outputs while monitoring an input voltage all with a minimum of external components. high performance dsp, fpga, p and various subsystems require input power sequencing for proper functionality at initial power-up and the isl870x provides this function while monitoring the distributed voltage for over and undervoltage compliance. the isl8700 and isl8701 operate over the +2.5v to +24v nominal voltage range, whereas the isl8702 operates over the +2.5v to +12v nominal voltage range. all three have a user adjustable time from uv and ov voltage compliance to sequencing start via an external capacitor when in auto start mode and adjustable time delay to subsequent enable output signal via external resistors. additionally, the isl8702 provides an input for sequencing on and off operation (seq_en) and for voltage window compliance reporting (fault) over the +2.5v to +12v voltage range. easily daisy chained for more than 4 sequenced signals. altogether, the isl870x provides these adjustable features with a minimum of external bom. see figure 1 for typical implementation. features ? adjustable delay to subsequent enable signal ? adjustable delay to sequence auto start ? adjustable distributed voltage monitoring ? undervoltage and overvoltage adjustable delay to auto start sequence ? i/o options enable (isl8700, isl8702) and enable# (isl8701) seq_en (isl8702) ? voltage compliance fault output ? pb-free (rohs compliant) applications ? power supply sequencing ? system timing function ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8700IBZ* isl 8700ibz -40 to +85 14 ld soic m14.15 isl8701ibz* isl 8701ibz -40 to +85 14 ld soic m14.15 isl8702ibz* isl 8702ibz -40 to +85 14 ld soic m14.15 isl870xeval1 evaluation platform *add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. enable_a uv ov gnd tb tc td time vin fault* seq_en* enable_b enable_c enable_d 2.5v to 24v (2.5v to 12v for isl8702) dc/dc en vo1 vo2 vo3 vo4 figure 1. isl870x implementation * seq_en and fault are not available on isl8700 and isl8701 ru rm rl dc/dc en dc/dc en dc/dc en data sheet march 21, 2008
2 fn9250.2 march 21, 2008 pinouts isl8700 (14 ld soic) top view isl8701 (14 ld soic) top view isl8702 (14 ld soic) top view enable_d enable_c enable_b enable_a 1 2 3 4 5 vin td tc tb 6 78 9 14 time nc nc ov uv gnd 13 12 11 10 enable#_d enable#_c enable#_b enable#_a 1 2 3 4 5 vin td tc tb 6 78 9 14 time nc nc ov uv gnd 13 12 11 10 enable_d enable_c enable_b enable_a 1 2 3 4 5 vin td tc tb 6 78 9 14 time seq_en fault ov uv gnd 13 12 11 10 isl8700, isl8701, isl8702
3 fn9250.2 march 21, 2008 absolute maximum rati ngs thermal information isl8700, isl8701 v in , enable(#), fault . . . . . . . . 27v, to -0.3v isl8702 v in , enable(#), fault . . . . . . . . . . . . . . . . 14v, to -0.3v time, tb, tc, td, uv, ov . . . . . . . . . . . . . . . . . . . . . +6v, to -0.3v seq_en(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v in +0.3v, to -0.3v enable, enable # output current . . . . . . . . . . . . . . . . . . . 10ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage range (nominal). . . . . . . . . . . . . . . . . . 2.5v to 24v i sl8702 supply voltage range (nominal) . . . . . . . . . . 2.5v to 12v thermal resistance (typical, note 1) ja (c/w) 14 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 maximum junction temperature (plastic package) . . . . . . . +125c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications nominal v in = 2.5v to +24v, t a = t j = -40c to +85c, unless otherwise specified. isl8702 v in = 2.5v to +12v parameter symbol test conditions min typ max unit uv and ov inputs uv/ov rising threshold v uvrvth 1.16 1.21 1.28 v uv/ov falling threshold v uvfvth 1.06 1.10 1.18 v uv/ov hysteresis v uvhys v uvrvth - v uvfvth - 104 - mv uv/ov input current i uv -10-na time, enable/enable# outputs time pin charging current i time -2.6-a time pin threshold v time_vth 1.9 2.0 2.25 v time from v in valid to enable_a t vinseqpd seq_en = high, c time = open - 30 - s t vinseqpd_10 seq_en = high, c time = 10nf - 7.7 - ms t vinseqpd500 seq_en = high, c time = 500nf - 435 - ms time from v in invalid to shutdown t shutdown uv or ov to simultaneous shutdown - - 1 s enable output resistance r en i enable = 1ma - 100 - enable output low vol i enable = 1ma - 0.1 - v enable pull-down current i pulld enable = 1v 10 15 - ma delay to subsequent enable turn-on/off t del_120 r tx = 120k 155 195 240 ms t del_3 r tx = 3k 3.5 4.7 6 ms t del_0 r tx = 0 -0.5-ms sequence enable and fault i/o v in valid to fault low t fltl 15 30 50 s v in invalid to fault high t flth -0.5- s fault pull-down current fault = 1v 10 15 - ma seq_en pull-up voltage v seq seq_en open - v in -v seq_en low threshold voltage vil seq_en --0.3v seq_en high threshold voltage vih seq_en 1.2 - - v delay to enable_a deasserted t seq_en_ena seq_en low to enable_a low - 0.2 1 s isl8700, isl8701, isl8702
4 fn9250.2 march 21, 2008 bias ic supply current i vin_2.2v v in = 2.2v - 191 - a i vin_12v v in = 12v - 246 400 a i vin_24v v in = 24v - 286 - a v in power on reset v in_por v in low to high - 2.08 2.5 v pin descriptions pin number pin name function description isl8700 isl8701 isl8702 na 1 na enable#_d active low open drain sequenced output. sequenced on after enable#_c and first output to sequence off for th e isl8701. tracks v in upon bias. 1 na 1 enable_d active high open drain sequenced output. sequenced on after enable_c and first output to sequence off for the isl8700, isl8702. pulls low with v in < 1v. na 2 na enable#_c active low open drain sequenced output. sequenced on after enable#_b and sequenced off after enable#_d for the isl8701. tracks v in upon bias. 2 na 2 enable_c active high open drain sequenced output. sequenced on after enable_b and sequenced off after enable_d for the isl8700, isl8702. pulls low with v in < 1v. na 3 na enable#_b active low open drain sequenced output. sequenced on after enable#_a and sequenced off after enable#_c for the isl8701. tracks v in upon bias. 3 na 3 enable_b active high open drain sequenced output. sequenced on after enable_a and sequenced off after enable_c for the isl8700, isl8702. pulls low with v in < 1v. na 4 na enable#_a active low open drain sequenced output. sequenced on after ctime period and sequenced off after enable#_b for the isl8701. tracks v in upon bias. 4 na 4 enable_a active high open drain sequenced output. sequenced on after ctime period and sequenced off after enable_b for the isl8700, isl8702. pulls low with v in < 1v. 5 5 5 ov the voltage on this pin must be under its 1.22v vth or the four en able outputs will be immediately pulled down. conversely the 4 enable# outputs will be released to be pull ed high via external pull ups. 6 6 6 uv the voltage on this pin must be over its 1.22 v vth or the four enable outputs will be immediately pulled down. conversely the 4 enable# outputs will be released to be pull ed high via external pull ups. 7 7 7 gnd ic ground. na na 8 fault the v in voltage when not within the desired uv to ov window will cause fault to be released to be pulled high to a voltage equal to or less than v in via an external resistor. na na 9 seq_en this pin provides a sequence on signal input with a high input. internally pulled high to v in . na na na seq_en# this pin provides a sequence on signal in put with a low input. internally pulled high to v in . 10 10 10 time this pin provides a 2.6a current output so that an adjustable v in valid to sequencing on and off start delay period is created with a capacitor to ground. 11 11 11 tb a resistor connected from this pin to ground determines the time delay from enable_a being active to enable _b being active on turn-on and also going inactive on turn-off via the seq_in input. 12 12 12 tc a resistor connected from this pin to ground determines the time delay from enable_b being active to enable _c being active on turn-on and also going inactive on turn-off via the seq_in input. 13 13 13 td a resistor connected from this pin to ground determines the time delay from enable_c being active to enable _d being active on turn-on and also going inactive on turn-off via the seq_in input. 14 14 14 v in ic bias pin nominally 2.5v to 24v (2.5v to 12v for isl8702) . this pin requires a 1f decoupling capacitor close to ic pin. electrical specifications nominal v in = 2.5v to +24v, t a = t j = -40c to +85c, unless otherwise specified. isl8702 v in = 2.5v to +12v (continued) parameter symbol test conditions min typ max unit isl8700, isl8701, isl8702
5 fn9250.2 march 21, 2008 functional block diagram functional description the isl870x family of ics provides four delay adjustable sequenced outputs while monitoring a single distributed voltage in the nominal range of 2.5v to 24v for both under and overvoltage. only when the voltage is in compliance will the isl870x initiate the pre-progra mmed a-b-c-d sequence of the enable (isl8700, isl8702) or enable# (isl8701) outputs. although this ic has a bias range of 2.5v to 24v (12v for isl8702) it can monitor any voltage >1.22v via the external divider if a suitable bias voltage is otherwise provided. during initial bias voltage (v in ) application, the isl8700, isl8702 enable outputs are held low once v in = 1v whereas the isl8701 enable# outputs follow the rising v in . once v in > the v bias power-on reset threshold (por) of 2.0v, v in is constantly monitored for compliance via the input voltage resistor divider and the voltages on the uv and ov pins and reported by the fault output. internally, voltage regulators generate 3.5v and 1.17v 5% voltage rails for internal usage once v in > por. once uv > 1.22v and with the seq_en pin high or open, the auto sequence of the four enable (enable#) outputs begins as the time pin charges its external capacitor with a 2.6a current source. the voltage on time is compared to the internal reference (v time_vth ) comparator input and when greater than v time_vth the isl8700, isl8702 enable_a is released to go high via an external pull-up resistor or a pull-up in a dc/dc convertor enable input, for example. conversely, enable#_a output will be pulled low at this time on an isl8701. the time delay generated by the external capacitor is to assure continued voltage compliance within the programmed limits, as during this time any ov or uv condition will halt the start-up process. time capacitor is discharged once v time_vth is met. once enable_a is active (eit her released high on the isl8700, isl8702 or pulled low on the isl8701), a counter is started and using the resistor on tb as a timing component, a delay is generated before enable_b is activated. at this time, the counter is restarted using the resistor on tc as its timing component for a separate timed delay until enable_c is activated. this process is repeated for the resistor on td to complete the a-b-c-d sequencing order of the enable or enable# outputs. at any time during sequencing if an ov or uv event is registered, all four enable outputs will immediately return to their reset state; low for isl8700, isl8702 and high for isl8701. c time is immediately discharged after initial ramp- up thus waiting for subsequent voltage compliance to restart. once sequencing is complete, any subsequently registered uv or ov event will trigger an immediate and simultaneous reset of all enable or enable# outputs. vin voltage 1.17v internal voltage regulator vin (2.2v min to 27v max, 2.5v to 12v for isl8702) 2.0v vin por 3.5v logic vreg programmable delay timer v time_vth 2.6 a vin tb tc td enable_a enable_b enable_c enable_d time gnd fault seq_en uv ov + - - + eo vref 30s reference isl8700, isl8701, isl8702
6 fn9250.2 march 21, 2008 on the isl8702, enabling of on or off sequencing can also be signaled via the seq_en input pin once voltage compliance is met. initially the seq_en pin should be held low and released when sequence start is desired. the on sequence of the enable outputs is as previously described. the off sequence feature is only available on the variants having the seq_en or the seq_en# inputs, this being the isl8702. the sequence is d off, then c off, then b off and finally a off. once seq_en (seq_en#) is signaled low (high) the time cap is charged to 2v once again. once this vth is reached enable_d transitions to its reset state and ctim is discharged. a delay and subsequent sequence off is then determined by td resistor to enable_c. likewise, a del ay to enable_b and then enable_a turn-off is determined by tc and tb resistor values respectively. with the isl8700, isl8701, a quasi down sequencing of the enable outputs can be achieved by loading the enable pins with various value capacitors to ground. when a simultaneous output latch off is invoked, the caps will set the falling ramp of the various enable outputs thus adjusting the time to vth for various dc/dc convertors or other circuitry. regardless of ic variant, the fault signal is always valid at operational voltages and can be used as justification for seq_en release or even controlled with an rc timer for sequence on. programming the undervoltage and overvoltage limits when choosing resistors for the divider, remember to keep the current through the string bounded by power loss at the top end and noise immunity at the bott om end. for most applications, total divider resistance in the 10k to 1000k range is advisable with high precision resistors being used to reduce monitoring error. although for the isl870x two dividers of two resistors each can be employed to separately monitor the ov and uv levels for the v in voltage which will be discussed here using a single three resistor string for monitoring the v in voltage, referencing figure 1. in the three resistor divider string with r u (upper), r m (middle) and r l (lower), the ratios of each in combination to the other two is balanced to achieve the desired uv and ov trip levels. although this ic has a bias range of 2.5v to 24v (12v for isl8702), it can monitor any voltage >1.22v. the ratio of the desired overvolt age trip point to the internal reference is equal to the ratio of the two upper resistors to the lowest (ground connected) resistor. the ratio of the desired undervoltage trip point to the internal reference voltage is equal to the ratio of the uppermost (voltage connected) resistor to the lower two resistors. these assumptions are true for both rising (turn-on) or falling (shutdown) voltages. the following is a practical example worked out. for detailed equations on how to perform this operation for a given supply requirement, please refe r to the next section. 1. determine if turn-on or shutdown limits are preferred and in this example we will determine the resistor values based on the shutdown limits. 2. establish lower and upper trip level: 12v 10% or 13.2v (ov) and 10.8v (uv) 3. establish total resistor string value: 100k , i r = divider current 4. (r m + r l ) x i r = 1.1v @ uv and r l x i r = 1.2v @ ov 5. r m + r l = 1.1v/ir @ uv = r m + r l = 1.1v/(10.8v/100k ) = 10.370k 6. r l = 1.2v/ir @ ov = rl = 1.2v/(13.2v/100k ) = 9.242k 7. r m = 10.370k - 9.242k = 1.128k 8. r u = 100k - 10.370k = 89.630k 9. choose standard value resistors that most closely approximate these ideal values . choosing a different total divider resistance value may yield a more ideal ratio with available resistors values . in our example with the closest standard values of r u = 90.9k , r m = 1.13k and r l = 9.31k , the nominal uv falling and ov rising will be at 10.9v and 13.3v respectively. an advanced tutorial on setting uv and ov levels this section discusses in additional detail the nuances of setting the uv and ov levels, providing more insight into the isl870x than the earlier text. the following equation set can alternatively be used to work out ideal values for a 3 resistor divider string of r u , r m and r l . these equations assume that v ref is the center point between v uvrvth and v uvfvth (i.e. (v uvrvth + v uvfvth )/2 = 1.17v), i load is the load current in the resistor string (i.e. v in /(r u + r m + r l )), v in is the nominal input voltage and v tol is the acceptable voltage tolerance, such that the uv and ov thresholds are centered at v in v tol . the actual acceptable voltage window will also be affected by the hysteresis at the uv and ov pins. this hysteresis is amplified by the resistor string such that the h ysteresis at the top of the string is calculated in equation 1: this means that the v in v tol thresholds will exhibit hysteresis resulting in thresholds of v in + v tol v hys /2 and v in - v tol v hys /2. there is a window between the v in rising uv threshold and the v in falling ov threshold where the input level is guaranteed not to be detected as a fault. this window exists between the limits v in (v tol - v hys /2). there is an extension of this window in each direction up to v in (v tol +v hys /2), where the voltage may or may not be vhys v uvhys = v out v ref ? (eq. 1) isl8700, isl8701, isl8702
7 fn9250.2 march 21, 2008 detected as a fault, depending on the direction from which it is approached. these two equations may be used to determine the required value of vtol for a given system. for example, if v in is 12v, vhys = (0.1 x 12)/1.17 = 1.03v. if v in must remain within 12v 1.5v, v tol = 1.5 - 1.03/2 = 0.99v. this will give a window of 12 0.48v where the system is guaranteed not to be in fault and a limit of 12 1.5v beyond which the system is guaranteed to be in fault. it is wise to check both these voltages for if the latter is made too tight, the former will cease to exist. this point comes when v tol < v hys /2 and results from the fact that the acceptable window for the ov pin no longer aligns with the acceptable window for the uv pin. in this case, the application will have to be changed such that uv and ov are provided separate resistor strings. in this case the uv and ov thresholds can be individually controlled by adjusting the relevant divider. the previous example will give voltage thresholds: with v in rising with v in falling so with a single three resistor string, the resistor values can be calculated using equation 4: for the above example with vtol = 0.99v, assuming a 100a iload at v in = 12v: r l = 10.7k r m = 1.9k r u = 107.3k programming the e nable output delays the delay timing between the four sequenced enable outputs are programmed with four external passive components. the delay from a valid v in (isl8700 and isl8701) to enable_a and seq_en being valid (isl8702) to enable_a is determined by the value of the capacitor on the time pin to gnd. the external time pin capacitor is charged with a 2.6a current source. once the voltage on time is charged up to the internal reference voltage, (v time_vth ) the enable_a output is released out of its reset state. the capacitor value for a desired delay (10%) to enable_a once v in and seq_en where applicable has been satisfied is determined by using equation 5: once enable_a reaches v time_vth , the time pin is pulled low in preparation for a sequenced off signal via seq_en. at this time, the sequencing of the subsequent outputs is started. enable_b is released out of reset after a programmable time, then enable_c, then enable _d, all with their own programmed delay times. the subsequent delay times are programmed with a single external resistor for each enable output providing maximum flexibility to the designer through th e choice of the resistor value connected from tb, tc and td pins to gnd. the resistor values determine the charge and discharge rate of an internal capacitor comprising an rc time constant for an oscillator whose output is fed into a counter generating the timing delay to enable output sequencing. the r tx value for a given delay time is defined as equation 6: u vr v in v tol v hys 2 ? + ? 11.5vand == (eq. 2) o vr v in v tol v hys 2 ? ++ 13.5v == o vf v in v tol v hys 2 ? ? + 12.5vand == (eq. 3) u vf v in v tol v hys 2 ? ? ? 10.5v == r i v ref i load ? () 1v tol ? v in ? () = (eq. 4) r m 2v ref v tol () v in i load () ? = r u 1i load ? () v in v ref ? () 1v tol + v in ? () = c time t vinseqpd 770k ? = (eq. 5) r tx t del 1667nf -------------------- - = (eq. 6) isl8700, isl8701, isl8702
8 fn9250.2 march 21, 2008 typical performance curves figure 4. uv/ov rising threshold figure 5. v in current figure 2. isl8702 operational diagram enable outputs abcd fault a b c d seq_en time figure 3. isl8702 fault operational diagram undervoltage overvoltage monitored voltage fault output t flth limit limit ramping up and down t flth t fltl t fltl 9 fn9250.2 march 21, 2008 applications usage using the isl870xeval1 platform the isl870xeval1 platform is the primary evaluation board for this family of sequencers. see figure 15 for a photograph and schematic.the evaluation board is shipped with an isl8702 mounted in the left pos ition and with the other device variants loosely packed. in the following discussion, test points names are bold on initial occurrence for identification. the v in test point is the chip bias and can be biased from 2.5v to 24v. the vhi test point is for the enable and fault pull-up voltage which are limited to a maximum of 24v independent of v in . the uv/ov resistor divider is set so that a nominal 12v on the vmonitor test point is compliant and with a rising ov set at 13.2v and a falling uv set at 10.7v. these three test points (v in ,vhi and vmonitor) are brought out separately for maximum flexibility in evaluation. vmonitor ramping up and down through the uv and ov levels will result in the fault output signaling the out of bound conditions by being released to pull high to the vhi voltage as shown in figures 6 and 7. once the voltage monitoring fault is resolved and where applicable, the seq_en (#) is satisfied, sequencing of the enable_x(#) outputs begins. when sequence enabled the enable_a , enable_b , enable_c and lastly enable_d are asserted in that order and when seq_en is disabled, the order is reversed. see figures 8 and 9 demonstrating the sequenced enabling and disabling of the enable outputs. the timing between enable outputs is set by the resistor values on the tb, tc, td pins as shown. figure 10 illustrates the timing from either seq_en and/or vmonitor being valid to enable_a being asserted with a 10nf time capacitor. figure 11 shows that enable_x outputs are pulled low even before v in = 1v. this is critical to ensure that a false enable is not signaled. figure 12 shows the time from seq_en transition with the voltage ramping across the time capacitor to time vth being met. this results in the immediate pull down of the time pin and simultaneous enable_a enabling. figure 13 illustrates the immunity of the uv and ov inputs to transients. figure 6. vmonitor rising to fault figure 7. vmonitor falling to fault fault output vmon rising vmon > uv vmon > ov level level vmon falling vmon > ov vmon > uv level level fault output isl8700, isl8701, isl8702
10 fn9250.2 march 21, 2008 figure 8. enable_x to enable_x enabling figure 9. enable_x to enable_x disabling figure 10. v in /seq_en valid to enable_a figure 11. enable as v in rises figure 12. seq_en to enable_a figure 13. ov and uv transient immunity r td = 120k delay = 196ms r tc = 51k r tb = 3k delay = 5ms delay = 86ms r td = 120k delay = 196ms r tb = 3k delay = 5ms r tc = 51k delay = 86ms c time = 10nf delay = 8.5ms 1v/div 10ms/div v in rising enable outputs tracks v in to < 0.8v enable_a time seq_en 0.5v/div 8s/div fault = low vmonitor ov vmonitor uv isl8700, isl8701, isl8702
11 fn9250.2 march 21, 2008 application concerns and recommendations when designing the isl8700 family of products into applications with low supply voltages such as 3.3v, additional filtering to help reduce system noise on the voltage supply input is necessary to ensure proper voltage sequencing operation. it is important that the user-programmed uv threshold is set sufficiently above (i.e. >200mv) the isl8700 ic?s internal por level, v in_por , over the entire operating tem perature range. best design practices include proper decoupling on the supply input (i.e. at least 1f) as well as an rc filter that can adequately suppress noise on the supply in the user?s application, whereby the resistor should be kept < 13 to reduce voltage loss to the already low biased vin pin. coupling from the enable_x pins to the sensitive uv and ov pins can cause false ov/uv events to be detected. this is most relevant for isl8700, isl8702 parts due to the enable_a and ov pins being adjacent. this coupling can be reduced by adding a ground trace between uv and the enable/fault signals, as shown in figure 14. the pcb traces on ov and uv should be kept as small as practical and the enable_x and fault traces should ideally not be routed under/over the ov/uv traces on different pcb layers unless there is a ground or power plane in between. other methods that can be used to el iminate this issue are by reducing the value of the resist ors in the network connected to uv and ov (r 2 , r 3 , r 5 in figure 15) or by adding small decoupling capacitors to ov and uv (c 2 and c 7 in figure 15). both these methods act to reduce the ac impedance at the nodes, although the latter method acts to filter the signals, which will also cause an increase in the time that a uv/ov fault takes to be detected . when the isl870x is implemented on a hot swappable card that is plugged into an always powered passive back plane, an rc filter is required on the v in pin to prevent a high dv/dt transient. with the already existing 1f decoupling capacitor, the addition of a small series r (<13 ) to provide a time constant >50s is all that is necessary. only the isl8702 has a v in limitation of 14v maximum. figure 14. layout detail of gnd between pins 4 and 5 pin 4 pin 5 gnd gnd isl8700, isl8701, isl8702
12 fn9250.2 march 21, 2008 . figure 15. isl870xeval1 photograph and schematic of left channel timing components resistors uv/ov set resistors pull-up table 1. isl870xeval1 left channel component listing component designator component functi on component description u1 isl8702 , quad under/overvoltage sequencer intersil, isl8702 , quad undervoltage, overvoltage sequencer r3 uv resistor for divider string 1.1k 1%, 0603 r2 vmonitor resistor for divider string 88.7k 1%, 0603 r5 ov resistor for divider string 9.1k 1%, 0603 c1 c time sets delay from sequence start to first enable 0.01f, 0603 r1 r td sets delay from third to fourth enable 120k 1%, 0603 r9 r tb sets delay from first to second enable 3.01k 1%, 0603 r7 r tc sets delay from second to third enable 51k 1%, 0603 r4, r6, r8, r10, r11 enable_x(#) and fault pull-up resistors 4k 10%, 0402 c3 decoupling capacitor 1f, 0603 isl8700, isl8701, isl8702
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9250.2 march 21, 2008 isl8700, isl8701, isl8702 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93

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