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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD10465 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 dual channel, 14-bit, 65 msps a/d converter with analog input signal conditioning features dual, 65 msps minimum sample rate channel-to-channel matching, 0.5% gain error channel-to-channel isolation, >90 db dc-coupled signal conditioning included selectable bipolar input voltage range ( 0.5 v, 1.0 v, 2.0 v) gain flatness up to 25 mhz: < 0.2 db 80 db spurious-free dynamic range twos complement output format 3.3 v or 5 v cmos-compatible output levels 1.75 w per channel industrial and military grade applications phased array receivers communications receivers flir processing secure communications gps antijamming receivers multichannel, multimode receivers functional block diagram vref drout output buffering timing a in a3 a in a2 a in a1 ref a 3 11 14 vref drout a in b2 a in b1 14 a in b3 enc enc d11a d12a d13a (msb) output buffering d0b (lsb) d1b d3b d2b d4b d5b d6b d7b d8b timing d9b 9 5 enc enc drbout d10b d11b d12b d13b ref b d0a (lsb) d1a d2a d3a d4a d5a d6a d7a d8a d9a d10a AD10465 draout product description the AD10465 is a full channel adc solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. the module includes two wide dynamic range ad6644 adcs. each ad6644 has a dc- coupled amplifier front end including an ad8037 low distortion, high bandwidth amplifier, providing a high input impedance and gain, and driving the ad8138 single-to-differential ampli- fier. the ad6644s have on-chip track-and-hold circuitry and utilize an innovative multipass architecture to achieve 14-bit, 65 msps performance. the AD10465 uses innovative high- density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance, while still maintaining excellent isolation and providing for significant board area savings. the AD10465 operates with 5.0 v for the analog signal condi- tioning with a separate 5.0 v supply for the analog-to-digital conversion and 3.3 v digital supply for the output stage. each channel is completely independent, allowing operation with independent encode and analog inputs. the AD10465 also offers the user a choice of analog input signal ranges to fur- ther minimize additional external signal conditioning, while still remaining general-purpose. the AD10465 is packaged in a 68-lead ceramic gull wing package, footprint-compatible with the earlier generation ad10242 (12-bit, 40 msps) and ad10265 (12-bit, 65 msps). manufac- turing is done on analog devices, inc. mil-38534 qualified manufacturers line (qml) and components are available up to class-h (?0 c to +85 c). the ad6644 internal components are manufactured on analog d evices, inc. high-speed comple- mentary bipolar process (xfcb). product highlights 1. guaranteed sample rate of 65 msps. 2. input amplitude options, user configurable. 3. input signal conditioning included; both channels matched for gain. 4. fully tested/characterized performance. 5. footprint compatible family; 68-lead lcc.
rev. 0 C2C AD10465?pecifications test mil AD10465az/bz/qml-h parameter temp level subgroup min typ max unit resolution 14 bits dc accuracy no missing codes full vi 1, 2, 3 guaranteed offset error 25 c i 1 ?.2 0.02 +2.2 % fs full vi 2, 3 ?.2 1.0 +2.2 % fs offset error channel match full v 1 1.0 +1 % gain error 1 25 c i 1 3 ?.0 +1 % fs full vi 2, 3 5 2.0 +5 % fs gain error channel match 25 c i 1 ?.5 0.5 +1.5 % max i 2 ? 1.0 +3 % min i 3 ? +5 % analog input (a in ) input voltage range a in 1 full v 0.5 v a in 2 full v 1.0 v a in 3 full v 2v input resistance a in 1 full iv 12 99 100 101 ? a in 2 full iv 12 198 200 202 ? a in 3 full iv 12 396 400 404 ? input capacitance 2 25 c iv 12 0 4.0 7.0 pf analog input bandwidth 3 full v 100 mhz encode input (enc, enc ) 4 differential input voltage 17 full iv 0.4 v p-p differential input resistance 25 cv 10 k ? differential input capacitance 25 c v 2.5 pf switching performance maximum conversion rate 5 full vi 4, 5, 6 65 msps minimum conversion rate 5 full v 12 20 msps aperture delay (t a )25 c v 1.5 ns aperture delay matching 25 c iv 12 250 500 ps aperture uncertainty (jitter) 25 c v 0.3 ps rms encode pulsewidth high 25 c iv 12 6.2 7.7 9.2 ns encode pulsewidth low 25 c iv 12 6.2 7.7 9.2 ns output delay (t od ) full v 6.8 ns encode, rising to data ready, rising delay (t e_dr ) full 11.5 ns snr 6 analog input @ 4.98 mhz 25 c v 70 dbfs analog input @ 9.9 mhz 25 c i 4 69 70 dbfs full ii 5, 6 68 70 dbfs analog input @ 19.5 mhz 25 c i 4 68 70 dbfs full ii 5, 6 67 70 dbfs analog input @ 32.1 mhz 25 c i 4 67 69 dbfs full ii 5, 6 67 69 dbfs sinad 7 analog input @ 4.98 mhz 25 cv 70 db analog input @ 9.9 mhz 25 c i 4 67.5 69 db full ii 5, 6 67.5 69 db analog input @ 19.5 mhz 25 ci 4 65 68 db full ii 5, 6 65 68 db analog input @ 32.1 mhz 25 ci 4 60 63 db full ii 5, 6 58 61 db (av cc = +5 v; av ee = ? v; dv cc = 3.3 v applies to each adc unless otherwise noted.)
rev. 0 C3C AD10465 test mil AD10465az/bz/qml-h parameter temp level subgroup min typ max unit spurious-free dynamic range 8 analog input @ 4.98 mhz 25 c v 85 dbfs analog input @ 9.9 mhz 25 c i 4 73 82 dbfs full ii 5, 6 70 82 dbfs analog input @ 19.5 mhz 25 c i 4 72 78 dbfs full ii 5, 6 70 78 dbfs analog input @ 32.1 mhz 25 c i 4 62 68 dbfs full ii 5, 6 60 66 dbfs two-tone imd rejection 9 f in = 10 mhz and 11 mhz 25 c i 4 78 87 dbfs f 1 and f 2 are ? db ii 5, 6 78 f in = 31 mhz and 32 mhz 25 c i 4 68 70 dbfs f 1 and f 2 are ? db full ii 5, 6 60 channel-to-channel isolation 10 25 civ 12 90 db transient response 25 c v 15.3 ns overvoltage recovery time 11 vin = 2.0 f s full iv 12 40 100 ns vin = 4.0 f s full iv 12 150 200 ns digital outputs 12 logic compatibility cmos dv cc = 3.3 v logic ??voltage full i 1, 2, 3 2.5 dv cc ?0.2 v logic ??voltage full i 1, 2, 3 0.2 0.5 v dv cc = 5 v logic ??voltage full v dv cc ?0.3 v logic ??voltage full v 0.35 v output coding two? complement power supply av cc supply voltage 13 full vi 4.85 5.0 5.25 v i (av cc ) current full i 270 308 ma av ee supply voltage 13 full vi ?.25 ?.0 ?.75 v i (av ee ) current full v 38 49 ma dv cc supply voltage 13 full vi 3.135 3.3 3.465 v i (dv cc ) current full v 30 46 ma i cc (total) supply current per channel full i 1, 2, 3 338 403 ma power dissipation (total) full i 1, 2, 3 3.5 3.9 w power supply rejection ratio (psrr) full v 0.02 % fsr/% v s passband ripple to 10 mhz v 0.1 db passband ripple to 25 mhz v 0.2 db notes 1 gain tests are performed on a in 1 input voltage range. 2 input capacitance spec. combines ad8037 die capacitance and ceramic package capacitance. 3 full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is reduced by 3 db. 4 all ac specifications tested by driving encode and encode differentially. 5 minimum and maximum conversion rates allow for variation in encode duty cycle of 50% 5%. 6 analog input signal power at ? dbfs; signal-to-noise ratio (snr) is the ratio of signal level to total noise (first five harmo nics removed). encode = 65 msps. snr is reported in dbfs, related back to converter full power. 7 analog input signal power at ? dbfs; signal-to-noise and distortion (sinad) is the ratio of signal level to total noise + harm onics. encode = 65 msps. 8 analog input signal power swept from ? dbfs to ?0 dbfs; sfdr is ratio of converter full scale to worst spur. 9 both input tones at ? dbfs; two-tone intermodulation distortion (imd) rejection is the ratio of either tone to the worst third order intermod product. 10 channel-to-channel isolation tested with a channel grounded and a full-scale signal applied to b channel. 11 input driven to 2 and 4 a in 1 range for > four clock cycles. output recovers inband in specified time with encode = 65 msps. 12 digital output logic levels: dv cc = 3.3 v, c load = 10 pf. capacitive loads > 10 pf will degrade performance. 13 supply voltage recommended operating range. av cc may be varied from 4.85 v to 5.25 v. however, rated ac (harmonics) performance is valid only over the range av cc = 5.0 v to 5.25 v. all specifications guaranteed within 100 ms of initial power-up regardless of sequencing. specifications subject to change without notice.
rev. 0 AD10465 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD10465 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 parameter min max units electrical v cc voltage 0 7 v v ee voltage ? 0 v analog input voltage v ee v cc v analog input current ?0 +10 ma digital input voltage (encode) 0 v cc v encode, encode differential voltage 4 v digital output current ?0 +10 ma environmental 2 operating temperature (case) ?0 +85 c maximum junction temperature 174 c lead temperature (soldering, 10 sec) 300 c storage temperature range (ambient) ?5 +150 c notes 1 absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedance for ?s?package: jc = 2.2 c/w; ja = 24.3 c/w. test level i. 100% production tested. ii. 100% production tested at 25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at temperature at 25 c, sample tested at temperature extremes. ordering guide model temperature range package description AD10465az ?5 c to +85 c (case) 68-lead ceramic leaded chip carrier AD10465bz ?0 c to +85 c (case) 68-lead ceramic leaded chip carrier 5962-9961601hxa ?0 c to +85 c (case) 68-lead ceramic leaded chip carrier AD10465/pcb 25 c evaluation board with AD10465az
rev. 0 AD10465 C5C pin function descriptions pin no. name function 1 shield internal ground shield between channels. 2, 4, 5, 9?1 agnda a channel analog ground. a and b grounds should be connected as close to the device as possible. 3 ref_a a channel internal voltage reference. 6a in a1 analog input for a side adc (nominally 0.5 v). 7a in a2 analog input for a side adc (nominally 1.0 v). 8a in a3 analog input for a side adc (nominally 2.0 v). 12 draout data ready a output. 13 av ee analog negative supply voltage (nominally ?.0 v or ?.2 v). 14 av cc analog positive supply voltage (nominally 5.0 v). 26, 27 dgnda a channel digital ground. 15?5, 31?3 d0a?13a digital outputs for adc a. d0 (lsb). 28 encodea encode is complement of encode. 29 encodea data conversion initiated on rising edge of encode input. 30 dv cc digital positive supply voltage (nominally 5.0 v/3.3 v). 43, 44 dgndb b channel digital ground. 34?2, 45?9 d0b-d13b digital outputs for adc b. d0 (lsb). 53?4, 57?1, 65, 68 agndb b channel analog ground. a and b grounds should be connected as close to the device as possible. 50 dv cc digital positive supply voltage (nominally 5.0 v/3.3 v). 51 encodeb data conversion initiated on rising edge of encode input. 52 encodeb encode is complement of encode. 55 drbout data ready b output. 56 ref_b b channel internal voltage reference. 62 a in b1 analog input for b side adc (nominally 0.5 v). 63 a in b2 analog input for b side adc (nominally 1.0 v). 64 a in b3 analog input for b side adc (nominally 2.0 v). 66 av cc analog positive supply voltage (nominally ?.0 v). 67 av ee analog negative supply voltage (nominally ?.0 v or ?.2 v). . pin configuration 68-lead ceramic leaded chip carrier 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 961 8765 68676665646362 4321 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pin 1 identifier top view (not to scale) AD10465 agndb agndb agndb agndb ref b drbout agndb d12a dgnda encodea encodea dv cc d11a d13a(msba) agnda agnda draout av ee d0a(lsba) d1a d2a d3a d4a d5a agndb encodeb encodeb dv cc d0b(lsbb) d1b d2b d3b agnda agnda a in a3 agnda agnda ref a av ee a in b3 av cc agndb agndb a in a1 a in a2 agndb shield a in b1 a in b2 d4b d5b d6b d7b d8b dgndb d6a d7a d8a d9a d10a dgnda d13b(msbb) d12b d11b d10b d9b dgndb av cc
rev. 0 frequency ?mhz ?30 0 2.5 db encode = 65msps a in = 5mhz (?dbfs) snr = 71.02 sfdr = 92.11dbc 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 6 2 3 4 5 tpc 1. single tone @ 5 mhz frequency mhz 130 0 2.5 db encode = 65msps a in = 20mhz ( 1dbfs) snr = 70.71 sfdr = 79.73dbc 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 120 110 100 90 80 70 60 50 40 30 20 10 0 6 2 3 4 5 tpc 2. single tone @ 20 mhz frequency mhz 130 0 2.5 db encode = 65msps a in = 32mhz ( 1dbfs) snr = 70.22 sfdr = 66.40dbc 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 120 110 100 90 80 70 60 50 40 30 20 10 0 6 2 3 4 5 tpc 3. single tone @ 32 mhz AD10465 typical performance characteristics C6C frequency mhz 130 0 2.5 db encode = 65msps a in = 10mhz ( 1dbfs) snr = 70.79 sfdr = 86.06dbc 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 120 110 100 90 80 70 60 50 40 30 20 10 0 6 2 3 4 5 tpc 4. single tone @ 10 mhz frequency mhz 130 0 2.5 db encode = 65msps a in = 25mhz ( 1dbfs) snr = 70.36 sfdr = 74.58dbc 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 120 110 100 90 80 70 60 50 40 30 20 10 0 6 2 3 4 5 tpc 5. single tone @ 25 mhz input frequency mhz 4.989 dbc 0 10 20 30 40 50 60 70 80 90 100 sfdr sinad 9.989 19.000 32.000 tpc 6. sfdr and sinad vs. frequency
rev. 0 AD10465 C7C frequency mhz 130 0 2.5 db encode = 65msps a in = 9mhz and 10mhz ( 7dbfs) sfdr = 82.83dbc 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 120 110 100 90 80 70 60 50 40 30 20 10 0 f2 f1 f1+ f2 2f1 f2 2f2 f1 2f1+ f2 2f2+ f1 tpc 7. two tone @ 9/10 mhz 1.0 0 2048 lsb encode = 65msps dnl max = +0.549 codes dnl min = 0.549 codes 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 4096 6144 8192 10240 12288 14336 16384 tpc 8. differential nonlinearity frequency mhz 1.0 4.2 dbfs 10 9 8 7 6 5 4 3 2 1 0 7.4 10.6 13.8 17.0 20.2 23.4 26.6 29.8 33.0 tpc 9. gain flatness frequency mhz 130 0 2.5 db encode = 65msps a in = 17mhz and 18mhz ( 7dbfs) sfdr = 77.68dbc 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 120 110 100 90 80 70 60 50 40 30 20 10 0 f2 f1 f1+ f2 2f1+ f2 2f2+ f1 2f1 f2 2f2 f1 tpc 10. two tone @ 17/18 mhz 3.0 0 2048 lsb encode = 65msps inl max = +1.173 codes inl min = 1.332 codes 2.0 0 2.0 3.0 4096 6144 8192 10240 12288 14336 16384 1.0 1.0 tpc 11. integral nonlinearity a in mhz 5 snrfs 67.5 68.0 68.5 69.0 69.5 70.0 70.5 71.0 71.5 72.0 +25 c 10 19 32 40 c +85 c '()*#+! ! 0
1
rev. 0 AD10465 C8C definition of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between a differential crossing of encode and encode and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential nonlinearity the deviation of any code from an ideal 1 lsb step. encode pul sewidth /duty cycle pulsewidth high is the minimum amount of time that the encode pulse should be left in logic ??state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. at a given clock rate, these specs define an acceptable encode duty cycle. harmonic distortion the ratio of the rms signal amplitude to the rms value of the worst harmonic component. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a ?est straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed, above which converter performance may degrade. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. overvoltage recovery time the amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. may be reported in db (i.e., relative to signal level) or in dbfs (always related back to converter full scale). signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. may be reported in db (i.e., relative to signal level) or in dbfs (always related back to converter full scale). spurious-free dynamic range the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. transient response the time required for the converter to achieve 0.03% accu- racy when a one-half full-scale step function is applied to the analog input. two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbfs. t a a in enc, enc d[13:0] dry n n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4 n 3n 2n 1n t encl t ench t enc t e, dr t od figure 1. timing diagram
rev. 0 AD10465 C9C current mirror dr out dv cc v ref current mirror dv cc figure 4. digital output stage current mirror d0 d13 dv cc v ref current mirror dv cc 100 figure 5. digital output stage av in 3 av in 2 av in 1 200 100 100 to ad8037 figure 2. analog input stage loads loads 10k 10k encode av cc av cc 10k 10k encode av cc av cc figure 3. encode inputs theory of operation the AD10465 is a high dynamic range 14-bit, 65 mhz pipeline delay (three pipelines) analog-to-digital converter. the custom analog input section maintains the same input ranges (1 v p-p, 2 v p-p, and 4 v p-p) and input impedance (100 ? , 200 ? , and 400 ? ) as the ad10242. the AD10465 employs four monolithic adi components per channel (ad8037, ad8138, ad8031, and ad6644), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 14-bit analog-to-digital converter. the input signal is passed through a precision laser-trimmed resistor divider allowing the user to externally select operation with a full-scale signal of 0.5 v, 1.0 v or 2.0 v by choosing the proper input terminal for the application. the AD10465 analog input includes an ad8037 amplifier featuring an innovative architecture that maximizes the dynamic range capability on the amplifiers inputs and outputs. the ad8037 amplifier provides a high input impedance and gain for driving the ad8138 in a single-ended to differential amplifier configu- ration. the ad8138 has a ? db bandwidth at 300 mhz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. the ad8138 differential outputs help balance the differential inputs to the ad6644, maximizing the performance of the adc. the ad8031 provides the buffer for the internal reference of the ad6644. the internal reference voltage of the ad6644 is designed to track the offsets and drifts of the adc and is used to ensure matching over an extended temperature range of operation. the reference voltage is connected to the output common mode input on the ad8138. the ad6644 reference voltage sets the output common-mode on the ad8138 at 2.4 v, which is the midsupply level for the ad6644. the ad6644 has complementary analog input pins, ain and ain . each analog input is centered at 2.4 v and should swing 0.55 v around this reference. since ain and ain are 180 degrees out of phase, the differential analog input signal is 2.2 v peak-to-peak. both analog inputs are buffered prior to the first track-and-hold, th1. the high state of the encode pulse places th1 in hold mode. the held value of th1 is applied to the input of a 5-bit coarse adc1. the digital output of adc1 drives 14 bits of precision which is achieved through laser trimming. the output of dac1 is subtracted from the delayed analog signal at the input of th3 to generate a first residue signal. th2 provides an analog pipeline delay to compensate for the digital delay of adc1. the first residue signal is applied to a second conversion stage consisting of a 5-bit adc2, 5-bit dac2, and pipeline th4. the second dac requires 10 bits of precision which is met by the process with no trim. the input to th5 is a second residue signal generated by subtracting the quantized output of dac2 from the first residue signal held by th4. th5 drives a final 6-bit adc3. the digital outputs from adc1, adc2, and adc3 are added together and corrected in the digital error correction logic to generate the final output data. the result is a 14-bit parallel digital cmos-compatible word, coded as two? complement. using the flexible input the AD10465 has been designed with the user? ease of opera- tion in mind. multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. while the standard inputs are 0.5 v, 1.0 v and 2.0 v, the user can select the input impedance of the
rev. 0 AD10465 C10C AD10465 on any input by using the other inputs as alternate locations for gnd or an external resistor. the following chart summarizes the impedance options available at each input location: a in 1 = 100 ? when a in 2 and a in 3 are open. a in 1 = 75 ? when a in 3 is shorted to gnd. a in 1 = 50 ? when a in 2 is shorted to gnd. a in 2 = 200 ? when a in 3 is open. a in 2 = 100 ? when a in 3 is shorted to gnd. a in 2 = 75 ? when a in 2 to a in 3 has an external resistor of 300 ? , with a in 3 shorted to gnd. a in 2 = 50 ? when a in 2 to a in 3 has an external resistor of 100 ? , with a in 3 shorted to gnd. a in 3 = 400 ? . a in 3 = 100 ? when a in 3 has an external resistor of 133 ? to gnd. a in 3 = 75 ? when a in 3 has an external resistor of 92 ? to gnd. a in 3 = 50 ? when a in 3 has an external resistor of 57 ? to gnd. applying the AD10465 encoding the AD10465 the AD10465 encode signal must be a high quality, extremely low phase noise source, to prevent degradation of performance. maintaining 14-bit accuracy places a premium on encode clock phase noise. snr performance can easily degrade by 3 db to 4 db with 32 mhz input signals when using a high-jitter clock source. see analog devices?application note an-501, ?per- ture uncertainty and adc system performance?for complete details. for optimum performance, the AD10465 must be clocked differentially. the encode signal is usually ac-coupled into the encode and encode pins via a transformer or capacitors. these pins are biased internally and require no additional bias. shown below is one preferred method for clocking the AD10465. the clock source (low jitter) is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the AD10465 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD10465, and limits the noise presented to the encode inputs. a crystal clock oscillator can also be used to drive the rf transformer if an appropriate limiting resistor (typically 100 ? ) is placed in the series with the primary. t1-4t 100 0.1nf encode encode AD10465 hsms2812 diodes clock source figure 6. crystal clock oscillator, differential encode if a low jitter ecl/pecl clock is available, another option is to ac-couple a differential ecl/pecl signal to the encode input pins as shown below. a device that offers excellent jitter perfor- mance is the mc100lvel16 (or same family) from motorola. encode encode AD10465 0.1 f ecl/ pecl vt vt 0.1 f figure 7. differential ecl for encode jitter considerations the signal-to-noise ratio (snr) for an adc can be predicted. when normalized to adc codes, equation 1 accurately predicts the snr based on three terms. these are jitter, average dnl error, and thermal noise. each of these terms contributes to the noise within the converter. snr f t rms v n analog noise rms n =? + ? ? ? ? ? ? + () + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 20 1 2 2 2 2 2 12 log / j (1) f analog = analog input frequency. t j rms = rms jitter of the encode (rms sum of encode source and internal encode circuitry). = average dnl of the adc (typically 0.50 lsb). n = number of bits in the adc. v noise rms = v rms noise referred to the analog input of the adc (typically 5 lsb). for a 14-bit analog-to-digital converter like the AD10465, aper- ture jitter can greatly affect the snr performance as the analog frequency is increased. the chart below shows a family of curves that demonstrates the expected snr performance of the AD10465 as jitter increases. the chart is derived from the above equation. for a complete discussion of aperture jitter, please consult analog devices application note an-501, aperture uncer- tainty and adc system performance. rms clock jitter ps 0.1 snr dbfs 60 a in = 5mhz a in = 10mhz a in = 20mhz a in = 32mhz 0.3 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 0.7 1.1 1.5 1.9 2.3 2.7 3.1 3.5 3.9 61 62 63 64 65 66 67 68 69 70 71 figure 8. snr vs. jitter
rev. 0 AD10465 C11C power supplies care should be taken when selecting a power source. linear supplies are strongly recommended. switching supplies tend to have radiated components that may be received by the AD10465. each of the power supply pins should be decoupled as closely to the package as possible using 0.1 f chip capacitors. the AD10465 has separate digital and analog power supply pins. the analog supplies are denoted av cc and the digital supply pins are denoted dv cc . av cc and dv cc should be separate power supplies. this is because the fast digital output swings can couple switching current back into the analog sup- plies. note that av cc must be held within 5% of 5 v. the AD10465 is specified for dv cc = 3.3 v as this is a common supply for digital asics. output loading care must be taken when designing the data receivers for the AD10465. the digital outputs drive an internal series resistor (e.g., 100 ? ) followed by a gate like 75lcx574. to minimize capacitive loading, there should only be one gate on each output pin. an example of this is shown in the evaluation board sche- matic shown in figure 10. the digital outputs of the AD10465 have a constant output slew rate of 1 v/ns. a typical cmos gate combined with a pcb trace will have a load of approxi- mately 10 pf. therefore, as each bit switches, 10 ma (10 pf 1 v , 1 ns ) of dynamic current per bit will flow in or out of the device. a full-scale transition can cause up to 140 ma (14 bits 10 ma/bit) of current flow through the output stages. these switching currents are confined between ground and the dv cc pin. standard ttl gates should be avoided since they can appreciably add to the dynamic switching currents of the AD10465. it should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. digital out- put timing is guaranteed with 10 pf loads. layout information the schematic of the evaluation board (figure 10) represents a typical implementation of the AD10465. the pinout of the AD10465 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. it is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. all capacitors can be standard high quality ceramic chip capacitors. care should be taken when placing the digital output runs. because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. internal circuitry buffers the outputs of the adc through a resistor network to eliminate the need to externally isolate the device from the receiving gate. evaluation board the AD10465 evaluation board (figure 9) is designed to pro- vide optimal performance for evaluation of the AD10465 analog- to-digital converter. the board encompasses everything needed to insure the highest level of performance for evaluating the AD10465. the board requires an analog input signal, encode clock and power supply inputs. the clock is buffered on-board to provide clocks for the latches. the digital outputs and clocks are available at the standard 40-pin connectors j1 and j2. power to the analog supply pins is connected via banana jacks. the analog supply powers the associated components and the analog section of the AD10465. the digital outputs of the AD10465 are powered via banana jacks with 3.3 v. contact the factory if additional layout or applications assistance is required. figure 9a. evaluation board mechanical layout
rev. 0 AD10465 C12C u1 AD10465 draout agnda dgnda dgndb l10 47 l7 47 c22 10 f 5.2vaa c53 10 f +5vaa agndb drbout c61 0.1 f agndb +3.3vdb c58 10 f l6 47 c64 0.1 f dgndb l9 47 c59 10 f 5.2vab c57 0.1 f agnda agnda agndb c52 10 f agndb l8 47 47 at 100mhz c63 0.1 f l11 47 c62 10 f dgnda dgnda +3.3vda 47 at 100mhz 47 at 100mhz agnda 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 agndb agndb agndb agndb refb drbout agndb agndb encbb encb +3.3vdb d13b(msb) d12b d11b d10b d9b dgndb encbb encb dut 3.3vdb d13b(msb) d12b d11b d10b d9b 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 agnda a in a3 a in a2 a in a1 agnda agnda refa agnda shield agndb 5.2vab +5vab agndb ainb3 ainb2 ainb1 agndb +5vab a in b3 a in b2 a in b1 a in a3 a in a2 a in a1 agnda agnda draout 5.2vaa +5vaa d0a(lsb) d1a d2a d3a d4a d5a d6a d7a d8b d9a d10a dgnda 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 dgnda encab enca +3.3vda d11a d12a d13a(msb) d0b(lsb) d1b d2b d3b d4b d5b d6b d7b d8b dgndb 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 encab enca dut 3.3vda d11a d12a d13a db0b d1b d2b d3b d4b d5b d6b d7b d8b +5vaa d0a d1a d2a d3a d4a d5a d6a d7a d8b d9a d10a +5vab a in b3 j1 agndb a in b2 j2 agndb a in b1 j22 agndb a in a3 j7 agnda a in a2 j8 agnda a in a1 j20 agnda dut 3.3vdb c26 0.1 f dgndb dgndb spare gate u2:c dut 3.3vda c27 0.1 f dgnda dgnda spare gate u4:c 10 9 10 9 88 74lcx00m 74lcx00m u2:a 1 2 jp5 3 u2:d 13 12 11 u2:b 4 5 6 jp1 buflatb latchb jp3 jp4 u4:a 1 2 3 u4:d 12 11 u4:b 4 5 6 13 74lcx00m 74lcx00m 74lcx00m 74lcx00m 74lcx00m 74lcx00m jp2 buflata clklatchb2 clklatchb1 drbout draout clklatcha2 clklatcha1 jp6 latcha figure 9b. evaluation board
rev. 0 AD10465 C13C j18 agnda r83 51 c40 0.1 f agnda j6 agnda r82 51 c42 0.1 f agnda jp8 jp11 open encodea e ncodea nc = no connect vcc q q vee nc d d vbb u7 mc10ep16d agnda 1 2 3 4 8 7 6 5 out nr in sd u6 agnda 2 6 1 8 err 3 +5vaa c45 100pf gnd agnda jp7 r140 33k 4 +5vaa c41 0.47 f agnda r89 100 agnda r94 100 c49 0.1 f c44 0.1 f encab enca adp3330 j17 agndb r79 51 c39 0.1 f agndb j16 agndb r76 51 c37 0.1 f agndb jp10 jp12 open encodeb e ncodeb nc = no connect vcc q q vee nc d d vbb u9 mc10ep16d agndb 1 2 3 4 8 7 6 5 out nr in sd u8 agndb 2 6 1 8 err 3 +5vaa c43 100pf gnd agndb jp9 r141 33k 4 +5vaa c38 0.47 f agndb r95 100 agndab r97 100 c46 0.1 f c48 0.1 f encb encbb adp3330 figure 9c. evaluation board
rev. 0 AD10465 C14C out 3.3vda c20 0.1 f c15 0.1 f c14 0.1 f c13 0.1 f dgnda e1 e2 e3 e4 e5 e6 e7 e8 e9 +5vaa +5vab +3.3vda +3.3vdb 5.2vab agndb agnda dgnda dgndb 5.2vaa e10 u21 25 24 26 27 42 31 7 16 29 30 32 33 23 22 20 19 35 36 48 17 16 14 13 1 37 38 40 12 11 41 43 44 9 8 6 5 46 47 28 3 2 21 15 34 39 18 4 cp2 oe2 i15 i14 i10 i4 i0 45 i11 i12 i8 i13 i7 i6 i5 i1 i3 i2 gnd i9 o10 o7 o3 o0 gnd o6 o5 o4 o2 o1 gnd gnd gnd o9 o11 o12 o13 o14 o15 vcc vcc vcc vcc o8 cp1 oe1 gnd gnd gnd 74lcx163743mtd (lsb) d0a d1a d2a d3a d4a d5a d12a (msb) d13a d11a d10a d9a d8a d7a d6a r99 0 dgnda r100 0 r98 51 dgnda out 3.3vda 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 33 34 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 33 34 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 r113 100 r105 100 r104 100 r106 100 r117 100 r115 100 r116 100 r114 100 dgnda r108 100 r107 100 r110 100 r111 100 r102 100 r101 100 r109 100 r103 100 j3 r118 51 buflata latcha msb out 3.3vda c24 0.1 f c23 0.1 f c21 0.1 f c25 0.1 f dgndb u22 25 24 26 27 42 31 7 16 29 30 32 33 23 22 20 19 35 36 48 17 16 14 13 1 37 38 40 12 11 41 43 44 9 8 6 5 46 47 28 3 2 21 15 34 39 18 4 cp2 oe2 i15 i14 i10 i4 i0 45 i11 i12 i8 i13 i7 i6 i5 i1 i3 i2 gnd i9 o10 o7 o3 o0 gnd o6 o5 o4 o2 o1 gnd gnd gnd o9 o11 o12 o13 o14 o15 vcc vcc vcc vcc o8 cp1 oe1 gnd gnd gnd 74lcx163743mtd (lsb) d0b d1b d2b d3b d4b d5b d12b (msb) d13b d11b d10b d9b d8b d7b d6b r124 0 dgndb r123 0 r119 51 dgndb out 3.3vdb 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 33 34 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 33 34 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 r130 100 r129 100 r128 100 r134 100 r112 100 r127 100 r126 100 r125 100 dgndb r133 100 r120 100 r121 100 r122 100 r136 100 r131 100 r132 100 r135 100 j4 r137 51 buflatb latchb msb e162 e163 e164 e165 e166 e171 e172 e177 e179 e181 e186 e187 e207 e209 e211 e213 e215 e217 e219 e221 e227 e229 e231 e233 e159 e160 e161 e167 e168 e169 e170 e178 e180 e182 e183 e191 e192 e193 e208 e210 e212 e214 e216 e218 e220 e222 e228 e230 e232 e234 dgndb agndb e89 e139 e143 e146 e148 e149 e152 e153 e184 e188 e189 e190 e195 e197 e199 e201 e203 e205 e224 e226 e87 e88 e72 e140 e141 e142 e144 e145 e147 e150 e151 e154 e185 e194 e196 e198 e200 e202 e204 e206 e223 e225 dgnda agnda banana jacks for gnds and pwrs figure 9d. evaluation board
rev. 0 AD10465 C15C bill of materials list for AD10465 evaluation board reference manufacturer and component qty designator value description part number name 2 u2, u4 ic, low-voltage quad 2-input nand, soic-14 toshiba/tc74lcx00fn 74lcx00m 2 u21, u22 ic, 16-bit transparent latch with three-state fairchild/74lcx163743mtd 74lcx163743mtd outputs, tssop-48 1 u1 dut, ic 14-bit analog-to-digital converter adi/AD10465az adi/AD10465az 2 u6, u8 ic, voltage regulator 3.3 v, rt-6 analog devices/adp3330art-3, adp3330 3-rlt 10 e1 e10 banana jack, socket johnson components/08-0740-001 banana hole 22 c13 c15, 0.1 f capacitor, 0.1 f, 20%, 12 v dc, 0805 mena/grm40x7r104k025bl cap 0805 c20, c21, c23 c27, c37, c39, c40, c42, c44, c46, c48, c49, c57, c61, c63, c64 2 c38, c41 0.47 f capacitor, 0.47 f, 5%, 12 v dc, 1206 vitramon/vj1206u474mfxmb cap 1206 2 c43, c45 100 pf capacitor, 100 pf, 10%, 12 v dc, 0805 johansen/500r15n101jv4 cap 0805 2 j3, j4 connector, 40-pin header male st. samtec/tsw-120-08-g-d hd40m 6l6 l11 47 h inductor, 47 h @ 100 mhz, 20%, ind2 fair-rite/2743019447 ind2 2 u7, u9 ic, differential receiver, soic-8 motorola/mc10ep16d mc10ep16d 6 c22, c50, c52, c53, c59, c62 10 f capacitor, 10 f, 20%, 16 v dc, 1812pol kemet/t491c106m016a57280 polcap 1812 4 r99, r100, r123, r124 0.0 ? resistor, 0.0 ? , 0805 panasonic/erj-6gey0r00v res2 0805 2 r140, r141 33,000 ? resistor, 33,000 ? , 5%, 0.10 watt, 0805 panasonic/erj-6geyj333v res2 0805 8 r76, r79, r82, 51 ? resistor, 51 ? , 5%, 0.10 watt, 0805 panasonic/erj-6geyj510v res2 0805, res 0805 r83, r98, r118, r119, r137 36 r89, r94, r95, 100 ? resistor, 100 ? , 5%, 0.10 watt, 0805 panasonic/erj-6geyj101v res2 0805, res 0805 r97, r101 r117, r120 r122, r125 r136 8 j1, j2, j6 j8, connector, sma female st. johnson components/142-0701-201 sma j16 j18, j20, j22
rev. 0 AD10465 C16C figure 10a. top layer copper figure 10b. second layer copper
rev. 0 AD10465 C17C figure 10c. third layer copper figure 10d. fourth layer copper
rev. 0 AD10465 C18C figure 10e. fifth layer copper figure 10f. bottom layer copper
rev. 0 AD10465 C19C figure 10g. bottom silkscreen figure 10h. bottom assembly
rev. 0 C20C c02356C4.5C1/01 (rev. 0) printed in u.s.a. AD10465 outline dimensions dimensions shown in inches and (mm). 68-lead ceramic leaded chip carrier (es-68a) 0.950 (24.13) sq top view (pins down) pin 1 10 26 9 61 60 44 43 27 0.050 (1.27) 0.018 (0.457) 0.800 (20.32) 1.180 (29.97) sq 0.060 (1.52) 0.240 (6.096)

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