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| data sheet c-5e network processor silicon revision a1 C5ENPA1-DS/d rev 03 preliminary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet c-5e network processor silicon revision a1 C5ENPA1-DS/d rev 03 preli m inary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . copyright ? 2002 motorola, inc. all rights reserved. no part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from motorola. motorola reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of motorola to provide notification of such revision or change. motorola provides this documentation without warranty, term, or condition of any kind, either implied or expressed, including, but not limited to, the implied warranties, terms or conditions of merchantability, satisfactory quality, and fitness for a particular purpose. motorola may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. c-5e, c-3e, c-5, q-5, q-3, c-port, and c-ware are all trademarks of c-port, a motorola company. motorola and the stylized motorola logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 contents about this guide guide overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data sheet classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 using pdf documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 guide conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 related product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 c hapter 1 functional description features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 massive processing power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 high functional integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 channel processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 executive processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 system interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 fabric processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 buffer management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table lookup unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 queue management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 c hapter 2 signal descriptions signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 pin descriptions grouped by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 lvttl and lvpecl specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 cp interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ds1/t1 framer interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10/100 ethernet (rmii) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 gigabit ethernet (gmii) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6 contents C5ENPA1-DS/d rev 03 motorola general business information gigabit ethernet and fibre channel tbi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 sonet oc-3 transceiver interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 sonet oc-12 transceiver interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 executive processor system interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 serial interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 prom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 general system interface signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 fabric processor interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 bmu sdram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 tlu sram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 qmu sram (internal mode) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 qmu to q-5 tmc (external mode) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 power supply signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 no connection pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 signals grouped by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 jtag support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 jtag data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 boundary scan restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 boundary scan cell types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 idcode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 jtag instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 boundary scan description language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 c hapter 3 electrical specifications absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 power and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 thermal management information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 internal package conduction resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 heat sink selection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ac timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 clock timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . contents 7 motorola general business information C5ENPA1-DS/d rev 03 cp timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ds1/ds3 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10/100 ethernet timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 gigabit gmii ethernet, tbi and mii interface timing specifications . . . . . . . . . . . . . . . . . . 85 oc-3 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 oc-12 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 executive processor timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 pci timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 mdio serial interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 low speed serial interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 prom interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 fabric processor timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 bmu timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 tlu timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 qmu sram (internal mode) timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 qmu to q-5 (external mode) timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 c hapter 4 mechanical specifications package views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 package measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 marking codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8 contents C5ENPA1-DS/d rev 03 motorola general business information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 list of figures 1 c-5e network processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 pin locations (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 pin locations (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 gmii/tbi transmit and receive pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 prom interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6 prom interface timing outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7 observe-only cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8 cell design that can be used for both input and output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9 bringup clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10 package cross section view with several heat sink options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11 package with heat sink mounted to the printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12 test loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13 system clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 14 ds1/ds3 ethernet timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 15 10/100 ethernet timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 16 gigabit ethernet and tbi interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 17 oc-3 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 18 oc-12 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 19 pci timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20 mdio serial interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 21 low speed serial interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 22 prom interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 23 fabric processor timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 24 bmu timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 25 tlu timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 26 qmu sram (internal mode) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 27 qmu to q-5 (external mode) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 28 c-5e network processor bga package side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 29 c-5e network processor bga package (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 30 c-5e network processor bga package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10 list of figures C5ENPA1-DS/d rev 03 motorola general business information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 list of tables 1 data sheet classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 navigating within a pdf document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 c-5e network processor data sheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 c-port silicon documentation set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 tlu sram configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 clock and reference signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 cp physical interface signals and pins (grouped by clusters) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 ds1/t1 framer interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 10/100 ethernet signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 transmit and receive pin combinations for gigabit ethernet and fibre channel . . . . . . . . . . . 35 11 gigabit ethernet (gmii/mii) signals one cluster example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 gigabit ethernet and fibre channel tbi signals example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13 oc-3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 oc-12 signals example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 15 pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 16 serial interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 17 prom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 18 general system interface signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 19 fabric interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 20 utopia1*, 2, 3 atm mode, c-5e network processor to fabric interface pin mapping . . . . . . 49 21 utopia1*, 2, 3 phy mode, c-5e network processor to fabric interface pin mapping . . . . . . . 49 22 prizma mode, c-5e network processor to fabric interface pin mapping . . . . . . . . . . . . . . . . 50 23 power x(csix-l0) mode, c-5e network processor to fabric interface pin mapping . . . . . . . . 50 24 csix-l1 mode, c-5e network to fabric interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 51 25 bmu sdram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 26 tlu sram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 27 qmu sram (internal mode) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 28 qmu to q-5 (external mode) interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 29 power supply signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 30 miscellaneous test signals for jtag, scan, and internal test routines . . . . . . . . . . . . . . . . 58 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 12 list of tables C5ENPA1-DS/d rev 03 motorola general business information 31 no connection pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 32 signals listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 33 jtag internal register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 34 jtag identification code and its subcomponents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 35 instruction register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 36 c-5e network processor absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 37 c-5e network processor recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . .74 38 c-5e network processor dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 39 c-5e network processor capacitance data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 40 c-5e network processor power and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 41 system clock timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 42 ds1/ds3 ethernet timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 43 10/100 ethernet timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 44 gigabit gmii/mii ethernet interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 45 gigabit tbi interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 46 oc-3 timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 47 oc-12 timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 48 pci timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 49 mdio serial interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 50 low speed serial interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 51 prom interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 52 fabric processor timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 53 bmu timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 54 signal groups in bmu timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 55 tlu timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 56 signal groups in tlu timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 57 qmu sram (internal mode) timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 58 signal groups in qmu sram (internal mode) timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 100 59 qmu to q-5 (external mode) timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 60 signal groups in qmu to q-5 (external mode) timimg diagrams . . . . . . . . . . . . . . . . . . . . . . . 102 61 package measurements (reference figure 28 , figure 29 and figure 30 for symbols) . . . . 106 62 c-5e network processor marking codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 about this guide guide overview the c-5e network processor data sheet describes hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications. this document contains information on a pre-production product. specifications and information herein are subject to change without notice. this guide assumes a good understanding of the c-5e tm network processor (np) architecture. see the c-5e/c-3e network processor architecture guide (part number c5ec3earch-rm/d) for more detail about the hardware. this guide also assumes good working knowledge of the c-ware software toolset. this guide covers the following topics: ? functional description signal descriptions electrical specifications mechanical specifications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 14 about this guide C5ENPA1-DS/d rev 03 motorola general business information data sheet classifications table 1 describes the data sheet classifications of advance, preliminary, and production. using pdf documents electronic documents are provided as pdf files. open and view them using the adobe? acrobat? reader application, version 3.0 or later. if necessary, download the acrobat reader from the adobe systems, inc. web site: http://www.adobe.com/prodindex/acrobat/readstep.html pdf files offer several ways for moving among the document?s pages, as follows: to move quickly from section to section within the document, use the acrobat bookmarks that appear on the left side of the acrobat reader window. the bookmarks provide an expandable outline view of the document ? s contents. to display the document ? s acrobat bookmarks, press the ? display both bookmarks and page ? button on the acrobat reader tool bar. to move to the referenced page of an entry in the document ? s contents or index, click on the entry itself, each of which is hyperlinked. to follow a cross-reference to a heading, figure, or table, click the blue text. table 1 data sheet classifications classification description advance information used to advise customers of the proposed addition to the product line. this document will typically contain some useful information including interfacing with the user ? s system and some specifications. the goal of this document is to allow customers to begin designs but with expectation of changes. specification details may be changed later without notice. preliminary information describes pre-production or first production devices and is usually indicative of production stage performance. minor changes should be expected as characteristic spreads become better controlled. specification details may be changed slightly without notice, but the customer can design their product based on this data sheet. production data defines the long-term specified production limits based on fully characterized data. it includes a disclaimer to allow improvements in specifications and modifications that do not affect form, fit or function in original applications; if absolute maximum ratings are changed, they should improve rather than downgrade. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . using pdf documents 15 motorola general business information C5ENPA1-DS/d rev 03 to move to the beginning or end of the document, to move page by page within the document, or to navigate among the pages you displayed by clicking on hyperlinks, use the acrobat reader navigation buttons shown in this figure: table 2 summarizes how to navigate within an electronic document. table 2 navigating within a pdf document to navigate this way click this move from section to section within the document. a bookmark on the left side of the acrobat reader window move to an entry in the table of contents. the entry itself move to an entry in the index. the page number move to an entry in the list of figures or list of tables. the figure or table number follow a cross-reference (highlighted in blue text). the cross-reference text move page by page. the appropriate acrobat reader navigation buttons move to the beginning or end of the document. the appropriate acrobat reader navigation buttons move backward or forward among a series of hyperlinks you have selected. the appropriate acrobat reader navigation buttons beginning of document end of next page previous previous or next hyperlink f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 16 about this guide C5ENPA1-DS/d rev 03 motorola general business information guide conventions the following visual elements are used throughout this guide, where applicable: this icon and text designates information of special note. warning: this icon and text indicate a potentially dangerous procedure. instructions contained in the warnings must be followed. warning: this icon and text indicate a procedure where the reader must take precautions regarding laser light. this icon and text indicate the possibility of electrostatic discharge (esd) in a procedure that requires the reader to take the proper esd precautions. revision history table 3 provides details about changes made for each revision of this guide. table 3 c-5e network processor data sheet revision history revision date cst revision cds revision changes november 8, 2002 2.2 2.0 added information about optional capacitors, nominal values for recommended operating conditions, and updated package measurement values. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . related product documentation 17 motorola general business information C5ENPA1-DS/d rev 03 related product documentation table 4 lists the user and reference documentation for motorola ? s c-port silicon documentation set. table 4 c-port silicon documentation set document subject document name purpose document id processor information c-5 network processor architecture guide describes the full architecture of the c-5 network processor. c5nparch-rm/d c-5 network processor data sheet describes hardware design specifications for the c-5 network processor. c5npdata-ds/d c-5e/c-3e network processor architecture guide describes the full architecture of the c-5e and c-3e network processors. c5ec3earch-rm/d c-5e network processor data sheet describes hardware design specifications for the c-5e network processor. C5ENPA1-DS/d c-3e network processor data sheet describes hardware design specifications for the c-3e network processor. c3enpa1-ds/d c-5 network processor to c-5e network processor comparison delta document describes key architectural features of the c-5e, and highlights main differences between c-5 and c-5e. c5c5edelta-rm/d m-5 channel adapter architecture guide describes the full architecture of the m-5 channel adapter. m5caarch-rm/d m-5 channel adapter data sheet describes hardware design specifications for the m-5 channel adapter. m5ca0-ds/d q-5/q-3 traffic management coprocessor architecture guide describes the full architecture of the q-5 and q-3 traffic management coprocessor. q5q3arch-rm/d q-5 traffic management coprocessor data sheet describes hardware design specifications for the q-5 traffic management coprocessor. q5tmca0-ds/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 18 about this guide C5ENPA1-DS/d rev 03 motorola general business information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 chapter 1 functional description features key features of the c-5e tm network processor (np) are its massive processing capabilities and its high level of functional integration on one chip. massive processing power operating frequencies: up to 266mhz 5gbps of bandwidth (for non-blocking throughput) more than 4,500mips of computing power (for adding services throughout the protocol stack) up to 15 million packets per second transmitted at wire speed 17 programmable risc cores (for cell/packet forwarding) 32 programmable serial data processors (for processing bit streams) up to 133 million table lookups per second three internal buses for 68gbs of aggregate bandwidth high functional integration 840 pin ball grid array (bga) package 16 channel processors including: ? embedded oc-3c , oc-12 , oc-12c sonet framers ? programmable mac interface ? risc cores ? programmable pin phy interfaces embedded coprocessors for table lookup (classification), buffer management (payload control), and queue management (cos/qos implementation) dedicated fabric processor and port f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 20 chapter 1: functional description C5ENPA1-DS/d rev 03 motorola general business information embedded risc executive processor integrated 32bit 33/66mhz pci bus interface block diagram the c-5e tm np, has an architecture specifically designed for networking applications. the following sections describe each component of the c-5e np. the main components of the c-5e np are: channel processors executive processor fabric processor buffer management unit table lookup unit queue management unit the c-5e np conforms with both sonet and sdh. therefore, oc-3(sts-3/stm-1), oc-12 (sts-12/stm-4, and oc48 (sts-48/stm-16). figure 1 shows a block diagram of the c-5e np, including its potential external interfaces. for more information about the architecture of the c-5e np, see the c-5e/c-3e network processor architecture guide (part number c5ec3earch-rm/d) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . block diagram 21 motorola general business information C5ENPA1-DS/d rev 03 figure 1 c-5e network processor block diagram phy phy phy phy phy phy phy phy buses (68gbps bandwidth) cluster cluster cp-1 cp-0 cp-2 cp-3 cp-12 cp-13 cp-14 cp-15 external host cpu (optional) oc-3 phy interface examples: oc-12 gigabit ethernet - aggregated 10/100 ethernet external prom (optional) control logic (optional) fabric processor boundary buffer mgmt unit channel processors sdram c-5e np sram sram ta b l e lookup unit fabric processor executive processor queue mgmt unit pci serial prom 1xoc-48c or 48x sts-1 with m-5 companion device q-5 (optional) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 22 chapter 1: functional description C5ENPA1-DS/d rev 03 motorola general business information channel processors the c-5e np contains sixteen programmable channel processors (cps) that receive, process, and transmit network data. the number of cps per port is configurable, depending on the line interface. typically one cp is assigned to each port for medium bandwidth applications (fast ethernet to oc-3). multiple cps can be assigned to a port in a configuration called channel aggregation in high bandwidth applications (greater than oc-3). multiple logical ports can be assigned to a single cp, with the addition of an external multiplexor, for low bandwidth applications, such as ds1 to ds3. the c-5e np ? s architecture supports a variety of industry-standard serial and parallel protocols and individual port data rates including: 10/100mb ethernet (rmii) 1gb ethernet (gmii and tbi) oc-3c oc-12 oc-48c (using various configurations with m-5 channel adapter) oc-48 (using various configurations with m-5 channel adapter) 100mbit fibrechannel ds1/ds3, supported through the use of external framers/multiplexors the c-5e np?s programmability can also support a variety of special interfaces, such as various xdsl encapsulations and proprietary protocols. key components of each cp are a risc core (cprc) that orchestrates cell/packet processing and a set of microprogrammable, special-purpose processors, called serial data processors (sdps), that provide features such as ethernet mac and sonet/sdh framing, multichannel hdlc, and atm cell delineation. this means you usually only need to include phys to complete the system. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . executive processor 23 motorola general business information C5ENPA1-DS/d rev 03 executive processor the executive processor (xp) serves as a centralized computing resource for the c-5e np and manages the system interfaces. the xp performs conventional supervisory tasks in the c-5e np, including: reset and initialization of the c-5e np program loading and control of cps centralized exception handling management of a host interface through the pci management of system interfaces (pci, serial bus, prom) system interfaces the system interfaces to the xp are: pci ? provides an industry standard 32bit 33/66mhz pci channel used for chip-level shared resources. the pci has both initiator and target capabilities. the pci interface is typically connected to a host processor. serial bus interface ? provides a general purpose bi-directional, two-wire serial bus and i/o port that allows the c-5e np to control external logic with either of two standard protocols: ? the mdio (high-speed) protocol : uses a 16bit data format with 10bits of addressing and supports transfers up to 25mhz. ? the low-speed protocol : uses an 8bit data format followed by an acknowledge bit and supports transfers up to 400kbps. software is used to select which protocol to use, by setting the appropriate bits in the serial bus configuration register. when a serial bus transfer is active, an external pin is driven by the c-5e np to indicate which protocol is being used (spld=0 indicates mdio protocol; spld=1 indicates low-speed protocol). both sida and sicl are bi-directional lines that are connected, via an external pull-up resistor, to a positive supply voltage. when the bus is free, both lines are high because of the pull-up resistor. the output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-and function required for its arbitration mechanism. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 24 chapter 1: functional description C5ENPA1-DS/d rev 03 motorola general business information prom interface ? allows the xp to boot from nonvolatile, flash memory. the prom interface is a low-speed, serial i/o port that runs at 1 / 2 to 1 / 16 the core clock rate. the maximum prom size addressable is 4mbytes, and must use a ? by 16 ? part. external board logic is required to perform serial-to-parallel conversion for prom address outputs and parallel-to-serial conversion for prom data inputs. fabric processor the fabric processor (fp) acts as a high-speed network interface port with advanced functionality. it allows the c-5e np to interface to an application-specific switching solution internal to your design. the fp port supports the bidirectional transfer of segments from the c-5e np to a hardware interface that provides connectivity to other network processors or other similar line processing hardware. there are numerous parameters that can be configured within the fp to allow the interface to be adapted to different fabric protocols. the fp can be configured to conform to seven (7) different fabric interfaces that include: csix-l1, utopia-1, -2, -3, prizma, power x(csix-l0), and utopia3 like to m-5. the fp can be configured to run at any frequency up to 125mhz, with the receive and transmit data buses up to 32 bits wide. this allows a wide range of supported bandwidths to and from the switching fabric, all the way up to 4000 mbps full duplex bandwidth. buffer management unit the buffer management unit (bmu) interfaces the c-5e np to external pipeline architecture, single data rate synchronous dram. the external memory is partitioned and used as buffers for receiving and transmitting data between cps, the fp, and the xp. it is also used as second level storage in the xp memory hierarchy. the interface to an array of sdram chips is 139bits wide, composed of 128 data bits, two internal control bits, and nine secded (single error correction-double error detection) ecc (error correction code) bits. the interface is compliant with the pc100 standard and operates at up to 133mhz with 3.3v lvttl-compatible inputs and outputs. the refresh period, trcd, tcas, trp, tmrd, and trc are configurable via boot time configuration (see the c-5e/c-3e network processor architecture guide (part number c5ec3earch-rm/d) for more details). the c-5e np non-configurable interface transfers four beats of data for each read and write using a sequential burst type. in addition, the c-5e np uses an auto-refresh mode for the ram ? s. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table lookup unit 25 motorola general business information C5ENPA1-DS/d rev 03 some of these parameters are programmed into the sdrams ? mode register and can be applied only once per power cycle. the ecc functionality can be enabled or disabled via configuration register writes. if needed, the interface can narrowed to 128bits by disabling ecc and providing board pull-ups for the two control bits and nine ecc bits. this is useful if dimms are used in the board design. if individual sdram parts are used, x16 and x32 are supported. the bmu supports sdram devices that use 12 address lines. internal address calculation paths limit the maximum memory size to 128mbytes. only one physical bank of sdram is supported. table lookup unit the table lookup unit (tlu) performs table lookups in external sram. it can also be used for statistics accumulation and retrieval and as general data storage. the tlu simultaneously supports multiple application-defined tables and multiple search strategies, such as those needed for routing, circuit switching, and qos lookup tasks. the c-5e np uses external 64bit wide zbt pipelined bursting static ram (sram) modules (at frequencies up to 133mhz) for storage of its tables. these modules allow implementation of tables with 2 25 x 64bit entries using 8mbit sram technology. the maximum amount of memory supported by the tlu is 128mbytes in four banks, when sram technology supports 4m x 18pins parts. table 5 tlu sram configurations sram technology min table size (one bank) maximum table size (four banks) 1mbit (32k x 32pins) 256kbytes 1mbytes 2mbit (64k x 32pins) 512kbytes 2mbytes 4mbit (256k x 18pins) 2mbytes 8mbytes 8mbit (512k x 18pins) 4mbytes 16mbytes 16mbit (1m x 18pins) 8mbytes 32mbytes 32mbit (2m x 18pins) 16mbytes 64mbytes 64mbit (4m x 18pins) 32mbytes 128mbytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 26 chapter 1: functional description C5ENPA1-DS/d rev 03 motorola general business information queue management unit the queue management unit (qmu) autonomously manages a number of application-defined descriptor queues. it handles inter-cp and inter-c-5e np descriptor flows by providing switching and buffering. it also performs descriptor replication for multicast applications. a number of up to 128 queues can be assigned to each cprc for qos-based services. the qmu provides a queuing engine internal to the chip and uses external sram to store the descriptors. scheduling is done by the cps. the qmu supports up to 512 queues and 16, 384 descriptor buffers. a descriptor buffer holds an application-defined ? descriptor ? , which is a structure that defines the payload buffer handle and other attributes of the forwarded cell or packet. the qmu ? s external sram interface uses zbt synchronous srams organized in a single bank of up to 128k, 32bit words. this interface runs at up to 175mhz frequency. the c-5e provides two modes for managing queues. they consist of: internal mode (using the internal qmu only) external mode (using the internal qmu and the external q-5 traffic management coprocessor) see the c-5e/c-3e network processor architecture guide (part number c5ec3earch-rm/d), as well as, the q-5/q-3 traffic management coprocessor architecture guide (part number q5q3arch-rm/d) for more details. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 chapter 2 signal descriptions signal summary there are ten (10) functional groupings of signals in the c-5e network processor: clock ? 11 pins channel processors (cp0 - cp15) ? 16x7 = 112 pins executive processor (xp) ? 57 pins ? pci interface ? 50 pins ? prom interface ? 4 pins ? serial bus interface ? 2 pins ? general system interface ? 1 pin fabric processor (fp) ? 80 pins buffer management unit (bmu) ? 160 pins table lookup unit (tlu) ? 99 pins queue management unit (qmu) ? 59 pins power ? 245 pins test ? 14 pins no connection (nc) ? 3 pins two (2) of the sections (cps and fp) are configurable, depending on the type of device being implemented. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 28 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information pinout diagram the c-5e np contains 840 pins. these pin numbers are referenced throughout the remaining chapter. figure 2 shows the pin locations from the top view. in contrast, figure 3 shows the pin locations from the bottom view. figure 2 pin locations (top view) 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 aj cp0_0 cp1_0 cp1_5 cp2_4 cp3_4 cp5_2 cp6_1 cp7_1 cp8_1 cp8_6 fout0 fout6 fout12 fout19 fout24 fout31 ftxctl5 fin3 fin10 fin15 fin22 fin29 frxctl3 pad0 p ad1 pad2 pad3 pad4 aj ah cp0_1 vdd33 cp1_6 cp2_5 cp3_5 cp5_3 cp6_2 cp7_2 vdd33 cp9_0 fout1 fout7 fout13 gnd fout25 ftxctl0 ftxctl6 fin4 vddf fin16 fin23 fin30 gnd pad5 pad6 pad7 vdd33 pad8 ah ag cp0_2 cp1_1 cp2_0 cp2_6 cp3_6 cp5_4 cp6_3 cp7_3 cp8_2 cp9_1 fout2 vddf fout14 fout20 fout26 vddf ftxclk fin5 fin11 fin17 fin24 fin31 frxctl4 pad9 pad10 pad11 pad12 pad13 ag af cp0_3 cp1_2 vdd33 cp3_0 cp4_0 gnd cp6_4 cp7_4 cp8_3 cp9_2 gnd fout8 fout15 fout21 fout27 ftxctl1 gnd fin6 fin12 fin18 fin25 gnd frxctl5 pad14 pad15 vdd3 3pad16 pad17 af ae cp0_4 gnd cp2_1 cp3_1 cp4_1 cp5_5 cp6_5 cp7_5 gnd cp9_3 fout3 fout9 fout16 vddf fout28 ftxctl2 fin0 fin7 gnd fin19 fin26 frxctl0 vddf pad18 pad19 pad20 g nd pad21 ae ad cp0_5 cp1_3 cp2_2 cp3_2 cp4_2 cp5_6 cp6_6 cp7_6 cp8_4 cp9_4 fout4 fout10 fout17 fout22 fout29 ftxctl3 fin1 fin8 fin13 fin20 fin27 frxctl1 frxctl6 pad2 2 pad23 pad24 pad25 pad26 ad ac cp0_6 cp1_4 cp2_3 cp3_3 cp4_3 cp6_0 cp7_0 cp8_0 cp8_5 cp9_5 fout5 fout11 fout18 fout23 fout30 ftxctl4 fin2 fin9 fin14 fin21 fin28 frxctl2 frxclk pad27 pad28 pad29 pad30 pad31 ac ab cp9_6 cpa_0 vdd33 cpa_1 cpa_2 gnd cpa_4 cpa_5 vdd33 gnd vdd33 gnd vddf gnd vddf gnd vddf gnd vdd33 ptrdyx pirdyx gnd pcbex0 pcbex1 pcbex2 vdd33 pcbex3 ppa r ab aa cpa_6 gnd cpb_0 cpb_1 cpb_2 cpb_3 cpb_4 cpb_5 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd preqx prstx pclk vdd33 pstopx pdevselx pperrx gnd pserrx aa y cpb_6 cpc_0 cpc_1 cpc_2 cpc_3 cpc_5 cpc_6 cpd_0 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt pinta pidsel pgntx sida sicl spck spld spdi spdo y w cpd_1 cpd_2 cpd_3 cpd_4 cpd_5 cpe_0 cpe_1 cpe_2 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd pframex xpuhot ta21 ta20 ta19 ta18 ta17 ta16 ta15 w v cpe_3 cpe_4 gnd cpe_5 cpe_6 vdd33 cpf_1 cpf_2 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt ta14 ta13 vddt ta12 ta11 ta10 gnd ta9 ta8 v u cpf_3 vdd33 cpf_4 cpf_5 cpf_6 md0 md1 md2 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd ta7 ta6 ta5 gnd ta4 ta3 ta2 vddt ta1 u t md3 md4 md5 md6 md7 md9 md10 md11 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt twe3x twe2x twe1x twe0x tce3x tce2x tce1x tce0x ta0 t r md12 md13 md14 md15 md16 md18 md19 md20 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd td63 td62 td61 td60 tpar3 tpar2 tpar1 tpar0 tclki r p md21 md22 vdd33 md23 md24 gnd md26 md27 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt td59 td58 gnd td57 td56 td55 vddt td54 td53 p n md28 gnd md29 md30 md31 md32 md33 md34 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt gnd td52 td51 td50 vddt td49 td48 td47 gnd td46 n m md35 md36 md37 md38 md39 md41 md42 md43 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt td45 td44 td43 td42 td41 td40 td39 td38 td37 m l md44 md45 md46 md47 md48 md50 md51 md52 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd td36 td35 td34 td33 td32 td31 td30 td29 td28 l k md53 md54 gnd md55 md56 vdd33 md58 md59 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt td27 td26 vddt td25 td24 td23 gnd td22 td21 k j md60 vdd33 md61 md62 md63 md64 md65 md66 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt gnd td20 td19 td18 gnd td17 td16 td15 vddt td14 j h md67 md68 md69 md70 md71 md73 md74 md75 vdd33 gnd vdd33 gnd vdd33 gnd vdd33 gnd vdd33 gnd vddt td13 td12 td11 td10 td9 td8 td7 td6 td5 h g md76 md77 md78 md79 md80 md82 md83 md84 mdecc7 mdecc2 mdqm ma11 ma5 sclk cclk0 cclk3 cpref qa13 td4 td3 td2 td1 td0 qd23 qd16 qd11 qd6 qd0 g f md85 md86 vdd33 md87 md88 vdd33 md90 md91 mdecc6 mdecc1 mdqml ma10 ma4 sclkx cclk1 cclk4 cclk6 qa14 qa9 qa3 qdph vddt qd30 qd24 qd17 vddt qd7 qd1 f e md92 gnd md93 md94 md95 md96 md97 md98 gnd mdecc0 mba0 ma9 ma3 vdd33 cclk2 cclk5 cclk7 qa15 gnd qa4 qardy qbclki gnd qd25 qd18 qd12 gnd qd2 e d md99 md100 md101 md102 md103 md105 md106 md107 mdecc5 mcasx gnd ma8 ma2 jse jso0 jso2 gnd qa16 qa10 qa5 qnqrdy qaclko qd31 qd26 qd19 qd13 qd8 qd3 d c md108 md109 gnd md110 md111 vdd33 md113 md114 mdecc4 mrasx mba1 vdd33 ma1 jtck jclkbyp vdd33 jso3 qdqpar qa11 qa6 qa0 vddt qwex qd27 qd20 gnd qd9 qd4 c b md115 vdd33 md116 md117 md118 md119 md120 md121 vdd33 mwex mdclk ma7 ma0 gnd jtdi jhighz jso5 nc3 vddt qa7 qa1 qaclki gnd qd28 qd21 qd14 vddt qd5 b a md122 md123 md124 md125 md126 md128 md129 mdecc8 mdecc3 mcsx nc5 ma6 jso1 jso4 jtms jtdo jtrstx nc4 qa12 qa8 qa2 qdpl qbclko qd29 qd22 qd15 qd10 a 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 24 cp4_4 gnd cp4_5 cp4_6 vdd33 cp5_0 cp5_1 cpa_3 vdd33 cpc_4 cpd_6 cpf_0 gnd md8 md17 md25 vdd33 md40 md49 md57 gnd md72 md81 md89 gnd md104 md112 gnd md127 24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pinout diagram 29 motorola general business information C5ENPA1-DS/d rev 03 figure 3 pin locations (bottom view) 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 aj cp0_0 cp1_0 cp1_5 cp2_4 cp3_4 cp5_2 cp6_1 cp7_1 cp8_1 cp8_6 fout0 fout6 fout12 fout19 fout24 fout31 ftxctl5 fin3 fin10 fin15 fin22 fin29 frxctl3 pad0 pad1 pad2 pad3 pad4 aj ah cp0_1 vdd33 cp1_6 cp2_5 cp3_5 cp5_3 cp6_2 cp7_2 vdd33 cp9_0 fout1 fout7 fout13 gnd fout25 ftxctl0 ftxctl6 fin4 vddf fin16 fin23 fin30 gnd pad5 pad6 pad7 vdd33 pad8 ah ag cp0_2 cp1_1 cp2_0 cp2_6 cp3_6 cp5_4 cp6_3 cp7_3 cp8_2 cp9_1 fout2 vddf fout14 fout20 fout26 vddf ftxclk fin5 fin11 fin17 fin24 fin31 frxctl4 pad9 pad10 pad11 pad12 pad13 ag af cp0_3 cp1_2 vdd33 cp3_0 cp4_0 gnd cp6_4 cp7_4 cp8_3 cp9_2 gnd fout8 fout15 fout21 fout27 ftxctl1 gnd fin6 fin12 fin18 fin25 gnd frxctl5 pad14 pad15 vdd33 pad16 pad17 af ae cp0_4 gnd cp2_1 cp3_1 cp4_1 cp5_5 cp6_5 cp7_5 gnd cp9_3 fout3 fout9 fout16 vddf fout28 ftxctl2 fin0 fin7 gnd fin19 fin26 frxctl0 vddf pad18 pad19 pad20 gnd pad21 ae ad cp0_5 cp1_3 cp2_2 cp3_2 cp4_2 cp5_6 cp6_6 cp7_6 cp8_4 cp9_4 fout4 fout10 fout17 fout22 fout29 ftxctl3 fin1 fin8 fin13 fin20 fin27 frxctl1 frxctl6 pad22 pad23 pad24 pad25 pad26 ad ac cp0_6 cp1_4 cp2_3 cp3_3 cp4_3 cp6_0 cp7_0 cp8_0 cp8_5 cp9_5 fout5 fout11 fout18 fout23 fout30 ftxctl4 fin2 fin9 fin14 fin21 fin28 frxctl2 frxclk pad27 pad28 pad29 pad30 pad31 ac ab cp9_6 cpa_0 vdd33 cpa_1 cpa_2 gnd cpa_4 cpa_5 vdd33 gnd vdd33 gnd vddf gnd vddf gnd vddf gnd vdd33 ptrdyx pirdyx gnd pcbex0 pcbex1 pcbex2 vdd33 pcbex3 ppar ab aa cpa_6 gnd cpb_0 cpb_1 cpb_2 cpb_3 cpb_4 cpb_5 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd preqx prstx pclk vdd33 pstopx pdevselx pperrx gnd pserrx aa y cpb_6 cpc_0 cpc_1 cpc_2 cpc_3 cpc_5 cpc_6 cpd_0 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt pinta pidsel pgntx sida sicl spck spld spdi spdo y w cpd_1 cpd_2 cpd_3 cpd_4 cpd_5 cpe_0 cpe_1 cpe_2 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd pframex xpuhot ta21 ta20 ta19 ta18 ta17 ta16 ta15 w v cpe_3 cpe_4 gnd cpe_5 cpe_6 vdd33 cpf_1 cpf_2 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt ta14 ta13 vddt ta12 ta11 ta10 gnd ta9 ta8 v u cpf_3 vdd33 cpf_4 cpf_5 cpf_6 md0 md1 md2 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd ta7 ta6 ta5 gnd ta4 ta3 ta2 vddt ta1 u t md3 md4 md5 md6 md7 md9 md10 md11 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt twe3x twe2x twe1x twe0x tce3x tce2x tce1x tce0x ta0 t r md12 md13 md14 md15 md16 md18 md19 md20 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd td63 td62 td61 td60 tpar3 tpar2 tpar1 tpar0 tclki r p md21 md22 vdd33 md23 md24 gnd md26 md27 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt td59 td58 gnd td57 td56 td55 vddt td54 td53 p n md28 gnd md29 md30 md31 md32 md33 md34 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt gnd td52 td51 td50 vddt td49 td48 td47 gnd td46 n m md35 md36 md37 md38 md39 md41 md42 md43 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt td45 td44 td43 td42 td41 td40 td39 td38 td37 m l md44 md45 md46 md47 md48 md50 md51 md52 gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd td36 td35 td34 td33 td32 td31 td30 td29 td28 l k md53 md54 gnd md55 md56 vdd33 md58 md59 vdd33 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt td27 td26 vddt td25 td24 td23 gnd td22 td21 k j md60 vdd33 md61 md62 md63 md64 md65 md66 gnd vdd gnd vdd gnd vdd gnd vdd gnd vddt gnd td20 td19 td18 gnd td17 td16 td15 vddt td14 j h md67 md68 md69 md70 md71 md73 md74 md75 vdd33 gnd vdd33 gnd vdd33 gnd vdd33 gnd vdd33 gnd vddt td13 td12 td11 td10 td9 td8 td7 td6 td5 h g md76 md77 md78 md79 md80 md82 md83 md84 mdecc7 mdecc2 mdqm ma11 ma5 sclk cclk0 cclk3 cpref qa13 td4 td3 td2 td1 td0 qd23 qd16 qd11 qd6 qd0 g f md85 md86 vdd33 md87 md88 vdd33 md90 md91 mdecc6 mdecc1 mdqml ma10 ma4 sclkx cclk1 cclk4 cclk6 qa14 qa9 qa3 qdph vddt qd30 qd24 qd17 vddt qd7 qd1 f e md92 gnd md93 md94 md95 md96 md97 md98 gnd mdecc0 mba0 ma9 ma3 vdd33 cclk2 cclk5 cclk7 qa15 gnd qa4 qardy qbclki gnd qd25 qd18 qd12 gnd qd2 e d md99 md100 md101 md102 md103 md105 md106 md107 mdecc5 mcasx gnd ma8 ma2 jse jso0 jso2 gnd qa16 qa10 qa5 qnqrdy qaclko qd31 qd26 qd19 qd13 qd8 qd3 d c md108 md109 gnd md110 md111 vdd33 md113 md114 mdecc4 mrasx mba1 vdd33 ma1 jtck jclkbyp vdd33 jso3 qdqpar qa11 qa6 qa0 vddt qwex qd27 qd20 gnd qd9 qd4 c b md115 vdd33 md116 md117 md118 md119 md120 md121 vdd33 mwex mdclk ma7 ma0 gnd jtdi jhighz jso5 nc3 vddt qa7 qa1 qaclki gnd qd28 qd21 qd14 vddt qd5 b a md122 md123 md124 md125 md126 md128 md129 mdecc8 mdecc3 mcsx nc5 ma6 jso1 jso4 jtms jtdo jtrstx nc4 qa12 qa8 qa2 qdpl qbclko qd29 qd22 qd15 qd10 a 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 24 cp4_4 gnd cp4_5 cp4_6 vdd33 cp5_0 cp5_1 cpa_3 vdd33 cpc_4 cpd_6 cpf_0 gnd md8 md17 md25 vdd33 md40 md49 md57 gnd md72 md81 md89 gnd md104 md112 gnd md127 24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 30 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information pin descriptions grouped by function the c-5e np pins are categorized in groups, reflecting interfaces to the chip: clock signals cp interface signals executive processor system interface signals fabric processor interface signals bmu sdram interface signals tlu sram interface signals qmu sram (internal mode) interface signals qmu to q-5 tmc (external mode) interface signals power supply signals test signals no connection pins pins conform to joint electronic devices engineering council (jedec) standards. lvttl and lvpecl specifications c-5e np pins are the following types: low voltage ttl-compatible (lvttl). the c-5e np ? s lvttl pins conform to the jedec jesd8-b specification. low voltage positive emitter coupled logic (lvpecl). all of the signals in the following tables in this chapter denote whether the individual signal is an input (i), output (o), both input and output (i/o), or power (p). in addition, a pu, pd, and nc are used. the pu indicates that an internal resistor will pullup the pad if left unconnected. pd indicates an internal pulldown resistor. nc means the pad is to be left unconnected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 31 motorola general business information C5ENPA1-DS/d rev 03 clock signals table 6 describes the c-5e np clock signals. table 6 clock and reference signals signal name pin # total type i/o signal description sclk* sclkx* * sclk and sclkx must not be ac-coupled. g15 f15 1 1 lvpecl lvpecl i i core clock rate (differential) cclk0 g14 1 lvt tl i pd 1_544mhz_clk (t1) ? ? the frequencies specified for cclk0 - cclk7 allow full flexibility for the c-5e np. it is also possible to use one or more cclk n inputs for other frequencies. contact your motorola representative for more information. cclk1 f14 1 lvt tl i pd 2_048mhz_clk (e1) ? cclk2 e14 1 lvt tl i pd 34_368mhz_clk (e3) ? cclk3 g13 1 lvt tl i pd 44_736mhz_clk (t3) ? cclk4 f13 1 lvt tl i pd 50mhz_clk (100mbit ethernet) ? cclk5 e13 1 lvt tl i pd 106_25mhz_clk (fibre channel) ? cclk6 f12 1 lvt tl i pd 125mhz_clk (gigabit ethernet) ? cclk7 e12 1 lvt tl i pd 155_52mhz_clk (oc-3) ? cpref ? ? if any of the cps are configured for lvpecl operation (oc3) using the pin mode registers, then cpref must be wired to an external reference, as specified in table 38 on page 75. if none of the cps are configured for lvpecl operation, then the cpref pin can be left unconnected. g12 1 lvpecl i pd reference total 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 32 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information cp interface signals the c-5e np ? s 16 cps support various network physical interfaces, providing a serial interface to the phy layer. interfaces are configured via bits in the c-5e np register set. many interfaces are possible by programming the configuration registers. cps can be used individually or in a cluster (four cps) to implement the various interfaces. table 7 provides a quick reference of all the cp pins organized by clusters. there are seven physical i/o pins associated with each cp. all pins are capable of receiving data, with some configurable to be input clocks, output clocks, or data drivers. in addition, pairs of pins can be configured as differential pairs for lvpecl compatibility. in the case of rmii, oc-3, ds1, and ds3, the drivers and receivers at the pin are locally configured to match the relevant phy or framer chip. oc-12 uses the aggregation of four cps (one cluster), while gmii and ten bit interface (tbi) can use either eight cps (four for receive and four for transmit) or four cps that share the transmit and receive functions for non-wire speed applications. during cp aggregation, all 28 pins associated with a cluster are routed to all of the serial data processors (sdps) in that cluster. this allows round-robin usage of portions of the sdps, with each getting access to the necessary i/o pins. the signals for the following cp physical interfaces are included in this section: ds1/t1 framer interface configuration 10/100 ethernet (rmii) configuration gigabit ethernet (gmii) configuration gigabit ethernet and fibre channel tbi configuration sonet oc-3 transceiver interface configuration sonet oc-12 transceiver interface configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 33 motorola general business information C5ENPA1-DS/d rev 03 table 7 cp physical interface signals and pins (grouped by clusters) cp cluster 1 cp cluster 2 cp cluster 3 cp cluster 4 signal pin # signal pin # signal pin # signal pin # cp0_0 aj29 cp4_0 af25 cp8_0 ac21 cpc_0 y28 cp0_1 ah29 cp4_1 ae25 cp8_1 aj20 cpc_1 y27 cp0_2 ag29 cp4_2 ad25 cp8_2 ag20 cpc_2 y26 cp0_3 af29 cp4_3 ac25 cp8_3 af20 cpc_3 y25 cp0_4 ae29 cp4_4 aj24 cp8_4 ad20 cpc_4 y24 cp0_5 ad29 cp4_5 ag24 cp8_5 ac20 cpc_5 y23 cp0_6 ac29 cp4_6 af24 cp8_6 aj19 cpc_6 y22 cp1_0 aj28 cp5_0 ad24 cp9_0 ah19 cpd_0 y21 cp1_1 ag28 cp5_1 ac24 cp9_1 ag19 cpd_1 w29 cp1_2 af28 cp5_2 aj23 cp9_2 af19 cpd_2 w28 cp1_3 ad28 cp5_3 ah23 cp9_3 ae19 cpd_3 w27 cp1_4 ac28 cp5_4 ag23 cp9_4 ad19 cpd_4 w26 cp1_5 aj27 cp5_5 ae23 cp9_5 ac19 cpd_5 w25 cp1_6 ah27 cp5_6 ad23 cp9_6 ab29 cpd_6 w24 cp2_0 ag27 cp6_0 ac23 cpa_0 ab28 cpe_0 w23 cp2_1 ae27 cp6_1 aj22 cpa_1 ab26 cpe_1 w22 cp2_2 ad27 cp6_2 ah22 cpa_2 ab25 cpe_2 w21 cp2_3 ac27 cp6_3 ag22 cpa_3 ab24 cpe_3 v29 cp2_4 aj26 cp6_4 af22 cpa_4 ab22 cpe_4 v28 cp2_5 ah26 cp6_5 ae22 cpa_5 ab21 cpe_5 v26 cp2_6 ag26 cp6_6 ad22 cpa_6 aa29 cpe_6 v25 cp3_0 af26 cp7_0 ac22 cpb_0 aa27 cpf_0 v24 cp3_1 ae26 cp7_1 aj21 cpb_1 aa26 cpf_1 v22 cp3_2 ad26 cp7_2 ah21 cpb_2 aa25 cpf_2 v21 cp3_3 ac26 cp7_3 ag21 cpb_3 aa23 cpf_3 u29 cp3_4 aj25 cp7_4 af21 cpb_4 aa22 cpf_4 u27 cp3_5 ah25 cp7_5 ae21 cpb_5 aa21 cpf_5 u26 cp3_6 ag25 cp7_6 ad21 cpb_6 y29 cpf_6 u25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 34 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information ds1/t1 framer interface configuration table 8 describes the serial framer interface signals. for each cp (0-15), you can implement one serial framer interface. 10/100 ethernet (rmii) configuration table 9 describes the 10/100base-t ethernet reduced media independent interface (rmii) signals. for each cp (0-15), you can implement one 10/100 ethernet interface. table 8 ds1/t1 framer interface signals signal name* pin #? total type i/o label signal description cp n _0 table 7 1 lvt tl o pd tclk transmit clock (1.544mhz) cp n _1 table 7 1 lvt tl i pu rclk receive clock (1.544mhz) cp n _2 table 7 1 lvt tl o pd tdata transmit data cp n _3 table 7 1 lvt tl o pu tframe transmit frame synchronization cp n _4 table 7 1 lvt tl i pd rdata receive data cp n _5 table 7 1 lvt tl i pu rframe receive frame synchronization cp n _6 table 7 1 nc nc pu nc nc total pins 7 * n can be from 0 to 15. see table 7 . ? reference table 7 for pin numbers for the actual cluster(s) you are configuring. table 9 10/100 ethernet signals signal name* pin # total type i/o label signal description cp n _0 table 7 1 lvt tl o pd ref_clk transmit and receive clock (50mhz) cp n _1 table 7 1 lvt tl i pu crs_dv carrier sense (crs)/ receive data valid (rx_dv). crs indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... rx_dv indicates that a receive frame is in progress and the data present on the rxd pins is valid. it is asserted if this signal is a 1 for more than one cycle. cp n _2 table 7 1 lvt tl o pd txd(0) transmit data 0 (first on wire) cp n _3 table 7 1 lvt tl o pu txd(1) transmit data 1 (second on wire) cp n _4 table 7 1 lvt tl i pd rxd(0) receive data 0 (first on wire) cp n _5 table 7 1 lvt tl i pu rxd(1) receive data 1 (second on wire) cp n _6 table 7 1 lvt tl o pu tx_en transmit enable. when asserted, the data on txd is encoded and transmitted on the twisted pair cable. total pins 7 * n can be from 0 to 15. see table 7 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 35 motorola general business information C5ENPA1-DS/d rev 03 gigabit ethernet (gmii) configuration gigabit ethernet media independent interface (gmii) is configured in one of two ways: use one cp cluster when density is more important than wire-speed performance because you can then implement up to four gigabit ethernet ports per c-5e np. use two cp clusters for wire-speed performance and additional processing power. you can implement up to two gigabit ethernet ports per c-5e np. table 10 lists the possible cp cluster combinations you can use and figure 4 shows receive and transmit pin configurations by cluster. table 11 lists the signals and pinouts for gigabit ethernet (gmii). table 10 transmit and receive pin combinations for gigabit ethernet and fibre channel cluster single cluster mode (tbi or gmii) two cluster mode (gmii)* * the two cluster mode column lists typical configurations. any cluster can be set up to either receive or transmit. so you could configure a dual cluster mode where cluster 0 receives and cluster 3 transmits. 0 port 1 tx and rx port 1 tx 1 port 2 tx and rx port 1 rx 2 port 3 tx and rx port 2 tx 3 port 4 tx and rx port 2 rx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 36 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information figure 4 gmii/tbi transmit and receive pin configurations cluster 0 cluster 1 cluster 2 cluster 3 port 1 port 2 port 3 port 4 } } } } tx tx tx tx rx rx rx rx single cluster mode pin configuration port 1 port 2 } tx tx tx tx rx rx rx rx two cluster mode pin configuration nc nc nc nc } nc = not connected cluster 0 cluster 1 cluster 2 cluster 3 table 11 gigabit ethernet (gmii/mii) signals one cluster example signal name* pin # ? total type i/o label signal description cp n _0 table 7 1 lvt tl o pd t_clk gmii transmit clock (125mhz). this clock is used to synchronize the transmit data. cp n _1 table 7 1 lvt tl i pu tclki mii transmit clock. transmit data aligned to this clock input from phy in mii mode. 25 mhz in 100baset, 2.5 in mhz in 10baset cp n _2 table 7 1 lvt tl o pd txd(0) transmit data (byte-wide data, least significant bit) cp n _3 table 7 1 lvt tl o pu txd(1) transmit data cp n _4 table 7 1 lvt tl o pd txd(2) transmit data cp n _5 table 7 1 lvt tl o pu txd(3) transmit data cp n _6 table 7 1 lvt tl o pu tx_en transmit enable. when asserted, the data on txd is encoded and transmitted on the twisted pair cable. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 37 motorola general business information C5ENPA1-DS/d rev 03 cp n+1 _0 table 7 1 nc nc pd nc nc cp n+1 _1 table 7 1 lvt tl i pu col collision. asserted when both rx_dv and tx_en are valid during half duplex operation. cp n+1 _2 table 7 1 lvt tl o pd txd(4) transmit data cp n+1 _3 table 7 1 lvt tl o pu txd(5) transmit data cp n+1 _4 table 7 1 lvt tl o pd txd(6) transmit data cp n+1 _5 table 7 1 lvt tl o pu txd(7) transmit data (byte-wide receive data, most significant bit) cp n+1 _6 table 7 1 lvt tl o pu tx_er transmit error. asserting tx_er when tx_en is a 1 causes transmission of the designated ? bad code ? in lieu of the normal encoded data on the twisted pair data. cp n+2 _0 table 7 1 nc nc pd nc nc cp n+2 _1 table 7 1 lvt tl i pu rclk receive clock (125mhz) cp n+2 _2 table 7 1 lvt tl i pd rxd(0) receive data (byte-wide receive data, least significant bit) cp n+2 _3 table 7 1 lvt tl i pu rxd(1) receive data cp n+2 _4 table 7 1 lvt tl i pd rxd(2) receive data cp n+2 _5 table 7 1 lvt tl i pu rxd(3) receive data cp n+2 _6 table 7 1 lvt tl i pu rx_dv receive data valid. indicates that there is a receive frame in progress and that the data present on the rxd signals is valid. cp n+3 _0 table 7 1 nc nc pd nc nc cp n+3 _1 table 7 1 lvt tl i pu crs carrier sense. indicates traffic is on the link. crs is asserted when a non-idle condition is detected on the receive data stream. crs is deasserted when an end of frame or idle condition is detected. cp n+3 _2 table 7 1 lvt tl i pd rxd(4) receive data cp n+3 _3 table 7 1 lvt tl i pu rxd(5) receive data cp n+3 _4 table 7 1 lvt tl i pd rxd(6) receive data cp n+3 _5 table 7 1 lvt tl i pu rxd(7) receive data (most significant bit) cp n+3 _6 table 7 1 lvt tl i pu rx_er receive error detected. indicates that there has been an error received in the receive frame. total pins 28 * n can be 0, 4, 8, or 12. ? reference table 7 for pin numbers for the actual cluster(s) you are configuring. table 11 gigabit ethernet (gmii/mii) signals one cluster example (continued) signal name* pin # ? total type i/o label signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 38 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information gigabit ethernet and fibre channel tbi configuration 1000base-t gigabit ethernet and fibre channel tbi is implemented in much the same way as gigabit ethernet (gmii). table 10 shows the possible cp pin combinations you can use and figure 4 shows receive and transmit pin configurations by cluster. table 12 shows the signals and pinouts for a single cluster for gigabit ethernet and fibre channel tbi. the unused pins for the two cluster configurations should be wired down using a resistor. table 12 gigabit ethernet and fibre channel tbi signals example signal name* pin # ? total type i/o label signal description cp n _0 table 7 1 lvt tl o pd tclk transmit clock (125mhz). this clock is used to synchronize the transmit data. cp n _1 table 7 1 nc nc pu nc nc cp n _2 table 7 1 lvt tl o pd txd(9) transmit data (ten bits wide, last on wire) cp n _3 table 7 1 lvt tl o pu txd(8) transmit data cp n _4 table 7 1 lvt tl o pd txd(7) transmit data cp n _5 table 7 1 lvt tl o pu txd(6) transmit data cp n _6 table 7 1 lvt tl o pu txd(1) transmit data cp n+1 _0 table 7 1 nc nc pd nc nc cp n+1 _1 table 7 1 nc nc pu nc nc cp n+1 _2 table 7 1 lvt tl o pd txd(5) transmit data cp n+1 _3 table 7 1 lvt tl o pu txd(4) transmit data cp n+1 _4 table 7 1 lvt tl o pd txd(3) transmit data cp n+1 _5 table 7 1 lvt tl o pu txd(2) transmit data cp n+1 _6 table 7 1 lvt tl o pu txd(0) transmit data (ten bits wide, first on wire) cp n+2 _0 table 7 1 nc nc pd nc nc cp n+2 _1 table 7 1 lvt tl i pu rclk receive clock (62.5 mhz) cp n+2 _2 table 7 1 lvt tl i pd rxd(9) receive data (ten bits wide, last on wire) cp n+2 _3 table 7 1 lvt tl i pu rxd(8) receive data cp n+2 _4 table 7 1 lvt tl i pd rxd(7) receive data cp n+2 _5 table 7 1 lvt tl i pu rxd(6) receive data cp n+2 _6 table 7 1 lvt tl i pu rxd(1) receive data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 39 motorola general business information C5ENPA1-DS/d rev 03 sonet oc-3 transceiver interface configuration table 13 describes the sonet optical carrier (oc) 3 transceiver interface signals. for each cp (0-15), you can implement a single oc-3 interface. cp n+3 _0 table 7 1 nc nc pd nc nc cp n+3 _1 table 7 1 lvt tl i pu rclkn receive clock inverted cp n+3 _2 table 7 1 lvt tl i pd rxd(5) receive data cp n+3 _3 table 7 1 lvt tl i pu rxd(4) receive data cp n+3 _4 table 7 1 lvt tl i pd rxd(3) receive data cp n+3 _5 table 7 1 lvt tl i pu rxd(2) receive data cp n+3 _6 table 7 1 lvt tl i pu rxd(0) receive data (ten bits wide, first on wire) total pins 28 * n can be 0, 4, 8, or 12 ? reference table 7 for pin numbers for the actual cluster(s) you are configuring. table 12 gigabit ethernet and fibre channel tbi signals example (continued) signal name* pin # ? total type i/o label signal description table 13 oc-3 signals signal name* pin # ? total type i/o label signal description cp n _0 table 7 1 lvpecl i pd rclk_h receive clock noninverted side of pair (155.52mhz) cp n _1 table 7 1 lvpecl i pu rclk_l receive clock inverted side of pair (155.52mhz) cp n _2 table 7 1 lvpecl o pd txd_h transmit data noninverted side of pair cp n _3 table 7 1 lvpecl i pu txd_l transmit data inverted side of pair cp n _4 table 7 1 lvpecl i pd rxd_h receive data noninverted side of pair cp n _5 table 7 1 lvpecl i pu rxd_l receive data inverted side of pair cp n _6 table 7 1 lvpecl i pu signal_det a light level above a certain threshold is present at the optical receiver - single ended lvpecl. total pins 7 * n can be from 0 to 15. ? reference table 7 for pin numbers for the actual cluster(s) you are configuring. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 40 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information sonet oc-12 transceiver interface configuration sonet optical carrier (oc) 12 is implemented by using one cluster of cps. at any time, a cp within a cluster spends half its time performing receive functions, and the other half performing transmit functions. table 14 shows a cp cluster configured for one oc-12 interface. table 14 oc-12 signals example signal name* pin # ? total type i/o label signal description cp n _0 table 7 1 lvt tl o pd tclk deskewed transmit clock (77.76mhz). this clock is used to synchronize the transmit data. cp n _1 table 7 1 lvt tl i pu tclki transceiver transmit clock. this clock sets the frequency of the transmit data and is typically sourced by the phy chip. cp n _2 table 7 1 lvt tl o pd txd(0) transmit data (byte-wide data, least significant bit) cp n _3 table 7 1 lvt tl o pu txd(1) transmit data cp n _4 table 7 1 lvt tl o pd txd(2) transmit data cp n _5 table 7 1 lvt tl o pu txd(3) transmit data cp n _6 table 7 1 lvt tl o pu 00f out of frame cp n+1 _0 table 7 1 nc nc pd nc nc cp n+1 _1 table 7 1 nc nc pu nc nc cp n+1 _2 table 7 1 lvt tl o pd txd(4) transmit data cp n+1 _3 table 7 1 lvt tl o pu txd(5) transmit data cp n+1 _4 table 7 1 lvt tl o pd txd(6) transmit data cp n+1 _5 table 7 1 lvt tl o pu txd(7) transmit data (byte-wide data, most significant bit) cp n+1 _6 table 7 1 nc nc pu nc nc cp n+2 _0 table 7 1 nc nc pd nc nc cp n+2 _1 table 7 1 lvt tl i pu rclk receive clock (77.76mhz) cp n+2 _2 table 7 1 lvt tl i pd rxd(0) receive data (byte-wide receive data, least significant bit) cp n+2 _3 table 7 1 lvt tl i pu rxd(1) receive data cp n+2 _4 table 7 1 lvt tl i pd rxd(2) receive data cp n+2 _5 table 7 1 lvt tl i pu rxd(3) receive data cp n+2 _6 table 7 1 lvt tl i pu fp frame synchronization pulse. this is valid during the third a2 of the receive sonet frame. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 41 motorola general business information C5ENPA1-DS/d rev 03 cp n+3 _0 table 7 1 nc nc pd nc nc cp n+3 _1 table 7 1 nc nc pu nc nc cp n+3 _2 table 7 1 lvt tl i pd rxd(4) receive data cp n+3 _3 table 7 1 lvt tl i pu rxd(5) receive data cp n+3 _4 table 7 1 lvt tl i pd rxd(6) receive data cp n+3 _5 table 7 1 lvt tl i pu rxd(7) receive data (most significant bit) cp n+3 _6 table 7 1 nc nc pu nc nc total pins 28 * n can be 0, 4, 8, or 12 ? reference table 7 for pin numbers for a different cluster. table 14 oc-12 signals example (continued) signal name* pin # ? total type i/o label signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 42 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information executive processor system interface signals the xp ? s system interface manages the supervisory controls for the network interfaces, as well as the set of pins that provide interfaces to other components in the system that are not memories or network interfaces. it is also the primary interface used for initializing the c-5e np after reset. the xp signals include pci signals, serial interface signals, and prom interface signals. pci signals the pci can be configured to support a 32bit pci capable of operating at either 33mhz or 66mhz. the pci is fully compliant with pci specification revision 2.1. table 15 describes the pci signals. table 15 pci signals signal name pin # total type i/o signal description pad0 - pad31 aj5, aj4, aj3, aj2, aj1, ah5, ah4, ah3, ah1, ag5, ag4, ag3, ag2, ag1, af5, af4, af2, af1, ae5, ae4, ae3, ae1, ad5, ad4, ad3, ad2, ad1, ac5, ac4, ac3, ac2, ac1 32 pci i/o multiplexed address/data bus. these signals are multiplexed address and data bits. the c-5e np receives addresses as target and drives addresses as master. it drives the data and receives read data as master. pcbex0 - pcbex3 ab6, ab5, ab4, ab2 4 pci i/o command byte enables. these signals are multiplexed command and byte enabled signals. the c-5e np receives byte enables as target and drives byte enables as master. ppar ab1 1 pci i/o parity. this signal carries even parity for ad and cbe# pins. it has the same receive and drive characteristics as the address and data bus, except that it is one pci cycle later. pframex w9 1 pci i/o cycle frame ptrdyx ab9 1 pci i/o target ready for data transfer pirdyx ab8 1 pci i/o initiator ready for data transfer pstopx aa5 1 pci i/o target transaction stop request pdevselx aa4 1 pci i/o target device selected pperrx aa3 1 pci i/o bus parity error pserrx aa1 1 pci i/o system error pclk aa7 1 i pd i bus clock prstx aa8 1 pci i bus reset preqx aa9 1 pci o initiator bus request (arbitration) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 43 motorola general business information C5ENPA1-DS/d rev 03 serial interface signals the serial interface is a bidirectional two-wire serial bus. it can use one of the following formats: an 8bit data format followed by an acknowledge bit, which supports transfers at up to 400kbps (low speed). a 16bit ieee 802.3 mdio data format with 10bits of addressing, which supports transfers up to 25mhz (high speed). the signals and pins are identical for both the high and low speed protocols. which of the two data rates used is selected by the state of the prom interface ? s spld signal that is asserted while the prom interface is idle. when spld is asserted hi the low speed serial bus protocol is selected and when spld is asserted low the mdio protocol is selected. the bus only supports a single master hierarchy that can operate as either a receiver or a transmitter. both sida and sicl are bidirectional lines that are connected, through a pull-up resistor, to a positive supply voltage. when the bus is free, both lines are high. the output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-and function required for its arbitration mechanism. pgntx y7 1 i pd i initiator bus grant (arbitration) pidsel y8 1 pci i initialization device select pinta y9 1 pci o interrupt total pins 50 table 15 pci signals (continued) signal name pin # total type i/o signal description table 16 serial interface signals signal name pin # total type i/o signal description sicl y5 1 lvt tl i pd /o serial clock line sida y6 1 lvt tl i pd /o serial data line total pins 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 44 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information prom interface signals the prom interface is a low speed i/o port that allows the c-5e np to communicate through external logic to prom. the prom clock is 1 / 2 to 1 / 16 the core clock rate. the maximum prom size addressable is 4mbytes, and must use a ? by 16 ? part. the prom signals are listed in table 17 . figure 5 shows the connections between the prom interface and external board logic. the application is required to provide an external shift register with parallel-in and parallel-out capabilities, and a parallel load register. both devices should be positive-edge-triggered and perform a parallel load whenever spld is asserted. when spld is deasserted the shift register shifts. table 17 prom interface signals signal name pin # total type i/o signal description spdo y1 1 lvt tl o serial data out spdi y2 1 lvt tl i pd serial data in spld y3 1 lvt tl o when load is asserted on a positive clock edge, the external logic performs a parallel load. on each positive clock edge when load is de-asserted, the shift registers shift. when the prom interface is idle: if spld is asserted hi it indicates low speed serial protocol, if asserted low it indicates mdio serial protocol. spck y4 1 lvt tl o clock total pins 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 45 motorola general business information C5ENPA1-DS/d rev 03 figure 5 prom interface diagram the prom interface operates in the following manner (note that two accesses are piplined together to execute one 32-bit fetch). the steps are shown in figure 6 . 1 the prom_addr is loaded into the network processor internal shift register. 2 the prom_addr is shifted into the external shift register for 22 spclk cycles. 3 spld is asserted for one spclk cycle, loading the prom_addr into the external presentation register. 4 spld is deasserted for 22 spclk cycles. the prom presents the first 16bit prom_data. at the same time, the next prom_addr is shifted into the external shift register. 5 spld is asserted for one spclk cycle, loading the prom_addr into the external presentation register and the first prom_data into the external shift register. 6 spld is deasserted for 22 spclk cycles, shifting the first prom_data into the network processor internal shift register. 7 spld is asserted for one spclk cycle, loading the first prom_data into the network processor prom_return_data register and the second prom_data into the external shift register. external logic prom_addr<21:1> 15 15 16 prom _h_word c-5e network processor prom clock gen. 31 21 21 6 1 0 prom _return_data prom sequencer 21 0 0 ce spclk spld spdo spdi internal shift register prom_addr<21:1> ce prom _lo_word 21 6 0 21 0 21 1 prom prom_data 16 external shift register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 46 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information 8 spld is deasserted for 22 spclk cycles, shifting the second prom_data into the network processor internal shift register. 9 spld is asserted for one spclk cycle, loading the second prom_data into the network processor prom_return_data register. figure 6 prom interface timing outline spclk spld 12 456789 11 10 12 13 14 15 16 17 18 19 20 21 22 23 1234567891011 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 21 22 23 1 2 3 4 5 6 7 x a 20 a 19 a 18 spdto a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce the prom_addr is loaded into the c-5's internal shift register. the prom_addr is shifted into the external shift register. (spclk rising edge used for shifting) the prom_addr is loaded into the external presentation register. the prom_data is presenting. the prom_data is loaded into the external shift register. the prom_data is shifted into the c-5's internal shift register. the prom_data is loaded into the c-5's internal prom_return_data register. spdti x d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xxxxxx xp prom interface outline xp prom interface detail spld spdto spdti ?` ?` a1 a2 ?` ?` ` a3 a4 a5 d1 d2 d3 d1 d2 a1 a2 a3 a4 1 2 3 4 5 6 7 8 9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 47 motorola general business information C5ENPA1-DS/d rev 03 general system interface signal table 18 provides the signal for the executive processor reset power status and i/o clock. the c-5e np can be powered up with the xp either running or with the xp in reset mode similar to the cps. when the xp remains in reset mode, an external host can be used to control the initialization of the c-5e np. table 18 general system interface signal signal name pin # total type i/o signal description xpuhot w8 1 lvt tl i pd sample at power on reset determines if the xp risc core is held in reset. low equals reset and high equals active. during normal operation, this is an external interrupt. total pins 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 48 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information fabric processor interface signals the fp has logical signal interfaces: a receive data interface and a transmit data interface, each with its own control, data, and clock signals. the interface has the following characteristic: the interface clocks frxclk and ftxclk can have a different frequency from the core c-5e np clock frequency. the fp supports a fabric interface frequency from 10mhz to 125mhz. frxclk and ftxclk can be independent of each other; typically they have the same frequency, but are allowed to be skewed relative to each other. each data bus can be configured for widths of 8 (data bits 7:0 are used), 16 (bits 15:0), or 32 (bits 31:0). in 8bit mode, data bits 31:8 are unused. in 16bit mode, data bits 31:16 are unused. the following tables list the fabric interface pin mappings: utopia1, utopia2, utopia3 atm mode mappings are listed in table 20 utopia1, utopia2, utopia3 phy mode mappings are listed in table 21 prizma mode mappings are listed in table 22 (prizma protocol is a subset of utopia3 phy) table 19 fabric interface signals signal name pin # total type i/o signal description fin0 - fin31 ae12, ad12, ac12, aj11, ah11, ag11,af11, ae11, ad11, ac11, aj10, ag10, af10, ad10, ac10, aj9, ah9, ag9, af9, ae9, ad9, ac9, aj8, ah8, ag8, af8, ae8, ad8, ac8, aj7, ah7, ag7 32 lvt tl i pd fabric data bus in fout0 - fout31 aj18, ah18, ag18, ae18, ad18, ac18, aj17, ah17, af17, ae17, ad17, ac17, aj16, ah16, ag16, af16, ae16, ad16, ac16, aj15, ag15, af15, ad15, ac15, aj14, ah14, ag14, af14, ae14, ad14, ac14, aj13 32 lvt tl o fabric data bus out frxclk ac6 1 lvt tl i pd receive clock ftxclk ag12 1 lvt tl i pd transmit clock frxctl0 - frxctl6 ae7, ad7, ac7, aj6, ag6, af6, ad6 7 lvt tl i pd , o receive control signals ftxctl0 - ftxctl6 ah13, af13, ae13, ad13, ac13, aj12, ah12 7 lvt tl i pd , o transmit control signals total pins 80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 49 motorola general business information C5ENPA1-DS/d rev 03 power x(csix-l0) mode mappings are listed in table 23 csix-l1 mode mappings are listed in table 24 when configuring two c-5e network processors back-to-back using the fabric port, set up the transmit side of each c-5e network processor in utopia atm mode and the receive side of each c-5e network processor in utopia phy mode. table 20 utopia1*, 2*, 3 atm mode, c-5e network processor to fabric interface pin mapping receive signals transmit signals c-5e network processor i/o utopia note c-5e network processor i/o utopia note frxctl0 output rxenb* pullup or no connection ftxctl0 output txenb* pullup or no connection frxctl1 input rxclav ftxctl1 input txclav frxctl2 input rxsoc ftxctl2 output txsoc frxctl3 input n/a ftxctl3 input n/a frxctl4 input n/a ftxctl4 input n/a frxctl5 input n/a ftxctl5 input n/a frxctl6 input rxprty ftxctl6 output txprty * cell size must be 4byte aligned. both rxenb and txenb are active low. table 21 utopia1*, 2*, 3 phy mode, c-5e network processor to fabric interface pin mapping receive signals transmit signals c-5e network processor i/o utopia note c-5e network processor i/o utopia note frxctl0 input txenb* pullup ftxctl0 input rxenb* pullup frxctl1 output txclav no connection ftxctl1 output rxclav no connection frxctl2 input txsoc ftxctl2 output rxsoc frxctl3 input n/a ftxctl3 input n/a frxctl4 input n/a ftxctl4 input n/a frxctl5 input n/a ftxctl5 input n/a frxctl6 input txprty ftxctl6 output rxprty * cell size must be 4byte aligned. both txenb and rxenb are active low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 50 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information for the csix-l1 mode, vddf= 2.5v. table 22 prizma mode, c-5e network processor to fabric interface pin mapping receive signals transmit signals c-5e network processor i/o utopia note c-5e network processor i/o utopia note frxctl0 input txenb* not connected to fabric. ftxctl0 input rxenb* not connected to fabric. frxctl1 output txclav no connection ftxctl1 output rxclav no connection frxctl2 input txsop ftxctl2 output rxsop frxctl3 input n/a ftxctl3 input n/a frxctl4 input n/a ftxctl4 input n/a frxctl5 input n/a ftxctl5 input n/a frxctl6 input txprty optional ftxctl6 output rxprty optional * both txenb and rxenb are active low. table 23 power x(csix-l0) mode, c-5e network processor to fabric interface pin mapping receive signals transmit signals c-5e network processor i/o power x note c-5e network processor i/o power x note frxctl0 input rxctrl[0] ftxctl0 output txctrl[0] frxctl1 input rxctrl[1] ftxctl1 output txctrl[1] frxctl2 input rxctrl[2] ftxctl2 output txctrl[2] frxctl3 input rxprty[3] ftxctl3 output txprty[3] frxctl4 input rxprty[2] ftxctl4 output txprty[2] frxctl5 input rxprty[1] ftxctl5 output txprty[1] frxctl6 input rxprty[0] ftxctl6 output txprty[0] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 51 motorola general business information C5ENPA1-DS/d rev 03 table 24 csix-l1 mode, c-5e network to fabric interface pin mapping fprx signals fptx signals c-5e np i/o csix-l1 note c-5e np i/o csix-l1 note frxctl0 input n/a ftxctl0 input n/a frxctl1 input n/a ftxctl1 input n/a frxctl2 input txsof ftxctl2 output rxsof frxctl3 input n/a ftxctl3 input n/a frxctl4 input n/a ftxctl4 input n/a frxctl5 input n/a ftxctl5 input n/a frxctl6 input txprty ftxctl6 output rxprty f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 52 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information bmu sdram interface signals the bmu and sdram interface signals are described in table 25 . the bmu is designed to support sdram devices with 12 address lines. all 139 data lines and all 12 address lines must be connected to the sdram in order for the bmu to be able to read and write external sdram properly. table 25 bmu sdram interface signals signal name pin # total type i/o signal description md0 - md129 u23, u22, u21, t29, t28, t27, t26, t25, t24, t23, t22, t21, r29, r28, r27, r26, r25, r24, r23, r22, r21, p29, p28, p26, p25, p24, p22, p21, n29, n27, n26, n25, n23, n22, n21, m29, m28, m27, m26, m25, m24, m23, m22, m21, l29, l28, l27, l26, l25, l24, l23, l22, l21, k29, k28, k26, k25, k24, k22, k21, j29, j27, j26, j25, j23, j22, j21, h29, h28, h27, h26, h25, h24, h23, h22, h21, g29, g28, g27, g26, g25, g24, g23, g22, g21, f29, f28, f26, f25, f24, f22, f21, e29, e27, e26, e25, e23, e22, e21, d29, d28, d27, d26, d25, d24, d23, d22, d21, c29, c28, c26, c25, c24, c22, c21, b29, b27, b26, b25, b23, b22, b21, a29, a28, a27, a26, a25, a24, a23, a22 130 lvt tl i pd /o data lines in mdecc0 - mdecc8 e19, f19, g19, a20, c20, d20, f20, g20, a21 9 lvt tl i pd /o stored as data, ecc bits ma0 - ma11 b16, c16, d16, e16, f16, g16, a17, b17, d17, e17, f17, g17 12 lvt tl o pd address outputs: a0-a11 are sampled during the active command and read/write to select one location out of the memory array in the respective bank. the address inputs also provide the op-code during a load mode register command mba0 - mba1 e18, c18 2 lvt tl o pd bank address outputs: ba0 and ba1 define which bank the active, read, write or precharge command is being applied mcasx d19 1 lvt tl o pd command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. note: mcsx is considered part of the command code. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 53 motorola general business information C5ENPA1-DS/d rev 03 mrasx c19 1 lvt tl o pd command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. mcsx is considered part of the command code. mwex b19 1 lvt tl o pd command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. mcsx is considered part of the command code. mcsx a19 1 lvt tl o pd chip select: mcsx enables (registered low) and disables (registered high) the command decoder. all commands are masked when mcsx is registered high. mcsx provides the external bank selection on systems with multiple banks. mcsx is considered part of the command code. mdqm mdqml g18 f18 1 1 lvt tl lvt tl o pd o pd input/output mask: mdqm is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when mdqm is sampled high during a write cycle. the output buffers are placed in a high z state (two-clock latency) when mdqm is sampled high during the read cycle. note: mdqml is an identical copy of mdqm used to drive the loading on sdram configurations with 2 dqm pins. mdclk b18 1 lvt tl i pd clock: mdclk is driven by the system clock. all sdram input signals are sampled on the positive edge of the mdclk. mdclk also increments the internal burst counter and controls the output registers. total pins 160 table 25 bmu sdram interface signals (continued) signal name pin # total type i/o signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 54 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information tlu sram interface signals the tlu sram interface supports up to 128mbytes of sram at frequencies to 133mhz using lvttl signaling levels (in single bank-mode only) and sram technologies up to 64mbits. the tlu sram interface signals are described in table 26 . table 26 tlu sram interface signals signal name pin # total type i/o signal description td0 - td63 g6, g7, g8, g9, g10, h1, h2, h3, h4, h5, h6, h7, h8, h9, j1, j3, j4, j5, j7, j8, j9, k1, k2, k4, k5, k6, k8, k9, l1, l2, l3, l4, l5, l6, l7, l8, l9, m1, m2, m3, m4, m5, m6, m7, m8, m9, n1, n3, n4, n5, n7, n8, n9, p1, p2, p4, p5, p6, p8, p9, r6, r7, r8, r9 64 lvt tl i pd /o tlu memory data ta0 - ta21 t1, u1, u3, u4, u5, u7, u8, u9, v1, v2, v4, v5, v6, v8, v9, w1, w2, w3, w4, w5, w6, w7 22 lvt tl o pd tlu memory address tpar0 - tpar3 r2, r3, r4, r5 4 lvt tl i pd /o word data parity (i.e. tpar0 across td15:0) tce0x - tce3x t2, t3, t4, t5 4 lvt tl o pd tlu memory chip enable twe0x - twe3x t6, t7, t8, t9 4 lvt tl o pd tlu memory write enable tclki r1 1 lvt tl i pd tlu clock input total pins 99 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 55 motorola general business information C5ENPA1-DS/d rev 03 qmu sram (internal mode) interface signals the qmu signals are described in table 27 . table 27 qmu sram (internal mode) interface signals signal name pin # total type i/o signal description qa0 - qa16 c8, b8, a8, f9, e9, d9, c9, b9, a9, f10, d10, c10, a10, g11, f11, e11, d11 17 lvt tl o address [16:0] qd0 - qd31 g1, f1, e1, d1, c1, b1, g2, f2, d2, c2, a2, g3, e3, d3, b3, a3, g4, f4, e4, d4, c4, b4, a4, g5, f5, e5, d5, c5, b5, a5, f6, d6 32 lvt tl i pd /o data qdqpar c11 1 lvt tl i pd nc qardy e8 1 lvt tl i pd nc qnqrdy d8 1 lvt tl i pd nc qwex c6 1 lvt tl o write enable qbclko a6 1 lvt tl o nc qbclki e7 1 lvt tl i pd nc qaclko d7 1 lvt tl o nc qaclki b7 1 lvt tl i pd input clock qdpl a7 1 lvt tl i pd /o data parity low qdph f8 1 lvt tl i pd /o data parity high total pins 59 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 56 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information qmu to q-5 tmc (external mode) interface signals the qmu to q-5 traffic management coprocessor (tmc) signals are described in table 28 . table 28 qmu to q-5 (external mode) interface signals signal name pin # total type i/o signal description qa0 - qa15 c8, b8, a8, f9, e9, d9, c9, b9, a9, f10, d10, c10, a10, g11, f11, e11 16 lvt tl o enqueue data [8:23] qa16 d11 1 lvt tl o enqueue parity qd0 - qd23 g1, f1, e1, d1, c1, b1, g2, f2, d2, c2, a2, g3, e3, d3, b3, a3, g4, f4, e4, d4, c4, b4, a4, g5 24 lvt tl i pd dequeue data [0:23] qd24 - qd31 f5, e5, d5, c5, b5, a5, f6, d6 8 lvt tl i pd enqueue data [0:7] qdqpar c11 1 lvt tl i pd dequeue parity qardy e8 1 lvt tl i pd dequeue ack ready qnqrdy d8 1 lvt tl i pd enqueue ready qwex c6 1 lvt tl o dequeue ready qbclko a6 1 lvt tl o output clockb qbclki e7 1 lvt tl i pd input clockb qaclko d7 1 lvt tl o output clocka qaclki b7 1 lvt tl i pd input clocka qdpl a7 1 lvt tl o dequeue ack [0] qdph f8 1 lvt tl o dequeue ack [1] total pins 59 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions grouped by function 57 motorola general business information C5ENPA1-DS/d rev 03 power supply signals power supply, and ground signals are described in table 29 . table 29 power supply signals signal name pin # total type signal description vdd j13, j15, j17, j19, k12, k14, k16, k18, l11, l13, l15, l17, l19, m12, m14, m16, m18, n13, n15, n17, n19, p12, p14, p16, p18, r11, r13, r15, r17, r19, t12, t14, t16, t18, u11, u13, u15, u17, u19, v12, v14, v16, v18, w11, w13, w15, w17, w19, y12, y14, y16, y18, aa11, aa13, aa15, aa17, aa19, 57 p core supply voltage (1.2v input) vdd33 b20, b28, c13, c17, c23, e15, f23, f27, h12, h14, h16, h18, h20, j28, k20, k23, m20, n24, p20, p27, t20, u28, v20, v23, y20, aa6, aa24, ab3, ab10, ab18, ab20, ab27, ae24, af3, af27, ah2, ah20, ah28 38 p i/o supply voltage (3.3v input) gnd b6, b15, b24, c3, c27, d12, d18, e2, e6, e10, e20, e24, e28, h11, h13, h15, h17, h19, j6, j10, j12, j14, j16, j18, j20, j24, k3, k11, k13, k15, k17, k19, k27, l10, l12, l14, l16, l18, l20, m11, m13, m15, m17, m19, n2, n10, n12, n14, n16, n18, n20, n28, p7, p11, p13, p15, p17, p19, p23, r10, r12, r14, r16, r18, r20, t11, t13, t15, t17, t19, u6, u10, u12, u14, u16, u18, u20, u24, v3, v11, v13, v15, v17, v19, v27, w10, w12, w14, w16, w18, w20, y11, y13, y15, y17, y19, aa2, aa10, aa12, aa14, aa16, aa18, aa20, aa28, ab7, ab11, ab13, ab15, ab17, ab19, ab23, ae2, ae10, ae20, ae28, af7, af12, af18, af23, ah6, ah15, ah24 122 p ground vddf ab12, ab14, ab16, ae6, ae15, ag13, ag17, ah10 8 p fabric i/o supply (3.3 or 2.5v) vddt b2, b10, c7, f3, f7, h10, j2, j11, k7, k10, m10, n6, n11, p3, p10, t10, u2, v7, v10, y10 20 p tlu and qmu i/o supply (3.3v) total pins 245 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 58 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information test signals test signals are described in table 30 . during jtag, sclk and sclkx must remain as differential inputs. no connection pins no connection pins are listed in table 31 . table 30 miscellaneous test signals for jtag, scan, and internal test routines signal name pin # total type i/o signal description jtck c15 1 lvt tl i pd test clock jtms a14 1 lvt tl i pd test mode select. high selects modes as defined in the ieee 1149.1 jtag specification. jtrstx ? a12 1 lvt tl i pd test reset (low active) jtdi ? b14 1 lvt tl i pd test data in jtdo a13 1 lvt tl o test data out jhighz b13 1 lvt tl i pd turns off all output drivers when high jclkbyp c14 1 lvt tl i pd 1x or 2x clock mode select. low selects 1x, high selects 2x. jse d15 1 lvt tl i pd scan enable. high enables scan test. js00-js05 d14, a16, d13, c12, a15, b12 6 lvt tl o scan out pins total pins 14 table 31 no connection pins signal name pin # total type i/o signal description nc3 - nc5 b11, a11, a18 3 nc i pd /o reserved for future functionality total pins 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signals grouped by pin number 59 motorola general business information C5ENPA1-DS/d rev 03 signals grouped by pin number the c-5e np signals are listed by pin number in table 32 . table 32 signals listed by pin number pin function pin function pin function pin function a 1-29 a1 not present a9 qa8 a17 ma6 a25 md126 a2 qd10 a10 qa12 a18 nc5 a26 md125 a3 qd15 a11 nc4 a19 mcsx a27 md124 a4 qd22 a12 jtrstx a20 mdecc3 a28 md123 a5 qd29 a13 jtdo a21 mdecc8 a29 md122 a6 qbclko a14 jtms a22 md129 a7 qdpl a15 jso4 a23 md128 a8 qa2 a16 jso1 a24 md127 b 1-29 b1 qd5 b9 qa7 b17 ma7 b25 md118 b2 vddt b10 vddt b18 mdclk b26 md117 b3 qd14 b11 nc3 b19 mwex b27 md116 b4 qd21 b12 jso5 b20 vdd33 b28 vdd33 b5 qd28 b13 jhighz b21 md121 b29 md115 b6 gnd b14 jtdi b22 md120 b7 qaclki b15 gnd b23 md119 b8 qa1 b16 ma0 b24 gnd c 1-29 c1 qd4 c9 qa6 c17 vdd33 c25 md111 c2 qd9 c10 qa11 c18 mba1 c26 md110 c3 gnd c11 qdqpar c19 mrasx c27 gnd c4 qd20 c12 jso3 c20 mdecc4 c28 md109 c5 qd27 c13 vdd33 c21 md114 c29 md108 c6 qwex c14 jclkbyp c22 md113 c7 vddt c15 jtck c23 vdd33 c8 qa0 c16 ma1 c24 md112 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 60 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information d 1-29 d1 qd3 d9 qa5 d17 ma8 d25 md103 d2 qd8 d10 qa10 d18 gnd d26 md102 d3 qd13 d11 qa16 d19 mcasx d27 md101 d4 qd19 d12 gnd d20 mdecc5 d28 md100 d5 qd26 d13 jso2 d21 md107 d29 md99 d6 qd31 d14 jso0 d22 md106 d7 qaclko d15 jse d23 md105 d8 qnqrdy d16 ma2 d24 md104 e 1-29 e1 qd2 e9 qa4 e17 ma9 e25 md95 e2 gnd e10 gnd e18 mba0 e26 md94 e3 qd12 e11 qa15 e19 mdecc0 e27 md93 e4 qd18 e12 cclk7 e20 gnd e28 gnd e5 qd25 e13 cclk5 e21 md98 e29 md92 e6 gnd e14 cclk2 e22 md97 e7 qbclki e15 vdd33 e23 md96 e8 qardy e16 ma3 e24 gnd f 1-29 f1 qd1 f9 qa3 f17 ma10 f25 md88 f2 qd7 f10 qa9 f18 mdqml f26 md87 f3 vddt f11 qa14 f19 mdecc1 f27 vdd33 f4 qd17 f12 cclk6 f20 mdecc6 f28 md86 f5 qd24 f13 cclk4 f21 md91 f29 md85 f6 qd30 f14 cclk1 f22 md90 f7 vddt f15 sclkx f23 vdd33 f8 qdph f16 ma4 f24 md89 table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signals grouped by pin number 61 motorola general business information C5ENPA1-DS/d rev 03 g 1-29 g1 qd0 g9 td3 g17 ma11 g25 md80 g2 qd6 g10 td4 g18 mdqm g26 md79 g3 qd11 g11 qa13 g19 mdecc2 g27 md78 g4 qd16 g12 cpref g20 mdecc7 g28 md77 g5 qd23 g13 cclk3 g21 md84 g29 md76 g6 td0 g14 cclk0 g22 md83 g7 td1 g15 sclk g23 md82 g8 td2 g16 ma5 g24 md81 h 1-29 h1 td5 h9 td13 h17 gnd h25 md71 h2 td6 h10 vddt h18 vdd33 h26 md70 h3 td7 h11 gnd h19 gnd h27 md69 h4 td8 h12 vdd33 h20 vdd33 h28 md68 h5 td9 h13 gnd h21 md75 h29 md67 h6 td10 h14 vdd33 h22 md74 h7 td11 h15 gnd h23 md73 h8 td12 h16 vdd33 h24 md72 j 1-29 j1 td14 j9 td20 j17 vdd j25 md63 j2 vddt j10 gnd j18 gnd j26 md62 j3 td15 j11 vddt j19 vdd j27 md61 j4 td16 j12 gnd j20 gnd j28 vdd33 j5 td17 j13 vdd j21 md66 j29 md60 j6 gnd j14 gnd j22 md65 j7 td18 j15 vdd j23 md64 j8 td19 j16 gnd j24 gnd table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 62 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information k 1-29 k1 td21 k9 td27 k17 gnd k25 md56 k2 td22 k10 vddt k18 vdd k26 md55 k3 gnd k11 gnd k19 gnd k27 gnd k4 td23 k12 vdd k20 vdd33 k28 md54 k5 td24 k13 gnd k21 md59 k29 md53 k6 td25 k14 vdd k22 md58 k7 vddt k15 gnd k23 vdd33 k8 td26 k16 vdd k24 md57 l 1-29 l1 td28 l9 td36 l17 vdd l25 md48 l2 td29 l10 gnd l18 gnd l26 md47 l3 td30 l11 vdd l19 vdd l27 md46 l4 td31 l12 gnd l20 gnd l28 md45 l5 td32 l13 vdd l21 md52 l29 md44 l6 td33 l14 gnd l22 md51 l7 td34 l15 vdd l23 md50 l8 td35 l16 gnd l24 md49 m 1-29 m1 td37 m9 td45 m17 gnd m25 md39 m2 td38 m10 vddt m18 vdd m26 md38 m3 td39 m11 gnd m19 gnd m27 md37 m4 td40 m12 vdd m20 vdd33 m28 md36 m5 td41 m13 gnd m21 md43 m29 md35 m6 td42 m14 vdd m22 md42 m7 td43 m15 gnd m23 md41 m8 td44 m16 vdd m24 md40 table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signals grouped by pin number 63 motorola general business information C5ENPA1-DS/d rev 03 n 1-29 n1 td46 n9 td52 n17 vdd n25 md31 n2 gnd n10 gnd n18 gnd n26 md30 n3 td47 n11 vddt n19 vdd n27 md29 n4 td48 n12 gnd n20 gnd n28 gnd n5 td49 n13 vdd n21 md34 n29 md28 n6 vddt n14 gnd n22 md33 n7 td50 n15 vdd n23 md32 n8 td51 n16 gnd n24 vdd33 p 1-29 p1 td53 p9 td59 p17 gnd p25 md24 p2 td54 p10 vddt p18 vdd p26 md23 p3 vddt p11 gnd p19 gnd p27 vdd33 p4 td55 p12 vdd p20 vdd33 p28 md22 p5 td56 p13 gnd p21 md27 p29 md21 p6 td57 p14 vdd p22 md26 p7 gnd p15 gnd p23 gnd p8 td58 p16 vdd p24 md25 r 1-29 r1 tclki r9 td63 r17 vdd r25 md16 r2 tpar0 r10 gnd r18 gnd r26 md15 r3 tpar1 r11 vdd r19 vdd r27 md14 r4 tpar2 r12 gnd r20 gnd r28 md13 r5 tpar3 r13 vdd r21 md20 r29 md12 r6 td60 r14 gnd r22 md19 r7 td61 r15 vdd r23 md18 r8 td62 r16 gnd r24 md17 table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 64 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information t 1-29 t1 ta0 t9 twe3x t17 gnd t25 md7 t2 tce0x t10 vddt t18 vdd t26 md6 t3 tce1x t11 gnd t19 gnd t27 md5 t4 tce2x t12 vdd t20 vdd33 t28 md4 t5 tce3x t13 gnd t21 md11 t29 md3 t6 twe0x t14 vdd t22 md10 t7 twe1x t15 gnd t23 md9 t8 twe2x t16 vdd t24 md8 u 1-29 u1 ta1 u9 ta7 u17 vdd u25 cpf_6 u2 vddt u10 gnd u18 gnd u26 cpf_5 u3 ta2 u11 vdd u19 vdd u27 cpf_4 u4 ta3 u12 gnd u20 gnd u28 vdd33 u5 ta4 u13 vdd u21 md2 u29 cpf_3 u6 gnd u14 gnd u22 md1 u7 ta5 u15 vdd u23 md0 u8 ta6 u16 gnd u24 gnd v 1-29 v1 ta8 v9 ta14 v17 gnd v25 cpe_6 v2 ta9 v10 vddt v18 vdd v26 cpe_5 v3 gnd v11 gnd v19 gnd v27 gnd v4 ta10 v12 vdd v20 vdd33 v28 cpe_4 v5 ta11 v13 gnd v21 cpf_2 v29 cpe_3 v6 ta12 v14 vdd v22 cpf_1 v7 vddt v15 gnd v23 vdd33 v8 ta13 v16 vdd v24 cpf_0 table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signals grouped by pin number 65 motorola general business information C5ENPA1-DS/d rev 03 w 1-29 w1 ta15 w9 pframex w17 vdd w25 cpd_5 w2 ta16 w10 gnd w18 gnd w26 cpd_4 w3 ta17 w11 vdd w19 vdd w27 cpd_3 w4 ta18 w12 gnd w20 gnd w28 cpd_2 w5 ta19 w13 vdd w21 cpe_2 w29 cpd_1 w6 ta20 w14 gnd w22 cpe_1 w7 ta21 w15 vdd w23 cpe_0 w8 xpuhot w16 gnd w24 cpd_6 y 1-29 y1 spdo y9 pinta y17 gnd y25 cpc_3 y2 spdi y10 vddt y18 vdd y26 cpc_2 y3 spld y11 gnd y19 gnd y27 cpc_1 y4 spck y12 vdd y20 vdd33 y28 cpc_0 y5 sicl y13 gnd y21 cpd_0 y29 cpb_6 y6 sida y14 vdd y22 cpc_6 y7 pgntx y15 gnd y23 cpc_5 y8 pidsel y16 vdd y24 cpc_4 aa 1-29 aa1 pserrx aa9 preqx aa17 vdd aa25 cpb_2 aa2 gnd aa10 gnd aa18 gnd aa26 cpb_1 aa3 pperrx aa11 vdd aa19 vdd aa27 cpb_0 aa4 pdevselx aa12 gnd aa20 gnd aa28 gnd aa5 pstopx aa13 vdd aa21 cpb_5 aa29 cpa_6 aa6 vdd33 aa14 gnd aa22 cpb_4 aa7 pclk aa15 vdd aa23 cpb_3 aa8 prstx aa16 gnd aa24 vdd33 table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 66 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information ab 1-29 ab1 ppar ab9 ptrdyx ab17 gnd ab25 cpa_2 ab2 pcbex3 ab10 vdd33 ab18 vdd33 ab26 cpa_1 ab3 vdd33 ab11 gnd ab19 gnd ab27 vdd33 ab4 pcbex2 ab12 vddf ab20 vdd33 ab28 cpa_0 ab5 pcbex1 ab13 gnd ab21 cpa_5 ab29 cp9_6 ab6 pcbex0 ab14 vddf ab22 cpa_4 ab7 gnd ab15 gnd ab23 gnd ab8 pirdyx ab16 vddf ab24 cpa_3 ac 1-29 ac1 pad31 ac9 fin21 ac17 fout11 ac25 cp4_3 ac2 pad30 ac10 fin14 ac18 fout5 ac26 cp3_3 ac3 pad29 ac11 fin9 ac19 cp9_5 ac27 cp2_3 ac4 pad28 ac12 fin2 ac20 cp8_5 ac28 cp1_4 ac5 pad27 ac13 ftxctl4 ac21 cp8_0 ac29 cp0_6 ac6 frxclk ac14 fout30 ac22 cp7_0 ac7 frxctl2 ac15 fout23 ac23 cp6_0 ac8 fin28 ac16 fout18 ac24 cp5_1 ad 1-29 ad1 pad26 ad9 fin20 ad17 fout10 ad25 cp4_2 ad2 pad25 ad10 fin13 ad18 fout4 ad26 cp3_2 ad3 pad24 ad11 fin8 ad19 cp9_4 ad27 cp2_2 ad4 pad23 ad12 fin1 ad20 cp8_4 ad28 cp1_3 ad5 pad22 ad13 ftxctl3 ad21 cp7_6 ad29 cp0_5 ad6 frxctl6 ad14 fout29 ad22 cp6_6 ad7 frxctl1 ad15 fout22 ad23 cp5_6 ad8 fin27 ad16 fout17 ad24 cp5_0 table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signals grouped by pin number 67 motorola general business information C5ENPA1-DS/d rev 03 ae 1-29 ae1 pad21 ae9 fin19 ae17 fout9 ae25 cp4_1 ae2 gnd ae10 gnd ae18 fout3 ae26 cp3_1 ae3 pad20 ae11 fin7 ae19 cp9_3 ae27 cp2_1 ae4 pad19 ae12 fin0 ae20 gnd ae28 gnd ae5 pad18 ae13 ftxctl2 ae21 cp7_5 ae29 cp0_4 ae6 vddf ae14 fout28 ae22 cp6_5 ae7 frxctl0 ae15 vddf ae23 cp5_5 ae8 fin26 ae16 fout16 ae24 vdd33 af 1-29 af1 pad17 af9 fin18 af17 fout8 af25 cp4_0 af2 pad16 af10 fin12 af18 gnd af26 cp3_0 af3 vdd33 af11 fin6 af19 cp9_2 af27 vdd33 af4 pad15 af12 gnd af20 cp8_3 af28 cp1_2 af5 pad14 af13 ftxctl1 af21 cp7_4 af29 cp0_3 af6 frxctl5 af14 fout27 af22 cp6_4 af7 gnd af15 fout21 af23 gnd af8 fin25 af16 fout15 af24 cp4_6 ag 1-29 ag1 pad13 ag9 fin17 ag17 vddf ag25 cp3_6 ag2 pad12 ag10 fin11 ag18 fout2 ag26 cp2_6 ag3 pad11 ag11 fin5 ag19 cp9_1 ag27 cp2_0 ag4 pad10 ag12 ftxclk ag20 cp8_2 ag28 cp1_1 ag5 pad9 ag13 vddf ag21 cp7_3 ag29 cp0_2 ag6 frxctl4 ag14 fout26 ag22 cp6_3 ag7 fin31 ag15 fout20 ag23 cp5_4 ag8 fin24 ag16 fout14 ag24 cp4_5 table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 68 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information ah 1-29 ah1 pad8 ah9 fin16 ah17 fout7 ah25 cp3_5 ah2 vdd33 ah10 vddf ah18 fout1 ah26 cp2_5 ah3 pad7 ah11 fin4 ah19 cp9_0 ah27 cp1_6 ah4 pad6 ah12 ftxctl6 ah20 vdd33 ah28 vdd33 ah5 pad5 ah13 ftxctl0 ah21 cp7_2 ah29 cp0_1 ah6 gnd ah14 fout25 ah22 cp6_2 ah7 fin30 ah15 gnd ah23 cp5_3 ah8 fin23 ah16 fout13 ah24 gnd aj 1-29 aj1 pad4 aj9 fin15 aj17 fout6 aj25 cp3_4 aj2 pad3 aj10 fin10 aj18 fout0 aj26 cp2_4 aj3 pad2 aj11 fin3 aj19 cp8_6 aj27 cp1_5 aj4 pad1 aj12 ftxctl5 aj20 cp8_1 aj28 cp1_0 aj5 pad0 aj13 fout31 aj21 cp7_1 aj29 cp0_0 aj6 frxctl3 aj14 fout24 aj22 cp6_1 aj7 fin29 aj15 fout19 aj23 cp5_2 aj8 fin22 aj16 fout12 aj24 cp4_4 table 32 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag support 69 motorola general business information C5ENPA1-DS/d rev 03 jtag support the c-5e np contains jtag test logic compliant with the ieee 1149.1 specification. all required public instructions are implemented, as well as some optional instructions. this section contains information regarding the pinout, instructions, identification codes, and boundary scan cell types. pinout the c-5e np uses the standard jtag pins including the optional test reset pin. table 30 describes the pins and their functions. jtag data registers the c-5e np contains the standard internal registers as specified in ieee 1149.1. these registers are described in table 33 . boundary scan restriction sclk/sclkx inputs must not toggle when exercising the boundary scan function for jtag. boundary scan cell types the c-5e np boundary scan register contains only two cell types. all input cells are observe only cells of type bc_4. all enable and output cells are standard cells of type bc_1. in ieee 1149.1-1990 specification, the bc_4 cell is shown in figure 7 and the bc_1 cell is shown in figure 8 . table 33 jtag internal register descriptions register name register length description bypass 1 standard jtag bypass register boundary 1549 boundary scan register device identification 32 standard jtag idcode register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 70 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information figure 7 observe-only cell figure 8 cell design that can be used for both input and output pins g1 0 1 1d c1 from system pin to next cell to system logic shift dr from last cell clock dr g1 0 1 1d c1 to/from system pin to next cell from/to system shift dr from last cell clock dr 1d c1 g1 0 1 update dr node f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . jtag support 71 motorola general business information C5ENPA1-DS/d rev 03 idcode register the c-5e np implements a standard 32bit jtag identification register. table 34 lists the value of the code for full identification and its subcomponents. the concatenated 32bit value is hexidecimal 0002132d. jtag instruction register the c-5e np contains a 4bit instruction register. table 35 lists the instructions that are supported. table 34 jtag identification code and its subcomponents field name width bit positions binary value version 4 31-28 0000 part number 16 27-12 0000_0000_0010_0001 manufacturer identity 11 11-1 001_1001_0110 lsb 1 0 1 table 35 instruction register instructions instruction mnemonic selected register instruction opcode extest boundary scan 0000 idcode identification register 0001 sample/preload boundary scan 0010 highz bypass register 0011 clamp bypass register 0100 bypass bypass register 0101 reserved* bypass register 0110 reserved* bypass register 0111 bypass bypass register 1000 bypass bypass register 1001 bypass bypass register 1010 bypass bypass register 1011 bypass bypass register 1100 bypass bypass register 1101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 72 chapter 2: signal descriptions C5ENPA1-DS/d rev 03 motorola general business information boundary scan description language in order to simplify board test, motorola corporation has provided a boundary scan description language (bsdl) file (c5e.bsdl) in the motorola web site that describes the complete set of instructions, boundary scan order, and identification code value in an industry standard format. http://www.motorola.com/networkprocessors bypass bypass register 1110 bypass bypass register 1111 * there are two reserved instructions intended for motorola corporation ? s internal use. these should not be programmed by users. table 35 instruction register instructions (continued) instruction mnemonic selected register instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 chapter 3 electrical specifications absolute maximum ratings table 36 lists the absolute maximum ratings for the c-5e network processor. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and do not imply that operation under any conditions other than those listed under ? recommended operating conditions ? ( table 37 ) is possible. exposure to conditions beyond table 36 can: reduce device reliability result in premature device failure, even with no immediate sign of failure prolonged exposure to conditions at or near the absolute maximum ratings could also result in reduced useful life and reliability of the c-5e np. table 36 c-5e network processor absolute maximum ratings parameter min max unit v dd33/vddt/vddf supply voltage (3.3v input)* * voltages are relative to ground -0.5 +5 v v dd supply voltage (1.2v input)* -0.5 +2.2 v voltage on any pin -0.5 v dd33 + 0.5 v static discharge voltage 2000/500 v storage temperature -40 +125 c absolute maximum junction temperature -40 +125 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 74 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information recommended operating conditions the recommended operating conditions describe an environment the c-5e np network processor is expected to encounter during normal operation. table 37 delineates the recommended operating parameters for the c-5e np. table 37 c-5e network processor recommended operating conditions parameter min nominal max unit v dd33 supply voltage 3.135 3.3 3.465 v v ddt supply voltage 3.135 3.3 3.465 v v ddf supply voltage 2.375 3.135 2.5 3.3 2.625* 3.465 ? * for fp operation with i/os @ 2.5v nominal. ? for fp operation with i/os @ 3.3v nominal. v v dd supply voltage 1.14 1.2 1.26 v i dd33 - v dd33 supply current 1.3 a i dd - v dd supply current 8.5 a t j junction temperature -40 125 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dc characteristics 75 motorola general business information C5ENPA1-DS/d rev 03 dc characteristics the dc electrical characteristics define the input operating conditions for proper operation and the output responses to applied dc signals and switch characteristics over specified voltage and temperature ranges. the dc electrical characteristics are specified within the recommended operating conditions including operating temperature and power supply range as stated in this data sheet. table 38 outlines the c-5e np dc characteristics. each control input pin has a capacitance associated with it. the capacitance at the control input is due to the package and the input circuitry connected to the pin. capacitance is based on these conditions: t a = 25 c ; v dd33 = 3.3v; f = 1mhz. table 39 provides capacitance data. table 38 c-5e network processor dc characteristics parameter* * all voltages are relative to ground unless otherwise indicated. min max unit notes lvt tl input high voltage 2.0 v dd33 +.3 v lvttl input low voltage -0.3 0.8 v lvt tl output high voltage 2.4 v @i oh = -2ma lvttl output low voltage 0.4 v @i ol = +2ma lvttl input current -100 +100 a v in = 0v or v dd33 lvpecl input high voltage v dd33 -1.165 v dd33 +.3v v lvpecl input low voltage -0.3 v dd33 -1.475 v lvpecl output high voltage v dd33 -1.025 v dd33 -0.60 v load = 50ohm to v dd33 - 2v lvpecl output low voltage v dd33 -2.20 v dd33 -1.620 v load = 50ohm to v dd33 - 2v lvpecl input current -100 +100 a cpref v dd33 -1.38 v dd33 -1.26 v single-ended lvpecl reference table 39 c-5e network processor capacitance data parameter typical unit all pins 5 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 76 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information power sequencing it is intended that the vdd33/vddt/vddf and vdd rails are sequenced to their final value together for most applications. vdd33, vddt and vddf must be above vdd at all times. vdd must be brought to its final value within 100ms of sequencing on vdd33, vddt and vddf. it is also required that sclk, sclkx, tclki, pclk, mdclk, ftxclk, and frxclk be running or begin running during power sequencing to propagate reset inside the c-5e np. figure 9 indicates the relationship between the clocks and prstx. there is no requirement that the asserting and deasserting edges of prstx be synchronous to the clocks. reset must be asserted within 100 s of power initiation. typically, reset is held low during power initiation. figure 9 bringup clock timing diagram tclki, pclk, sclk, sclkx, mdclk, ftxclk, frxclk prstx 3 1ms 3 100 s ( ( ) ) 100 s vdd, vdd33, vddt, vddf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . power and thermal characteristics 77 motorola general business information C5ENPA1-DS/d rev 03 power and thermal characteristics table 40 provides the derived power and thermal characteristics for the production version of the c-5e np. table 40 note: power dissipation values assume the following conditions: bmu memory operating at 133mhz. tlu memory operating at 133mhz. qmu operating at 175mhz. vdd = 1.2v, vdd33 = 3.3v, tj at approximately 50 c for typical values. vdd and vdd33 are 5% higher for maximum values. ?minimum? pd based on idle condition (clocks running and no programs executing). ? typical ? pd based on test application that implements fast ethernet forwarding actively running on all cps. ? maximum ? pd based on maximum consumption for any high-bandwidth communications application executing on all cps, fp, and xp. thermal management information this section provides thermal management information for the ceramic ball grid array (cbga) package for air-cooled applications. proper thermal control design is primarily dependent on the system-level design ? the heat sink, airflow, and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods ? spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (refer to figure 10 ); however, due to the potential table 40 c-5e network processor power and thermal characteristics parameter min typ max units test conditions power dissipation, p d 5.5 9.2 13.0 w 266mhz core clock see note below maximum junction temperature, t j 125 o c see note below thermal resistance, junction to case, jc <0.1 o c/w see note below thermal resistance, junction to printed circuit board, jb 4.8 o c/w see note below f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 78 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information large mass of the heat sink, attachment through the printed circuit board is suggested. if a spring clip is used, the spring force should not exceed 5.5 pounds. figure 10 package cross section view with several heat sink options internal package conduction resistance for the exposed-die packaging technology the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case (or top-of-die for exposed silicon) thermal resistance the die junction-to-ball thermal resistance figure 11 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. cbga package heat sink heat sink clip thermal interface material printed circuit board f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . power and thermal characteristics 79 motorola general business information C5ENPA1-DS/d rev 03 figure 11 package with heat sink mounted to the printed circuit board heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by convection. because the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms. heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( jc + int + sa ) x p d where: t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet external resistance internal resistance external resistance radiation heat sink printed circuit board (pcb) radiation convection thermal interface material die/package die junction package/leads convection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 80 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 40 . the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material ( int ) is typically about 1.5 c/w. for example, assuming a t a of 30 c, a t r of 5 c, a cbga package jc = 0.1, and a maximum power consumption (p d ) of 13.0 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 1.5 c/w + sa ) x 13.0 w for this example, a sa value of 5.3 c/w or less is required to maintain the die junction temperature below the maximum value of table 40 . though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature ? airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 81 motorola general business information C5ENPA1-DS/d rev 03 ac timing specifications ac timing specifications consist of input requirements and output responses. the input requirements include setup and hold times, pulse widths, and high and low times. the output responses include delays from clock to signal. the ac timing specifications are defined separately for each interface to the c-5e np. see figure 12 . output timing specifications for lvttl pins are given with a 20pf load on the output. other loads can be simulated with the ibis model available from motorola. the lvpecl driver is specified into a 50 ? load terminated to a (vdd33 - 2v) reference. figure 12 test loading conditions + 2v lvttl lvpecl dut dut 20pf 50 ? vdd33 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 82 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information clock timing specifications the system clock timing is shown in figure 13 and described in table 41 . figure 13 system clock timing diagram t sc t sh sclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 sclkx cclkn t ccn t sl t cch t ccl table 41 system clock timing description symbol parameter min typ max unit comment tsc system cycle time 3.76 ns 266mhz core clock tsh sys clk high pulse 45 55 duty cycle* * pulse duty cycle measured at crossing voltage of sclk/sclkx tsl sys clk low pulse 45 55 duty cycle* tcc0 cclk0 cycle time 647.67 ns t1 ? tcc1 cclk1 cycle time 488.28 ns e1 ? tcc2 cclk2 cycle time 29.097 ns e3 ? tcc3 cclk3 cycle time 22.353 ns t3 ? tcc4 cclk4 cycle time 20.00 ns rmii ? tcc5 cclk5 cycle time 9.412 ns fibre channel ? tcc6 cclk6 cycle time 8.00 ns gmii ? tcc7 cclk7 cycle time 6.43 ns oc-3 ? tcch cclkm high time 40% 60% % cycle pulse is high tccl cclkm low time 40% 60% % cycle pulse is low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 83 motorola general business information C5ENPA1-DS/d rev 03 cp timing specifications this section describes the timing for the following cp interfaces: ds1/ds3 10/100 ethernet gigabit ethernet oc-3 oc-12 ds1/ds3 timing specifications the ds1/ds3 interface timing is shown in figure 14 and described in table 42 . figure 14 ds1/ds3 ethernet timing diagram ? the frequencies specified for cclk0 - cclk7 allow full flexibility for the c-5e np. it is also possible to use one or more cclk n inputs for other frequencies; contact your motorola representative for more information. cpn_0 (tclk) cycle 1 cycle 2 cycle 2 cycle 3 cycle 3 cycle 4 cycle 4 cycle 5 cycle 5 cpn_2/3 (tx) cpn_1 (rclk) cpn_4/5 (rx) t cdt t cdo t cdr t cds t cdh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 84 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information 10/100 ethernet timing specifications the 10/100 ethernet interface timing is shown in figure 15 and described in table 43 . figure 15 10/100 ethernet timing diagram table 42 ds1/ds3 ethernet timing description symbol parameter min typ max unit tcdt ds1/ds3 transmit cycle time 647/22.4 ns tcdo ds1/ds3 output time 3.0/3.0 400/15.0 ns tcdr ds1/ds3 receive cycle time 647/22.4 ns tcds ds1/ds3 setup time 2.0 ns tcdh ds1/ds3 hold time 0 ns cpn_0 (tclk) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_2/3/6 (tx) cpn_1/4/5 (rx) t cet t ceo t ces t ceh table 43 10/100 ethernet timing description symbol parameter min typ max unit tcet transmit cycle time* * std/fast ethernet 20 ns tceo output time 3.0 15.0 ns tces setup time 2.0 ns tceh hold time 0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 85 motorola general business information C5ENPA1-DS/d rev 03 gigabit gmii ethernet, tbi and mii interface timing specifications the gigabit gmii ethernet interface timing is shown in figure 16 and described in table 44 . the tbi interface timing is shown in figure 16 and described in table 45 . figure 16 gigabit ethernet and tbi interface timing diagram cycle 1 cycle 2 cycle 3 t cmt t cmo mii tx cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t cgt t cgo gmii / tbi tx cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t ctr t ctd t cts t cth tbi rx mii cpn_1 (tclki) mii cpn_2-6 (tx) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn+2_1 (rclk) t cgr t cgs t cgh gmii/mii rx cpn+2_2-6 (rx) cpn+3_1-6 (rx) cpn_0 (tclk) cpn_2-6 (tx) cpn+1_2-6 (tx) cpn+2_1 (rclk) cpn+3_1 (rclkn) cpn+2_2-6 (rx) cpn+3_2-6 (rx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 86 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information table 44 gigabit gmii/mii ethernet interface timing description symbol gigabit parameter min typ max unit comment tcgt transmit cycle time, gmii 8.0 ns tcgo output time, gmii 3.0 6.0 ns tcgr receive cycle time 8.0 ns tcgs setup time 2.0 ns tcgh hold time 0.0 ns tcmt transmit cycle time, mii 40/400 ns 100baset/10baset tcmo output time, mii 2 8 ns table 45 gigabit tbi interface timing description symbol tbi parameter min typ max tol unit tctt transmit cycle time 8.0 ns tcto output time 3.0 6.0* * for fibre channel applications this value is 7.0ns for a transmit cycle time of 9.4ns. ns tctr receive cycle time 16.0 ns tctd rclk/rclkn deviation 1.0 ns tcts setup time 2.0 ns tcth hold time 0.0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 87 motorola general business information C5ENPA1-DS/d rev 03 oc-3 timing specifications the oc-3 interface timing is shown in figure 17 and described in table 46 . figure 17 oc-3 timing diagram cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_2 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_3 cpn_0 cpn_1 cpn_4 cpn_5 t c3t t c3r t c3d t c3i t c3s t c3h t c3s t c3h table 46 oc-3 timing description symbol parameter min typ max unit tc3t oc-3 transmit cycle time 6.43 ns tc3i oc-3 pulse width 2.0 ns tc3r oc-3 receive cycle time* * 155.52mhz 6.0 ns tc3d oc-3 clock duty cycle 40 60 % tc3s oc-3 setup time 2.0 ns tc3h oc-3 hold time 0.0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 88 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information oc-12 timing specifications the oc-12 interface timing is shown in figure 18 and described in table 47 . figure 18 oc-12 timing diagram cpn_1 (tclki) cycle 1 cycle 1 cycle 2 cycle 3 cycle 3 cycle 4 cycle 5 cpn_0 (tclk) cpn+1_2-5 (tx) cpn_1 (rclk) cpn+2_2-6 (rx) cpn+3_2-5 (rx) t c12i t c12t t c12r t c12o t c12s t c12h cycle 2 t c12d table 47 oc-12 timing description symbol parameter min typ max unit tc12i oc-12 transmit cycle time* * input from phy 12.86 ns tc12d oc-3 clock duty cycle 40 60 % tc12t oc-12 transmit cycle time ? ? output from c-5e np 12.86 ns tc12o oc-12 output time ? ? aligned to tclk 3.0 10.0 ns tc12r oc-12 receive cycle time 12.0 12.86 ns tc12s oc-12 setup time 2.0 ns tc12h oc-12 hold time 0.0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 89 motorola general business information C5ENPA1-DS/d rev 03 executive processor timing specifications the xp timing specifications include: pci timing specifications mdio serial interface timing specifications low speed serial interface timing specifications prom interface timing specifications pci timing specifications the pci timing is shown in figure 19 and described in table 48 . figure 19 pci timing diagram pclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 pad/p_ctl (output) pad/p_ctl (input) pgntx (input) pidsel (input) t pc t pao t pav t paz t pas t pah t pgs t pgh t pis t pih f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 90 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information table 48 pci timing description symbol parameter min typ max unit tpc pci cycle time* * 66mhz pci 15.0 ns tpas pad/p_c tl ? setup ? p_ctl includes all pci control parameters including: ppar, pframex, ptrdyx, pirdyx, pstopx, pdevselx, pperrx, pserrx 3.0 ns tpah pad/p_ctl hold 0.0 ns tpao pad/p_c tl output 2.0 6.0 ns tpaz pad/p_c tl clk to tri ? ? not fully tested, values based on design/characterization. 2.0 6.0 ns tpav pad/p_ctl clk to driven ? 2.0 6.0 ns tpgs pgntx setup 5.1 ns tpgh pgntx hold 0.0 ns tpis pidsel setup 3.0 ns tpih pidsel hold 0.0 ns prstx** ** asynchronous ns pinta** ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 91 motorola general business information C5ENPA1-DS/d rev 03 mdio serial interface timing specifications the mdio serial interface timing is shown in figure 20 and described in table 49 . figure 20 mdio serial interface timing diagram cycle 2 cycle 3 cycle 4 t sic t sids sicl sida (output) sida (input) t sods t sodh table 49 mdio serial interface timing description symbol parameter min typ max unit tsic sicl cycle time 40 ns tsids sida input setup 10 ns tsidh sida input hold 0.0 ns tsods sida output setup 10 ns tsodh sida output hold 10 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 92 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information low speed serial interface timing specifications the low speed serial interface timing is shown in figure 21 and described in table 50 . figure 21 low speed serial interface timing diagram cycle 2 cycle 3 t slc t slss t slhd t slsd t slhs sicl sida t slst t slb table 50 low speed serial interface timing description symbol parameter min max unit tslc sicl cycle time 2500 ns tslss set-up time for repeated start condition 600 ns tslhs hold time start condition 600 ns tslsd data set-up time 250 ns tslhd data hold time 0.0 ns tslst set-up time for stop condition 600 ns tslb bus free time between a stop and start condition 1250 ns cmax capacitive load for each line of the bus 400 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 93 motorola general business information C5ENPA1-DS/d rev 03 prom interface timing specifications the prom interface timing is shown in figure 22 and described in table 51 . figure 22 prom interface timing diagram spck cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 spdi spld spdo t spc t splo t spis t spih t spdo table 51 prom interface timing description symbol parameter min typ max unit tspc spck cycle time 40.0 ns tspis spdi setup 10.0 ns tspih spdi hold 0.0 ns tsplo spld output tsc tsc + 3.0 ns tspdo spdo output tsc tsc + 3.0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 94 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information fabric processor timing specifications the fp timing specifications are shown in figure 23 and described in table 52 . figure 23 fabric processor timing diagram frxclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 frxctl (output) frxctl (input) finn t frc t frco t frcv t frcz t frcs t frch t frds t frdh t ftcs t ftch ftxclk ftxctl (output) ftxctl (input) foutn t ftc t ftco t ftcv t ftcz t ftdo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 95 motorola general business information C5ENPA1-DS/d rev 03 table 52 fabric processor timing description symbol parameter min typ max unit comment tfrc frx cycle time 8.0 ns tfrcs frxctl setup 4.0 1.5 ns utopia2 mode all other modes tfrch frxctl hold 0.0 ns tfrco frxctl output 1.0 4.0 ns tfrcz frxctl clk to tri* * not fully tested, values based on design/characterization. 1.0 4.0 ns tfrcv frxctl clk to driven* 1.0 4.0 ns tfrds fin setup 4.0 1.5 ns utopia2 mode all other modes tfrdh fin hold 0.0 ns tftc ftx cycle time 8.0 ns tftcs ftxctl setup 4.0 1.5 ns utopia2 mode all other modes tftch ftxctl hold 0.0 ns tftco ftxctl output 1.0 4.0 ns tftcz ftxctl clk to tri* 1.0 4.0 ns tftcv ftxctl tri to driven* 1.0 4.0 ns tftdo fout output 1.0 4.0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 96 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information bmu timing specifications the bmu timing specifications are shown in figure 24 and described in table 53 . the bmu synchronous dram interface is pc100-compliant and designed to work with industry standard sdram components with 12 or fewer address lines. the information below is intended to provide the output, setup, and hold data required to design this interface without duplicating the transaction waveform diagrams in sdram data sheets. figure 24 bmu timing diagram mdclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 m_ctl man mdn (output) mdn (input) t mc t mdo t mco t mao t mdv t mds t mdz t mdh table 53 bmu timing description symbol parameter min typ max unit tmc bmu cycle time 7.5 ns tmco bmu ctrl output 0.8 3.4 ns tmao bmu addr output 0.8 3.4 ns tmds bmu data setup 0.5 ns tmdh bmu data hold 1.1 ns tmdo bmu data output 0.8 4.0 ns tmdz bmu data clk to tri* * not fully tested, values based on design/characterization. 0.8 4.0 ns tmdv bmu data clk to driven* 0.8 4.0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 97 motorola general business information C5ENPA1-DS/d rev 03 table 54 signal groups in bmu timing diagrams signal group included signals control (m_ctl) mba0, mba1, mcasx, mrasx, mwex, mcsx, mdqm, mdqml address (man) ma0 - ma11 data (mdn) md0 - md129, mdecc0 - mdecc8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 98 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information tlu timing specifications the tlu timing specifications are shown in figure 25 and described in table 55 . figure 25 tlu timing diagram tclki cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t_ctl tan tdn (output) tdn (input) t tc t tdo t tco t tao t tdv t tds t tdz t tdh table 55 tlu timing description symbol parameter min typ max unit ttc tlu cycle time 7.5 ns ttco tlu ctrl output 0.8 3.4 ns ttao tlu addr output 0.8 3.4 ns ttds tlu data setup 1.0 ns ttdh tlu data hold 1.2 ns ttdo tlu data output 0.8 3.7 ns ttdz tlu data clk to tri* * not fully tested, values based on design/characterization. 0.8 3.7 ns ttdv tlu data clk to driven* 0.8 3.7 ns table 56 signal groups in tlu timing diagrams signal group included signals control (t_ctl) tce0x - tce3x, twe0x - twe3x address (tan) ta0 - ta21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 99 motorola general business information C5ENPA1-DS/d rev 03 qmu sram (internal mode) timing specifications the qmu sram (internal mode) timing specifications are shown in figure 26 and described in table 57 . figure 26 qmu sram (internal mode) timing diagram data (tdn) td0 - td63, tpar0-3 table 56 signal groups in tlu timing diagrams signal group included signals qaclki cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 q_ctl qan qdn (output) qdn (input) t qc t qdo t qco t qao t qdv t qds t qdz t qdh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 100 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information table 57 qmu sram (internal mode) timing description symbol parameter min typ max unit comment tqc qmu cycle time 5.7 ns tqco qmu ctrl output 0.8 3.4 ns loading is 50 ? transmission line. tqao qmu addr output 0.8 3.4 ns loading is 50 ? transmission line. tqds qmu data setup 0.8 ns tqdh qmu data hold 0.8 ns tqdo qmu data output 0.9 3.4 ns loading is 50 ? transmission line. tqdz qmu data clk to tri* * not fully tested, values based on design/characterization. 0.9 3.4 ns tqdv qmu data clk to driven* 0.9 3.4 ns table 58 signal groups in qmu sram (internal mode) timing diagrams signal group included signals control (q_ctl) qwex address (qan) qa0-qa16 data (qdn) qd0-qd31, qdpl, qdph f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac timing specifications 101 motorola general business information C5ENPA1-DS/d rev 03 qmu to q-5 (external mode) timing specifications the qmu to q-5 (external mode) timing specifications are shown in figure 27 and describded in table 59 . figure 27 qmu to q-5 (external mode) timing diagram qaclki cycle 1 cycle 2 t qes qbclki dqdata t qeh t qeh qaclko qbclko nqdata t qeomin t qeomax t qes t qep t qec t qep t qec t qep t qec t qep t qec t qeomin t qeomax f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 102 chapter 3: electrical specifications C5ENPA1-DS/d rev 03 motorola general business information table 59 qmu to q-5 (external mode) timing description symbol parameter min typ max unit comment tqec qmu external cycle time 10.0 ns qaclko/qbclko derived from qaclki/qbclki tqep qmu clka-clkb delta between rising edges 4.8 ns tqes qmu input data setup 0.6 ns tqeh qmu input data hold 0.8 ns tqeo qmu data output -.85 1.3 ns determines valid time for data from each clock rising edge table 60 signal groups in qmu to q-5 (external mode) timimg diagrams signal group included signals input clocks (qnclki) qaclki, qbclki output clocks (qnclko) qaclko, qbclko input data (dqdata) qd0-23, qardy, qdpl, qdph, qnqrdy, qdqpar output data (nqdata) qa0-16, qwex, qd24-31 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 chapter 4 mechanical specifications package views the c-5e network processor is an 840 pin (29 pins x 29 pins) ball grid array (bga) package as shown in the following illustrations. table 61 defines the package measurements. figure 28 c-5e network processor bga package side view hitce: green ceramic is thermally matched to fr4 circuit board. a seating plane a 1 a 2 a 3 a 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 104 chapter 4: mechanical specifications C5ENPA1-DS/d rev 03 motorola general business information figure 29 c-5e network processor bga package (bottom view) e b e d e d 1 e 1 aj ah a g af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . package views 105 motorola general business information C5ENPA1-DS/d rev 03 figure 30 c-5e network processor bga package (top view) probe pad die 18ars10517d001 optional capacitor pads optional capacito r pads 1.65 1.70 0.7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 106 chapter 4: mechanical specifications C5ENPA1-DS/d rev 03 motorola general business information package measurements table 61 defines the c-5e np package measurements, providing nominal, minimum, and maximum sizes where appropriate. at motorola ? s discretion up to fourteen (14) capacitors may or may not be attached on the top of the package. marking codes table 62 explains the marking on the c-5e np. table 61 package measurements (reference figure 28 , figure 29 and figure 30 for symbols) symbol definition nom. (mm) min. (mm) max. (mm) a overall 3.26 2.97 3.55 a 1 ball height 0.70 0.6 0.8 a 2 c4 and die 0.86 0.82 0.9 a 3 body thickness 1.7 1.55 1.85 a 4 capacitor pads 0.6 d body size 31.00 30.80 31.20 d 1 ball footprint (x) 28.00 e body size 31.00 30.80 31.20 e 1 ball footprint (y) 28.00 e ball pitch 1.00 b ball diameter 0.70 table 62 c-5e network processor marking codes marking (explanation of codes) top logo/part#/date code bottom n/a pin 1 marking chamfered corner f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . reflow 107 motorola general business information C5ENPA1-DS/d rev 03 reflow typical reflow profile for the c-5e switch module comprises: 1 follow the guidelines recommended by your solder paste supplier. flux requirements must be met for best solderability. 2 the temperature profile should be carefully characterized to ensure uniform temperature across the board and package. solder ball voiding may be affected by ramp rates and dwell times below and above liquids. 3 a nitrogen atmosphere is not required, but will make the process more robust. it can make a difference for marginally solderable pc board pads. 4 full convection forced air furnaces work best, but ir, convection/ir, or vapor phase can be used. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 108 chapter 4: mechanical specifications C5ENPA1-DS/d rev 03 motorola general business information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola general business information C5ENPA1-DS/d rev 03 C5ENPA1-DS/d rev 03 index symbols 10/100 ethernet (rmii) configuration 34 10/100 ethernet signals 34 10/100 ethernet timing description 84 10/100 ethernet timing diagram 84 10/100 ethernet timing specifications 84 a absolute maximum ratings 73 ac timing specifications 81 b block diagram, c-5e network processor 20 bmu sdram interface signals 52 bmu signal groups 97 bmu timing description 96 bmu timing diagram 96 bmu timing specifications 96 boundary scan cell types 69 boundary scan description language 72 bringup clock timing diagram 76 buffer management unit 24 c c-5e network processor absolute maximum ratings 73 c-5e network processor bga package, bottom view 104 c-5e network processor bga package, side view 103 c-5e network processor capacitance data 75 c-5e network processor dc characteristics 75 c-5e network processor power and thermal characteristics 77 c-5e np channel processors 22 channel processor interface signals 32 channel processors 22 channel processors physical interface signals and pins grouped by clusters 33 clock and reference signals 31 clock signals 31 clock timing specifications 82 configuration 10/100 ethernet (rmii) 34 ds1/t1 framer interface 34 fibrechannel tbi 38 gigabit ethernet 38 gigabit ethernet (gmii) 35 sonet oc-12 transceiver interface 40 sonet oc-3 transceiver interface 39 configurations gmii/tbi transmit and receive pin 36 cp timing specifications 83 csix-l1 mode, c-5e network processor to fabric interface pin mapping 51 d data registers jtag 69 dc characteristics 75 description functional 19 description language boundary scan 72 descriptions signal 27 diagram 10/100 ethernet timing 84 bmu timing 96 bringup clock timing 76 ds1/ds3 ethernet timing 83 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 110 index C5ENPA1-DS/d rev 03 motorola general business information fabric processor timing 94 gigabit ethernet (tbi) timing 85 low speed serial interface timing 92 mdio serial interface timing 91 oc-3 timing 87 pci timing 89 pinout 28 prom interface 45 prom interface timing 93 qmu timing 99 signal groups in bmu timing 97 signal groups in qmu timing 100 signal groups in tlu timing 98 system clock timing 82 tlu timing 98 diagram, block c-5e network processor 20 ds1/ds3 ethernet timing description 84 ds1/ds3 ethernet timing diagram 83 ds1/ds3 timing specifications 83 ds1/t1 framer interface configuration 34 ds1/t1 framer interface signals 34 e electrical specifications 73 absolute maximum ratings 73 executive processor 23 pci 23 prom interface 24 serial bus interface 23 system interface signals 42 system interfaces 23 executive processor timing specifications 89 f fabric interface pin mapping csix-l1 mode 51 power x(csix-l0) mode 50 prizma mode 50 utopia2/utopia3 atm mode 49 utopia2/utopia3 phy mode 49 fabric processor 24 fabric processor interface signals 48 fabric processor timing description 95 fabric processor timing diagram 94 fabric processor timing specifications 94 functional description 19 g general system interface signal 47 gigabit ethernet (gmii) configuration 35 gigabit ethernet (gmii) signals one cluster example 36 gigabit ethernet (tbi) timing description 86 , 86 gigabit ethernet (tbi) timing diagram 85 gigabit ethernet and fibrechannel tbi configuration 38 gigabit ethernet and fibrechannel tbi signals example 38 gigabit gmii ethernet, tbi and mii interface timing specification 85 gmii/tbi transmit and receive pin configurations 36 i idcode register 71 instruction register instructions 71 j jtag data registers 69 jtag identification code and its sub-components 71 jtag instruction register 71 jtag internal register descriptions 69 jtag support pinouts 69 l low speed serial interface timing description 92 low speed serial interface timing diagram 92 low speed serial interface timing specifications 92 lvpecl specifications 30 lvttl specifications 30 m f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index 111 motorola general business information C5ENPA1-DS/d rev 03 mdio serial interface timing description 91 mdio serial interface timing diagram 91 mdio serial interface timing specifications 91 measurements c-5e network processor 106 mechanical specifications 103 miscellaneous test signals for jtag, scan, and internal test routines 58 n no connection pins 58 o oc-12 signals 40 oc-12 timing description 88 oc-12 timing specifications 88 oc-3 signals 39 oc-3 timing description 87 oc-3 timing diagram 87 oc-3 timing specifications 87 operating conditions, recommended 74 p package measurements 106 pci signals 42 pci timing description 90 pci timing diagram 89 pci timing specifications 89 pin descriptions grouped by function 30 pin locations 28 pin number signals groups 59 pinout diagram 28 power sequencing 76 , 77 power supply signals 57 power x(csix-l0) mode, fabric interface pin mapping 50 prizma mode, c-5e network processor to fabric interface pin mapping 50 processor, executive 23 processor, fabric 24 prom interface diagram 45 prom interface signals 44 prom interface timing description 93 prom interface timing diagram 93 prom interface timing outline 46 prom interface timing specifications 93 q qmu signal groups 100 qmu sram (internal mode) timing diagram 99 qmu sram interface signals 55 , 56 qmu timing description 100 qmu timing specifications 99 qmu to q-5 (external mode) timing diagram 101 queue management unit 26 r recommended operating conditions 74 register idcode 71 jtag instruction 71 s serial interface signals 43 serial port signals 43 signal general system interface 47 signal descriptions 27 signal summary 27 signals 10/100 ethernet 34 bmu sdram interface 52 channel processor interface 32 clock 31 clock and reference 31 ds1/t1 framer interface 34 fabric processor interface 48 grouped by pin number 59 oc-12 40 oc-3 39 pci 42 power supply 57 prom interface 44 qmu sram interface 55 , 56 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 112 index C5ENPA1-DS/d rev 03 motorola general business information serial interface 43 serial port 43 test 58 tlu sram interface 54 sonet oc-12 transceiver interface configuration 40 sonet oc-3 transceiver interface configuration 39 specifications 10/100 ethernet timing 84 ac timing 81 bmu timing 96 clock timing 82 cp timing 83 ds1/ds3 timing 83 electrical 73 executive processor timing 89 fabric processor timing 94 gigabit gmii ethernet, tbi and mii interface timing specification 85 low speed serial interface timing 92 mdio serial interface timing 91 mechanical 103 oc-12 timing 88 oc-3 timing 87 pci timing 89 prom interface timing 93 qmu timing 99 tlu timing 98 xp timing 89 system clock timing description 82 system clock timing diagram 82 system interfaces executive processor 23 t table lookup unit 25 test signals 58 test signals, miscellaneous, for jtag, scan, and internal test routines 58 timing outline prom interface 46 tlu signal groups 98 tlu sram interface signals 54 tlu timing description 98 tlu timing diagram 98 tlu timing specifications 98 transceiver interface configuration sonet oc-12 40 sonet oc-3 39 transmit and receive pin combinations for gigabit ethernet and fibrechannel 35 u utopia2/utopia3 atm mode, c-5e network processor to fabric interface pin mapping 49 utopia2/utopia3 phy mode, c-5e network processor to fabric interface pin mapping 49 x xp timing specifications 89 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola, inc . c-port family of network processors 120 water street, no. andover, ma 01845 voice: (978) 773-2300 fax: (978) 773-2301 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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