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1/19 tda7439ds june 2004 1features input multiplexer ? 4 stereo inputs ? selectable input gain for optimal adaptation to different sources one stereo output treble, middle and bass control in 2.0db steps volume control in 1.0db steps two speaker attenuators: ? two independent speaker control in 1.0db steps for balance facility ? independent mute function all function are programmable via serial bus 2description the tda7439ds is a volume tone (bass, middle and treble) balance (left/right) processor for quality audio applications in car-radio and hi-fi systems. selectable input gain is provided. con- trol of all the functions is accomplished by serial bus. the ac signal setting is obtained by resistor net- works and switches combined with operational amplifiers. thanks to the used bipolar/cmos technology, low distortion, low noise and dc stepping are obtained three bands digitally controlled audio processor figure 2. block diagram 0/30db 2db step muxoutl volume volume treble treble treble(l) middle middle muxoutr treble(r) bout(l) spkr att left lout scl sda dig_gnd rout d97au621 i 2 cbus decoder + latches 100k 100k 100k 100k g l-in1 l-in2 l-in3 l-in4 100k 100k 100k 100k r-in1 r-in2 r-in3 r-in4 g input multiplexer + gain mout(l) bass bin(l) bass spkr att right min(r) mout(r) bout(r) bin(r) supply cref agnd v s min(l) 27 4 5 6 7 3 2 1 28 21 22 20 26 24 25 9 191011121323 8 1817161415 r m r b r m r b v ref rev.2 figure 1. package t able 1. order codes part number package tda7439ds sdip30 TDA7439DS13TR tape & reel so28
tda7439ds 2/19 figure 3. pin connection table 2. absolute maximum ratings table 3. thermal data table 4. quick reference data symbol parameter value unit v s operating supply voltage 10.5 v t amb operating ambient temperature 0 to 70 c t stg storage temperature range -55 to 150 c symbol parameter value unit r th j-pin thermal resistance junction-pins 85 c/w symbol parameter min. typ. max. unit v s supply voltage 7 9 10.2 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio v out = 1vrms (mode = off) 106 db s c channel separation f = 1khz 90 db input gain in (2db step) 0 30 db volume control (1db step) -47 0 db treble control (2db step) -14 +14 db middle control (2db step) -14 +14 db bass control (2db step) -14 +14 db balance control 1db step -79 0 db mute attenuation 100 db l_in3 l_in4 muxoutl muxoutr min(r) bin(r) mout(r) bout(r) bin(l) 1 3 2 4 5 6 7 8 9 bout(l) mout(l) min(l) treble(r) treble(l) scl sda dig-gnd cref 23 22 21 20 19 17 18 16 15 d97au622 10 11 12 13 14 28 27 26 25 24 r_in3 r_in2 r_in1 l_in1 l_in2 v s agnd rout lout r_in4
3/19 tda7439ds table 5. electrical characteristcs (refer to the test circuit t amb = 25c, v s = 9v, r l = 10k ? , r g = 600 ? , all controls flat (g = 0db), unless otherwise specified) symbol parameter test condition min. typ. max. unit supply v s supply voltage 7 9 10.2 v i s supply current 4 7 10 ma svr ripple rejection 60 90 db input stage r in input resistance 70 100 130 k ? v cl clipping level thd = 0.3% 2 2.5 vrms s in input separation the selected input is grounded through a 2.2 capacitor 80 100 db g inmin minimum input gain -1 0 1 db g inman maximum input gain 29 30 31 db g step step resolution 1.5 2 2.5 db volume control r i input resistance 20 33 50 k ? c range control range 45 47 49 db a vmax max. attenuation 45 47 49 db a step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -24db -1.0 0 1.0 db a v = -24 to -47db -1.5 0 1.5 db e tracking error a v = 0 to -24db 01db a v = -24 to -47db 02db v dc dc step adjacent attenuation steps from 0db to a v max 0 0.5 3mv mv a mute mute attenuation 80 100 db bass control (1) gb control range max. boost/cut 12.0 14.0 16.0 db b step step resolution 1 2 3 db r b internal feedback resistance 33 44 55 k ? treble control (1) gt control range max. boost/cut 13.0 14.0 15.0 db t step step resolution 1 2 3 db middle control (1) gm control range max. boost/cut 12.0 14.0 16.0 db m step step resolution 1 2 3 db r m internal feedback resistance 18.75 25 31.25 k ?
tda7439ds 4/19 notes: 1. the device is functionally good at vs = 5v. a step down, on vs, to 4v does?t reset the device. 2. bass, middle and treble response: the center frequency and the response quality can be chosen by the external circuitry. speaker attenuators c range control range 70 76 82 db s step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -20db -1.5 0 1.5 db a v = -20 to -56db -2 0 2 db v dc dc step adjacent attenuation steps 0 3 mv a mute mute attenuation 80 100 db audio outputs v clip clipping level d = 0.3% 2.1 2.6 v rms r l output load resistance 2 k ? r o output impedance 10 40 70 ? v dc dc voltage level 3.5 3.8 4.1 v general e no output noise all gains = 0db; bw = 20hz to 20khz flat 515 v e t total tracking error a v = 0 to -24db 0 1 db a v = -24 to -47db 02db s/n signal to noise ratio all gains 0db; v o = 1v rms ; 95 106 db s c channel separation left/right 80 100 db d distortion a v = 0; v i = 1v rms ; 0.01 0.08 % bus input v il input low voltage 1v v ih input high voltage 3 v i in input current v in = 0.4v -5 0 5 a v o output voltage sda acknowledge i o = 1.6ma 0.4 0.8 v table 5. electrical characteristcs (continued)
5/19 tda7439ds figure 4. test circuit 3 application suggestions the first and the last stages are volume control blocks. the control range is 0 to -47db (mute) for the first one, 0 to -79db (mute) for the last one. both of them have 1db step resolution. the very high resolution allows the implementation of systems free from any noisy acoustical effect. the tda7439ds audioprocessor provides 3 bands tones control. 3.1 bass, middle stages the bass and the middle cells have the same structure. the bass cell has an internal resistor ri = 44k ? typical. the middle cell has an internal resistor ri = 25k ? typical. several filter types can be implemented, connecting external components to the bass/middle in and out pins. figure 5. 0/30db 2db step muxoutl volume volume treble treble treble(l) middle middle muxoutr treble(r) bout(l) min(l) spkr att left lout scl sda diggnd rout d98au886 i 2 cbus decoder + latches 5.6nf 100k 100k 100k 100k g l-in1 l-in2 l-in3 l-in4 0.47 f 0.47 f 0.47 f 0.47 f 100k 100k 100k 100k r-in1 r-in2 r-in3 r-in4 0.47 f 0.47 f 0.47 f 0.47 f g input multiplexer + gain mout(l) bass bin(l) 18nf 22nf 100nf 100nf 2.7k 5.6k bass spkr att right min(r) mout(r) bout(r) bin(r) 5.6nf 18nf 22nf 100nf 100nf 2.7k 5.6k supply 10 f cref agnd v s r m r b r m r b 27 4 5 6 7 3 2 1 28 21 22 20 26 24 25 9 19 10 11 12 13 23 81817161415 v ref ri internal c 2 out in c 1 r 2 d95au313
tda7439ds 6/19 the fig.5 refers to basic t type bandpass filter starting from the filter component values (r1 internal and r2,c1,c2 external) the centre frequency fc, the gain av at max. boost and the filter q factor are computed as follows: viceversa, once fc, av, and ri internal value are fixed, the external components values will be: 3.2 treble stage the treble stage is a high pass filter whose time constant is fixed by an internal resistor (25k ? typical) and an external capacitor connected between treble pins and ground typical responses are reported in figg. 10 to 13. 3.3 cref the suggested 10 f reference capacitor (cref) value can be reduced to 4.7 f if the application requires faster power on. f c 1 2 r1 r2 c1 c 2 ??? ?? -------------------------------------------------------------- --- = a v r2c2 r2c1 ric1 ++ r2c1 r2c2 + --------------------------------------------------------- --- = q r1 r2 c1 c 2 ??? r2c1 r2c2 + ----------------------------------------------- -- - = c 1 a v 1 ? 2 fc ri q ?? ? ? ------------------------------------------ c2 q 2 c1 ? a v 1 ? q 2 ? --------------------------- -- - = = r 2 a v 1 ? q 2 ? 2 c1 fc a v 1 ? () q ?? ?? ? ------------------------------------------------------------------- --- = figure 6. thd vs. frequency figure 7. thd vs. rload
7/19 tda7439ds figure 8. channel separation vs. frequency figure 9. bass response figure 10. treble response figure 11. middle response figure 12. typical tone response
tda7439ds 8/19 4i 2 c bus interface data transmission from microprocessor to the tda7439ds and vice versa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). 4.1 data validity as shown in fig. 13, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 4.2 start and stop conditions as shown in fig.14 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. 4.3 byte format every byte transferred on the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 4.4 acknowledge the master ( p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 15). the peripheral (audio processor) that acknowl edges has to pull-down (low) the sda line during this clock pulse. the audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. 4.5 transmission without acknowledge avoiding to detect the acknowledge of the audio processor, the mp can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking. figure 13. data validity on the i 2 cbus figure 14. s da s cl data line stable, data valid change data allowed d99au1031 s cl s da start i 2 cbu s stop d99au1032
9/19 tda7439ds figure 15. 5 software specification 5.1 interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the tda7439ds address a subaddress bytes a sequence of data (n byte + acknowledge) a stop condition (p) figure 16. ack = acknowledge s = start p = stop a = address b = auto increment 6 examples 6.1 no incremental bus the tda7439 receives a start condition, the correct chip address, a subaddress with the b = 0 (no incre- mental bus), n-data (all these data concern the subaddress selected), a stop condition. figure 17. s cl 1 msb 23789 s da start acknowledgmen t from receiver d99au1033 s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au420 x data subaddress data 1 to data n x x b s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au421 x d3 subaddress data x x 0 d2 d1 d0
tda7439ds 10/19 6.2 incremental bus the tda7439ds receive a start conditions, the correct chip address, a subaddress with the b = 1 incre- mental bus): now it is in a loop condition with an autoincrease of the s ubaddress whereas subaddress from "xxx1000" to "xxx1111" of data are ignored. the data 1 concern the subaddress sent, and the data 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. figure 18. table 6. power on reset condition 7 data bytes address = 88 hex (addr:open). figure 19. function selection: first byte (subaddress) b = 1: incremental bus active b = 0: no incremental bus x = don?t care input selection in2 input gain 28db volume mute bass 0db middle 2db treble 2db speaker mute msb lsb subaddress d7 d6 d5 d4 d3 d2 d1 d0 x x x b 0 0 0 0 input select x x x b 0 0 0 1 input gain x xxb0010volume x xxb0011bass x xxb0100middle x xxb0101treble x x x b 0 1 1 0 speaker attenuate "r" x x x b 0 1 1 1 speaker attenuate "l" s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au422 x d3 subaddress data 1 to data n x x 1 d2 d1 d0
11/19 tda7439ds table 7. input selection table 8. input gain selection gain = 0 to 30db msb lsb input multiplexer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxx0 0 in4 xxxxxx0 1 in3 xxxxxx1 0 in2 xxxxxx1 1 in1 msb lsb input gain d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0000 0db 0001 2db 0010 4db 0011 6db 0100 8db 0101 10db 0110 12db 0111 14db 1000 16db 1001 18db 1010 20db 1011 22db 1100 24db 1101 26db 1110 28db 1111 30db
tda7439ds 12/19 table 9. volume selection volume = 0 to 47db/mute table 10. bass selection msb lsb volume d7 d6 d5 d4 d3 d2 d1 d0 1db steps 000 0db 001 -1db 010 -2db 011 -3db 100 -4db 101 -5db 110 -6db 111 -7db 0000 0db 0001 -8db 0 0 1 0 -16db 0 0 1 1 -24db 0 1 0 0 -32db 0 1 0 1 -40db x11 1xxx mute msb lsb bass d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0000 -14db 0001 -12db 0010 -10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1010 10db 1001 12db 1000 14db
13/19 tda7439ds table 11. middle selection table 12. treble selection msb lsb middle d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0000 - 14db 0001 - 12db 0010 - 10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1010 10db 1001 12db 1000 14db msb lsb treble d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0 0 0 0 -14db 0 0 0 1 -12db 0 0 1 0 -10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1010 10db 1001 12db 1000 14db
tda7439ds 14/19 table 13. speaker attenuate selection speaker attenuation = 0 to -79db/mute msb lsb speaker attenuation d7 d6 d5 d4 d3 d2 d1 d0 1db 0 0 0 0db 0 0 1 -1db 0 1 0 -2db 0 1 1 -3db 1 0 0 -4db 1 0 1 -5db 1 1 0 -6db 1 1 1 -7db 0000 0db 0001 -8db 0 0 1 0 -16db 0 0 1 1 -24db 0 1 0 0 -32db 0 1 0 1 -40db 0 1 1 0 -48db 0 1 1 1 -56db 1 0 0 0 -64db 1 0 0 1 -72db 1111xxx mute
15/19 tda7439ds figure 20. pins: 23 figure 21. pins: 26, 27 figure 22. pins 1, 2, 3, 4, 5, 6, 7, 28 figure 23. pins 8, 9 figure 24. pins 11, 16 figure 25. pins 10, 17 20k 20k cref v s d96au430 v s v s d96au434 20 a rout 24 lout 20 a v s 100k v ref d96au425 in v s d96au426 20 a v s mixout gnd 25k v s mout(r) d96au431 20 a mout(l) 25k v s mout(r) d96au431 20 a mout(l)
tda7439ds 16/19 figure 26. pins 12, 14 figure 27. pins 13, 15 figure 28. pins 18, 19 figure 29. pin 21 figure 30. pin 22 44k v s bin(r) d96au428 20 a bin(l) 44k v s bout(r) d96au429 20 a bout(l) 50k v s treble(r) d96au433 20 a treble(l) 44k v s bout(r) d96au429 20 a bout(l) d96au423 20 a sda
17/19 tda7439ds figure 31. so28 mechanical data & package dimensions so-28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data
tda7439ds 18/19 table 14. revision history date revision description of changes january 2004 1 first issue in edocs dms june 2004 2 changed the style-sheet in compliance to the new ?corporate technical pubblications design guide?
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