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lxt9761/9781 fast ethernet 10/100 multi-port transceiver with rmii datasheet the lxt9781 is an eight-port phy fast ethernet transceiver that supports ieee 802.3 physical layer applications at both 10 mbps and 100 mbps. it provides a reduced media independent interface (rmii) for switching and other independent port applications. the lxt9761 offers the same features and functionality in a six-port device. this data sheet uses the singular designation ?lxt97x1? to refer to both devices. all network ports provide a combination twisted-pair (tp) or pseudo-ecl (pecl) interface for a 10/100base-tx or 100base-fx connection. the lxt97x1 provides three discrete led driver outputs for each port, as well as eight global serial led outputs. the device supports both half- and full-duplex operation at 10 mbps and 100 mbps, and requires only a single 3.3v power supply. applications product features 100base-t, 10/100-tx, or 100base-fx switches and multi-port nics. six or eight ieee 802.3-compliant 10base-t or 100base-tx ports with integrated filters 3.3v operation optimized for dual-high stacked r45 applications proprietary optimal signal processing? architecture improves snr by 3 db over ideal analog filters robust baseline wander correction 100base-fx fiber-optic capability on all ports supports both auto-negotiation and legacy systems without auto-negotiation capability jtag boundary scan multiple reduced mii (rmii) ports for independent phy port operation configurable via mdio port or external control pins. maskable interrupts low power consumption (390 mw per port, typical) 208-pin pqfp (lxt9761 and lxt9781) 272-pin pbga (lxt9781 only) as of january 15, 2001, this document replaces the level one document order number: 249048-001 lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii . january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt9761/9781 may contain design defects or errors known as errata which may cause the product to deviate from published spe cifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 contents 1.0 pin assignments and signal descriptions ....................................................10 2.0 functional description ...........................................................................................21 2.1 introduction..........................................................................................................21 2.1.1 osp ? architecture ................................................................................21 2.1.2 comprehensive functionality .................................................................21 2.2 interface descriptions..........................................................................................22 2.2.1 10/100 network interface .......................................................................22 2.2.1.1 twisted-pair interface ...............................................................22 2.2.1.2 fiber interface ...........................................................................23 2.2.2 rmii interface.........................................................................................23 2.2.3 configuration management interface .....................................................23 2.2.3.1 mdio management interface ....................................................23 2.2.3.2 hardware control interface .......................................................25 2.3 operating requirements .....................................................................................25 2.3.1 power requirements..............................................................................25 2.3.2 clock requirements ...............................................................................26 2.3.2.1 reference clock ........................................................................26 2.4 initialization..........................................................................................................26 2.4.1 mdio control mode ...............................................................................26 2.4.2 hardware control mode .........................................................................26 2.4.3 power-down mode.................................................................................27 2.4.3.1 global (hardware) power down................................................27 2.4.3.2 port (software) power down .....................................................27 2.4.4 reset ......................................................................................................28 2.4.5 hardware configuration settings ...........................................................28 2.5 link establishment ..............................................................................................29 2.5.1 auto-negotiation.....................................................................................29 2.5.1.1 base page exchange................................................................29 2.5.1.2 next page exchange.................................................................29 2.5.1.3 controlling auto-negotiation .....................................................29 2.5.2 parallel detection ...................................................................................30 2.6 rmii operation ....................................................................................................30 2.6.1 reference clock.....................................................................................31 2.6.2 transmit enable .....................................................................................31 2.6.3 carrier sense & data valid ....................................................................31 2.6.4 receive error .........................................................................................31 2.6.5 loopback................................................................................................31 2.6.6 out of band signalling............................................................................31 2.6.7 4b/5b coding operations.......................................................................32 2.7 100 mbps operation............................................................................................32 2.7.1 100base-x network operations ...........................................................32 2.7.2 100base-x protocol sublayer operations ............................................33 2.7.2.1 pcs sublayer ............................................................................33 2.7.2.2 pma sublayer ...........................................................................35 2.7.2.3 twisted-pair pmd sublayer ......................................................36 2.7.2.4 fiber pmd sublayer ..................................................................37
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 4 datasheet 2.8 10 mbps operation.............................................................................................. 37 2.8.1 preamble handling................................................................................. 37 2.8.2 dribble bits............................................................................................. 38 2.8.3 link test................................................................................................. 38 2.8.3.1 link failure................................................................................ 38 2.8.4 jabber .................................................................................................... 38 2.9 monitoring operations......................................................................................... 38 2.9.1 monitoring auto-negotiation................................................................... 38 2.9.2 serial led functions ............................................................................. 38 2.9.3 per-port led driver functions............................................................... 40 2.9.3.1 led pulse stretching ................................................................ 40 2.9.4 using the quick status register ............................................................ 41 2.9.5 out-of-band signalling ........................................................................... 42 2.10 boundary scan (jtag1149.1) functions ........................................................... 42 2.10.1 boundary scan interface........................................................................ 42 2.10.2 state machine ........................................................................................ 42 2.10.3 instruction register ................................................................................ 43 2.10.4 boundary scan register ........................................................................ 43 3.0 application information ......................................................................................... 44 3.1 design recommendations .................................................................................. 44 3.1.1 general design guidelines .................................................................... 44 3.1.2 power supply filtering ........................................................................... 44 3.1.3 power and ground plane layout considerations .................................. 45 3.1.3.1 chassis ground......................................................................... 45 3.1.4 rmii terminations .................................................................................. 45 3.1.5 the rbias pin ....................................................................................... 45 3.1.6 the twisted-pair interface ..................................................................... 46 3.1.6.1 magnetics information ............................................................... 46 3.1.7 the fiber interface................................................................................. 46 3.2 typical application circuits ................................................................................. 46 4.0 test specifications .................................................................................................. 52 5.0 register definitions ................................................................................................ 62 6.0 package specifications ......................................................................................... 77
datasheet 5 fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 figures 1 lxt9781 block diagram ....................................................................................... 9 2 lxt9781 pqfp pin assignments .......................................................................10 3 lxt9781 pbga pin assignments ......................................................................11 4 lxt9761 pqfp pin assignments .......................................................................12 5 lxt97x1 interfaces ............................................................................................22 6 port address scheme .........................................................................................24 7 management interface read frame structure ...................................................24 8 management interface write frame structure ...................................................24 9 interrupt logic .....................................................................................................25 10 initialization sequence .......................................................................................27 11 hardware control settings .................................................................................28 12 auto-negotiation operation ................................................................................30 13 loopback paths ..................................................................................................31 14 rmii data flow ...................................................................................................32 15 100base-x frame format ................................................................................33 16 protocol sublayers .............................................................................................34 17 serial led streams.............................................................................................39 18 led pulse stretching ..........................................................................................41 19 quick status register..........................................................................................41 20 rmii programmable out of band signalling .......................................................42 21 power and ground supply connections ............................................................47 22 typical twisted-pair interface ............................................................................48 23 typical fiber interface ........................................................................................49 24 typical rmii interface ........................................................................................50 25 typical serial led interface................................................................................51 26 100base-tx receive timing ...........................................................................55 27 100base-tx transmit timing ..........................................................................55 28 100base-fx receive timing ...........................................................................56 29 100base-fx transmit timing ..........................................................................57 30 10base-t receive timing ................................................................................57 31 10base-t transmit timing ...............................................................................58 32 auto-negotiation and fast link pulse timing ...................................................59 33 fast link pulse timing .......................................................................................59 34 mdio write timing (mdio sourced by mac) ....................................................60 35 mdio read timing (mdio sourced by phy) ....................................................60 36 power-up timing ................................................................................................61 37 reset and power-down recovery timing ......................................................61 38 phy identifier bit mapping .................................................................................67 39 lxt97x1 pqfp specification .............................................................................77 40 lxt9781 pbga specification .............................................................................78 tables 1 lxt97x1 rmii signal descriptions......................................................................13 2 lxt97x1 signal detect/tp select signal descriptions .......................................15 3 lxt97x1 network interface signal descriptions .................................................16 4 lxt97x1 jtag test signal descriptions ............................................................16 5 lxt97x1 miscellaneous signal descriptions ......................................................17
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 6 datasheet 6 lxt97x1 power supply signal descriptions....................................................... 18 7 lxt97x1 led signal descriptions ...................................................................... 19 8 unused pins........................................................................................................ 20 9 hardware configuration settings ........................................................................ 29 10 4b/5b coding ...................................................................................................... 34 11 bsr mode of operation ...................................................................................... 43 12 supported jtag instructions .............................................................................. 43 13 device id register .............................................................................................. 43 14 magnetics requirements .................................................................................... 46 15 absolute maximum ratings ................................................................................ 52 16 operating conditions .......................................................................................... 52 17 digital i/o characteristics 1................................................................................. 52 18 digital i/o characteristics - rmii pins ................................................................. 53 19 required clock characteristics........................................................................... 53 20 100base-tx transceiver characteristics .......................................................... 53 21 100base-fx transceiver characteristics .......................................................... 54 22 10base-t transceiver characteristics............................................................... 54 23 100base-tx receive timing parameters ......................................................... 55 24 100base-tx transmit timing parameters ........................................................ 56 25 100base-fx receive timing parameters ......................................................... 56 26 100base-fx transmit timing parameters ........................................................ 57 27 10base-t receive timing parameters.............................................................. 58 28 10base-t transmit timing parameters............................................................. 58 29 auto-negotiation and fast link pulse timing parameters ................................. 59 30 mdio timing parameters ................................................................................... 60 31 power-up timing parameters............................................................................ 61 32 reset and power-down recovery timing parameters ................................... 61 33 register set ........................................................................................................ 62 34 register bit map.................................................................................................. 63 35 control register (address 0)............................................................................... 65 36 status register (address 1) ................................................................................ 65 37 phy identification register 1 (address 2)........................................................... 66 38 phy identification register 2 (address 3)........................................................... 67 39 auto-negotiation advertisement register (address 4) ....................................... 67 40 auto-negotiation link partner base page ability register (address 5) .............. 68 41 auto-negotiation expansion (address 6) ............................................................ 69 42 auto-negotiation next page transmit register (address 7)............................... 69 43 auto-negotiation link partner next page receive register (address 8) ........... 70 44 port configuration register (address 16, hex 10) .............................................. 70 45 quick status register (address 17, hex 11) ...................................................... 71 46 interrupt enable register (address 18, hex 12) ................................................. 72 47 interrupt status register (address 19, hex 13) .................................................. 73 48 led configuration register (address 20, hex 14) ............................................. 74 49 out of band signaling register (address 25) ..................................................... 75 50 transmit control register #1 (address 28)......................................................... 76 51 transmit control register #2 (address 30)......................................................... 76
datasheet 7 fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 revision history revision date description

fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 9 figure 1. lxt9781 block diagram decoder & descrambler rxd n _0 + - + - serial to parallel converter scrambler & encoder txd n_0 parallel/serial converter txen n carrier sense data valid error detect rxer n crs_dv n auto negotiation osp tm adaptive eq with baseline wander cancellation pwr supply / pwrdown manchester decoder manchester encoder 10 100 10 100 media select port 0 port 1 port 2 port 3 management / mode select logic rmii rmii per-port functions tp driver tp / fiber out 8 qstat add<4:0> mdio mdc qclk mdint port 4 port 5 global functions cim tx pcs rx pcs mgmt counters txd n_1 rxd n _1 ecl driver tpfon n tpfop n tpfin n tpfip n pwrdwn refclk vcc gnd leds<7:0> ledlatch ledclk sd n /tx n reset register set register set clock generator clock generator + - 100tx + - 100fx + - 10bt tp / fiber in port 6 port 7 osp tm pulse shaper osp tm slicer
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 10 datasheet 1.0 pin assignments and signal descriptions figure 2. lxt9781 pqfp pin assignments 1. ports 6 and 7 are available only on the lxt9781. these ports are not bonded out on the lxt9761. package topside markings marking definition part # lxt9781 is the unique identifier for this product family. rev # identifies the particular silicon ? stepping ? (refer to specification update for additional stepping information.) lot # identifies the batch. fpo # identifies the finish process order. gndd .......1 rxd7_1 .......2 rxd7_0 .......3 crs_dv7 .......4 rxer7 .......5 txen7 .......6 txd7_0 .......7 txd7_1 .......8 rxd6_1 .......9 rxd6_0 .......10 crs_dv6 .......11 rxer6 .......12 txen6 .......13 txd6_0 .......14 vccio .......15 gndd .......16 txd6_1 .......17 rxd5_1 .......18 rxd5_0 .......19 crs_dv5 .......20 rxer5 ......21 txen5 .......22 txd5_0 .......23 txd5_1 .......24 rxd4_1 .......25 rxd4_0 .......26 crs_dv4 .......27 rxer4 .......28 txen4 .......29 txd4_0 .......30 vccio .......31 gndd .......32 txd4_1 .......33 rxd3_1 .......34 rxd3_0 .......35 crs_dv3 .......36 rxer3 .......37 txen3 .......38 txd3_0 .......39 txd3_1 .......40 rxd2_1 .......41 rxd2_0 .......42 crs_dv2 .......43 rxer2 .......44 txen2 .......45 txd2_0 .......46 txd2_1 .......47 gndd .......48 gndd .......49 gndd .......50 gndd .......51 vccio .......52 156 ..........tpfin7 155 ..........vccr 154 ..........tpfop7 153 ..........tpfon7 152 ..........gnda 151 ..........tpfon6 150 ..........tpfop6 149 ..........vcct 148 ..........vccr 147 ..........tpfin6 146 ..........tpfip6 145 ..........gnda 144 ..........gnda 143 ..........tpfip5 142 ..........tpfin5 141 ..........vccr 140 ..........tpfop5 139 ..........tpfon5 138 ..........gnda 137 ..........tpfon4 136 ..........tpfop4 135 ..........vcct 134 ..........vccr 133 ..........tpfin4 132 ..........tpfip4 131 ..........gnda 130 ..........gnda 129 ..........tpfip3 128 ..........tpfin3 127 ..........vccr 126 ..........vcct 125 ..........tpfop3 124 ..........tpfon3 123 ..........gnda 122 ..........tpfon2 121 ..........tpfop2 120 ..........vccr 119 ..........tpfin2 118 ..........tpfip2 117 ..........gnda 116 ..........gnda 115 ..........tpfip1 114 ..........tpfin1 113 ..........vccr 112 ..........vcct 111 ..........tpfop1 110 ..........tpfon1 109 ..........gnda 108 ..........tpfon0 107 ..........tpfop0 106 ..........vccr 105 ..........tpfin0 208 ..........vccio 207 ..........qclk 206 ..........qstat 205 ..........led/cfg0_3 204 ..........led/cfg0_2 203 ..........led/cfg0_1 202 ..........led/cfg1_3 201 ..........led/cfg1_2 200 ..........led/cfg1_1 199 ..........led/cfg2_3 198 ..........led/cfg2_2 197 ..........led/cfg2_1 196 ..........led/cfg3_3 195 ..........led/cfg3_2 194 ..........led/cfg3_1 193 ..........vccio 192 ..........gndd 191 ..........led/cfg4_3 190 ..........led/cfg4_2 189 ..........led/cfg4_1 188 ..........led/cfg5_3 187 ..........led/cfg5_2 186 ..........led/cfg5_1 185 ..........led/cfg6_3 184 ..........led/cfg6_2 183 ..........led/cfg6_1 182 ..........led/cfg7_3 181 ..........led/cfg7_2 180 ..........led/cfg7_1 179 ..........vccd 178 ..........gndd 177 ..........leds0 176 ..........leds1 175 ..........leds2 174 ..........leds3 173 ..........leds4 172 ..........leds5 171 ..........leds6 170 ..........leds7 169 ..........ledlatch 168 ..........ledclk 167 .......... trst 166 ..........tck 165 ..........tms 164 ..........tdo 163 ..........tdi 162 ..........sd/tp4 161 ..........sd/tp5 160 ..........sd/tp6 159 ..........sd/tp7 158 ..........gnda 157 ..........tpfip7 gndd ...... 53 rxd1_1 ...... 54 rxd1_0 ...... 55 crs_dv1 ...... 56 rxer1 ...... 57 txen1 ...... 58 txd1_0 ...... 59 txd1_1 ...... 60 rxd0_1 ...... 61 rxd0_0 ...... 62 crs_dv0 ...... 63 rxer0 ...... 64 txen0 ...... 65 txd0_0 ...... 66 vccio ...... 67 gndd ...... 68 txd0_1 ...... 69 mdc ...... 70 mdio ...... 71 gndd ...... 72 gndd ...... 73 gndd ...... 74 gndd ...... 75 txslew_0 ...... 76 txslew_1 ...... 77 gnds ...... 78 pause ...... 79 vccd ...... 80 gndd ...... 81 pwrdwn ...... 82 reset ...... 83 mdint ...... 84 mddis ...... 85 gndd ...... 86 gndd ...... 87 vccd ...... 88 gndd ...... 89 gndd ...... 90 gndd ...... 91 refclk ...... 92 add_0 ...... 93 add_1 ...... 94 add_2 ...... 95 add_3 ...... 96 add_4 ...... 97 sd/tp3 ...... 98 sd/tp2 ...... 99 sd/tp1 ...... 100 sd/tp0 ...... 101 rbias ...... 102 gnda ...... 103 tpfip0 ...... 104 lxt9781 xx xxxxxx xxxxxxxx part # lot # fpo # rev #
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 11 figure 3. lxt9781 pbga pin assignments 1. ports 6 and 7 are available only on the lxt9781. rxd3 _1 crs_ dv3 rxd3 _0 tp fop3 rxd2 _1 crs_ dv2 rxd2 _0 tp fip2 gnda n/c n/c n/c gndd rxd0 _0 n/c n/c rxd0 _1 gndd gndd vccr gnda gnda n/c qclk n/c gndd tp fin7 sd6/ tp6 vccd tp fip7 trst vcct rxd7 _1 gndd rxd7 _0 tp fop6 tdo gndd txd3 _0 gndd txd3 _1 tp fop2 tp fon2 gnda txd2 _1 txd2 _0 vcct vccr gnda n/c gndd txd0 _0 rxd1 _1 txd1 _1 gnds crs_ dv0 mdc gndd n/c gndd gndd vccd tp fon7 led clk sd5/ tp5 vccd tp fop7 tms vcct txd7 _0 txd7 _1 tp fip6 tck leds _0 rxd6 _1 rxd6 _0 gndd gndd vcct vccr gnda gndd txd6 _1 gndd tp fop5 txd5 _0 gndd txd5 _1 gndd gndd vccr gndd tp fip4 txd4 _0 gndd gndd gndd gnda gndd vcct gnda n/c crs_ dv1 vccd n/c rxd1 _0 n/c vccd vccd gndd tp fip0 gndd gndd tp fin0 gndd vcct txd6 _0 tp fin5 tp fip5 gnda rxd5 _1 rxd5 _0 gndd crs_ dv5 vccr tp fon4 gndd rxd4 _0 gndd rxd4 _1 crs_ dv4 gndd gndd gnda gndd vcct gndd gndd gndd gndd gndd gndd vccr gndd tp fip3 n/c n/c gndd gndd txd1 _0 mdio gndd gndd tp fop0 gndd tp fon0 vcct 1 2 3 4 5 6 7 8 9 1011121314151617181920 1 2 3 4 5 6 7 8 9 1011121314151617181920 a b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y mdint refclk mddis gnda sd0/ tp0 sd3/ tp3 sd4/ tp4 gnda sd7/ tp7 tp fon1 tp fin2 tp fin3 tp fin4 gnda tp fin6 gnda tp fop1 gnda vccr gnda gnda tp fop4 gnda tp fon6 vcct gnda vcct vcct gnda gnda vccr gnda gnda tp fon3 gnda gnda tp fon5 vcct gnda txslew_0 txslew_1 pause pwrdwn reset add_0 add_3 add_4 rbias qstat vccio vccio led/ cfg4_1 vccio txd4_1 gndd txd0_1 leds_4 leds_1 leds_2 leds_3 led latch leds_5 leds_6 leds_7 tdi led/ cfg0_1 led/ cfg0_2 led/ cfg0_3 led/ cfg1_1 led/ cfg1_2 led/ cfg1_3 led/ cfg2_1 led/ cfg2_2 led/ cfg2_3 led/ cfg3_1 led/ cfg3_2 led/ cfg3_3 led/ cfg6_3 led/ cfg4_2 led/ cfg4_3 led/ cfg5_1 led/ cfg5_2 led/ cfg5_3 led/ cfg6_1 led/ cfg6_2 led/ cfg7_2 gndd led/ cfg7_1 led/ cfg7_3 crs_dv7 rxer7 txen7 crs_dv6 rxer6 txen6 rxer4 txen4 vccio rxer5 txen5 rxer3 txen3 rxer2 txen2 sd2/ tp2 sd1/ tp1 tp fin1 tp fip1 add_1 add_2 rxer1 txen1 rxer0 txen0 vccio vccio top view lxt9781bc
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 12 datasheet figure 4. lxt9761 pqfp pin assignments 1. ports 6 and 7 are available only on the lxt9781. package topside markings marking definition part # lxt9761 is the unique identifier for this product family. rev # identifies the particular silicon ? stepping ? (refer to specification update for additional stepping information.) lot # identifies the batch. fpo # identifies the finish process order. gndd ...... 1 rxd5_1 ...... 2 rxd5_0 ...... 3 crs_dv5 ...... 4 rxer5 ...... 5 txen5 ...... 6 txd5_0 ...... 7 txd5_1 ...... 8 rxd4_1 ...... 9 rxd4_0 ...... 10 crs_dv4 ...... 11 rxer4 ...... 12 txen4 ...... 13 txd4_0 ...... 14 vccio ...... 15 gndd ...... 16 txd4_1 ...... 17 rxd3_1 ...... 18 rxd3_0 ...... 19 crs_dv3 ...... 20 rxer3 ...... 21 txen3 ...... 22 txd3_0 ...... 23 txd3_1 ...... 24 n/c ...... 25 n/c ...... 26 n/c ...... 27 n/c ...... 28 n/c ...... 29 n/c ...... 30 vccio ...... 31 gndd ...... 32 n/c ...... 33 n/c ...... 34 n/c ...... 35 n/c ...... 36 n/c ...... 37 n/c ...... 38 n/c ...... 39 n/c ...... 40 rxd2_1 ...... 41 rxd2_0 ...... 42 crs_dv2 ...... 43 rxer2 ...... 44 txen2 ...... 45 txd2_0 ...... 46 txd2_1 ...... 47 gndd ...... 48 gndd ...... 49 gndd ...... 50 gndd ...... 51 vccio ...... 52 156 ..........tpfin5 155 ..........vccr 154 ..........tpfop5 153 ..........tpfon5 152 ..........gnda 151 ..........tpfon4 150 ..........tpfop4 149 ..........vcct 148 ..........vccr 147 ..........tpfin4 146 ..........tpfip4 145 ..........gnda 144 ..........gnda 143 ..........tpfip3 142 ..........tpfin3 141 ..........vccr 140 ..........tpfop3 139 ..........tpfon3 138 ..........gnda 137 ..........n/c 136 ..........n/c 135 ..........n/c 134 ..........n/c 133 ..........n/c 132 ..........n/c 131 ..........n/c 130 ..........n/c 129 ..........n/c 128 ..........n/c 127 ..........n/c 126 ..........n/c 125 ..........n/c 124 ..........n/c 123 ..........gnda 122 ..........tpfon2 121 ..........tpfop2 120 ..........vccr 119 ..........tpfin2 118 ..........tpfip2 117 ..........gnda 116 ..........gnda 115 ..........tpfip1 114 ..........tpfin1 113 ..........vccr 112 ..........vcct 111 ..........tpfop1 110 ..........tpfon1 109 ..........gnda 108 ..........tpfon0 107 ..........tpfop0 106 ..........vccr 105 ..........tpfin0 208 ..........vccio 207 ..........qclk 206 ..........qstat 205 ..........led/cfg0_3 204 ..........led/cfg0_2 203 ..........led/cfg0_1 202 ..........led/cfg1_3 201 ..........led/cfg1_2 200 ..........led/cfg1_1 199 ..........led/cfg2_3 198 ..........led/cfg2_2 197 ..........led/cfg2_1 196 ..........n/c 195 ..........n/c 194 ..........n/c 193 ..........vccio 192 ..........gndd 191 ..........n/c 190 ..........n/c 189 ..........n/c 188 ..........led/cfg3_3 187 ..........led/cfg3_2 186 ..........led/cfg3_1 185 ..........led/cfg4_3 184 ..........led/cfg4_2 183 ..........led/cfg4_1 182 ..........led/cfg5_3 181 ..........led/cfg5_2 180 ..........led/cfg5_1 179 ..........vccd 178 ..........gndd 177 ..........leds0 176 ..........leds1 175 ..........leds2 174 ..........leds3 173 ..........leds4 172 ..........leds5 171 ..........leds6 170 ..........leds7 169 ..........ledlatch 168 ..........ledclk 167 .......... trst 166 ..........tck 165 ..........tms 164 ..........tdo 163 ..........tdi 162 ..........n/c 161 ..........sd/tp3 160 ..........sd/tp4 159 ..........sd/tp5 158 ..........gnda 157 ..........tpfip5 gndd .......53 rxd1_1 .......54 rxd1_0 .......55 crs_dv1 .......56 rxer1 .......57 txen1 .......58 txd1_0 .......59 txd1_1 .......60 rxd0_1 .......61 rxd0_0 .......62 crs_dv0 .......63 rxer0 .......64 txen0 .......65 txd0_0 .......66 vccio .......67 gndd .......68 txd0_1 .......69 mdc .......70 mdio .......71 gndd .......72 gndd .......73 gndd .......74 gndd .......75 txslew_0 .......76 txslew_1 .......77 gnds .......78 pause .......79 vccd .......80 gndd .......81 pwrdwn .......82 reset .......83 mdint .......84 mddis .......85 vccd .......86 gndd .......87 vccd .......88 gndd .......89 gndd .......90 gndd .......91 refclk .......92 add_0 .......93 add_1 .......94 add_2 .......95 add_3 .......96 add_4 .......97 n/c .......98 sd/tp2 .......99 sd/tp1 .......100 sd/tp0 .......101 rbias .......102 gnda .......103 tpfip0 .......104 lxt9761 xx xxxxxx xxxxxxxx part # lot # fpo # rev
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 13 table 1. lxt97x1 rmii signal descriptions 9761 pin# 9781 pin# symbol type 1 signal description 2, 3 pqfp pqfp pbga rmii data interface pins 92 92 y15 refclk i reference clock . 50 mhz rmii reference clock is required at this pin. the lxt97x1 samples rmii inputs on the rising edge of refclk, and drives rmii outputs on the falling edge. 66 69 66 69 v7 w7 txd0_0 txd0_1 i transmit data - port 0 . inputs containing 2-bit parallel di-bits to be transmitted from port 0 are clocked in synchronously to refclk. 59 60 59 60 w4 v4 txd1_0 txd1_1 i transmit data - port 1 . inputs containing 2-bit parallel di-bits to be transmitted from port 1 are clocked in synchronously to refclk. 46 47 46 47 t2 t3 txd2_0 txd2_1 i transmit data - port 2 . inputs containing 2-bit parallel di-bits to be transmitted from port 2 are clocked in synchronously to refclk. 23 24 39 40 p3 p4 txd3_0 txd3_1 i transmit data - port 3 . inputs containing 2-bit parallel di-bits to be transmitted from port 3 are clocked in synchronously to refclk. 14 17 30 33 l3 l4 txd4_0 txd4_1 i transmit data - port 4 . inputs containing 2-bit parallel di-bits to be transmitted from port 4 are clocked in synchronously to refclk. 7 8 23 24 j3 j4 txd5_0 txd5_1 i transmit data - port 5 . inputs containing 2-bit parallel di-bits to be transmitted from port 5 are clocked in synchronously to refclk. ? 14 17 f4 g2 txd6_0 txd6_1 i transmit data - port 6 . inputs containing 2-bit parallel di-bits to be transmitted from port 6 are clocked in synchronously to refclk. ? 7 8 d3 d4 txd7_0 txd7_1 i transmit data - port 7 . inputs containing 2-bit parallel di-bits to be transmitted from port 7 are clocked in synchronously to refclk. 65 58 45 22 13 6 ? ? 65 58 45 38 29 22 13 6 y5 w3 t1 p1 l2 j2 f3 d2 txen0 txen1 txen2 txen3 txen4 txen5 txen6 txen7 i transmit enable - ports 0 - 7 . active high input enables respective port transmitter. this signal must be synchronous to the refclk. 62 61 62 61 u7 u6 rxd0_0 rxd0_1 o receive data - port 0 . receive data signals (2-bit parallel di- bits) are driven synchronously to refclk. 55 54 55 54 y2 v2 rxd1_0 rxd1_1 o receive data - port 1 . receive data signals (2-bit parallel di- bits) are driven synchronously to refclk. 1. type column coding: i = input, o = output, od = open drain 2. the lxt97x1 supports the 802.3 mdio register set. specific bits in the registers are referenced using an ? x.y ? notation, where x is the register number (0-32) and y is the bit number (0-15). 3. ports 6 and 7 are available only on the lxt9781. these pins are not bonded out on the lxt9761.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 14 datasheet 42 41 42 41 r2 r1 rxd2_0 rxd2_1 o receive data - port 2 . receive data signals (2-bit parallel di- bits) are driven synchronously to refclk. 19 18 35 34 n2 n1 rxd3_0 rxd3_1 o receive data - port 3 . receive data signals (2-bit parallel di- bits) are driven synchronously to refclk. 10 9 26 25 k3 k2 rxd4_0 rxd4_1 o receive data - port 4 . receive data signals (2-bit parallel di- bits) are driven synchronously to refclk. 3 2 19 18 h3 h1 rxd5_0 rxd5_1 o receive data - port 5 . receive data signals (2-bit parallel di-bits) are driven synchronously to refclk. ? ? 10 9 e3 e1 rxd6_0 rxd6_1 o receive data - port 6 . receive data signals (2-bit parallel di- bits) are driven synchronously to refclk. ? ? 3 2 c2 c1 rxd7_0 rxd7_1 o receive data - port 7 . receive data signals (2-bit parallel di-bits) are driven synchronously to refclk. 63 56 43 20 11 4 ? ? 63 56 43 36 27 20 11 4 v6 y3 r3 n3 k4 h4 f1 b3 crs_dv0 crs_dv1 crs_dv2 crs_dv3 crs_dv4 crs_dv5 crs_dv6 crs_dv7 o carrier sense/receive data valid - ports 0 - 7 . on detection of valid carrier, these signals are asserted asynchronously with respect to refclk. crs_dv n is deasserted on loss of carrier, synchronous to refclk. 64 57 44 21 12 5 ? ? 64 57 44 37 28 21 12 5 w6 v3 r4 n4 l1 j1 f2 d1 rxer0 rxer1 rxer2 rxer3 rxer4 rxer5 rxer6 rxer7 o receive error - ports 0 - 7 . these signals are synchronous to the respective refclk. active high indicates that received code group is invalid, or that pll is not locked. table 1. lxt97x1 rmii signal descriptions (continued) 9761 pin# 9781 pin# symbol type 1 signal description 2, 3 pqfp pqfp pbga 1. type column coding: i = input, o = output, od = open drain 2. the lxt97x1 supports the 802.3 mdio register set. specific bits in the registers are referenced using an ? x.y ? notation, where x is the register number (0-32) and y is the bit number (0-15). 3. ports 6 and 7 are available only on the lxt9781. these pins are not bonded out on the lxt9761.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 15 rmii control interface pins 70 70 v8 mdc i management data clock . clock for the mdio serial data channel. maximum frequency is 8 mhz. 71 71 w8 mdio i/o management data input/output . bidirectional serial data channel for phy/sta communication. 84 84 u12 mdint od management data interrupt . when bit 18.1 = 1, an active low output on this pin indicates status change. interrupt is cleared when register 19 is read. 85 85 y12 mddis i management disable . when mddis is high, the mdio is disabled from read and write operations. when mddis is low at power up or reset, the hardware control interface pins control only the initial or ? default ? values of their respective register bits. after the power-up/ reset cycle is complete, bit control reverts to the mdio serial channel. table 2. lxt97x1 signal detect/tp select signal descriptions 9761 pin# 9781 pin# symbol type 1 signal description 2 pqfp pqfp pbga 101 100 99 161 160 159 ? ? 101 100 99 98 162 161 160 159 v16 u13 u14 u15 c16 b17 a17 c17 sd0/tp0 sd1/tp1 sd2/tp2 sd3/tp3 sd4/tp4 sd5/tp5 sd6/tp6 sd7/tp7 i signal detect - ports 0 - 7 . tying the sd/tp n pins high or to a pecl input sets bit 16.0 = 1 and the respective port is forced to fx mode. in the absence of an active link, the pin must be pulled high to enable loopback in fx mode. do not enable auto-negotiation if fx mode is selected. the sd/tp n pins have internal pull-downs. when not using fx mode, sd/tp n pins should be tied to gnda. tp select - ports 0 - 7 . tying the sd/tp n pins low sets bit 16.0 = 0 and forces the respective port to tp mode. 1. type column coding: i = input, o = output. 2. ports 6 and 7 are available only on the lxt9781. these pins are not bonded out on the lxt9761. table 1. lxt97x1 rmii signal descriptions (continued) 9761 pin# 9781 pin# symbol type 1 signal description 2, 3 pqfp pqfp pbga 1. type column coding: i = input, o = output, od = open drain 2. the lxt97x1 supports the 802.3 mdio register set. specific bits in the registers are referenced using an ? x.y ? notation, where x is the register number (0-32) and y is the bit number (0-15). 3. ports 6 and 7 are available only on the lxt9781. these pins are not bonded out on the lxt9761.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 16 datasheet table 3. lxt97x1 network interface signal descriptions 9761 pin# 9781 pin# symbol type 1 signal description 2 pqfp pqfp pbga 107, 108 111, 110 121, 122 140, 139 150, 151 154, 153 ? , ? ? , ? 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 w19, w20 v20, v19 p19, p20 n20, n19 h19, h20 g20, g19 c19, c20 b20, b19 tpfop0, tpfon0 tpfop1, tpfon1 tpfop2, tpfon2 tpfop3, tpfon3 tpfop4, tpfon4 tpfop5, tpfon5 tpfop6, tpfon6 tpfop7, tpfon7 ao twisted-pair/fiber outputs, positive & negative - ports 0-7. during 100base-tx or 10base-t operation, tpfo pins drive 802.3 compliant pulses onto the line. during 100base-fx operation, tpfo pins produce differential pecl outputs for fiber transceivers. 104, 105 115, 114 118, 119 143, 142 146, 147 157, 156 ? , ? ? , ? 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 y19, y20 u20, u19 r19, r20 m20, m19 j20, j19 f20, f19 d19, d20 a20, a19 tpfip0, tpfin0 tpfip1, tpfin1 tpfip2, tpfin2 tpfip3, tpfin3 tpfip4, tpfin4 tpfip5, tpfin5 tpfip6, tpfin6 tpfip7, tpfin7 ai twisted-pair/fiber inputs, positive & negative - ports 0-7. during 100base-tx or 10base-t operation, tpfi pins receive differential 100base-tx or 10base-t signals from the line. during 100base-fx operation, tpfi pins receive differential pecl inputs from fiber transceivers. 1. type column coding: i = input, o = output. 2. ports 6 and 7 are available only on the lxt9781. these pins are not bonded out on the lxt9761. table 4. lxt97x1 jtag test signal descriptions pqfp pin# 1 9781 pbga pin# symbol type 2 signal description 163 d14 tdi i, ip test data input . test data sampled with respect to the rising edge of tck. 164 c15 tdo o test data output . test data driven with respect to the falling edge of tck. 165 b16 tms i, ip test mode select . 166 d15 tck i, id test clock . clock input for jtag test (refclk). 167 a16 trst i, ip test reset . reset input for jtag test. 1. pin numbers apply to both the lxt9761 and the lxt9781. 2. type column coding: i = input, o = output, ip = weak internal pull-up, id = weak internal pull-down.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 17 table 5. lxt97x1 miscellaneous signal descriptions pqfp pin# 1 9781 pbga pin# symbol type 2 signal description 3 76 77 y8 u10 txslew_0 txslew_1 i tx output slew controls 0 and 1 . these pins select the tx output slew rate (rise and fall time) as follows: txslew_1 txslew_0 slew rate (rise and fall time) 0 0 2.5 ns 0 1 3.1 ns 1 0 3.7 ns 1 1 4.3 ns 79 w10 pause i pause . sets the default value of bit 4.10 (pause). when high, the lxt97x1 advertises pause capabilities on all ports during auto- negotiation. 82 w12 pwrdwn i power-down . when high, forces the lxt97x1 into global power-down mode. refer to ? power-down mode ? on page 27 for more information. 83 v12 reset i reset . this active low input is or ? ed with the control register reset bit (0.15). when held low, all outputs are forced to inactive state. 97 96 95 94 93 w16 v15 v13 v14 w15 add_4 add_3 add_2 add_1 add_0 i i i i i address <4:0> . sets base address. each port adds its port number (starting with 0) to this address to determine its phy address. port 0 address = base + 0. port 1 address = base + 1. port 2 address = base + 2. port 3 address = base + 3. port 4 address = base + 4. port 5 address = base + 5. port 6 address = base + 6 (lxt9781 only). port 7 address = base + 7 (lxt9781 only). 102 v17 rbias ai bias . this pin provides bias current for the internal circuitry. must be tied to ground through a 22.1 k ? 1% resistor. 206 b4 qstat o quick status . provides continuous phy status updates, without the need for constant polling. 207 a3 qclk i quick clock . clock used for sending out qstat information. maximum frequency is 25 mhz. 1. pin numbers apply to both the lxt9761 and the lxt9781. 2. type column coding: i = input, o = output, a = analog, ip = weak internal pull-up, id = weak internal pull-down. 3. the lxt97x1 supports the 802.3 mdio register set. specific bits in the registers are referenced using an ? x.y ? notation, where x is the register number (0-32) and y is the bit number (0-15).
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 18 datasheet table 6. lxt97x1 power supply signal descriptions pqfp pin# 1 9781 pbga pin# symbol type signal description lxt9761/81: 80, 88, 179 a12, b11, b12, y9, y10, y11 vccd - digital power supply - core. +3.3v supply for core digital circuits. lxt9761 only: 86 15, 31, 52, 67, 193, 208 c4, d5, g1, m1, v1, y6 vccio - digital power supply - i/o ring. +3.3v supply for digital i/o circuits. regardless of the io supply, digital i/o pins remain tolerant of 5v signal levels. lxt9761/81: 106, 113, 120, 141, 148, 155 d17, e17, h17, j17, m17, n17, t17, u17 vccr - analog power supply. +3.3v supply for all analog receive circuits. lxt9781 only: 127, 134 lxt9761/81: 112, 149 a18, b18, e19, e20, k19, k20, l19, l20, t19, t20, w18, y18 vcct - analog power supply. +3.3v supply for all analog transmit circuits. lxt9781 only: 126, 135 lxt9761/81: 1, 16, 32, 48-51, 53, 68, 72-75, 81, 87, 89, 90, 91, 178, 192 a4, b2, b8, c3, c12, d11, e2, e4, g3, g4, h2, j9 - j12, k1, k9 - k12, l9 - l12, m2, m3, m4, m9 - m12, p2, t4, u5, u8, u11, v5, v11, w2, w5, w11,w13, w14, y13, y14, y16, y17 gndd - digital ground . ground return for both core and i/o digital supplies (vccd and vccio). all ground pins can be tied together using a single ground plane. lxt9781 only: 86 103, 109, 116, 117, 123, 138, 144, 145, 152, 158 (lxt9761 and lxt9781) c18, d16, d18, e18, f17, f18, g17, g18, h18, j18, k17, k18, l17, l18, m18, n18, p17, p18, r17, r18, t18, u16, u18, v18, w17 gnda - analog ground . ground return for analog supply. all ground pins can be tied together using a single ground plane. 130, 131 (lxt9781 only) 78 v10 gnds - substrate ground . ground for chip substrate. all ground pins can be tied together using a single ground plane. 1. unless otherwise noted, pin numbers apply to both the lxt9761 and the lxt9781.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 19 table 7. lxt97x1 led signal descriptions 9761 pin# 9781 pin# symbol type 1 signal description 2 pqfp pqfp pbga 177 176 175 174 173 172 171 170 177 176 175 174 173 172 171 170 d12 b13 c13 a14 a13 b14 c14 a15 leds_0 leds_1 leds_2 leds_3 leds_4 leds_5 leds_6 leds_7 o serial leds 0 - 7 . each serial led output indicates a particular status condition for every port. bit 0 is assigned to port 0, bit 1 to port 1, etc. there are 8 possible leds per port, for a total of 48 display leds. however, typical equipment designs use no more than 3 leds per port, selected by the designer. using per-event, rather than per-port outputs reduces the number of serial shift registers required. instead of requiring an external serial- to-parallel shift register for each port, this method requires only one per led type, reducing board space and component costs. refer to ? serial led functions ? on page 38 for details. 168 168 b15 ledclk o led clock. 1 mhz clock for led serial data output. 169 169 d13 ledlatch o led framing. framing signal for serial led outputs. 203 204 205 203 204 205 b5 d6 c5 led/cfg0_1 led/cfg0_2 led/cfg0_3 i/od/os port 0 led drivers 1 -3. these pins drive led indicators for port 0. each led can display one of several available status conditions as selected by the led configuration register (refer to table 48 on page 74 for details). port 0 configuration inputs 1-3. when operating in hardware control mode, these pins also provide configuration control options (refer to table 9 on page 29 for details). 200 201 202 200 201 202 d7 a5 c6 led/cfg1_1 led/cfg1_2 led/cfg1_3 i/od/os port 1 led drivers 1 -3. these pins drive led indicators for port 1. each led can display one of several available status conditions as selected by the led configuration register (refer to table 48 on page 74 for details). port 1 configuration inputs 1-3. when operating in hardware control mode, these pins also provide configuration control options (refer to table 9 on page 29 for details). 197 198 199 197 198 199 c7 a6 b6 led/cfg2_1 led/cfg2_2 led/cfg2_3 i/od/os port 2 led drivers 1 -3. these pins drive led indicators for port 2. each led can display one of several available status conditions as selected by the led configuration register (refer to table 48 on page 74 for details). port 2 configuration inputs 1-3. when operating in hardware control mode, these pins also provide configuration control options (refer to table 9 on page 29 for details). 186 187 188 194 195 196 a7 d8 b7 led/cfg3_1 led/cfg3_2 led/cfg3_3 i/od/os port 3 led drivers 1 -3. these pins drive led indicators for port 3. each led can display one of several available status conditions as selected by the led configuration register (refer to table 48 on page 74 for details). port 3 configuration inputs 1-3. when operating in hardware control mode, these pins also provide configuration control options (refer to table 9 on page 29 for details). 1. type column coding: i = input, o = output, a = analog, od = open drain, os = open source. 2. ports 6 and 7 are available only on the lxt9781. these pins are not bonded out on the lxt9761.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 20 datasheet 183 184 185 189 190 191 c8 a8 d9 led/cfg4_1 led/cfg4_2 led/cfg4_3 i/od/os port 4 led drivers 1 -3. these pins drive led indicators for port 4. each led can display one of several available status conditions as selected by the led configuration register (refer to table 48 on page 74 for details). port 4 configuration inputs 1-3. when operating in hardware control mode, these pins also provide configuration control options (refer to table 9 on page 29 for details). 180 181 182 186 187 188 d10 a9 b9 led/cfg5_1 led/cfg5_2 led/cfg5_3 i/od/os port 5 led drivers 1 -3. these pins drive led indicators for port 5. each led can display one of several available status conditions as selected by the led configuration register (refer to table 48 on page 74 for details). port 5 configuration inputs 1-3. when operating in hardware control mode, these pins also provide configuration control options (refer to table 9 on page 29 for details). ? ? ? 183 184 185 a10 b10 c9 led/cfg6_1 led/cfg6_2 led/cfg6_3 i/od/os port 6 led drivers 1 -3. these pins drive led indicators for port 6. each led can display one of several available status conditions as selected by the led configuration register (refer to table 48 on page 74 for details). port 6 configuration inputs 1-3. when operating in hardware control mode, these pins also provide configuration control options (refer to table 9 on page 29 for details). ? ? ? 180 181 182 c11 c10 a11 led/cfg7_1 led/cfg7_2 led/cfg7_3 i/od/os port 7 led drivers 1 -3. these pins drive led indicators for port 7. each led can display one of several available status conditions as selected by the led configuration register (refer to table 48 on page 74 for details). port 7 configuration inputs 1-3. when operating in hardware control mode, these pins also provide configuration control options (refer to table 9 on page 29 for details). table 8. unused pins lxt9761 pqfp pin# 1 lxt9781 pbga pin# symbol type signal description 25-30, 33-40, 98, 124-137, 162, 189-191, 194-196 a1,a2,b1,u1,u2,u3,u4, u9,v9,w1,w9, y1,y4,y7 n/c ? no connection. these pins should be left unconnected. 1. these pins are used for the two additional ports available on the lxt9781. they are not bonded out on the lxt9761. table 7. lxt97x1 led signal descriptions (continued) 9761 pin# 9781 pin# symbol type 1 signal description 2 pqfp pqfp pbga 1. type column coding: i = input, o = output, a = analog, od = open drain, os = open source. 2. ports 6 and 7 are available only on the lxt9781. these pins are not bonded out on the lxt9761.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 21 2.0 functional description 2.1 introduction the lxt9781 is an eight-port fast ethernet 10/100 transceiver that supports 10 mbps and 100 mbps networks. it complies with all applicable requirements of ieee 802.3. the lxt9781 provides a reduced mii (rmii) for each individual network port to interface with multiple 10/100 macs. each port can directly drive either a 100base-tx line (up to 100 meters) or a 10base-t line (up to 185 meters). the lxt9781 also supports 100base-fx operation via a pseudo-ecl (pecl) interface. the lxt9761 offers the same features and functionality in a six-port device. this data sheet uses the singular designation ? lxt97x1 ? to refer to both devices. 2.1.1 osp? architecture intel's lxt97x1 incorporates high-efficiency optimal signal processing ? design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. the receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 db over an ideal all-analog equalizer. using osp mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional dsp-based receivers (typically complex dsp engines with a/d converters). the result is improved receiver noise and cross-talk performance. the osp architecture also requires substantially less computational logic than traditional dsp- based designs. this lowers power consumption and also reduces the logic switching noise generated by dsp engines clocked at speeds up to 125 mhz. the logic switching noise can be a considerable source of emi generated on the device ? s power supplies. the osp-based lxt97x1 provides improved data recovery, emi performance and power consumption. 2.1.2 comprehensive functionality the lxt97x1 performs all functions of the physical coding sublayer (pcs) and physical media attachment (pma) sublayer as defined in the ieee 802.3 100base-x specification. this device also performs all functions of the physical media dependent (pmd) sublayer for 100base-tx connections. on power-up, the lxt97x1 reads its configuration pins to check for forced operation settings. if not configured for forced operation, each port uses auto-negotiation/parallel detection to automatically determine line operating conditions. if the phy device on the other side of the link supports auto-negotiation, the lxt97x1 will auto-negotiate with it using fast link pulse (flp) bursts. if the phy partner does not support auto-negotiation, the lxt97x1 will automatically detect the presence of either link pulses (10 mbps phy) or idle symbols (100 mbps phy) and set its operating conditions accordingly. the lxt97x1 provides half-duplex and full-duplex operation at 100 mbps and 10 mbps.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 22 datasheet 2.2 interface descriptions 2.2.1 10/100 network interface the lxt97x1 supports both 10base-t and 100base-tx ethernet over twisted-pair, or 100 mbps ethernet over fiber media (100base-fx). each network interface port consists of four external pins (two differential signal pairs). the pins are shared between twisted-pair (tp) and fiber. the lxt97x1 pinout is designed to interface seamlessly with dual-high stacked rj45 connectors. refer to table 3 for specific pin assignments. the lxt97x1 output drivers generate either 100base-tx, 10base-t, or 100base-fx output. when not transmitting data, the lxt97x1 generates 802.3-compliant link pulses or idle code. input signals are decoded either as a 100base-tx, 100-base-fx, or 10base-t input, depending on the mode selected. auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. 2.2.1.1 twisted-pair interface when operating at 100 mbps, mlt3 symbols are continuously transmitted and received. when not transmitting data, the lxt97x1 generates ? idle ? symbols. during 10 mbps operation, manchester-encoded data is exchanged. when no data is being exchanged, the line is left in an idle state. the lxt97x1 supports either 100base-tx or 10base-t connections over 100 ?, category 5, unshielded twisted pair (utp). only a transformer, series capacitors, load resistors, rj45 and bypass capacitors are required to complete this interface. on the receive side, the internal figure 5. lxt97x1 interfaces txen n rxd n_0 txd n_0 txd n_1 rxd n_1 crs_dv n rxer n rmii data i/f mddis mdc mdint mdio mdio mgmt i/f leds_ n led/cfgn_ n vcc ledlat ledclk port leds/ hardware control i/f add<4:0> qstat qclk quick status i/f tpfop n tpfon n tpfip n tpfin n network i/f rbias 22.1k vccio +3.3v vccd +3.3v gndd .01uf
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 23 impedance is high enough that it has no practical effect on the external termination circuit. on the transmit side, intel ? s patented waveshaping technology shapes the outgoing signal to help reduce the need for external emi filters. four slew rate settings (refer to table 5 on page 17 ) allow the designer to match the output waveform to the magnetic characteristics. 2.2.1.2 fiber interface the lxt97x1 provides a pecl interface that complies with the ansi x3.166 specification. this interface is suitable for driving a fiber-optic coupler. fiber ports cannot be enabled via auto-negotiation; they must be enabled via the hardware control interface or mdio registers. 2.2.2 rmii interface the lxt97x1 provides a separate rmii for each network port, each complying with the rmii standard. the rmii includes both a data interface and an mdio management interface. 2.2.3 configuration management interface the lxt97x1 provides both an mdio management interface and a hardware control interface (via the led/cfg pins) for device configuration and management. mode control selection is provided via the mddis pin as shown in table 1 . 2.2.3.1 mdio management interface the lxt97x1 supports the ieee 802.3 mii management interface also known as the management data input/output (mdio) interface. this interface allows upper-layer devices to monitor and control the state of the lxt97x1. the mdio interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. some registers are required and their functions are defined by the ieee 802.3 specification. additional registers allow for expanded functionality. specific bits in the registers are referenced using an ? x.y ? notation, where x is the register number (0-32) and y is the bit number (0-15). the physical interface consists of a data line (mdio) and clock line (mdc). operation of this interface is controlled by the mddis input pin. when mddis is high, the mdio read and write operations are disabled and the hardware control interface provides primary configuration control. when mddis is low, the mdio port is enabled for both read and write operations and the hardware control interface is not used. the timing for the mdio interface is shown in table 30 on page 60 . mdio read and write cycles are shown in figure 7 (read) and figure 8 (write). mii addressing the protocol allows one controller to communicate with multiple lxt97x1 chips. pins add_<4:0> determine the base address. each port adds its port number (0 through 5 for the lxt9761, or 0 through 7 for the lxt9781) to the base address to obtain its port address as shown in figure 6 .
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 24 datasheet figure 6. port address scheme figure 7. management interface read frame structure figure 8. management interface write frame structure base addr (ex. addr=4) phy addr (base+0) phy addr (base+1) phy addr (base+2) phy addr (base+3) phy addr (base+4) phy addr (base+5) ex. 4 ex. 5 ex. 6 ex. 7 ex. 8 ex. 9 lxt9781 port 0 port 1 port 2 port 3 port 4 port 5 phy addr (base+4) phy addr (base+5) ex. 10 ex. 11 port 6 port 7 1. ports 6 and 7 not available on the lxt9761. mdc mdio (read) 32 "1"s 0110 preamble st op code phy address turn around z0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 data write read d15 d14 d1 d0 idle high z mdc mdio (write) 32 "1"s 0101 preamble st op code phy address turn around 1 0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 d0 data idle idle write
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 25 mii interrupts the lxt97x1 provides a single interrupt pin available to all ports. interrupt logic is shown in figure 9 . the lxt97x1 also provides two dedicated interrupt registers for each port. register 18 provides interrupt enable and mask functions and register 19 provides interrupt status. setting bit 18.1 = 1, enables a port to request interrupt via the mdint pin. an active low on this pin indicates a status change on the lxt97x1. however, because it is a shared interrupt, it does not indicate which port is requesting service. interrupts may be caused by any one of the following conditions: auto-negotiation complete. speed status change. duplex status change. link status change. 2.2.3.2 hardware control interface the lxt97x1 provides a hardware control interface for applications where the mdio is not desired. the hardware control interface uses the three led driver pins for each port. 2.3 operating requirements 2.3.1 power requirements the lxt97x1 requires four power supply inputs: vccd, vcct, vccr, and vccio. the digital and analog circuits require 3.3 v supplies (vccd, vcct and vccr). these inputs may be supplied from a single source although decoupling is required to each respective ground. an additional supply may be used for the rmii (vccio). vccio should be supplied from the same power source used to supply the controller on the other side of the rmii interface. refer to table 18 on page 53 for rmii i/o characteristics. figure 9. interrupt logic force interrupt interrupt enable event x enable reg event x status reg interrupt pin . . . and or and . . . per port per event port combine logic 1. interrupt (event) status register is cleared on read. 2. x = any interrupt capability
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 26 datasheet as a matter of good practice, these supplies should be as clean as possible. typical filtering and decoupling are shown in figure 21 on page 47 . 2.3.2 clock requirements 2.3.2.1 reference clock the lxt97x1 requires a constant 50 mhz reference clock (refclk). the reference clock is used to generate transmit signals and recover receive signals. a crystal-based clock is recommended over a derived clock (i.e, pll-based) to minmize transmit jitter. refer to table 19 on page 53 for clock timing requirements. 2.4 initialization when the lxt97x1 is first powered on, reset, or encounters a link failure state, it checks the mdio register configuration bits to determine the line speed and operating conditions to use for the network link. the configuration bits may be set by the hardware control or mdio interface as shown in figure 10 . 2.4.1 mdio control mode in the mdio control mode, the lxt97x1 reads the hardware control interface pins to set the initial (default) values of the mdio registers. once the initial values are set, bit control reverts to the mdio interface. 2.4.2 hardware control mode in the hardware control mode, lxt97x1 disables direct write operations to the mdio registers via the mdio interface. on power-up or hardware reset the lxt97x1 reads the hardware control interface pins and sets the mdio registers accordingly. the following modes are available using either hardware control or mdio control: force network link to 100fx (fiber). force network link operation to: 100tx, full-duplex. 100tx, half-duplex. 10base-t, full-duplex. 10base-t, half-duplex. allow auto-negotiation / parallel-detection. when the network link is forced to a specific configuration, the lxt97x1 immediately begins operating the network interface as commanded. when auto-negotiation is enabled, the lxt97x1 begins the auto-negotiation / parallel-detection operation.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 27 2.4.3 power-down mode the lxt97x1 offers both global and per-port power-down modes. 2.4.3.1 global (hardware) power down the global power-down mode is controlled by pwrdwn pin 82 (pqfp) or w12 (pbga). when pwrdwn is high, the following conditions are true: all lxt97x1 ports and clock are shut down. all outputs are tri-stated. all weak pad pull-up and pull-down resistors are disabled. the mdio registers are not accessible. the mdio registers are reset after power down. 2.4.3.2 port (software) power down individual port power-down control is provided by bit 0.11 in the respective port control registers (refer to table 35 on page 65 ). during individual port power-down, the following conditions are true: the individual port is shut down. the mdio registers remain accessible. the mdio registers are unaffected. figure 10. initialization sequence mddis voltage level? high low mdio control mode hardware control mode disable mdio read and write operations reset mdio registers to values read at h/w control interface at last hardware reset pass control to mdio interface (read/write) power-up or reset initialize mdio registers read h/w control interface software reset? yes
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 28 datasheet 2.4.4 reset the lxt97x1 provides both hardware and software resets. configuration control of auto- negotiation, speed and duplex mode selection is handled differently for each. during a hardware reset, settings for bits 0.13, 0.12 and 0.8 are read in from the pins (refer to table 9 on page 29 for pin settings and to table 35 on page 65 for register bit definitions). during a software reset (0.15 = 1), these bit settings are not re-read from the pins. they revert back to the values that were read in during the last hardware reset. therefore, any changes to pin values made since the last hardware reset will not be detected during a software reset. during a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. during a software reset (0.15 = 1) the registers are available for reading. the reset bit should be polled to see when the part has completed reset (0.15 = 0). 2.4.5 hardware configuration settings the lxt97x1 provides a hardware option to set the initial device configuration. the hardware option uses the three led/cfg driver pins for each port. this provides three control bits per port, as listed in table 9 . the led drivers can operate as either open drain or open source circuits as shown in figure 11 . the led/cfg pins are sensitive to polarity and will automatically pull up or pull down to configure for either open drain or open source circuits (10 ma max current rating) as required by the hardware configuration. in applications where all ports are configured the same, several pins may be tied together with a single resistor. note: auto-negotiation must be disabled before selecting fiber operation. . figure 11. hardware control settings configuration bit = 1 configuration bit = 0 led/cfg pin led/cfg pin 1. leds will automatically correct their polarity upon power-up or reset. vcc
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 29 2.5 link establishment 2.5.1 auto-negotiation the lxt97x1 attempts to auto-negotiate with its counter-part across the link by sending fast link pulse (flp) bursts. each burst consists of 33 link pulses spaced 62.5 s apart. odd link pulses (clock pulses) are always present. even link pulses (data pulses) may be present or absent to indicate a ? 1 ? or a ? 0 ? . each flp burst exchanges 16 bits of data, which are referred to as a ? page ? . all devices that support auto-negotiation must implement the ? base page ? defined by ieee 802.3 (registers 4 and 5). the lxt97x1 also supports the optional ? next page ? function (registers 7 and 8). 2.5.1.1 base page exchange by exchanging base pages, the lxt97x1 and its link partner communicate their capabilities to each other. both sides must receive at least three identical base pages for negotiation to proceed. each side finds the highest common capabilities that both sides support. both sides then exchange more pages, and finally agree on the operating state of the line. 2.5.1.2 next page exchange additional information, above that required by base page exchange is also sent via ? next pages ? . the lxt97x1 fully supports the 802.3 method of negotiation via next page exchange. 2.5.1.3 controlling auto-negotiation when auto-negotiation is controlled by software, the following steps are recommended: table 9. hardware configuration settings desired configuration pin settings resulting register bit values autoneg mode speed mode duplex mode led/cfg n _ 1 control register an advertisement register 123 autoneg 0.12 speed 0.13 fd 0.8 100fd 4.8 100tx 4.7 10 fd 4.6 10t 4.5 disabled 10 half 0 0 0 0 0 0 x x x x 2 auto-negotiation advertisement full 0 0 1 1 100 half 0 1 0 1 0 full 0 1 1 1 enabled 3 100 half 1 0 0 11 00 1 00 full 1 0 1 1 1 10/100 half 1 1 0 0 0 0 1 full 1 1 1 1 1 1 1. these pins set the default values for registers 0 and 4 accordingly. 2. x = don ? t care. 3. do not select fiber mode with auto-negotiation enabled.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 30 datasheet after power-up, power-down, or reset, the power-down recovery time, (see table 31 on page 61) , must be exhausted before proceeding. set the auto-negotiation advertisement bits. enable auto-negotiation (set mdio bit 0.12 = 1). note: do not enable auto-negotiation if fiber mode is selected. 2.5.2 parallel detection in parallel with auto-negotiation, the lxt97x1 also monitors for 10 mbps normal link pulses (nlp) or 100 mbps idle symbols. if either is detected, the device automatically reverts to the corresponding operating mode. parallel detection allows the lxt97x1 to communicate with devices that do not support auto-negotiation. 2.6 rmii operation the lxt97x1 provides an independent reduced mii port for each network port. each rmii uses four signals to pass received data to the mac: rxd n <1:0>, rxer n , and crs_dv n (where n reflects the port number). three signals are used to transmit data from the mac: txd n _<1:0>, and txen n . both receive and transmit signals are clocked by refclk. data transmission across the rmii is implemented in di-bit pairs which equal a 4-bit-wide nibble. figure 12. auto-negotiation operation check value 0.12 start done enable auto-neg/parallel detection go to forced settings attempt auto- negotiation listen for 10t link pulses listen for 100tx idle symbols link set no yes power-up, reset, link failure disable auto-negotiation 0.12 = 0 0.12 = 1
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 31 2.6.1 reference clock the lxt97x1 requires a 50 mhz reference clock (refclk). the lxt97x1 samples the rmii input signals on the rising edge of refclk and drives rmii output signals on the falling edge. 2.6.2 transmit enable txen n must be asserted and de-asserted synchronously with refclk. the mac must assert txen n the same time as the first nibble of preamble. txen n must be de-asserted after the last bit of the packet. 2.6.3 carrier sense & data valid the lxt97x1 asserts crs_dv n when it detects activity on the line. however, rxd n outputs zeros until the received data is decoded and available for transfer to the controller. 2.6.4 receive error whenever the lxt97x1 receives an errored symbol from the network, it asserts rxer n . when it detects a bad start-of-stream delimiter (ssd) it drives a ? 10 ? jam pattern on the rxd pins to indicate a false carrier event. 2.6.5 loopback a test loopback function is available for 100 mbps rmii testing. bits 0.8, 0.13 and 0.14 must be set high for correct operation. when data is looped back, whatever the mac transmits is looped back in its entirety, including the preamble. in fx mode, the respective sigdet pin must be pulled high to enable loopback. 2.6.6 out of band signalling the lxt97x1 has the capability of encoding status information in the rxdata stream during ipg. refer to the section on monitoring operations ( page 42 ) for details. figure 13. loopback paths 10t loopback digital block mii tx driver 100x loopback fx driver analog block lxt97x1
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 32 datasheet 2.6.7 4b/5b coding operations the 100base-x protocol specifies the use of a 5-bit symbol code on the network media. however, data is normally transmitted across the rmii interface in 2-bit nibblets or ? di-bits ? . the lxt97x1 incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit nibbles, and a 4b/5b encoder/decoder circuit that translates between 4-bit nibbles and 5-bit symbols for the 100base-x connection. figure 14 shows the data conversion flow from nibbles to symbols. table 10 on page 34 shows 4b/5b symbol coding (not all symbols are valid). 2.7 100 mbps operation 2.7.1 100base-x network operations during 100base-x operation, the lxt97x1 transmits and receives 5-bit symbols across the network link. figure 15 shows the structure of a standard frame packet. when the mac is not actively transmitting data, the lxt97x1 sends out idle symbols on the line. in 100tx mode, the lxt97x1 scrambles the data and transmits it to the network using mlt-3 line code. the mlt-3 signals received from the network are descrambled and decoded and sent across the rmii to the mac. in 100fx mode, the lxt97x1 transmits and receives nrzi signals across the pecl interface. an external 100fx transceiver module is required to complete the fiber connection. as shown in figure 15 , the mac starts each transmission with a preamble pattern. as soon as the lxt97x1 detects the start of preamble, it transmits a j/k start of stream delimiter (ssd) symbol to the network. it then encodes and transmits the rest of the packet, including the balance of the preamble, the start of frame delimiter (sfd), packet data, and crc. once the packet ends, the lxt97x1 transmits the t/r end of stream delimiter (esd) symbol and then returns to transmitting idle symbols. figure 14. rmii data flow d0 d1 d0 d1 parallel to serial serial to parallel d0 d1 d2 d3 4b/5b s0 s1 s2 s3 s4 mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scramble de- scramble reduced mii mode data flow di-bit pairs 4-bit nibbles 5-bit symbols 1. an independent rmii port serves each independent network port. network port configurations are independently selectable. 2. the scrambler can be bypassed by setting 16.12 = 0.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 33 2.7.2 100base-x protocol sublayer operations with respect to the 7-layer communications model, the lxt97x1 is a physical layer 1 (phy) device. the lxt97x1 implements the physical coding sublayer (pcs), physical medium attachment (pma), and physical medium dependent (pmd) sublayers of the reference model defined by the ieee 802.3u specification. the following paragraphs discuss lxt97x1 operation from the reference model point of view. 2.7.2.1 pcs sublayer the physical coding sublayer (pcs) provides the rmii interface, as well as the 4b/5b encoding/ decoding function. for 100tx and 100fx operation, the pcs layer provides idle symbols to the pmd-layer line driver as long as txen is de-asserted. for 10t operation, the pcs layer merely provides a bus interface and serialization/de-serialization function. 10t operation does not use the 4b/5b encoder. preamble handling when the mac asserts txen, the pcs substitutes a /j/k symbol pair, also known as the start of stream delimiter (ssd), for the first two nibbles received across the rmii. the pcs layer continues to encode the remaining rmii data, following table 10 on page 34 , until txen is de- asserted. it then returns to supplying idle symbols to the line driver. in the receive direction, the pcs layer performs the opposite function, substituting two preamble nibbles for the ssd. dribble bits the lxt97x1 handles dribbles bits in all modes. if between 1-4 dribble bits are received, the nibble will be passed across the rmii. if between 5-7 dribble bits are received, the second nibble will not be sent onto the rmii bus. figure 15. 100base-x frame format p0 p1 p6 sfd 64-bit preamble (8 octets) start-of-frame delimiter (sfd) da da sa sa destination and source address (6 octets each) l1 l2 packet len g th (2 octets) d0 d1 dn data field (pad to minimum packet size) frame check field (4 octets) crc i0 interframe gap / idle code (> 12 octets) replaced by /t/r/ code-groups end-of-stream delimiter (esd) ifg replaced by /j/k/ code-groups start-of-stream delimiter (ssd)
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 34 datasheet figure 16. protocol sublayers table 10. 4b/5b coding code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 1 0 6 0 1 1 1 0 data 6 data 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition. encoder/decoder serializer/de-serializer link/carrier detect pcs sublayer pma sublayer mii interface pecl interface fiber transceiver lxt97x1 100base-tx 100base-fx scrambler/ de-scrambler pmd sublayer
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 35 2.7.2.2 pma sublayer link in 100mbps mode, the lxt97x1 establishes a link whenever the scrambler becomes locked and remains locked for approximately 50 ms. whenever the scrambler loses lock (<12 consecutive idle symbols during a 2 ms window), the link will be taken down. this provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. furthermore 100m idle patterns will not bring up a 10m link. the lxt97x1 reports link failure via the rmii status bits (1.2, 17.10, and 19.4) and interrupt functions. if auto-negotiate is enabled, link failure causes the lxt97x1 to re-negotiate. link failure override the lxt97x1 will normally transmit 100 mbps data packets or idle symbols only if it detects the link is up, and transmits only flp bursts if the link is not up. setting bit 16.14 = 1 overrides this function, allowing the lxt97x1 to transmit data packets even when the link is down. this feature is provided as a diagnostic tool. note that auto-negotiation must be disabled to transmit data packets in the absence of link. if auto-negotiation is enabled, the lxt97x1 will automatically begin transmitting flp bursts if the link goes down. idle undefined i 1 1 1 1 11 idle. used as inter-stream fill code 0 1 0 1 j 2 1 1 0 0 0 start-of-stream delimiter (ssd), part 1 of 2 control 0 1 0 1 k 2 1 0 0 0 1 start-of-stream delimiter (ssd), part 2 of 2 undefined t 3 0 1 1 0 1 end-of-stream delimiter (esd), part 1 of 2 undefined r 3 0 0 1 1 1 end-of-stream delimiter (esd), part 2 of 2 undefined h 4 0 0 1 0 0 transmit error. used to force signaling errors undefined invalid 0 0 0 0 0 invalid undefined invalid 0 0 0 0 1 invalid undefined invalid 0 0 0 1 0 invalid invalid undefined invalid 0 0 0 1 1 invalid undefined invalid 0 0 1 0 1 invalid undefined invalid 0 0 1 1 0 invalid undefined invalid 0 1 0 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 1 0 0 0 0 invalid undefined invalid 1 1 0 0 1 invalid table 10. 4b/5b coding (continued) code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 36 datasheet carrier sense/data valid the lxt97x1 asserts crs_dv whenever the respective port receiver is non-idle (as defined by the rmii specification revision 1.2), including false carrier events. assertion of crs_dv is asynchronous with respect to refclk. in the event that signal decoding is not complete when crs_dv is asserted, the lxt97x1 outputs 00 on the rxd1:0 lines until the decoded data is available. when the line returns to an idle state crs_dv is de-asserted, asynchronously with respect to refclk. in the event that the fifo still contains data to be passed to the mac via the rmii when crs is de-asserted, crs_dv will toggle on nibble boundaries until the fifo is empty. for 100base-x signals, crs_dv toggles at 25 mhz. for 10base-t signals, crs_dv toggles at 2.5 mhz. 2.7.2.3 twisted-pair pmd sublayer the twisted-pair physical medium dependent (pmd) layer provides the signal scrambling and descrambling, line coding and decoding (mlt-3 for 100tx, manchester for 10t), as well as receiving, polarity correction, and baseline wander correction functions. scrambler/descrambler (100tx only) the purpose of the scrambler is to spread the signal power spectrum and further reduce emi using an 11-bit, non-data-dependent polynomial. the receiver automatically decodes the polynomial whenever idle symbols are received. the scrambler/descrambler can be bypassed by setting bit 16.12 = 1. the scrambler is automatically bypassed when the fiber port is enabled. scramber bypass is provided for diagnostic and test support. baseline wander correction (100tx only) the lxt97x1 provides a baseline wander correction function which makes the device robust under all network operating conditions. the mlt3 coding scheme used in 100base-tx is by definition ? unbalanced ? . this means that the dc average value of the signal voltage can ? wander ? significantly over short time intervals (tenths of seconds). this wander can cause receiver errors, particularly in less robust designs, at long line lengths (100 meters). the exact characteristics of the wander are completely data dependent. the lxt97x1 baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case ? killer ? packets over all cable lengths. polarity correction the lxt97x1 automatically detects and corrects for the condition where the receive signal (tpfip/n) is inverted. reversed polarity is detected if eight inverted link pulses, or four inverted end-of-frame (eof) markers, are received consecutively. if link pulses or data are not received by the maximum receive time-out period, the polarity state is reset to a non-inverted state.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 37 2.7.2.4 fiber pmd sublayer the lxt97x1 provides a pecl interface for connection to an external fiber-optic transceiver. (the external transceiver provides the pmd function for fiber media.) the lxt97x1 uses an nrzi format and operates at 100 mbps. the lxt97x1 does not support 10fl applications. signal fault indications the lxt97x1 signal detect pins receive signal fault indications from local fiber transceivers via the sd pins. the device can also detect far end fault code in the received data stream. the lxt97x1 ? ors ? both fault conditions to set bit 1.4. bit 1.4 is set once and clears when read. either fault condition causes the lxt97x1 to drop the link unless forced link pass is selected (16.14 = 1). link down condition is then reported via interrupts and status bits. in response to locally detected signal faults (sd activated by the local fiber transceiver), the affected port can transmit the far end fault code if fault code transmission is enabled by bit 16.2. when bit 16.2 = 1, transmission of the far end fault code is enabled. the lxt97x1 transmits far end fault code if fault conditions are detected by the signal detect pins. when bit 16.2 = 0, the lxt97x1 does not transmit far end fault code. it continues to transmit idle code and may or may not drop link depending on the setting for bit 16.14. 2.8 10 mbps operation the lxt97x1 will operate as a standard 10base-t transceiver and supports all the standard 10 mbps functions. during 10base-t (10t) operation, the lxt97x1 transmits and receives manchester-encoded data across the network link. when the mac is not actively transmitting data, the lxt97x1 sends out link pulses on the line. in 10t mode, the polynomial scrambler/descrambler is inactive. manchester-encoded signals received from the network are decoded by the lxt97x1 and sent across the rmii to the mac. the 10m reversed polarity correction function is the same as the 100m function described on page 36 . the lxt97x1 does not support fiber connections at 10 mbps. 2.8.1 preamble handling the lxt97x1 offers two options for preamble handling, selected by bit 16.5. in 10t mode when 16.5 = 0, the lxt97x1 strips the entire preamble off of received packets. crs_dv is asserted coincident with sfd. crs_dv is held low for the duration of the preamble. when crs_dv is asserted, the very first two nibbles driven by the lxt97x1 are the sfd ? 5d ? hex followed by the body of the packet. in 10t mode with 16.5 = 1, the lxt97x1 passes the preamble through the rmii and asserts crs_dv simultaneously.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 38 datasheet 2.8.2 dribble bits the lxt97x1 device handles dribbles bits in all modes. if between 1-4 dribble bits are received, the nibble will be passed across the rmii, padded with 1s if necessary. if between 5-7 dribble bits are received, the second nibble will not be sent onto the rmii bus. 2.8.3 link test in 10t mode, the lxt97x1 always transmit link pulses. if the link test function is enabled, it monitors the connection for link pulses. once link pulses are detected, data transmission will be enabled and will remain enabled as long as either the link pulses or data transmission continue. if the link pulses stop, the data transmission will be disabled. if the link test function is disabled, the lxt97x1 will transmit to the connection regardless of detected link pulses. the link test function can be disabled by setting bit 16.14 = 1. 2.8.3.1 link failure link failure occurs if link test is enabled and link pulses or packets stop being received. if this condition occurs, the lxt97x1 returns to the auto-negotiation phase if auto-negotiation is enabled. 2.8.4 jabber if a transmission exceeds the jabber timer, the lxt97x1 will disable the transmit and loopback functions. the rmii does not include a jabber pin, however the mac may read register 1 to determine jabber status. the lxt97x1 automatically exits jabber mode after the unjab time has expired. this function can be disabled by setting bit 16.10 = 1. 2.9 monitoring operations 2.9.1 monitoring auto-negotiation auto-negotiation can be monitored as follows: bits 1.2 and 17.10 = 1 once the link is established. additional bits in register 1 (refer to table 36 on page 65 ) and register 17 (refer to table 45 on page 71 ) can be used to determine the link operating conditions and status. 2.9.2 serial led functions the lxt97x1 provide eight serial led outputs (leds7:0) which may be attached to external hc595-type shift registers (refer to figure 25 on page 51 ). the ledclk signal is used to shift data into the 595 ? s internal shift register. the ledlatch signal is used to load data from the 595 ? s internal shift register to the 595 ? s internal storage register. the lxt97x1 drives the leds n and ledlatch outputs on the falling edge of ledclk. all serial leds will be stretched in accordance with 20.1 & 20.3:2.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 39 each serial output reports a specific status condition for all ports. ports 0 through 7 are assigned bits 0:7 in each stream (bits 3 and 4 are not used on the lxt9761). serial outputs report the following conditions for each port: leds0 serial output indicates activity. 0 = active1 = inactive leds1 serial output indicates polarity 0 = switched polarity1 = normal polarity leds2 serial output indicates duplex (d). 0 = full duplex1 = half duplex leds3 serial output indicates link. 0 = link active1 = link inactive leds4 serial output indicates collision. 0 = collision active1 = collision inactive leds5 serial output indicates receive. 0 = receive active1 = receive inactive leds6 serial output indicates transmit. 0 = transmit active1 = transmit inactive leds7 serial output indicates speed. 0 = 100 mbps1 = 10 mbps figure 17. serial led streams ledclk leds(0) ledlatch leds(1) leds(2) leds(4) leds(5) leds(3) leds(6) leds(7) activity (port 0) activity (port 1) activity (port 2) activity (port 3) activity (port 4) activity (port 5) (port 6) (port 7) activity (port 0) activity (port 1) activity (port 2) activity (port 3) activity (port 4) activity (port 5) polarity (port 0) polarity (port 1) polarity (port 2) polarity (port 3) polarity (port 4) polarity (port 5) (port 6) (port 7) polarity (port 0) polarity (port 1) polarity (port 2) polarity (port 3) polarity (port 4) polarity (port 5) duplex (port 0) duplex (port 1) duplex (port 2) duplex (port 3) duplex (port 4) duplex (port 5) (port 6) (port 7) duplex (port 0) duplex (port 1) duplex (port 2) duplex (port 3) duplex (port 4) duplex (port 5) collision (port 0) collision (port 1) collision (port 2) collision (port 3) collision (port 4) collision (port 5) (port 6) (port 7) collision (port 0) collision (port 1) collision (port 2) collision (port 3) collision (port 4) collision (port 5) receive (port 0) receive (port 1) receive (port 2) receive (port 3) receive (port 4) receive (port 5) (port 6) (port 7) receive (port 0) receive (port 1) receive (port 2) receive (port 3) receive (port 4) receive (port 5) link (port 0) link (port 1) link (port 2) link (port 3) link (port 4) link (port 5) (port 6) (port 7) link (port 0) link (port 1) link (port 2) link (port 3) link (port 4) link (port 5) transmit (port 0) transmit (port 1) transmit (port 2) transmit (port 3) transmit (port 4) transmit (port 5) (port 6) (port 7) transmit (port 0) transmit (port 1) transmit (port 2) transmit (port 3) transmit (port 4) transmit (port 5) speed (port 0) speed (port 1) speed (port 2) speed (port 3) speed (port 4) speed (port 5) (port 6) (port 7) speed (port 0) speed (port 1) speed (port 2) speed (port 3) speed (port 4) speed (port 5) activity activity polarity polarity duplex duplex link link collision collision receive receive transmit transmit speed speed (1 mhz) alternate port positions for lxt9761 port 0 port 1 port 2 spare port 3 port 4 port 5 port 0 port 1 port 2 spare spare port 3 spare port 5 leds(0:7) spare on lxt9761 spare on lxt9761
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 40 datasheet 2.9.3 per-port led driver functions the lxt97x1 incorporates three direct drive leds per port. on power up all the leds will light for approximately 1 second after reset de-asserts. each led can be programmed to one of several different display modes using the led configuration register. each per-port led can be programmed (refer to table 48 on page 74 ) to indicate one the following conditions: operating speed. transmit activity. receive activity. collision condition. link status. duplex mode. the leds can also be programmed to display various combined status conditions. for example, setting bits 20.15:12 = 1101 produces the following combination of link and activity indications: if link is down led is off. if link is up led is on. if link is up and activity is detected, the led will blink at the stretch interval selected by bits 20.3:2 and will continue to blink as long as activity is present. the led/cfg driver pins are also used to provide initial configuration settings. the led pins are sensitive to polarity and will automatically pull up or pull down to configure for either open drain or open source circuits (10ma max current rating) as required by the hardware configuration. refer to the discussion of ? hardware control interface ? on page 25 for details. 2.9.3.1 led pulse stretching the led configuration register also provides optional led pulse stretching to 30, 60, or 100 ms. if during this pulse stretch period, the event occurs again, the pulse stretch time will be further extended. when an event such as receiving a packet occurs it will be edge detected and it will start the stretch timer. the led driver will remain asserted until the stretch timer expires. if another event occurs before the stretch timer expires then the stretch timer will be reset and the stretch time will be extended. when a long event (such as duplex status) occurs it will be edge detected and it will start the stretch timer. when the stretch timer expires the edge detector will be reset so that a long event will cause another pulse to be generated from the edge detector which will reset the stretch timer and cause the led driver to remain asserted. figure 18 shows how the stretch operation functions.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 41 2.9.4 using the quick status register the lxt97x1 continuously sends out the quick status register (address 17) contents on the qstat pin. this output provides a continuous, real-time status update of several different lxt97x1 attributes and modes. the information can be used to sense rx, tx, col and to monitor the status and speed of the auto-negotiation process. a simple signature is used to delineate the start of the qstat register information allowing a very simple interface to be designed. the 16 bits of the quick status register are separated by a 16-bit signature frame (1111111111111111). the lxt97x1 sources this status information separated by the signature with respect to the falling edge of the qclk input. this allows an asic to provide only 1 clock output for multiple phy devices. the asic can also select a frequency up to 25 mhz to operate this interface. refer to table 45 on page 71 for quick status bits descriptions. figure 18. led pulse stretching event led note: the direct drive led outputs in this diagram are shown as active low. stretch stretch stretch figure 19. quick status register 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 qstat 16 bit signature quick status register- port n (0) (0) quick status register- port 0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (0) (0) port 2 thru n-1 1. qclk is used to output the above information. 2. bits d15 and d0 are always set to 0. d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 42 datasheet 2.9.5 out-of-band signalling the lxt97x1 provides an out-of-band signalling option to transfer status information across the rmii receive interface. enabled when 25.0=1, this feature uses the rxd(1:0) data bus during the ipg time as shown in figure 20 . the two status bits that are transferred across the rxd bus are software selectable via register 25 (refer to table 49 on page 75 ). in normal operation the lxt97x1 stuffs the rxd bus with zeros during the inter-packet gap (ipg). a software-selectable bit enables the rmii out of band signalling feature. once this bit is set the lxt97x1 replaces those zeros with the selected status bits during the ipg. 2.10 boundary scan (jtag1149.1) functions the lxt97x1 includes a ieee 1149.1 boundary scan test port for board level testing. all digital input, output, and input/output pins are accessible. 2.10.1 boundary scan interface this interface consists of five pins (tms,tdi,tdo, tck and trst). it includes a state machine, data register array, and instruction register. the tms and tdi pins are internally pulled up. tck is internally pulled down. tdo does not have an internal pull-up or pull-down. 2.10.2 state machine the tap controller is a 16 bit state machine driven by the tck and tms pins. upon reset the test_logic_reset state is entered. the state machine is also reset when tms is high for five tck periods. figure 20. rmii programmable out of band signalling refclk crs_dv rxd(1) rxd(0) data data data data data data data data status 0 status 0 status 0 status 0 status 0 status 0 status 1 status 1 status 1 status 1 status 1 status 1 0s 1. when network activity is detected, the lxt97x1 asserts crs_dv asynchronously with respect to refclk. 2. after crs_dv is asserted, the lxt97x1 will zero-stuff the rxdata bits until the received data has been processed through the fifo. 3. when network activity ceases, the lxt97x1 de-asserts crs_dv synchronously with respect to refclk. crs_dv will toggle until all data in the fifo has been processed through the rmii. once the fifo is empty, the lxt97x1 will drive the status bits selected by the out-of-band signalling register (refer to table 49 on page 75 ) on the rxd outputs. status 1 status 0 0s
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 43 2.10.3 instruction register after the state machine resets, the idcode instruction is always invoked. the decode logic ensures the correct data flow to the data registers according to the current instruction. valid instructions are listed in table 12 . 2.10.4 boundary scan register each bsr cell has two stages. a flip-flop and a latch are used for the serial shift stage and the parallel output stage. there are four modes of operation as listed in table 11 . table 11. bsr mode of operation mode description 1 capture 2shift 3 update 4 system function table 12. supported jtag instructions name code description data register extest 0000000000000000 external test bsr idcode 1111111111111110 id c ode inspection id reg sample 1111111111111110 sample b oundary bsr high z 111111111 1001111 force float bypass clamp 1111111111101111 clamp bsr bypass 1111111111111111 bypass scan bypass table 13. device id register 31:28 27:12 11:8 7:1 0 version part id (hex) jedec continuation characters jedec id 1 reserved 0000 2621 (lxt9761) 2635 (lxt9781) 0000 111 1110 1 1. the jedec id is an 8-bit identifier. the msb is for parity and is ignored. intel ? s jedec id is fe (1111 1110) which becomes 111 1110.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 44 datasheet 3.0 application information 3.1 design recommendations the lxt97x1 is designed to comply with ieee requirements and to provide outstanding receive bit error rate (ber) and long-line-length performance. to achieve maximum performance from the lxt97x1, attention to detail and good design practices are required. refer to the lxt97x1 design and layout guide for detailed design and layout information. 3.1.1 general design guidelines adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. up to 50 mv of noise is considered acceptable. 50 to 80 mv of noise is considered marginal. high-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: fill in unused areas of the signal planes with solid copper and attach them with vias to a vcc or ground plane that is not located adjacent to the signal layer. use ample bulk and decoupling capacitors throughout the design (a value of .01 f is recommended for decoupling caps). provide ample power and ground planes. provide termination on all high-speed switching signals and clock lines. provide impedance matching on long traces to prevent reflections. route high-speed signals next to a continuous, unbroken ground plane. filter and shield dc-dc converters, oscillators, etc. do not route any digital signals between the lxt97x1 and the rj45 connectors at the edge of the board. do not extend any circuit power and ground plane past the center of the magnetics or to the edge of the board. use this area for chassis ground, or leave it void. 3.1.2 power supply filtering power supply ripple and digital switching noise on the vcc plane can cause emi problems and degrade line performance. the best approach is to minimize ground noise as much as possible using good general techniques and by filtering the vcc plane. it is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having problems: poorly-regulated or over-burdened power supplies wide data busses (32-bits+) running at a high clock rate dc-to-dc converters
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 45 intel recommends filtering the power supply to the analog vcc pins of the lxt97x1. this has two benefits. first, it keeps digital switching noise out of the analog circuitry inside the lxt97x1, which helps line performance. second, if the vcc planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing emi problems. the recommended implementation is to break the vcc plane into two sections. the digital section supplies power to the vccd and vccio pins of the lxt97x1. the analog section supplies power to the vcca pins. the break between the two planes should run underneath the device. in designs with more than one lxt97x1, a single continuous analog vcc plane can be used to supply them all. the digital and analog vcc planes should be joined at one or more points by ferrite beads. the beads should produce at least a 100 ? impedance at 100 mhz. beads should be placed so that current flow is evenly distributed. the maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. a bulk cap (2.2 -10 uf) should be place on each side of each bead. in addition, a high-frequency bypass cap (.01uf) should be placed near each analog vcc pin. 3.1.3 power and ground plane layout considerations great care needs to be taken when laying out the power and ground planes. follow the guidelines in the lxt97x1 design and layout guide for locating the split between the digital and analog vcc planes. keep the digital vcc plane away from the tpfop/n and tpfip/n signals, away from the magnetics, and away from the rj45 connectors. place the layers so that the tpfop/n and tfpip/n signals can be routed near or next to the ground plane. for emi reasons, it is more important to shield tpfop/n than tpfip/n. 3.1.3.1 chassis ground for esd reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. chassis ground should extend from the rj-45 connectors to the magnetics, and can be used to terminate unused signal pairs ( ? bob smith ? termination). in single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kv isolation capacitor. in multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kv isolation to the bob smith termination. 3.1.4 rmii terminations series termination resistors are not typically required on the rmii signals driven by the lxt97x1. 3.1.5 the rbias pin the lxt97x1 requires a 22.1 k ?, 1% resistor directly connected between the rbias pin and ground. place the rbias resistor as close to the rbias pin as possible. run an etch directly from the pin to the resistor, and sink the other side of the resistor to a filtered ground. surround the rbias trace with a filtered ground; do not run high-speed signals next to rbias.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 46 datasheet 3.1.6 the twisted-pair interface follow standard guidelines for a twisted-pair interface: place the magnetics as close as possible to the lxt97x1. keep transmit pair traces as short as possible; both traces should have the same length. avoid vias and layer changes as much as possible. keep the transmit and receive pairs apart to avoid cross-talk. route the transmit pair adjacent to a ground plane. the optimum arrangement is to place the transmit traces two to three layers from the ground plane, with no intervening signals. improve emi performance by filtering the tpo center tap. a single ferrite bead may be used to supply center tap current to all ports. all ports draw a combined total of 505 ma so the bead should be rated at 760 ma. 3.1.6.1 magnetics information the lxt97x1 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit transformers. the transformer isolation voltage should be rated at 1.5 kv to protect the circuitry from static voltages across the connectors and cables. refer to table 14 for transformer requirements. before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application. 3.1.7 the fiber interface the fiber interface consists of a pecl transmit and receive pair to an external fiber-optic transceiver. the transmit and receive pair should be dc-coupled to the transceiver, and biased appropriately. refer to the fiber transceiver manufacturer ? s recommendations for termination circuitry. figure 23 on page 49 shows a typical example. 3.2 typical application circuits figure 21 through figure 25 show typical application circuits. table 14. magnetics requirements parameter min nom max units test condition rx turns ratio ? 1 : 1 ?? tx turns ratio ? 1 : 1 ?? insertion loss 0.0 0.6 1.1 db primary inductance 350 ?? h transformer isolation ? 1.5 ? kv differential to common mode rejection 40 ?? db .1 to 60 mhz 35 ?? db 60 to 100 mhz return loss -16 ?? db 30 mhz -10 ?? db 80 mhz
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 47 figure 21. power and ground supply connections rbias gnda vcct 22.1 k ? 1% gndd vccd .01 f ferrite bead 10 f lxt97x1 vccio +3.3v +3.3v .01 f gnds + 10 f + 10 f + vccr .01 f .01 f analog supply plane digital supply plane
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 48 datasheet figure 22. typical twisted-pair interface tpfop tpfon rj45 * = 0.001 f / 2.0 kv to twisted-pair network 3 6 1 2 1:1 lxt97x1 50 ? 50 ? 50 ? 50 ? 50 ? 50 ? 4 5 8 7 1:1 3 tpfip tpfin vcct gnda 0.1 f .01 f 1 270 pf 5% 270 pf 5% 0.01 f 50 ? 1% 50 ? 1% ** 2 5 4 1. the 100 ? transmit load termination resistor typically required is integrated in the lxt97xx. 2. magnetics without a receive pair center-tap do not require a 2 kv termination. 3. center tap current may be supplied from 3.3v vcca as shown. however, additional power savings may be realized by supplying the center-tap from from a 2.5v current source. in either case a single ferrite bead (rated at 800 ma) may be used to supply center tap current to all ports. 4. receive common mode bypass cap may improve ber performance in systems with noisy power supplies. 5. recommended 0.1 f capacitor to improve the emi performance.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 49 figure 23. typical fiber interface 1. refer to fiber transceiver manufacturer ? s recommendations for termination circuitry. example shown above is suitable for hfbr5900-series devices. tpfon n tpfop n tpfin n tpfip n 50 ? 50 ? fiber txcvr to fiber network 0.1 m f 82 ? 82 ? 130 ? 130 ? 0.1 m f td- td+ rd- rd+ gndd gndd gndd 1 sd/tp n lxt97x1 sd 130 ? 82 ? gndd vccd +3.3v vccd +3.3v vccd +3.3v 16 ?
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 50 datasheet figure 24. typical rmii interface 8 port mac txd n_ 1 rxd n_ 0 refclk 50mhz system clock from switch asic or external source 8 8 txdata rxdata sysclk lxt9781 magnetics/fiber transceiver txd n _0 8 txen n 8 rxd n_ 1 8 rxer n 8 crs_dv n 8
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 51 figure 25. typical serial led interface lxt9781 595 activity(7) activity(6) activity(5) activity(4) activity(3) activity(2) activity(1) activity(0) 595 polarity(7) polarity(6) polarity(5) polarity(4) polarity(3) polarity(2) polarity(1) polarity(0) 595 duplex(7) duplex(6) duplex(5) duplex(4) duplex(3) duplex(2) duplex(1) duplex(0) 595 link(7) link(6) link(5) link(4) link(3) link(2) link(1) link(0) 595 collision(7) collision(6) collision(5) collision(4) collision(3) collision(2) collision(1) collision(0) 595 receive(7) receive(6) receive(5) receive(4) receive(3) receive(2) receive(1) receive(0) 595 transmit(7) transmit(6) transmit(5) transmit(4) transmit(3) transmit(2) transmit(1) transmit(0) 595 speed(7) speed(6) speed(5) speed(4) speed(3) speed(2) speed(1) speed(0) leds(0) leds(1) leds(2) leds(3) leds(4) leds(5) leds(6) leds(7) ledclk ledclk ledclk ledclk ledclk ledclk ledclk ledclk ledlatch ledlatch ledlatch ledlatch ledlatch ledlatch ledlatch ledlatch qa qh qh qh qh qh qh qh qh qa qa qa qa qa qa qa rclk rclk rclk rclk rclk rclk rclk rclk srclk srclk srclk srclk srclk srclk srclk srclk ser ser ser ser ser ser ser ser 1. note: the outputs are always enabled on the 595 chips. 2. ports 6 and 7 are not available on the lxt9761. serial outputs are re-mapped as shown in detail at right. see detail for lxt9761 configuration. 595 activity(5) activity(4) activity(3) not used not used activity(2) activity(1) activity(0) leds(0) ledclk ledlatch qa qh rclk srclk ser alternate configuration for lxt9761
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 52 datasheet 4.0 test specifications note: table 15 through table 31 and figure 26 through figure 36 represent the performance specifications of the lxt97x1. these specifications are guaranteed by test, except where noted ? by design. ? minimum and maximum values listed in table 17 through table 31 apply over the recommended operating conditions specified in table 16 . table 15. absolute maximum ratings parameter sym min max units supply voltage v cc -0.3 tbd v operating temperature ambient t opa -15 +85 o c case t opc ? +120 o c storage temperature t st -65 +150 o c caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 16. operating conditions parameter sym min typ 1 max units recommended operating temperature ambient t opa 0 ? 70 o c case t opc 0 ? 110 o c recommended supply voltage 2 analog & digital vcca, vccd 3.15 ? 3.45 v i/o vccio 3.15 ? 3.45 v v cc current 100base-tx i cc ? 118 3 138 3 ma 100base-fx i cc ?? ? ma 10base-t i cc ? 118 3 138 3 ma power-down mode i cc ? 25 ? ma auto-negotiation 3 i cc ? 114.5 3 138 3 ma 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. voltages with respect to ground unless otherwise specified. 3. per-port @ 3.3v. table 17. digital i/o characteristics 1 parameter sym min typ 2 max units test conditions input low voltage 3 v il ?? 0.8 v ? input high voltage 3 v ih 2.0 ?? v ? 1. applies to all pins except rmii pins. refer to table 18 for rmii i/o characteristics. 2. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 3. does not apply to refclk. refer to table 19 for clock input levels.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 53 input current i i -100 ? 100 a0.0 < v i < v cc output low voltage v ol ?? 0.4 v i ol = 4 ma output high voltage v oh 2.4 ?? vi oh = -4 ma table 18. digital i/o characteristics - rmii pins parameter sym min typ 2 max units test conditions input low voltage v il ?? 0.8 v ? input high voltage v ih 2.0 ?? v ? input current i i -100 ? 100 a0.0 < v i < v cc output low voltage v ol ?? 0.4 v i ol = 4 ma output high voltage v oh 2.2 ?? vi oh = -4 ma, v cc = 3.3v driver output resistance (line driver output enabled) r o 1 ? 100 ? ? v cc = 2.5v r o 1 ? 100 ? ? v cc = 3.3v 1. parameter is guaranteed by design; not subject to production testing. 2. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 19. required clock characteristics parameter sym min typ 2 max units test conditions input low voltage v il ?? 0.8 v ? input high voltage v ih 2.0 ?? v ? input frequency f ? 50 ? mhz ? input clock frequency tolerance 1 ? f ?? 50 ppm ? input clock duty cycle 1 tdc 35 50 65 % ? 1. parameter is guaranteed by design; not subject to production testing. 2. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 20. 100base-tx transceiver characteristics parameter sym min typ 1 max units test conditions peak differential output voltage v p 0.95 ? 1.05 v note 2 signal amplitude symmetry vss 98 ? 102 % note 2 signal rise/fall time t rf 3.0 ? 5.0 ns note 2 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at the line side of the transformer, line replaced by 100 ? (+/-1%) resistor. table 17. digital i/o characteristics 1 (continued) parameter sym min typ 2 max units test conditions 1. applies to all pins except rmii pins. refer to table 18 for rmii i/o characteristics. 2. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 3. does not apply to refclk. refer to table 19 for clock input levels.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 54 datasheet rise/fall time symmetry t rfs ?? 0.5 ns note 2 duty cycle distortion ??? 0.5 ns offset from 16ns pulse width at 50% of pulse peak overshoot v o ?? 5% ? table 21. 100base-fx transceiver characteristics parameter sym min typ 1 max units test conditions transmitter peak differential output voltage (single ended) v op 0.6 ? 1.5 v ? signal rise/fall time t rf ?? 1.9 ns 10 < ? > 90% 2.0 pf load jitter (measured differentially) ??? 1.4 ns ? receiver peak differential input voltage v ip 0.55 ? 1.5 v ? common mode input range v cmir ?? v cc - 0.7 v ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 22. 10base-t transceiver characteristics parameter sym min typ 1 max units test conditions transmitter peak differential output voltage v op 2.2 2.5 2.8 v note 2 link transmit period ? 8 ? 24 ms ? transmit timing jitter added by the mau and pls sections 3, 4 ? 0 ? 11 ns note 5 receiver link min receive timer tlrmin 2 4 7 ms ? link max receive timer tlrmax 50 64 150 ms ? time link loss receive tll 50 64 150 ms ? differential squelch threshold v ds ? 390 ? mv peak 5 mhz square wave input 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at the line side of the transformer, line replaced by 100 ? (+/-1%) resistor. 3. parameter is guaranteed by design; not subject to production testing. 4. ieee 802.3 specifies maximum jitter addition at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau. 5. after line model specified by ieee 802.3 for 10base-t mau table 20. 100base-tx transceiver characteristics (continued) parameter sym min typ 1 max units test conditions 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at the line side of the transformer, line replaced by 100 ? (+/-1%) resistor.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 55 figure 26. 100base-tx receive timing table 23. 100base-tx receive timing parameters parameter sym min typ 1 max units test conditions rxd<1:0>, crs_dv, rxer setup to refclk rising edge t1 4 ?? ns ? rxd<1:0>, crs_dv, rxer hold from refclk rising edge t2 2 ?? ns ? receive start of ? j ? to crs_dv asserted t3 ? 14 ? bt ? receive start of ? t ? to crs_dv de-asserted t4 ? 22 ? bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 27. 100base-tx transmit timing refclk rxd(1:0) tpfi t 1 t 2 t 3 crs_dv t 4 refclk txd(1:0) tpfo t 3 t 1 t 2 tx_en t 4 t 5
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 56 datasheet table 24. 100base-tx transmit timing parameters parameter sym min typ 1 max units test conditions txd<1:0> setup to refclk rising edge t1 4 ?? ns ? txd<1:0> hold from refclk rising edge t2 2 ?? ns ? tx_en sampled to tpfo out (tx latency) t3 ? 13 ? bt ? tx_en setup to refclk rising edge t4 4 ?? ns ? tx_en hold from refclk rising edge t5 2 ?? ns ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 28. 100base-fx receive timing table 25. 100base-fx receive timing parameters parameter sym min typ 1 max units test conditions rxd<1:0>, crs_dv, rxer setup to refclk rising edge t1 4 ?? ns ? rxd<1:0>, crs_dv, rxer hold from refclk rising edge t2 2 ?? ns ? receive start of ? j ? to crs_dv asserted t3 ? 12 ? bt ? receive start of ? t ? to crs_dv de-asserted t4 ? 20 ? bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. refclk rxd(1:0) tpfi t 1 t 2 t 3 crs_dv t 4
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 57 figure 29. 100base-fx transmit timing table 26. 100base-fx transmit timing parameters parameter sym min typ 1 max units test conditions txd<1:0> setup to refclk rising edge t1 4 ?? ns ? txd<1:0> hold from refclk rising edge t2 2 ?? ns ? tx_en sampled to tpfo out (tx latency) t3 ? 13 ? bt ? tx_en setup to refclk rising edge t4 4 ?? ns ? tx_en hold from refclk rising edge t5 2 ?? ns ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 30. 10base-t receive timing refclk txd(1:0) tpfo t 3 t 1 t 2 tx_en t 4 t 5 refclk rxd(1:0) tpfi t 1 t 2 t 3 crs_dv t 4
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 58 datasheet table 27. 10base-t receive timing parameters parameter sym min typ 1 max units test conditions rxd<1:0>, crs_dv setup to refclk rising edge t1 4 ?? ns ? rxd<1:0>, rx_dv hold from refclk rising edge t2 2 ?? ns ? tpfi in to crs_dv asserted t3 ? 3 ? bt ? tpfi quiet to crs_dv de-asserted t4 ? 13 ? bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 31. 10base-t transmit timing table 28. 10base-t transmit timing parameters parameter sym min typ 1 max units test conditions txd<1:0> setup to refclk rising edge t1 4 ?? ns ? txd<1:0> hold from refclk rising edge t2 2 ?? ns ? tx_en sampled to tpfo out (tx latency) t3 ? 15 ? bt ? tx_en setup to refclk rising edge t4 4 ?? ns ? tx_en hold from refclk rising edge t5 2 ?? ns ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. refclk txd(1:0) tpfo t 3 t 1 t 2 tx_en t 4 t 5
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 59 figure 32. auto-negotiation and fast link pulse timing figure 33. fast link pulse timing table 29. auto-negotiation and fast link pulse timing parameters parameter sym min typ 1 max units test conditions clock/data pulse width t1 ? 100 ? ns ? clock pulse to data pulse t2 55.5 ? 69.5 s ? clock pulse to clock pulse t3 111 ? 139 s ? flp burst width t4 ? 2 ? ms ? flp burst to flp burst t5 8 ? 24 ms ? clock/data pulses per burst ? 17 ? 33 ea ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. tpfop t1 t1 t2 t3 clock pulse data pulse clock pulse tpfop t4 t5 flp burst flp burst
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 60 datasheet figure 34. mdio write timing (mdio sourced by mac) figure 35. mdio read timing (mdio sourced by phy) table 30. mdio timing parameters parameter sym min typ 1 max units test conditions mdio setup before mdc, sourced by sta t1 10 ?? ns mdc = 2.5 mhz 1 ?? ns mdc = 8 mhz mdio hold after mdc, sourced by sta t2 10 ?? ns mdc = 2.5 mhz 1 ?? ns mdc = 8 mhz mdc to mdio output delay, sourced by phy t3 10 ? 300 ns mdc = 2.5 mhz ? 130 ? ns mdc = 8 mhz 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t1 mdc mdio t2 t3 mdc mdio
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 61 figure 36. power-up timing table 31. power-up timing parameters parameter sym min typ 1 max units test conditions voltage threshold v1 ? 2.9 ? v ? power up delay t1 ?? 500 ms ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. figure 37. reset and power-down recovery timing table 32. reset and power-down recovery timing parameters parameter sym min typ 1 max units test conditions reset pulse width t1 10 ?? ns ? reset recovery delay t2 ? 1 ? ms ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t1 vcc mdio,etc v1 t2 reset mdio,etc t1
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 62 datasheet 5.0 register definitions the lxt97x1 register set includes multiple 16-bit registers. table 33 presents a complete register listing and table 34 provides a consolidated memory map of all registers. table 35 through table 49 define individual registers. base registers (0 through 8) are defined in accordance with the ? reconciliation sublayer and media independent interface ? and ? physical layer link signaling for 10/100 mbps auto- negotiation ? sections of the ieee 802.3 specification. additional registers (16 through 30) are defined in accordance with the ieee 802.3 specification for adding unique chip functions. table 33. register set address register name bit assignments 0 control register refer to table 35 on page 65 1 status register refer to table 36 on page 65 2 phy identification register 1 refer to table 37 on page 66 3 phy identification register 2 refer to table 38 on page 67 4 auto-negotiation advertisement register refer to table 39 on page 67 5 auto-negotiation link partner base page ability register refer to table 40 on page 68 6 auto-negotiation expansion register refer to table 41 on page 69 7 auto-negotiation next page transmit register refer to table 42 on page 69 8 auto-negotiation link partner received next page register refer to table 43 on page 70 9 1000base-t/100base-t2 control register not implemented 10 1000base-t/100base-t2 status register not implemented 15 extended status register not implemented 16 port configuration register refer to table 44 on page 70 17 quick status register refer to table 45 on page 71 18 interrupt enable register refer to table 46 on page 72 19 interrupt status register refer to table 47 on page 73 20 led configuration register refer to table 48 on page 74 21-24 reserved 25 out of band signalling register refer to table 49 on page 75 26 - 27 reserved 28 transmit control register #1 refer to table 50 on page 76 29 reserved 30 transmit control register #2 refer to table 51 on page 76 31 reserved
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 63 table 34. register bit map reg title bit fields add r b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 control register control reset loopbac k speed select a/n enable power down reserved re-start a/n duplex mode col test speed select reserved 0 status register status 100base- t4 100base- x full duplex 100base- x half duplex 10mbps full duplex 10mbps half duplex 100base- t2 full duplex 100base- t2 half duplex extended status reserved mf preamble suppress a/n complete remote fault a/n ability link status jabber detect extende d capabilit y 1 phy id registers phy id 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 phy id2 phy id no mfr model no mfr rev no 3 auto-negotiation advertisement register a/n advertise next page reserved remote fault reserved asymm pause pause 100base- t4 100base- tx full duplex 100base- tx 10base- t full duplex 10base- t ieee selector field 4 auto-negotiation link partner base page ability register a/n link ability next page ack remote fault reserved asymm pause pause 100base- t4 100base- tx full duplex 100base- tx 10base- t full duplex 10base- t ieee selector field 5 auto-negotiation expansion register a/n expansion reserved base page parallel detect fault link partner next page able next page able page receive d link partner a/n able 6 auto-negotiation next page transmit register a/n next page txmit next page reserved message page ack 2 toggle message / unformatted code field 7 auto-negotiation link partner next page ability register a/n link next page next page ack message page ack 2 toggle message / unformatted code field 8 port configuration register port config reserved link disable txmit disable bypass scramble r (100tx) bypass 4b/5b (100tx) jabber (10t) sqe (10t) tp loopbac k (10t) reserved fifo size pre_en reserve d reserve d far end fault tx enable alternat e next page fiber select 16 quick status register
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 64 datasheet quick status reserved 10/100 mode transmit status receiver status collision status link duplex mode auto-neg auto-neg complete reserved polarity pause error reserve d reserve d reserve d 17 interrupt enable register interrupt enable reserved reserved auto-neg mask speed mask duplex mask link mask reserve d reserve d interrupt enable test interrupt 18 interrupt status register interrupt status reserved reserved auto-neg done speed change duplex change link change reserve d md interrupt reserve d reserve d 19 led configuration register led config led1 led2 led3 led freq pulse stretch invert polarity 20 programmable rmii out of band signalling register rmii oob signalling reserved bit 1 bit 0 program rmii 25 transmit control register #1 analog #1 line length reserved bandwidth control slew control 28 transmit control register #2 analog #2 reserved driver amp reserved 30 table 34. register bit map (continued) reg title bit fields add r b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 65 table 35. control register (address 0) bit name description type 1 default 0.15 reset 1 = phy reset 0 = normal operation r/w sc 0 0.14 loopback 1 = enable loopback mode 0 = disable loopback mode r/w 0 0.13 speed selection 0.6 0.13 1 1 = reserved 1 0 = 1000 mbps (not allowed) 0 1 = 100 mbps 0 0 = 10 mbps r/w note 2 00 0.12 auto-negotiation enable 3 1 = enable auto-negotiation process 0 = disable auto-negotiation process r/w note 2 0 0.11 power-down 1 = power-down 0 = normal operation r/w 0 0.10 reserved write as zero. ignore on read. r/w 0 0.9 restart auto-negotiation 1 = restart auto-negotiation process 0 = normal operation r/w sc 0 0.8 duplex mode 1 = full duplex 0 = half duplex r/w note 2 0 0.7 collision test this bit is ignored by the lxt97x1. 1 = enable col signal test 0 = disable col signal test r/w 0 0.6 speed selection 1000 mb/s 0.6 0.13 1 1 = reserved 1 0 = 1000 mbps (not allowed) 0 1 = 100 mbps 0 0 = 10 mbps r/w 00 0.5:0 reserved write as 0, ignore on read r/w 00000 1. r/w = read/write ro = read only sc = self clearing 2. default value of bits 0.12, 0.13 and 0.8 are determined by hardware pins. 3. do not enable auto-negotiation if fiber mode is selected. table 36. status register (address 1) bit name description type 1 defaul t 1.15 100base-t4 1 = phy able to perform 100base-t4 0 = phy not able to perform 100base-t4 ro 0 1.14 100base-x full duplex 1 = phy able to perform full-duplex 100base-x 0 = phy not able to perform full-duplex 100base-x ro 1 1.13 100base-x half duplex 1 = phy able to perform half-duplex 100base-x 0 = phy not able to perform half-duplex 100base-x ro 1 1. ro = read only ll = latching low lh = latching high 2. bit 1.4 is not valid if auto-negotiation is selected while operating in fiber mode.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 66 datasheet 1.12 10 mbps full duplex 1 = phy able to operate at 10 mbps in full-duplex mode 0 = phy not able to operate at 10 mbps full-duplex mode ro 1 1.11 10 mbps half duplex 1 = phy able to operate at 10 mbps in half-duplex mode 0 = phy not able to operate at 10 mbps in half-duplex ro 1 1.10 100base-t2 full duplex 1 = phy able to perform full-duplex 100base-t2 0 = phy not able to perform full-duplex 100base-t2 ro 0 1.9 100base-t2 half duplex 1 = phy able to perform half duplex 100base-t2 0 = phy not able to perform half-duplex 100base-t2 ro 0 1.8 extended status 1 = extended status information in register 15 0 = no extended status information in register 15 ro 0 1.7 reserved 1 = ignore when read ro 0 1.6 mf preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed ro 0 1.5 auto-negotiation complete 1 = auto-negotiation complete 0 = auto-negotiation not complete ro 0 1.4 remote fault 2 1 = remote fault condition detected 0 = no remote fault condition detected ro/lh 0 1.3 auto-negotiation ability 1 = phy is able to perform auto-negotiation 0 = phy is not able to perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber condition detected 0 = jabber condition not detected ro/lh 0 1.0 extended capability 1 = extended register capabilities 0 = extended register capabilities ro 1 table 37. phy identification register 1 (address 2) bit name description type 1 default 2.15:0 phy id number the phy identifier composed of bits 3 through 18 of the oui. ro 0013 hex 1. ro = read only table 36. status register (address 1) (continued) bit name description type 1 defaul t 1. ro = read only ll = latching low lh = latching high 2. bit 1.4 is not valid if auto-negotiation is selected while operating in fiber mode.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 67 table 38. phy identification register 2 (address 3) bit name description type 1 default 3.15:10 phy id number the phy identifier composed of bits 19 through 24 of the oui. ro 011110 3.9:4 manufacturer ? s model number 6 bits containing manufacturer ? s part number. ro 000111 (lxt9761) 001010 (lxt9781) 3.3:0 manufacturer ? s revision number 4 bits containing manufacturer ? s revision number. ro xxxx 1. ro = read only figure 38. phy identifier bit mapping table 39. auto-negotiation advertisement register (address 4) bit name description type 1 default 4.15 next page 1 = port has ability to send multiple pages. 0 = port has no ability to send multiple pages. r/w 0 4.14 reserved ignore. ro 0 4.13 remote fault 1 = remote fault. 0 = no remote fault. r/w 0 4.12 reserved ignore. r/w 0 4.11 asymmetric pause pause operation defined in clause 40 and 27 r/w 0 4.10 pause 1 = pause operation enabled for full-duplex links. 0 = pause operation disabled. r/w note 2 1. r/w = read/write ro = read only 2. the default setting of bit 4.10 (pause) is determined by pin 79. 3. default settings for bits 4.5:8 are determined by led?cfg pins as described in table 9 on page 29 . a bc 1 23 organizationally unique identifier rs 18 19 0 00 0 00 0 00 0 01 0 01 15 0 1 phy id register #1 (address 2) x 24 0 11 1 10 9 4 3 15 0 x phy id register #2 (address 3) 10 0 i/g 5 0 manufacturer ? s model number 3 0 revision number the level one oui is 00207b hex. 0 0013 0 002b7 xxx xxxxxx 7b 20 00 the intel
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 68 datasheet 4.9 100base-t4 1 = 100base-t4 capability is available. 0 = 100base-t4 capability is not available. (the lxt97x1 does not support 100base-t4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100base-t4 operation. an external 100base-t4 transceiver could be switched in if this capability is desired.) r/w 0 4.8 100base-tx full duplex 1 = port is 100base-tx full duplex capable. 0 = port is not 100base-tx full duplex capable. r/w note 2 4.7 100base-tx 1 = port is 100base-tx capable. 0 = port is not 100base-tx capable. r/w note 2 4.6 10base-t full duplex 1 = port is 10base-t full duplex capable. 0 = port is not 10base-t full duplex capable. r/w note 2 4.5 10base-t 1 = port is 10base-t capable. 0 = port is not 10base-t capable. r/w note 2 4.4:0 selector field, s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-n egotiation development. unspecified or reserved combinations should not be transmitted. r/w 00001 table 40. auto-negotiation link partner base page ability register (address 5) bit name description type 1 default 5.15 next page 1 = link partner has ability to send multiple pages. 0 = link partner has no ability to send multiple pages. ro 0 5.14 acknowledge 1 = link partner has received link code word from lxt97x1. 0 = link partner has not received link code word from the lxt97x1. ro 0 5.13 remote fault 1 = remote fault. 0 = no remote fault. ro 0 5.12 reserved ignore. ro 0 5.11 asymmetric pause pause operation defined in clause 40 and 27. 1 = link partner is pause capable. 0 = link partner is not pause capable. ro 0 5.10 pause 1 = link partner is pause capable. 0 = link partner is not pause capable. ro 0 5.9 100base-t4 1 = link partner is 100base-t4 capable. 0 = link partner is not 100base-t4 capable. ro 0 5.8 100base-tx full duplex 1 = link partner is 100base-tx full duplex capable. 0 = link partner is not 100base-tx full duplex capable. ro 0 5.7 100base-tx 1 = link partner is 100base-tx capable. 0 = link partner is not 100base-tx capable. ro 0 1. ro = read only table 39. auto-negotiation advertisement register (address 4) (continued) bit name description type 1 default 1. r/w = read/write ro = read only 2. the default setting of bit 4.10 (pause) is determined by pin 79. 3. default settings for bits 4.5:8 are determined by led?cfg pins as described in table 9 on page 29 .
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 69 5.6 10base-t full duplex 1 = link partner is 10base-t full duplex capable. 0 = link partner is not 10base-t full duplex capable. ro 0 5.5 10base-t 1 = link partner is 10base-t capable. 0 = link partner is not 10base-t capable. ro 0 5.4:0 selector field s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-n egotiation development. unspecified or reserved combinations shall not be transmitted. ro 00000 table 41. auto-negotiation expansion (address 6) bit name description type 1 default 6.15:6 reserved ignore on read. ro 0 6.5 base page this bit indicates the status of the auto_negotiation variable, base page. it flags synchronization with the auto_negotiation state diagram allowing detection of interrupted links. this bit is only used if bit 16.1 (alternate np feature) is set. 1 = base_page = true 0 = base_page = false ro 0 6.4 parallel detection fault 1 = parallel detection fault has occurred. 0 = parallel detection fault has not occurred. ro/ lh 0 6.3 link partner next page able 1 = link partner is next page able. 0 = link partner is not next page able. ro 0 6.2 next page able 1 = local device is next page able. 0 = local device is not next page able. ro 1 6.1 page received 1 = 3 identical and consecutive link code words have been received from link partner. 0 = 3 identical and consecutive link code words have not been received from link partner. ro lh 0 6.0 link partner a/n able 1 = link partner is auto-negotiation able. 0 = link partner is not auto-negotiation able. ro 0 1. ro = read only lh = latching high table 42. auto-negotiation next page transmit register (address 7) bit name description type 1 default 7.15 next page (np) 1 = additional next pages follow. 0 = last page. r/w 0 7.14 reserved write as 0, ignore on read. ro 0 7.13 message page (mp) 1 = message page. 0 = unformatted page. r/w 1 1. r/w = read write ro = read only table 40. auto-negotiation link partner base page ability register (address 5) (continued) bit name description type 1 default 1. ro = read only
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 70 datasheet 7.12 acknowledge 2 (ack2) 1 = will comply with message. 0 = can not comply with message. r/w 0 7.11 toggle (t) 1 = previous value of the transmitted link code word equalled logic zero. 0 = previous value of the transmitted link code word equalled logic one. r/w 0 7.10:0 message/unformatted code field r/w 00000000001 table 43. auto-negotiation link partner next page receive register (address 8) bit name description type 1 default 8.15 next page (np) 1 = link partner has additional next pages to send. 0 = link partner has no additional next pages to send. ro 0 8.14 acknowledge (ack) 1 = link partner has received link code word from lxt97x1. 0 = link partner has not received link code word from lxt97x1. ro 0 8.13 message page (mp) 1 = page sent by the link partner is a message page. 0 = page sent by the link partner is an unformatted page. ro 0 8.12 acknowledge 2 (ack2) 1 = link partner will comply with the message. 0 = link partner can not comply with the message. ro 0 8.11 toggle (t) 1 = previous value of the transmitted link code word equalled logic zero. 0 = previous value of the transmitted link code word equalled logic one. ro 0 8.10:0 message/unformatted code field ro 0 1. ro = read only table 44. port configuration register (address 16, hex 10) bit name description type 1 default 16.15 reserved write as zero. ignore on read. r/w 0 16.14 force link pass 1 = force link pass. sets appropriate registers and leds to pass. 0 = normal operation. r/w 0 16.13 transmit disable 1 = disable twisted pair transmitter. 0 = normal operation. r/w 0 16.12 bypass scramble (100base-tx) 1 = bypass scrambler and descrambler. 0 = normal operation. r/w 0 16.11 reserved write as zero. ignore on read. r/w 0 16.10 jabber (10base-t) 1 = disable jabber. 0 = normal operation. r/w 0 1. r/w = read /write 2. the default value of bit 16.0 is determined by the sd/tp n pin for the respective port. if sd/tp n is tied low, the default value of bit 16.0 = 0. if sd/tp n is not tied low, the default value of bit 16.0 = 1. table 42. auto-negotiation next page transmit register (address 7) bit name description type 1 default 1. r/w = read write ro = read only
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 71 16.9 sqe (10base-t) this bit is ignored by the lxt97x1. 1 = enable heart beat. 0 = disable heart beat. r/w 0 16.8 tp loopback (10base-t) 1 = disable tp loopback during half duplex operation. 0 = normal operation. r/w 1 16.7 crs select (10base-t) 1 = crs de-assert extends to rxdv de-assert. 0 = normal operation. r/w 1 16.6 fifo size 0 = fifo allows packets up to 2 kbytes. 1 = fifo allows packets up to 10 kbytes. packet sizes assume a 450 ppm difference between the reference clock and the recovered clock. r/w 0 16.5 pre_en (10base-t) preamble enable. 0 = set rx_dv high coincident with sfd. 1 = set rx_dv high and rxd=preamble when crs is asserted. r/w 0 16.4 reserved write as zero. ignore on read. r/w 0 16.3 reserved write as zero. ignore on read. r/w 0 16.2 far end fault transmit enable 1 = enable far end fault code transmission. 0 = disable far end fault code transmission. r/w 1 16.1 alternate np feature 1 = enable alternate auto-negotiate next page feature. 0 = disable alternate auto-negotiate next page feature. r/w 0 16.0 fiber select 1 = select fiber mode for this port. 0 = select tp mode for this port. r/w note 2 table 45. quick status register (address 17, hex 11) bit name description type 1 default 17.15 reserved always 0. ro 0 17.14 10/100 mode 1 = lxt97x1 is operating in 100base-tx mode. 0 = lxt97x1 is not operating 100base-tx mode. ro 0 17.13 transmit status 1 = lxt97x1 is transmitting a packet. 0 = lxt97x1 is not transmitting a packet. ro 0 17.12 receive status 1 = lxt97x1 is receiving a packet. 0 = lxt97x1 is not receiving a packet. ro 0 17.11 collision status 1 = collision is occurring. 0 = no collision. ro 0 17.10 link 1 = link is up. 0 = link is down. ro 0 17.9 duplex mode 1 = full duplex. 0 = half duplex. ro 0 17.8 auto-negotiation 1 = lxt97x1 is in auto-negotiation mode. 0 = lxt97x1 is in manual mode. ro 0 1. ro = read only table 44. port configuration register (address 16, hex 10) bit name description type 1 default 1. r/w = read /write 2. the default value of bit 16.0 is determined by the sd/tp n pin for the respective port. if sd/tp n is tied low, the default value of bit 16.0 = 0. if sd/tp n is not tied low, the default value of bit 16.0 = 1.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 72 datasheet 17.7 auto-negotiation complete 1 = auto-negotiation process completed. 0 = auto-negotiation process not completed. this bit is only valid when auto-negotiate is enabled, and is equivalent to bit 1.5. ro 0 17.6 reserved reserved. ro 0 17.5 polarity 1= polarity is reversed. 0= polarity is not reversed. ro 0 17.4 pause 1 = the lxt97x1 is pause capable. 0 = the lt97x1 is not pause capable. ro 0 17:3 error 1 = error occurred (remote fault, x,y,z). 0 = no error occurred. ro 0 17:2:0 reserved ignore. ro 0 table 46. interrupt enable register (address 18, hex 12) bit name description type 1 default 18.15:8 reserved write as 0; ignore on read. r/w n/a 18.7 anmsk mask for auto-negotiate complete 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.6 speedmsk mask for speed interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.5 duplexmsk mask for duplex interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.4 linkmsk mask for link status interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.3 reserved write as 0, ignore on read. r/w 0 18.2 reserved write as 0, ignore on read. r/w 0 18.1 inten 1 = enable interrupts on this port. 0 = disable interrupts on this port. r/w 0 18.0 tint 1 = force interrupt on mdint. 0 = normal operation. r/w 0 1. r/w = read /write table 45. quick status register (address 17, hex 11) bit name description type 1 default 1. ro = read only
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 73 table 47. interrupt status register (address 19, hex 13) bit name description type 1 default 19.15:8 reserved ignore ro n/a 19.7 andone auto-negotiation status 1= auto-negotiation has completed. 0= auto-negotiation has not completed. ro/sc n/a 19.6 speedchg speed change status 1 = a speed change has occurred since last reading this register. 0 = a speed change has not occurred since last reading this register. ro/sc 0 19.5 duplexchg duplex change status 1 = a duplex change has occurred since last reading this register. 0 = a duplex change has not occurred since last reading this register. ro/sc 0 19.4 linkchg link status change status 1 = a link change has occurred since last reading this register. 0 = a link change has not occurred since last reading this register. ro/sc 0 19.3 reserved ignore. ro 0 19.2 mdint 1 = rmii interrupt pending. 0 = no rmii interrupt pending. ro/sc 0 19.1:0 reserved ignore. ro 0 1. r/w = read/write ro = read only sc = self clearing
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 74 datasheet table 48. led configuration register (address 20, hex 14) bit name description type 1 default 20.15:12 led1 programming bits 0000 = display speed status (continuous, default). 0001 = display transmit status (stretched). 0010 = display receive status (stretched). 0011 = display collision status (stretched). 0100 = display link status (continuous). 0101 = display duplex status (continuous) 5 . 0110 =reserved. 0111 = display receive or transmit activity (stretched). 1000 = test mode- turn led on (continuous). 1001 = test mode- turn led off (continuous). 1010 = test mode- blink led fast (continuous). 1011 = test mode- blink led slow (continuous). 1100 = display link and receive status combined 2 (stretched) 3 . 1101 = display link and activity status combined 2 (stretched) 3 . 1110 = display duplex & collision status combined 4 (stretched) 3,5 . 1111 = reserved. r/w 0000 20.11:8 led2 programming bits 0000 = display speed status. 0001 = display transmit status. 0010 = display receive status. 0011 = display collision status. 0100 = display link status (default). 0101 = display duplex status 5 . 0110 = reserved. 0111 = display receive or transmit activity. 1000 = test mode- turn led on. 1001 = test mode- turn led off. 1010 = test mode- blink led fast. 1011 = test mode- blink led slow. 1100 = display link and receive status combined 2 (stretched) 3 . 1101 = display link and activity status combined 2 (stretched) 3 . 1110 = display duplex & collision status combined 4 (stretched) 3,5 . 1111 = reserved. r/w 0100 20.7:4 led3 programming bits 0000 = display speed status. 0001 = display transmit status. 0010 = display receive status (default). 0011 = display collision status. 0100 = display link status. 0101 = display duplex status 5 . 0110 = reserved. 0111 = display receive or transmit activity. 1000 = test mode- turn led on. 1001 = test mode- turn led off. 1010 = test mode- blink led fast. 1011 = test mode- blink led slow. 1100 = display link and receive status combined 2 (stretched) 3 . 1101 = display link and activity status combined 2 (stretched) 3 . 1110 = display duplex & collision status combined 4 (stretched) 3,5 . 1111 = reserved. r/w 0010 1. r/w = read /write ro = read only lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activity) causes the led to change state (blink). 3. combined event led settings are not affected by pulse stretch bit 20.1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. duplex led maybe active for a brief time after loss of link.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 75 20.3:2 ledfreq 00 = stretch led events to 30 ms. 01 = stretch led events to 60 ms. 10 = stretch led events to 100 ms. 11 = reserved. r/w 00 20.1 pulse- stretch 1 = enable pulse stretching of all leds. 0 = disable pulse stretching of all leds 2 . r/w 1 20.0 invpol 1 = use active high polarity for serial leds. 0 = use active low polarity for serial leds. r/w 0 table 49. out of band signaling register (address 25) bit name description type 1 default 25:15:7 reserved reserved. r/w 0 25:6:4 bit1 these 3 bits select which status information is available on the rxd(1) bit of the rmii bus. 000 = link 001 = speed 010 = duplex 011 = auto-negotiation complete 100 = polarity reversed 101 = jabber detected 110 = interrupt pending 111 = reserved r/w 000 25.3:1 bit0 these 3 bits select which status information is available on the rxd(0) bit of the rmii bus. 000 = link 001 = speed 010 = duplex 011 = auto-negotiation complete 100 = polarity reversed 101 = jabber detected 110 = interrupt pending 111 = reserved r/w 000 25.0 progrmii 1 = enable programmable rmii out of band signalling. when enabled, bits 6:1 specify which status bits are available on the rmii rxd data bus. 0 = disable out of band signalling. r/w 0 1. r/w = read/write ro = read only table 48. led configuration register (address 20, hex 14) (continued) bit name description type 1 default 1. r/w = read /write ro = read only lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activity) causes the led to change state (blink). 3. combined event led settings are not affected by pulse stretch bit 20.1. these display settings are stretched regardless of the value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. duplex led maybe active for a brief time after loss of link.
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 76 datasheet table 50. transmit control register #1 (address 28) bit name description type 2 default 28.15:4 reserved ignore. r/w n/a 28.3:2 bandwidth control 00 = nominal differential amp bandwidth 01 = slower 10 = fastest 11 = faster r/w 00 28.1:0 risetime control 00 = 2.5ns 01 = 3.1ns 10 = 3.7ns 11 = 4.3ns r/w note 3 1. transmit control functions are approximations. they are not guaranteed and not subject to production testing. 2. ro = read only. r/w = read/write. 3. the default setting of bits 28.1:0 (risetime) are determined by pins 91 and 94. table 51. transmit control register #2 (address 30) bit name description type default 30.15:14 reserved r/w n/a 30.13 increase driver amplitude 1 = increase driver amplitude 5% in all modes. 0 = normal operation. r/w 0 30.12:0 reserved r/w n/a 1. ro = read only.
fast ethernet 10/100 multi-port transceiver with rmii ? lxt9761/9781 datasheet 77 6.0 package specifications figure 39. lxt97x1 pqfp specification e / 2 a 1 a 2 l a b l 1 3 2 d d 1 e e 1 e dim millimeters min max a - 4.10 a1 0.25 - a2 3.20 3.60 b 0.17 0.27 d 30.30 30.90 d 1 27.70 28.30 e 30.30 30.90 e 1 27.70 28.30 e .50 b asic l 0.50 0.75 l 1 1.30 ref q 0 7 2 5 16 3 5 16 208-pin plastic quad flat package part number lxt9761hc (6-port model) part number LXT9781HC (8-port model) commercial temperature range (0 c to 70 c)
lxt9761/9781 ? fast ethernet 10/100 multi-port transceiver with rmii 78 datasheet figure 40. lxt9781 pbga specification 1.435 re f 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view note: 1. all dimensions in millimeters 2. all dimensions and tolerances conform to asme y 14.5m-1994 3. tolerance = 0.05 unless specified otherwise 15 16 17 19 20 18 1.27 a b c d e f g h j k l m n p r t u v w y 0.75 0.15 1.435 ref 1.27 24.13 24.13 pin #a1 corner 27.00 0.20 27.00 0.20 24.00 0.20 8.00 0.10 8.00 0.10 ? 1.00 (3 plcs) pin #a1 id top view 24.00 0.20 0.60 0.10 0.61 0.04 0.92 0.05 seating plane side view 2.13 0.19 272-lead plastic ball grid array part number lxt9781bc (8-port model) commercial temperature range (0 c to 70 c)

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