View RH80532NC029256_1919833.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mobile intel ? celeron ? processor on .13 micron process and in micro-fcpga package datasheet september 2002 order number: 251308-002
2 251308-002 datasheet information in this document is provided solely to enable use of intel products. intel assumes no liability whatsoever, includi ng infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such pro ducts. information contained herein supersedes previously published specifications on these devices from intel. actual system-level properties, such as skin temperature, are a function of various factors, including component placement, com ponent power characteristics, system power and thermal management techniques, software application usage and general system design. intel i s not responsible for its customers' system designs, nor is intel responsible for ensuring that its customers' products comply with all applicabl e laws and regulations. intel provides this and other thermal design information for informational purposes only. system design is the sole responsibi lity of intel's customers, and intel's customers should not rely on any intel-provided information as either an endorsement or recommendation of any parti cular system design characteristics. information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the mobile intel celeron processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtain ed by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com copyright ? 2002 intel corporation. intel, celeron, and intel netburst are registered trademarks or trademarks of intel corporation and its subsidiares in the unit ed states and other countries. * other brands and names may be claimed as property of others.
251308-002 3 datasheet contents contents 1 introduction.................................................................................................................. .................... 9 1.1 terminology ................................................................................................................. .......10 1.1.1 terminology ...........................................................................................................10 1.2 references .................................................................................................................. .......11 2 electrical specifications ..................................................................................................... ............13 2.1 system bus and gtlref ..................................................................................................13 2.2 power and ground pins......................................................................................................1 3 2.3 decoupling guidelines ....................................................................................................... .13 2.3.1 vcc decoupling ....................................................................................................14 2.3.2 system bus agtl+ decoupling ............................................................................14 2.3.3 system bus clock (bclk[1:0]) and processor clocking .......................................14 2.4 voltage identification and power sequencing ....................................................................15 2.4.1 phase lock loop (pll) power and filter ..............................................................16 2.4.2 catastrophic thermal protection ...........................................................................18 2.5 signal terminations, unused pins, and testhi[11:0] .......................................................18 2.6 system bus signal groups .................................................................................................19 2.7 asynchronous gtl+ signals ..............................................................................................21 2.8 test access port (tap) connection ...................................................................................21 2.9 system bus frequency select signals (bsel[1:0]) ...........................................................21 2.10 maximum ratings ............................................................................................................ ...22 2.11 processor dc specifications ..............................................................................................22 2.12 agtl+ system bus specifications .....................................................................................31 2.13 system bus ac specifications ...........................................................................................32 2.14 processor ac timing waveforms.......................................................................................37 3 system bus signal quality specifications .....................................................................................4 7 3.1 system bus clock (bclk) signal quality specifications and measurement guidelines ...47 3.2 system bus signal quality specifications and measurement guidelines ..........................48 3.3 system bus signal quality specifications and measurement guidelines ..........................51 3.3.1 overshoot/undershoot guidelines.........................................................................51 3.3.2 overshoot/undershoot magnitude .........................................................................51 3.3.3 overshoot/undershoot pulse duration ..................................................................51 3.3.4 activity factor ........................................................................................................52 3.3.5 reading overshoot/undershoot specification tables ...........................................52 3.3.6 conformance determination to overshoot/undershoot specifications..................53 4 package mechanical specifications ............................................................................................. .57 4.1 processor pin-out ........................................................................................................... ...60 5 pin listing and signal definitions ............................................................................................ ......63 5.1 mobile intel celeron processor pin assignments ...............................................................63 5.2 alphabetical signals reference..........................................................................................77 6 thermal specifications and design considerations ......................................................................85 6.1 thermal specifications ...................................................................................................... .86 6.1.1 thermal diode .......................................................................................................86
4 251308-002 datasheet contents 6.1.2 thermal monitor..................................................................................................... 87 7 configuration and low power features ........................................................................................ 89 7.1 power-on configuration options........................................................................................ 89 7.2 clock control and low power states ................................................................................. 89 7.2.1 normal state.......................................................................................................... 89 7.2.2 autohalt powerdown state ................................................................................. 90 7.2.3 stop-grant state.................................................................................................... 90 7.2.4 halt/grant snoop state....................................................................................... 91 7.2.5 sleep state ............................................................................................................ 91 7.2.6 deep sleep state................................................................................................... 92 8 debug tools specifications .................................................................................................... ....... 93 8.1 logic analyzer interface (lai) ............................................................................................ 93 8.1.1 mechanical considerations.................................................................................... 93 8.1.2 electrical considerations ....................................................................................... 93
251308-002 5 datasheet contents figures 1 vccvid pin voltage and current requirements .......................................................................15 2 typical vcciopll, vcca and vssa power distribution..........................................................17 3 phase lock loop (pll) filter requirements.............................................................................17 4 illustration of vcc static and transient tolerances (vid = 1.30 v) ...........................................25 5 illustration of deep sleep vcc static and transient tolerances (vid setting = 1.30 v) ...........26 6 itpclkout[1:0] output buffer diagram....................................................................................31 7 ac test circuit............................................................................................................... .............38 8 tck clock waveform ............................................................................................................ .....38 9 differential clock waveform ................................................................................................... ....39 10 differential clock crosspoint specification .................................................................................4 0 11 system bus common clock valid delay timings ......................................................................40 12 system bus reset and configuration timings ...........................................................................41 13 source synchronous 2x (address) timings...............................................................................41 14 source synchronous 4x timings ...............................................................................................4 2 15 power up sequence........................................................................................................... .......43 16 power down sequence .......................................................................................................... ....43 17 test reset timings........................................................................................................... ..........44 18 thermtrip# to vcc timing ..................................................................................................... .44 19 ferr#/pbe# valid delay timing...............................................................................................4 4 20 tap valid delay timing....................................................................................................... .......45 21 itpclkout valid delay timing................................................................................................. 45 22 stop grant/sleep/deep sleep timing.........................................................................................46 23 bclk signal integrity waveform ............................................................................................... .48 24 low-to-high system bus receiver ringback tolerance ............................................................49 25 high-to-low system bus receiver ringback tolerance ............................................................49 26 low-to-high system bus receiver ringback tolerance for pwrgood and tap buffers .......50 27 high-to-low system bus receiver ringback tolerance for pwrgood and tap buffers .......50 28 maximum acceptable overshoot/undershoot waveform...........................................................56 29 micro-fcpga package top and bottom isometric views..........................................................57 30 micro-fcpga package - top and side views ...........................................................................58 31 micro-fcpga package - bottom view .......................................................................................60 32 the coordinates of the processor pins as viewed from the top of the package.....................61 33 clock control states ......................................................................................................... ..........90
6 251308-002 datasheet contents tables 1 references .................................................................................................................... ............. 11 2 core frequency to system bus multipliers ................................................................................ 14 3 voltage identification definition ............................................................................................. ..... 15 4 system bus pin groups ......................................................................................................... .... 20 5 bsel[1:0] frequency table for bclk[1:0]................................................................................. 21 6 processor dc absolute maximum ratings ................................................................................ 22 7 voltage and current specifications ............................................................................................ 23 8 imvp-iii voltage regulator tolerances for vid = 1.30 v operating mode................................. 24 9 imvp-iii deep sleep state voltage regulator tolerances (vid = 1.30 v, vid offset = 4.62%) 25 10 system bus differential bclk specifications............................................................................. 27 11 agtl+ signal group dc specifications..................................................................................... 28 12 asynchronous gtl+ signal group dc specifications ............................................................... 29 13 pwrgood and tap signal group dc specifications .............................................................. 30 14 itpclkout[1:0] dc specifications ........................................................................................... 30 15 bsel [1:0] and vid[4:0] dc specifications ................................................................................ 31 16 agtl+ bus voltage definitions ................................................................................................ .. 32 17 system bus differential clock specifications ............................................................................. 33 18 system bus common clock ac specifications.......................................................................... 33 19 system bus source synch ac specifications agtl+ signal group ......................................... 34 20 miscellaneous signals ac specifications ................................................................................... 35 21 system bus ac specifications (reset conditions) .................................................................... 35 22 tap signals ac specifications................................................................................................ ... 36 23 itpclkout[1:0] ac specifications ........................................................................................... 36 24 stop grant/sleep/deep sleep ac specifications ....................................................................... 37 25 bclk signal quality specifications ........................................................................................... .47 26 ringback specifications for agtl+ and asynchronous gtl+ signal groups ........................... 48 27 ringback specifications for pwrgood input and tap signal groups .................................... 49 28 source synchronous (400 mhz) agtl+ signal group overshoot/undershoot tolerance........ 53 29 source synchronous (200 mhz) agtl+ signal group overshoot/undershoot tolerance........ 54 30 common clock (100 mhz) agtl+ signal group overshoot/undershoot tolerance................. 54 31 asynchronous gtl+, pwrgood input, and tap signal groups overshoot/undershoot tolerance...................................................................................................................... .............. 56 32 micro-fcpga package dimensions .......................................................................................... 59 33 pin listing by pin name ...................................................................................................... ....... 64 34 pin listing by pin number .................................................................................................... ...... 70 35 signal description........................................................................................................... ............ 77 36 power specifications for the mobile intel celeron processor ..................................................... 85 37 thermal diode interface ...................................................................................................... ....... 86 38 thermal diode specifications ................................................................................................. .... 86 39 power-on configuration option pins ......................................................................................... 89
251308-002 7 datasheet contents revision history date revision description june 2002 1.0 initial release of the datasheet september 2002 2.0 updates include: ? added specifications for 1.6 ghz, 1.7 ghz, and 1.8 ghz ? current and power specifications updated in table 7 and table 38 ? corrected stpclk#/slp# timing relationship in section 7.2.3 to match parameter t75.
8 251308-002 datasheet contents this page intentionally left blank.
251308-002 9 datasheet introduction 1 introduction the mobile intel ? celeron ? processor on .13 micron process and in micro-fcpga package utilizes a 478-pin, micro flip-chip pin grid array (micro-fcpga) package, and plugs into a surface-mount, zero insertion force (zif) socket. the mobile intel celeron processor on .13 micron process maintains the tradition of compatibility with ia-32 software. in this document the mobile intel celeron processor on .13 micron process and in micro-fcpga package will be referred to as the ?mobile intel celeron processor? or simply ?the processor?. the mobile intel celeron processor is designed for uni-processor based value pc mobile systems. features of the processor include hyper pipelined technology, a 400-mhz system bus, and an execution trace cache. the 400-mhz system bus is a quad-pumped bus running off a 100-mhz system clock making 3.2 gb/sec data transfer rates possible. the execution trace cache is a first level cache that stores approximately 12-k decoded micro-operations, which removes the decoder from the main execution path. additional features include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and streaming simd extensions 2 (sse2). the advanced dynamic execution improves speculative execution and branch prediction internal to the processor. the advanced transfer cache is a 256 kb, on-die level 2 (l2) cache. the floating point and multi media units have 128-bit wide registers with a separate register for data movement. finally, sse2 support includes instructions for double-precision floating point, simd integer, and memory management. power management capabilities such as autohalt, stop-grant, sleep, and deep sleep have been incorporated. the processor includes an address bus power down capability which removes power from the address and data pins when the system bus is not in use. this feature is always enabled on the processor. the mobile intel celeron processor?s 400-mhz system bus utilizes a split-transaction, deferred reply protocol. this system bus is not compatible with the p6 processor family bus. the 400-mhz system bus uses source-synchronous transfer (sst) of address and data to improve throughput by transferring data four times per bus clock (4x data transfer rate, as in agp 4x). along with the 4x data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ?double-clocked? or 2x address bus. working together, the 4x data bus and 2x address bus provide a data bus bandwidth of up to 3.2 gbytes/second. the processor system bus uses a variant of gtl+ signalling technology called assisted gunning transceiver logic (agtl+) signal technology. the mobile intel celeron processor is available at the following core frequencies: ? 1.8 ghz (at 1.30 v) ? 1.7 ghz (at 1.30 v) ? 1.6 ghz (at 1.30 v) ? 1.5 ghz (at 1.30 v) ? 1.4 ghz (at 1.30 v)
10 251308-002 datasheet introduction 1.1 terminology a ?#? symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data ), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). ?system bus? refers to the interface between the processor and system core logic (also known as the chipset components). the system bus is a multiprocessing interface to processors, memory, and i/o. 1.1.1 terminology commonly used terms are explained here for clarification: ? processor ? for this document, the term processor shall mean the mobile intel celeron processor in the 478-pin package. ? keep out zone ? the area on or near the processor that system design can not utilize. ? intel ? 845mp/845mz chipsets ? mobile chipsets that will support the mobile intel celeron processor. ? processor core ? mobile intel celeron processor core die with integrated l2 cache. ? micro-fcpga package ? micro flip-chip pin grid array package with 50-mil pin pitch.
251308-002 11 datasheet introduction 1.2 references material and concepts available in the following documents may be beneficial when reading this document. table 1. references document order number mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide 250688-002 intel architecture software developer's manual volume i: basic architecture 245470 volume ii: instruction set reference 245471 volume iii: system programming guide 245472
12 251308-002 datasheet introduction this page intentionally left blank.
251308-002 13 datasheet electrical specifications 2 electrical specifications 2.1 system bus and gtlref most mobile intel celeron processor system bus signals use assisted gunning transceiver logic (agtl+) signalling technology. as with the intel p6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. the termination voltage level for the mobile intel celeron processor agtl+ signals is v cc , which is the operating voltage of the processor core. previous generations of intel mobile processors utilize a fixed termination voltage known as v cct . the use of a termination voltage that is determined by the processor core allows better voltage scaling on the system bus for mobile intel celeron processor. because of the speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. design guidelines for the mobile intel celeron processor system bus will be detailed in the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide. the agtl+ inputs require a reference voltage (gtlref) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. gtlref must be generated on the system board. termination resistors are provided on the processor silicon and are terminated to its core voltage (v cc ). intel?s 845mp/845mz chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most agtl+ signals. however, some agtl+ signals do not include on-die termination and must be terminated on the system board. for more information, refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide. the agtl+ bus depends on incident wave switching. therefore, timing calculations for agtl+ signals are based on flight time as opposed to capacitive deratings. analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. 2.2 power and ground pins for clean on-chip power distribution, the mobile intel celeron processor have 85 v cc (power) and 181 v ss (ground) inputs. all power pins must be connected to v cc , while all v ss pins must be connected to a system ground plane.the processor v cc pins must be supplied with the voltage determined by the vid (voltage id) pins and the loadline specifications (see figure 4 to figure 5 ). 2.3 decoupling guidelines due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. this may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in table 7 . failure to do so can result in timing violations and affect
251308-002 14 datasheet electrical specifications the long term reliability of the processor. for further information and design guidelines, refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide. 2.3.1 v cc decoupling regulator solutions need to provide bulk capacitance with a low effective series resistance (esr) and keep a low interconnect resistance from the regulator to the socket. bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. for more details on decoupling recommendations, please refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide. 2.3.2 system bus agtl+ decoupling the mobile intel celeron processor integrates signal termination on the die and incorporates high frequency decoupling capacitance on the processor package. decoupling must also be provided by the system motherboard for proper agtl+ bus operation. for more information, refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide. 2.3.3 system bus clock (bclk[1:0]) and processor clocking bclk[1:0] directly controls the system bus interface speed as well as the core frequency of the processor. as in previous generation processors, the mobile intel celeron processor core frequency is a multiple of the bclk[1:0] frequency. refer to table 2 for the mobile intel celeron processor supported ratios. notes: 1. ratio is used for debug purposes only. 2. listed frequencies are not necessarily committed production frequencies. the mobile intel celeron processor uses a differential clocking implementation. table 2. core frequency to system bus multipliers core frequency multiplication of system core frequency to system bus frequency notes 2 800 mhz 1/8 1 1.20 ghz 1/12 1.40 ghz 1/14 1.50 ghz 1/15 1.60 ghz 1/16 1.70 ghz 1/17 1.80 ghz 1/18
251308-002 15 datasheet electrical specifications 2.4 voltage identification and power sequencing the voltage set by the vid pins is the nominal/typical voltage setting for the processor. a minimum voltage is provided in table 7 and changes with frequency. this allows processors running at a higher frequency to have a relaxed minimum voltage specification. the specifications have been set such that one voltage regulator can work with all supported frequencies. the mobile intel celeron processor uses five voltage identification pins, vid[4:0], to support automatic selection of power supply voltages. the vid pins for the mobile intel celeron processor are open drain outputs driven by the processor vid circuitry. table 3 specifies the voltage level corresponding to the state of vid[4:0]. a ?1? in this table refers to a high-voltage level and a ?0? refers to low-voltage level. power source characteristics must be stable whenever the supply to the voltage regulator is stable. refer to figure 15 for timing details of the power up sequence. also refer to mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for implementation details. mobile intel celeron processor?s voltage identification circuit requires an independent 1.2 v supply. this voltage must be routed to the processor vccvid pin. figure 1 shows the voltage and current requirements of the vccvid pin. figure 1. vccvid pin voltage and current requirements 1ma 80ma 150ma to 300ma 30ma 1v 1.2v+10% 1.2v-5% 5ns 70ns table 3. voltage identification definition (sheet 1 of 2) processor pins vid4 vid3 vid2 vid1 vid0 v cc_ 111110.600
251308-002 16 datasheet electrical specifications 2.4.1 phase lock loop (pll) power and filter v cca and v cciopll are power sources required by the pll clock generators on the mobile intel celeron processor silicon. since these plls are analog in nature, they require quiet power supplies for minimum jitter. jitter is detrimental to the system: it degrades external i/o timings as well as internal core timings (i.e. maximum frequency). to prevent this degradation, these supplies must be low pass filtered from v ccvid . a typical filter topology is shown in figure 2 . the ac low-pass requirements, with input at v ccvid and output measured across the capacitor (c a or c io in figure 2 ), is as follows: ? < 0.2 db gain in pass band ? < 0.5 db attenuation in pass band < 1 hz 111100.625 111010.650 111000.675 110110.700 110100.725 110010.750 110000.775 101110.800 101100.825 101010.850 101000.875 100110.900 100100.925 100010.950 100000.975 011111.000 011101.050 011011.100 011001.150 010111.200 010101.250 010011.300 010001.350 001111.400 001101.450 001011.500 001001.550 000111.600 000101.650 000011.700 000001.750 table 3. voltage identification definition (sheet 2 of 2)
251308-002 17 datasheet electrical specifications ? > 34 db attenuation from 1 mhz to 66 mhz ? > 28 db attenuation from 66 mhz to core frequency the filter requirements are illustrated in figure 3 . for recommendations on implementing the filter refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide . . notes: 1. diagram not to scale. figure 2. typical v cciopll , v cca and v ssa power distribution figure 3. phase lock loop (pll) filter requirements v ccvid vcca vssa vcciopll l l processor core pll c a c io 0 db -28 db -34 db 0.2 db forbidden zone -0.5 db forbidden zone 1 mhz 66 mhz f core f peak 1 hz dc passband high frequency band
251308-002 18 datasheet electrical specifications 1. no specification for frequencies beyond fcore (core frequency). 1. fpeak, if existent, should be less than 0.05 mhz. 2.4.2 catastrophic thermal protection the mobile intel celeron processor supports the thermtrip# signal for catastrophic thermal protection. alternatively, an external thermal sensor can be used to protect the processor and the system against excessive temperatures. even with the activation of thermtrip#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. if the external thermal sensor detects a catastrophic processor temperature of 135c (maximum), or if the thermtrip# signal is asserted, the vcc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. refer to section 5.2 for more details on thermtrip#. 2.5 signal terminations, unused pins and testhi[11:0] all nc pins must remain unconnected. connection of these pins to v cc , v ss , or to any other signal (including each other) can result in component malfunction or incompatibility with future mobile intel celeron processors. see section 5.2 for a processor pin listing and the location of all nc pins. for reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level. note that on-die termination has been included on the mobile intel celeron processor to allow signals to be terminated within the processor silicon. unused active low agtl+ inputs may be left as no connects if agtl+ termination is provided on the processor silicon. table 4 lists details on agtl+ signals that do not include on-die termination. unused active high inputs should be connected through a resistor to ground (v ss ). refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for the appropriate resistor values. unused outputs can be left unconnected, however, this may interfere with some tap functions, complicate debug probing, and prevent boundary scan testing. a resistor must be used when tying bidirectional signals to power or ground. when tying any signal to power or ground, a resistor will also allow for system testability. for unused agtl+ input or i/o signals that don?t have on-die termination, use pull-up resistors of the same value in place of the on-die termination resistors (r tt ). see table 16 . the tap, asynchronous gtl+ inputs, and asynchronous gtl+ outputs do not include on-die termination. inputs and used outputs must be terminated on the system board. unused outputs may be terminated on the system board or left unconnected. note that leaving unused outputs unterminated may interfere with some tap functions, complicate debug probing, and prevent boundary scan testing. signal termination for these signal types is discussed in the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide . the testhi pins should be tied to the processor v cc using a matched resistor, where a matched resistor has a resistance value within + 20% of the impedance of the board transmission line traces. for example, if the trace impedance is 50 ? , then a value between 40 ? and 60 ? is required. the testhi pins may use individual pull-up resistors or be grouped together as detailed below. a matched resistor should be used for each group: 1.testhi[1:0] 2.testhi[5:2]
251308-002 19 datasheet electrical specifications 3.testhi[10:8] 4.testhi[11] additionally, if the itpclkout[1:0] pins are not used then they may be connected individually to v cc using matched resistors or grouped with testhi[5:2] with a single matched resistor. if they are being used, individual termination with 1-k ? resistors is required. tying itpclkout[1:0] directly to v cc or sharing a pull-up resistor to v cc will prevent use of debug interposers. this implementation is strongly discouraged for system boards that do not implement an onboard debug port. as an alternative, group 2 (testhi[5:2]), and the itpclkout[1:0] pins may be tied directly to the processor v cc . this has no impact on system functionality. testhi[0] may also be tied directly to processor v cc if resistor termination is a problem, but matched resistor termination is recommended. in the case of the itpclkout[1:0] pins, direct tie to v cc is strongly discouraged for system boards that do not implement an onboard debug port. tying any of the testhi pins together will prevent the ability to perform boundary scan testing. pullup/down resistor requirements for the vid[4:0] and bsel[1:0] signals are included in the signal descriptions in section 5. 2.6 system bus signal groups in order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. agtl+ input signals have differential input buffers, which use gtlref as a reference level. in this document, the term "agtl+ input" refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, "agtl+ output" refers to the agtl+ output group as well as the agtl+ i/o group when driving. with the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals which are dependant upon the rising edge of bclk0 (ads#, hit#, hitm#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of bclk0. asychronous signals are still present (a20m#, ignne#, etc.) and can become active at any time during the clock cycle. table 4 identifies which signals are common clock, source synchronous, and asynchronous.
251308-002 20 datasheet electrical specifications notes: 1. refer to section 5.2 for signal descriptions. 2. these agtl+ signals do not have on-die termination. refer to section 2.5 for termination requirements. 3. in processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. in systems with the debug port implemented on the system board, these signals are no connects. 4. these signal groups are not terminated by the processor. signals not driven by the ich3-m component must be terminated on the system board. refer to section 2.5 and the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for termination requirements and further details . 5. the value of these pins during the active-to-inactive edge of reset# defines the processor configuration options. see section 7.1 for details. table 4. system bus pin groups signal group type signals 1 agtl+ common clock input common clock bpri#, defer#, reset# 2 , rs[2:0]#, rsp#, trdy# agtl+ common clock i/o synchronous ap[1:0]#, ads#, binit#, bnr#, bpm[5:0]# 2 , br0# 2 , dbsy#, dp[3:0]#, drdy#, hit#, hitm#, lock#, mcerr# agtl+ source synchronous i/o source synchronous agtl+ strobes common clock adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# asynchronous gtl+ input 4,5 asynchronous a20m#, dpslp#, ignne#, init# 5 , lint0/intr, lint1/ nmi, smi# 5 , slp#, stpclk# asynchronous gtl+ output 4 asynchronous ferr#/pbe#, ierr# 2 , thermtrip#, prochot# tap input 4 synchronous to tck tck, tdi, tms, trst# tap output 4 synchronous to tck tdo system bus clock n/a bclk[1:0], itp_clk[1:0] 3 power/other n/a v cc , v cca , v cciopll , vccvid, vid[4:0], v ss , v ssa , gtlref[3:0], comp[1:0], nc, testhi[5:0], testhi[10:8], testhi[11], itpclkout[1:0], pwrgood, thermda, thermdc, sktocc#, v cc_sense , v ss_sense, bsel[1:0], dbr# 3 signals associated strobe req[4:0]#, a[16:3]# 5 adstb0# a[35:17]# 5 adstb1# d[15:0]#, dbi0# dstbp0#, dstbn0# d[31:16]#, dbi1# dstbp1#, dstbn1# d[47:32]#, dbi2# dstbp2#, dstbn2# d[63:48]#, dbi3# dstbp3#, dstbn3#
251308-002 21 datasheet electrical specifications 2.7 asynchronous gtl+ signals mobile intel celeron processor does not utilize cmos voltage levels on any signals that connect to the processor. as a result, legacy input signals such as a20m#, ignne#, init#, lint0/intr, lint1/nmi, smi#, slp#, and stpclk# use gtl+ input buffers. legacy output ferr#/pbe# and other non-agtl+ signals (thermtrip# and prochot#) use gtl+ output buffers. all of these signals follow the same dc requirements as agtl+ signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between gtl+ and agtl+). these signals do not have setup or hold time specifications in relation to bclk[1:0]. however, all of the asynchronous gtl+ signals are required to be asserted for at least two bclks in order for the processor to recognize them. see section 2.11 and section 2.13 for the dc and ac specifications for the asynchronous gtl+ signal groups. 2.8 test access port (tap) connection due to the voltage levels supported by other components in the test access port (tap) logic, it is recommended that the mobile intel celeron processor be first in the tap chain and followed by any other components within the system. a translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level. similar considerations must be made for tck, tms, and trst#. two copies of each signal may be required, with each driving a different voltage level. 2.9 system bus frequency select signals (bsel[1:0]) the bsel[1:0] are output signals used to select the frequency of the processor input clock (bclk[1:0]). table 5 defines the possible combinations of the signals and the frequency associated with each combination. the required frequency is determined by the processor, chipset, and clock synthesizer. all agents must operate at the same frequency. the mobile intel celeron processor currently operates at a 400-mhz system bus frequency (selected by a 100-mhz bclk[1:0] frequency). individual processors will only operate at their specified system bus frequency. for more information about these pins refer to section 5.2 and the appropriate platform design guidelines. table 5. bsel[1:0] frequency table for bclk[1:0] bsel1 bsel0 function l l 100 mhz l h reserved h l reserved h h reserved
251308-002 22 datasheet electrical specifications 2.10 maximum ratings table 6 lists the processor?s maximum environmental stress ratings. the processor should not receive a clock while subjected to these conditions. functional operating parameters are listed in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from electro static discharge (esd), one should always take precautions to avoid high static voltages or electric fields. notes: 1. this rating applies to any processor pin. 2. contact intel for storage requirements in excess of one year. 2.11 processor dc specifications the processor dc specifications in this section are defined at the processor core (pads) unless noted otherwise. see section 5 for the pin signal definitions and signal pin assignments. most of the signals on the processor system bus are in the agtl+ signal group. the dc specifications for these signals are listed in table 11 . previously, legacy signals and test access port (tap) signals to the processor used low-voltage cmos buffer types. however, these interfaces now follow dc specifications similar to gtl+. the dc specifications for these signal groups are listed in table 12 and table 13 . table 7 through table 15 list the dc specifications for the mobile intel celeron processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. unless specified otherwise, all specifications for the mobile intel celeron processor are at t j = 100 c. care should be taken to read all notes associated with each parameter. table 6. processor dc absolute maximum ratings symbol parameter min max unit notes t storage processor storage temperature ?40 85 c 2 v cc any processor supply voltage with respect to v ss -0.3 1.75 v 1 v inagtl+ agtl+ buffer dc input voltage with respect to v ss -0.1 1.75 v v inasynch_gtl+ asynch gtl+ buffer dc input voltage with respect to v ss -0.1 1.75 v i vid max vid pin current 5 ma
251308-002 23 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table are based on latest post-silicon measurements available at the time of publication. 2. these voltages are targets only. a variable voltage source should exist on systems in the event that a different voltage is required. see section 2.4 and table 3 for more information. the vid bits will set the typical v cc with the minimum being defined according to current consumption at that voltage. 3. the voltage specification requirements are measured at the system board socket ball with a 100-mhz bandwidth oscilloscope, 1.5-pf maximum probe capacitance, and 1-m ? minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 4. refer to table 8 to ta b l e 9 and figure 4 to figure 5 for the minimum, typical, and maximum v cc (measured at the system board socket ball) allowed for a given current. the processor should not be subjected to any v cc and i cc combination wherein v cc exceeds v cc_max for a given current. failure to adhere to this specification can affect the long term reliability of the processor. 5. v cc_min is defined at i cc_max . 6. the current specified is also for autohalt state. 7. typical v cc indicates the vid encoded voltage. voltage supplied must conform to the load line specification shown in table 8 to table 9 . 8. the maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of prochot# is the same as the maximum i cc for the processor. 9. maximum specifications for i cc core, i cc stop-grant, i cc sleep, and i cc deep sleep are specified at v cc static max. derived from the tolerances in table 8 through ta b l e 9 , t j max., and under maximum signal loading conditions. 10.the specification is defined per pll pin. 11.the voltage response to a processor current load step (transient) must stay within the transient voltage tolerance window. the voltage surge or droop response measured in this window is typically on the order of several hundred nanoseconds to several microseconds. the transient voltage tolerance window is defined as follows: case a) load current step up: e.g., from icc = i_leakage to icc = icc_max. allowable vcc_min is defined as minimum transient voltage at icc = icc_max for a period of time lasting several hundred nanoseconds to several microseconds after the transient event. case b) load current step down: e.g., form icc = icc_max to icc = i_leakage. allowable vcc_max is defined as the maximum transient voltage at icc = i_leakage for a period of time lasting several hundred nanoseconds to several microseconds after the transient event. 12.this specification applies to both static and transient components. the rising edge of vccvid must be monotonic from 0 to 1.1 v. see figure 1 for current requirements. in this case, monotonic is defined as table 7. voltage and current specifications symbol parameter min typ max unit notes 1 v cc v cc for core logic 1.30 v 2, 3, 4, 5, 7, 8,11 vccvid vid supply voltage -5% 1.20 +10% v 2, 12 i cc current for v cc at core frequency 1.80 ghz & 1.30 v 1.70 ghz & 1.30 v 1.60 ghz & 1.30 v 1.50 ghz & 1.30 v 1.40 ghz & 1.30 v 31.0 29.9 28.7 27.5 26.3 a 4, 5, 8, 9 i vccvid current for vid supply 300 ma i sg nt , i slp i cc stop-grant and i cc sleep at 1.30 v 10.1 a6, 9 i dslp i cc deep sleep at 1.30 v 9.0 a 9 i tcc i cc tcc active i cc a8 i cc pll i cc for pll pins 60 ma 10
251308-002 24 datasheet electrical specifications continuously increasing with less than 50 mv of peak to peak noise for any width greater than 2 ns superimposed on the rising edge. table 8. imvp-iii voltage regulator tolerances for vid = 1.30 v operating mode i cc (a) v cc nominal (v) v cc static min (v) v cc static max (v) v cc transient min (v) v cc transient max (v) 0.0 1.300 1.275 1.325 1.255 1.345 1.0 1.298 1.273 1.323 1.253 1.343 2.0 1.296 1.271 1.321 1.251 1.341 3.0 1.294 1.269 1.319 1.249 1.339 4.0 1.292 1.267 1.317 1.247 1.337 5.0 1.290 1.265 1.315 1.245 1.335 6.0 1.288 1.263 1.313 1.243 1.333 7.0 1.286 1.261 1.311 1.241 1.331 8.0 1.284 1.259 1.309 1.239 1.329 9.0 1.282 1.257 1.307 1.237 1.327 10.0 1.280 1.255 1.305 1.235 1.325 11.0 1.278 1.253 1.303 1.233 1.323 12.0 1.276 1.251 1.301 1.231 1.321 13.0 1.274 1.249 1.299 1.229 1.319 14.0 1.272 1.247 1.297 1.227 1.317 15.0 1.270 1.245 1.295 1.225 1.315 16.0 1.268 1.243 1.293 1.223 1.313 17.0 1.266 1.241 1.291 1.221 1.311 18.0 1.264 1.239 1.289 1.219 1.309 19.0 1.262 1.237 1.287 1.217 1.307 20.0 1.260 1.235 1.285 1.215 1.305 21.0 1.258 1.233 1.283 1.213 1.303 22.0 1.256 1.231 1.281 1.211 1.301 23.0 1.254 1.229 1.279 1.209 1.299 24.0 1.252 1.227 1.277 1.207 1.297 25.0 1.250 1.225 1.275 1.205 1.295 26.0 1.248 1.223 1.273 1.203 1.293 27.0 1.246 1.221 1.271 1.201 1.291 28.0 1.244 1.219 1.269 1.199 1.289 29.0 1.242 1.217 1.267 1.197 1.287 30.0 1.240 1.215 1.265 1.195 1.285 31.0 1.238 1.213 1.263 1.193 1.283 32.0 1.236 1.211 1.261 1.191 1.281 33.0 1.234 1.209 1.259 1.189 1.279 34.0 1.232 1.207 1.257 1.187 1.277
251308-002 25 datasheet electrical specifications figure 4. illustration of v cc static and transient tolerances (vid = 1.30 v) 35.0 1.230 1.205 1.255 1.185 1.275 36.0 1.228 1.203 1.253 1.183 1.273 37.0 1.226 1.201 1.251 1.181 1.271 38.0 1.224 1.199 1.249 1.179 1.269 39.0 1.222 1.197 1.247 1.177 1.267 40.0 1.220 1.195 1.245 1.175 1.265 table 8. imvp-iii voltage regulator tolerances for vid = 1.30 v operating mode i cc (a) v cc nominal (v) v cc static min (v) v cc static max (v) v cc transient min (v) v cc transient max (v) table 9. imvp-iii deep sleep state voltage regulator tolerances (vid = 1.30 v, vid offset = 4.62%) i cc (a) v cc nominal (v) v cc static min (v) v cc static max (v) v cc transient min (v) v cc transient max (v) 0.0 1.240 1.215 1.265 1.195 1.285 1.0 1.238 1.213 1.263 1.193 1.283 2.0 1.236 1.211 1.261 1.191 1.281 3.0 1.234 1.209 1.259 1.189 1.279 4.0 1.232 1.207 1.257 1.187 1.277 5.0 1.230 1.205 1.255 1.185 1.275 6.0 1.228 1.203 1.253 1.183 1.273 7.0 1.226 1.201 1.251 1.181 1.271 1.050 1.100 1.150 1.200 1.250 1.300 1.350 1.400 0 2 4 6 8 10121416182022242628303234363840 icc maximum (a) vcc (v) vcc transient maximu m v c c st a tic ma x imum vcc nominal vcc transient minimu m v c c st at ic min imu m
251308-002 26 datasheet electrical specifications figure 5. illustration of deep sleep v cc static and transient tolerances (vid setting = 1.30 v) 8.0 1.224 1.199 1.249 1.179 1.269 9.0 1.222 1.197 1.247 1.177 1.267 10.0 1.220 1.195 1.245 1.175 1.265 table 9. imvp-iii deep sleep state voltage regulator tolerances (vid = 1.30 v, vid offset = 4.62%) i cc (a) v cc nominal (v) v cc static min (v) v cc static max (v) v cc transient min (v) v cc transient max (v) 1.120 1.140 1.160 1.180 1.200 1.220 1.240 1.260 1.280 1.300 01234567891011 isb maximum (a) vcc (v) vcc transient maximum vcc static maximum vcc static minimum vcc transient minimum vcc nominal
251308-002 27 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. crossing voltage is defined as the instantaneous voltage value when the rising edge of bclk0 equals the falling edge of bclk1. 3. v havg is the statistical average of the v h measured by the oscilloscope. 4. overshoot is defined as the absolute value of the maximum voltage. 5. undershoot is defined as the absolute value of the minimum voltage. 6. ringback margin is defined as the absolute voltage difference between the maximum rising edge ringback and the maximum falling edge ringback. 7. threshold region is defined as a region entered around the crossing point voltage in which the differential receiver switches. it includes input threshold hysteresis. 8. the crossing point must meet the absolute and relative crossing point specifications simultaneously. 9. v havg can be measured directly using "vtop" on agilent* scopes and "high" on tektronix* scopes. 10. ? v cross is defined as the total variation of all crossing voltages as defined in note 2. table 10. system bus differential bclk specifications symbol parameter min typ max unit figure notes 1 v l input low voltage -0.150 0.000 n/a v 9 v h input high voltage 0.660 0.710 0.850 v 9 v cross(abs) absolute crossing point 0.250 n/a 0.550 v 9 , 10 2,3,8 v cross(rel) relative crossing point 0.250 + 0.5(v havg - 0.710) n/a 0.550 + 0.5(v havg - 0.710) v 9 , 10 2,3,8,9 ? v cross range of crossing points n/a n/a 0.140 v 9 , 10 2,10 v ov overshoot n/a n/a v h + 0.3 v 9 4 v us undershoot -0.300 n/a n/a v 9 5 v rbm ringback margin 0.200 n/a n/a v 9 6 v tm threshold margin v cross - 0.100 n/a v cross + 0.100 v 9 7
251308-002 28 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. v il is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. v ih is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. v ih and v oh may experience excursions above v cc . however, input signal drivers must comply with the signal quality specifications in section 3. 5. refer to processor i/o buffer models for i/v characteristics. 6. the v cc referred to in these specifications is the instantaneous v cc . 7. vol max of 0.450 volts is guaranteed when driving into a test load of 50 ? as indicated in figure 7 . 8. leakage to v ss with pin held at v cc . 9. leakage to v cc with pin held at 300 mv. table 11. agtl+ signal group dc specifications symbol parameter min max unit notes 1 gtlref reference voltage 2/3 vcc - 2% 2/3 vcc + 2% v v ih input high voltage 1.10*gtlref v cc v2,6 v il input low voltage 0.0 0.9*gtlref v 3,4,6 v oh output high voltage n/a vcc v 7 i ol output low current n/a 50 ma 6 i hi pin leakage high n/a 100 a 8 i lo pin leakage low n/a 500 a 9 r on buffer on resistance 7 11 ? 5
251308-002 29 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all outputs are open-drain. 3. v ih and v oh may experience excursions above v cc . however, input signal drivers must comply with the signal quality specifications in chapter 3.0. 4. the v cc referred to in these specifications refers to instantaneous v cc . 5. this specification applies to the asynchronous gtl+ signal group. 6. the maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in figure 7 . 7. refer to the processor i/o buffer models for i/v characteristics. 8. vol max of 0.270 volts is guaranteed when driving into a test load of 50 ? as indicated in figure 7 for the asynchronous gtl+ signals. 9. leakage to v ss with pin held at v cc . 10. leakage to v cc with pin held at 300 mv. table 12. asynchronous gtl+ signal group dc specifications symbol parameter min max unit notes 1 v ih input high voltage asynch gtl+ 1.10*gtlref v cc v 3, 4, 5 v il input low voltage asynch. gtl+ 00.9*gtlrefv5 v oh output high voltage n/a v cc v 2, 3, 4 i ol output low current n/a 50 ma 6, 8 i hi pin leakage high n/a 100 a 9 i lo pin leakage low n/a 500 a 10 ron buffer on resistance asynch gtl+ 711 ? 5, 7
251308-002 30 datasheet electrical specifications table 13. pwrgood and tap signal group dc specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all outputs are open-drain. 3. tap signal group must comply with the signal quality specifications in section 3. 4. refer to i/o buffer models for i/v characteristics. 5. the v cc referred to in these specifications refers to instantaneous v cc . 6. the maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown if figure 7 . 7. vol max of 0.320 volts is guaranteed when driving into a test load of 50 ohms as indicated in figure 7 for the tap signals. 8. v hys represents the amount of hysteresis, nominally centered about 1/2 vcc for all tap inputs. 9. leakage to v ss with pin held at v cc . 10.leakage to v cc with pin held at 300 mv. table 14. itpclkout[1:0] dc specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. these parameters are not tested and are based on design simulations. 3. see figure 6 for itpclkout[1:0] output buffer diagram. symbol parameter min max unit notes 1 v hys input hysteresis 200 300 mv 8 v t+ input low to high threshold voltage 1/2*(vcc+v hys_min ) 1/2*(vcc+v hys_max )v 5 v t- input high to low threshold voltage 1/2*(vcc-v hys_max ) 1/2*(vcc-v hys_min )v 5 v oh output high voltage n/a v cc v2,3,5 i ol output low current n/a 40 ma 6,7 i hi pin leakage high n/a 100 a 9 i lo pin leakage low n/a 500 a 10 ron buffer on resistance 8.75 13.75 ? 4 symbol parameter min max unit notes 1 ron buffer on resistance 27 46 ? 2,3
251308-002 31 datasheet electrical specifications figure 6. itpclkout[1:0] output buffer diagram notes: 1. see table 14 for range of ron. 2. the vcc referred to in this figure is the instantaneous vcc. 3. refer to the appropriate platform design guidelines for the value of rext. table 15. bsel [1:0] and vid[4:0] dc specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. these parameters are not tested and are based on design simulations. 3. leakage to vss with pin held at 2.50 v. 2.12 agtl+ system bus specifications routing topology recommendations may be found in the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide. termination resistors are not required for most agtl+ signals, as these are integrated into the processor silicon. valid high and low levels are determined by the input buffers that compare a signal?s voltage with a reference voltage called gtlref (known as v ref in previous documentation). table 16 lists the gtlref specifications. the agtl+ reference voltage (gtlref) should be generated on the system board using high precision voltage divider circuits. it is important that the system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance vcc ron processor package rext to debug port symbol parameter min max unit notes 1 ron (bsel) buffer on resistance 9.2 14.3 ? 2 ron (vid) buffer on resistance 7.8 12.8 ? 2 i hi pin leakage hi n/a 100 a 3
251308-002 32 datasheet electrical specifications for the agtl+ signal group traces is known and well-controlled. for more details on platform design see the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 1. the tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of v cc . 1. gtlref should be generated from v cc by a voltage divider of 1% tolerance resistors or 1% tolerance matched resistors. refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for implementation details. 1. r tt is the on-die termination resistance measured at v ol of the agtl+ output driver. refer to processor i/o buffer models for i/v characteristics. 1. comp resistance must be provided on the system board with 1% tolerance resistors. see the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for implementation details. 1. the v cc referred to in these specifications is the instantaneous v cc . 2.13 system bus ac specifications the processor system bus timings specified in this section are defined at the processor core (pads) . see section 5.2 for the mobile intel celeron processor pin signal definitions. table 17 through table 24 list the ac specifications associated with the processor system bus. all agtl+ timings are referenced to gtlref for both ?0? and ?1? logic levels unless otherwise specified. the timings specified in this section should be used in conjunction with the i/o buffer models provided by intel. these i/o buffer models, which include package information, are available for the mobile intel celeron processor in ibis format. agtl+ layout guidelines are also available in the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide . unless specified otherwise, all mobile intel celeron processor ac specifications are at t j = 100 c. care should be taken to read all notes associated with a particular timing parameter. table 16. agtl+ bus voltage definitions symbol parameter min typ max units notes 1 gtlref bus reference voltage 2/3 v cc -2% 2/3 v cc 2/3 v cc +2% v 2, 3, 6 r tt termination resistance 45 50 55 ? 4 comp[1:0] comp resistance 50.49 51 51.51 ? 5
251308-002 33 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 1. the period specified here is the average period. a given period may vary from this specification as governed by the period stability specification (t2). 1. in this context, period stability is defined as the worst case timing difference between successive crossover voltages. in other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 1. slew rate is measured between the 35% and 65% points of the clock swing (v l to v h ). . notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 1. not 100% tested. specified by design characterization. 1. all common clock ac timings for agtl+ signals are referenced to the crossing voltage (v cross ) of the bclk[1:0] at rising edge of bclk0. all common clock agtl+ signal timings are referenced at gtlref at the processor core. 1. valid delay timings for these signals are specified into the test circuit described in figure 7 and with gtlref at 2/3 v cc 2%. 1. specification is for a minimum swing defined between agtl+ v il_max to v ih_min . this assumes an edge rate of 0.4 v/ns to 4.0 v/ns. 1. reset# can be asserted asynchronously, but must be deasserted synchronously. 1. this should be measured after v cc and bclk[1:0] become stable. 1. maximum specification applies only while pwrgood is asserted. . table 17. system bus differential clock specifications t# parameter min nom max unit figure notes 1 system bus frequency 100 mhz t1: bclk[1:0] period 10.0 10.2 ns 9 2 t2: bclk[1:0] period stability 200 ps 3 t3: bclk[1:0] high time 3.94 5 6.12 ns 9 t4: bclk[1:0] low time 3.94 5 6.12 ns 9 t5: bclk[1:0] rise time 175 700 ps 9 4 t6: bclk[1:0] fall time 175 700 ps 9 4 table 18. system bus common clock ac specifications t# parameter min max unit figure notes 1,2,3 t10: common clock output valid delay 0.12 1.55 ns 11 4 t11: common clock input setup time 0.65 ns 11 5 t12: common clock input hold time 0.40 ns 11 5 t13: reset# pulse width 1 10 ms 12 6, 7, 8
251308-002 34 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. not 100% tested. specified by design characterization. 3. all source synchronous ac timings are referenced to their associated strobe at gtlref. source synchronous data signals are referenced to the falling edge of their associated data strobe. source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. all source synchronous agtl+ signal timings are referenced to gtlref at the processor core. 4. unless otherwise noted these specifications apply to both data and address timings. 5. valid delay timings for these signals are specified into the test circuit described in figure 7 and with gtlref at 2/3 v cc 2%. 6. specification is for a minimum swing defined between agtl+ v il_max to v ih_min . this assumes an edge rate of 0.3 v/ns to 4.0v /ns. 7. all source synchronous signals must meet the specified setup time to bclk as well as the setup time to each respective strobe. 8. this specification represents the minimum time the data or address will be valid before its strobe. refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for more information on the definitions and use of these specifications. 9. this specification represents the minimum time the data or address will be valid after its strobe. refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for more information on the definitions and use of these specifications. 10.the rising edge of adstb# must come approximately 1/2 bclk period (5 ns) after the falling edge of adstb#. 11.for this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively. 12.the second data strobe (falling edge of dstbn#) must come approximately 1/4 bclk period (2.5 ns) after the first falling edge of dstbp#. the third data strobe (falling edge of dstbp#) must come approximately 2/4 bclk period (5 ns) after the first falling edge of dstbp#. the last data strobe (falling edge of dstbn#) must come approximately 3/4 bclk period (7.5 ns) after the first falling edge of dstbp#. 13.this specification applies only to dstbn[3:0]# and is measured to the second falling edge of the strobe. table 19. system bus source synch ac specifications agtl+ signal group t# parameter min typ max unit figure notes 1,2,3,4 t20: source synchronous data output valid delay (first data/address only) 0.20 1.20 ns 13 , 14 5 t21: t vbd : source synchronous data output valid before strobe 0.85 ns 14 5, 8 t22: t vad : source synchronous data output valid after strobe 0.85 ns 14 5, 9 t23: t vba : source synchronous address output valid before strobe 1.88 ns 13 5, 8 t24: t vaa : source synchronous address output valid after strobe 1.88 ns 13 5, 9 t25: t suss : source synchronous input setup time to strobe 0.21 ns 13 , 14 6 t26: t hss : source synchronous input hold time to strobe 0.21 ns 13 , 14 6 t27: t succ : source synchronous input setup time to bclk[1:0] 0.65 ns 13 , 14 7 t28: t fass : first address strobe to second address strobe 1/2 bclk 13 10 t29: t fdss : first data strobe to subsequent strobes n/4 bclk 14 11, 12 t30: data strobe ?n? (dstbn#) output valid delay 8.80 10.20 ns 14 13 t31: address strobe output valid delay 2.27 4.23 ns 13
251308-002 35 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all ac timings for the asynch gtl+ signals are referenced to the bclk0 rising edge at crossing voltage. all asynch gtl+ signal timings are referenced at gtlref. pwrgood is referenced to the bclk0 rising edge at 0.5*v cc 3. these signals may be driven asynchronously. 4. refer to the pwrgood definition for more details regarding the behavior of this signal. 5. length of assertion for prochot# does not equal internal clock modulation time. time is allocated after the assertion and before the deassertion of prochot# for the processor to complete current instruction execution. 6. see section 7.2 for additional timing requirements for entering and leaving the low power states. notes: 1. before the deassertion of reset#. 2. after clock that deasserts reset#. table 20. miscellaneous signals ac specifications t# parameter min max unit figure notes 1,2,3,6 t35: asynch gtl+ input pulse width 2 bclks t36: pwrgood to reset# de-assertion time 110ms 15 t37: pwrgood inactive pulse width 10 bclks 15 4 t38: prochot# pulse width 500 us 17 5 t39: thermtrip# to vcc removal 0.5 s 18 t40: ferr# valid delay from stpclk# deassertion 05bclks 19 table 21. system bus ac specifications (reset conditions) t# parameter min max unit figure notes t45: reset configuration signals (a[31:3]#, br0#, init#, smi#) setup time 4bclks 12 1 t46: reset configuration signals (a[31:3]#, br0#, init#, smi#) hold time 220bclks 12 2
251308-002 36 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. not 100% tested. specified by design characterization. 3. all ac timings for the tap signals are referenced to the tck signal at 0.5*v cc at the processor pins. all tap signal timings (tms, tdi, etc) are referenced at 0.5*v cc at the processor pins. 4. rise and fall times are measured from the 20% to 80% points of the signal swing. 5. referenced to the rising edge of tck. 6. referenced to the falling edge of tck. 7. specifications for a minimum swing defined between tap v t- to v t+ . this assumes a minimum edge rate of 0.5 v/ns 8. trst# must be held asserted for 2 tck periods to be guaranteed that it is recognized by the processor. 9. it is recommended that tms be asserted while trst# is being deasserted. table 23. itpclkout[1:0] ac specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. these parameters are not tested and are based on design simulations. 3. this delay is from rising edge of bclk0 to the falling edge of itpclk0. table 22. tap signals ac specifications parameter min max unit figure notes 1,2,3 t55: tck period 60.0 ns 8 t56: tck rise time 10.0 ns 8 4 t57: tck fall time 10.0 ns 8 4 t58: tms rise time 8.5 ns 8 4 t59: tms fall time 8.5 ns 8 4, 9 t61: tdi setup time 0 ns 20 5, 7 t62: tdi hold time 3 ns 20 5, 7 t63: tdo clock to output delay 3.5 ns 20 6 t64: trst# assert time 2 tck 17 8, 9 parameter min typ max unit figure notes 1,2 t65: itpclkout delay 400 560 ps 21 3 t66: slew rate 2 8 v/ns t67: itpclkout[1:0] high time 3.89 5 6.17 ns t68: itpclkout[1:0] low time 3.89 5 6.17 ns
251308-002 37 datasheet electrical specifications . notes: 1. input signals other than reset# must be held constant in the sleep state. 1. the bclk can be stopped after dpslp# is asserted. the bclk must be turned on and within specification before dpslp# is deasserted. 2.14 processor ac timing waveforms the following figures are used in conjunction with the ac timing tables, table 17 through table 24 . note: for figure 8 through figure 22 , the following apply: 5.all common clock ac timings for agtl+ signals are referenced to the crossing voltage (v cross ) of the bclk[1:0] at rising edge of bclk0. all common clock agtl+ signal timings are referenced at gtlref at the processor core. 6.all source synchronous ac timings for agtl+ signals are referenced to their associated strobe (address or data) at gtlref. source synchronous data signals are referenced to the falling edge of their associated data strobe. source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. all source synchronous agtl+ signal timings are referenced at gtlref at the processor core silicon. 7.all ac timings for agtl+ strobe signals are referenced to bclk[1:0] at v cross . all agtl+ strobe signal timings are referenced at gtlref at the processor core silicon. 8.all ac timings for the tap signals are referenced to the tck signal at 0.5*v cc at the processor pins. all tap signal timings (tms, tdi, etc) are referenced at 0.5*v cc at the processor pins. the circuit used to test the ac specifications is shown in . table 24. stop grant/sleep/deep sleep ac specifications t# parameter min max unit figure notes t70: slp# signal hold time from stop grant cycle completion 100 bclks 22 t71: input signals stable to slp# assertion 10 bclks 22 1 t72: slp# to dpslp# assertion 10 bclks 22 t73: deep sleep pll lock latency 0 30 s 22 2 t74: slp# hold time from pll lock 0 ns 22 t75: stpclk# hold time from slp# deassertion 10 bclks 22 t76: input signal hold time from slp# deassertion 10 bclks 22
251308-002 38 datasheet electrical specifications figure 7. ac test circuit figure 8. tck clock waveform 420 mils, 50 ohms, 169 ps / in 2.4nh 1.2pf v cc v cc rload= 50 ohms ac timings test measurements made here. tr = t56, t58 (rise time) tf = t57, t59 (fall time) tp = t55 (tck period) v2 v3 v1 v1,v2: for rise and fall times, tck is measured between 20% to 80% points on the waveform v3: tck is referenced to 0.5*vcc
251308-002 39 datasheet electrical specifications . figure 9. differential clock waveform crossing voltage threshold region vh vl overshoot undershoot ringback margin rising edge ringback falling edge ringback, bclk0 bclk1 crossing voltage tph tpl tp tp = t1 (bclk[1:0] period) t2 = bclk[1:0] period stability (not shown) tph =t3 (bclk[1:0] pulse high time) tpl = t4 (bclk[1:0] pulse low time) t5 = bclk[1:0] rise time through the threshold region t6 = bclk[1:0] fall time through the threshold region
251308-002 40 datasheet electrical specifications figure 10. differential clock crosspoint specification figure 11. system bus common clock valid delay timings crosspoint specification 200 250 300 350 400 450 500 550 600 650 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 vhavg (v) crossing point (v) 250 + 0.5 (vhavg - 710) 550 + 0.5 (vhavg - 710) 550 mv 250 mv vhavg (mv) crossing point (mv) crosspoint specification 200 250 300 350 400 450 500 550 600 650 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 vhavg (v) crossing point (v) 250 + 0.5 (vhavg - 710) 550 + 0.5 (vhavg - 710) 550 mv 250 mv crosspoint specification 200 250 300 350 400 450 500 550 600 650 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 vhavg (v) crossing point (v) 250 + 0.5 (vhavg - 710) 550 + 0.5 (vhavg - 710) 550 mv 250 mv vhavg (mv) crossing point (mv) bclk0 bclk1 common clock signal (@ driver) common clock signal (@ receiver) t0 t1 t2 t q t r valid valid valid t p t p = t10: t co (data valid output delay) t q = t11: t su (common clock setup) t r = t12: t h (common clock hold time)
251308-002 41 datasheet electrical specifications figure 12. system bus reset and configuration timings figure 13. source synchronous 2x (address) timings bclk reset configuration a[31:3], smi#, init#, br[3:0]# valid tv = t13 (reset# pulse width) tw = t45 (reset configuration signals setup time) tx = t46 (reset configuration signals hold time) tx tv tt tw t j bclk0 bclk1 adstb# (@ driver) a# (@ driver) a# (@ receiver) adstb# (@ receiver) t1 t2 2.5 ns 5.0 ns 7.5 ns t h t h t j t n t k t m valid valid valid valid t h = t23: source sync. address output valid before address strobe t j = t24: source sync. address output valid after address strobe t k = t27: source sync. input setup to bclk t m = t26: source sync. input hold time t n = t25: source sync. input setup time t p = t28: first address strobe to second address strobe t s = t20: source sync. output valid delay t r = t31: address strobe output valid delay t p t r t s
251308-002 42 datasheet electrical specifications figure 14. source synchronous 4x timings bclk0 bclk1 dstbp# (@ driver) dstbn# (@ driver) d# (@ driver) d# (@ receiver) dstbn# (@ receiver) dstbp# (@ receiver) t0 t1 t2 2.5 ns 5.0 ns 7.5 ns t a t a t b t c t e t e t g t g t d t a = t21: source sync. data output valid delay before data strobe t b = t22: source sync. data output valid delay after data strobe t c = t27: source sync. setup time to bclk t d = t30: source sync. data strobe 'n' (dstbn#) output valid delay t e = t25: source sync. input setup time t g = t26: source sync. input hold time t h = t29: first data strobe to subsequent strobes t j = t20: source sync. data output valid delay t j t h
251308-002 43 datasheet electrical specifications figure 15. power up sequence figure 16. power down sequence bclk vcc pwrgood reset# vccvid vid_good vid[4:0], bsel[1:0] tc td ta= 1us minimum (vccvid > 1v to vid_good high) tb= 50ms maximum (vid_good to vcc valid maximum time) tc= t37 (pwrgood inactive pulse width) td= t36 (pwrgood to reset# de-assertion time) note: vid_good is not a processor signal. this signal is routed to the output enable pin of the voltage regluator control s ilicon. for more information on implementation refer to the intel mobile northwood processor and intel 845mp platform rddp. ta tb note: vid_good is not a processor signal. this signal is routed to the output enable pin of the voltage regluator control silicon. for more information on implementation refer to the intel mobile northwood processor and intel 845mp platform rddp. 1. this timing diagram is not intended to show specific times. instead a general ordering of events with respect to time should be observed. 2. when vccvid is less than 1v, vid_good must be low. 3. vcc must be disabled before vid[4:0] becomes invalid. 4. vccvid and vcc regulator can be disabled simultaneously vcc pwrgood vccvid vid_good vid[4:0]
251308-002 44 datasheet electrical specifications figure 17. test reset timings figure 18. thermtrip# to vcc timing figure 19. ferr#/pbe# valid delay timing trst# pcb - 773 1.25v t q t q t37 (trst# pulse width) = tq = t64 (trst# pulse width), v=0.5*vcc t38 (prochot# pulse width), v=gtlref thermtrip# vcc t39 t39 < 0.5 seconds note: thermtrip# is undefined when reset# is active thermtrip# vcc t39 t39 < 0.5 seconds note: thermtrip# is undefined when reset# is active bclk stpclk# system bus ferr#/ pbe# sg ack ferr# undefined ferr# ta pbe# undefined ta = t40 (ferr# valid delay from stpclk# deassertion) note: ferr#/pbe# is undefined from stpclk# assertion until the stop grant acknowledge is driven on the processor system bus. ferr#/pbe# is also undefined for a period of ta from stpclk# deassertion. inside these undefined regions the pbe# signal is driven. ferr# is driven at all other times.
251308-002 45 datasheet electrical specifications figure 20. tap valid delay timing figure 21. itpclkout valid delay timing v valid signal tck th ts tx tx = t63 (valid time) ts = t61 (setup time) th = t62 (hold time) v = 0.5 * vcc v bclk itpclkout t65 = tx = bclk input to itpclkout output delay tx
251308-002 46 datasheet electrical specifications figure 22. stop grant/sleep/deep sleep timing tt = t70 (stop grant acknowledge bus cycle completion to slp# assertion delay) tu = t71 (input signals stable to slp# assertion requirement) tv = t72 (slp# to dpslp# assertion) tw = t73 (deep sleep pll lock latency) tx = t74 (slp# hold time) ty = t75 (stpclk# hold time) tz = t76 (input signal hold time) t u stpgnt bclk[1:0] stpclk# cpu bus slp# compatibility signals frozen changing normal stop grant sleep deep sleep sleep stop grant normal t t t v t y t z t w t x v0011-02 changing dpslp#
251308-002 47 datasheet system bus signal quality specifications 3 system bus signal quality specifications source synchronous data transfer requires the clean reception of data signals and their associated strobes. ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines. excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded. additionally, overshoot and undershoot can cause timing degradation due to the build up of inter-symbol interference (isi) effects. for these reasons, it is important that the designer work to achieve a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing. this section documents signal quality metrics used to derive topology and routing guidelines through simulation and for interpreting results for signal quality measurements of actual designs. the mobile intel celeron processor ibis models should be used while performing signal integrity simulations. 3.1 system bus clock (bclk) signal quality specifications and measurement guidelines table 25 describes the signal quality specifications at the processor pads for the processor system bus clock (bclk) signals. figure 23 describes the signal quality waveform for the system bus clock at the processor pads. notes: 1. unless otherwise noted, all specifications in this table apply to all mobile intel celeron processor frequencies. 1. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. this specification is an absolute value. table 25. bclk signal quality specifications parameter min max unit figure notes 1 bclk[1:0] overshoot n/a 0.30 v 23 bclk[1:0] undershoot n/a 0.30 v 23 bclk[1:0] ringback margin 0.20 n/a v 23 2 bclk[1:0] threshold region n/a 0.10 v 23
251308-002 48 datasheet system bus signal quality specifications 3.2 system bus signal quality specifications and measurement guidelines various scenarios have been simulated to generate a set of agtl+ layout guidelines which are available in the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide . table 26 and table 27 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor core silicon (pads). mobile intel celeron processor maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in table 28 through table 31 . figure 24 shows the system bus ringback tolerance for low-to-high transitions and figure 25 shows ringback tolerance for high-to- low transitions. notes: 1. all signal integrity specifications are measured at the processor silicon (pads). 1. unless otherwise noted, all specifications in this table apply to all mobile intel celeron processor frequencies. 1. specifications are for the edge rate of 0.3 - 4.0 v/ns. 1. all values specified by design characterization. 1. please see section 3.3 for maximum allowable overshoot. 1. ringback between gtlref + 10% and gtlref - 10% is not supported. 1. intel recommends simulations not exceed a ringback value of gtlref 200 mv to allow margin for other sources of system noise. figure 23. bclk signal integrity waveform crossing voltage threshold region vh vl overshoot undershoot ringback margin rising edge ringback falling edge ringback, bclk0 bclk1 crossing voltage table 26. ringback specifications for agtl+ and asynchronous gtl+ signal groups signal group transition maximum ringback (with input diodes present) unit figure notes all signals 0 1 gtlref + 10% v 24 1,2,3,4,5,6,7 all signals 1 0 gtlref - 10% v 25 1,2,3,4,5,6,7
251308-002 49 datasheet system bus signal quality specifications table 27. ringback specifications for pwrgood input and tap signal groups notes: 1. all signal integrity specifications are measured at the processor silicon. 2. unless otherwise noted, all specifications in this table apply to all mobile intel celeron processor frequencies. 3. please see section 3.3 for maximum allowable overshoot. 4. please see section 2.11 for the dc specifications. signal group transition maximum ringback (with input diodes present) unit figure notes tap and pwrgood 0 1v t+(max) to v t-(max) v 26 1,2,3,4 tap and pwrgood 1 0v t-(min) to v t+(min) v 27 1,2,3,4 figure 24. low-to-high system bus receiver ringback tolerance gtlref v cc noise margin +10% gtlref -10% gtlref v ss figure 25. high-to-low system bus receiver ringback tolerance v cc n oise margin v ss gtlref +10% gtlref -10% gtlref
251308-002 50 datasheet system bus signal quality specifications figure 26. low-to-high system bus receiver ringback tolerance for pwrgood and tap buffers figure 27. high-to-low system bus receiver ringback tolerance for pwrgood and tap buffers 0.5 * vcc vt+ (min) vt+ (max) vt- (max) vcc allowable ringback vss threshold region to switch receiver to a logic 1. 0.5 * vcc vt+ (min) vt- (max) vcc vss vt- (min) threshold region to switch receiver to a logic 0. allowable ringback
251308-002 51 datasheet system bus signal quality specifications 3.3 system bus signal quality specifications and measurement guidelines 3.3.1 overshoot/undershoot guidelines overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below v ss ) as shown in figure 28 . the overshoot guideline limits transitions beyond v cc or v ss due to the fast signal edge rates. the processor can be damaged by repeated overshoot or undershoot events on any input, output, or i/o buffer if the charge is large enough (i.e., if the over/undershoot is great enough). determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (af). permanent damage to the processor is the likely result of excessive overshoot/undershoot. when performing simulations to determine impact of overshoot and undershoot, esd diodes must be properly characterized. esd protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. esd diodes modelled within intel i/o buffer models do not clamp undershoot or overshoot and will yield correct simulation results. if other i/o buffer models are being used to characterize the mobile intel celeron processor system bus, care must be taken to ensure that esd models do not clamp extreme voltage levels. intel i/o buffer models also contain i/o capacitance characterization. therefore, removing the esd diodes from an i/o buffer model will impact results and may yield excessive overshoot/undershoot. 3.3.2 overshoot/undershoot magnitude magnitude describes the maximum potential difference between a signal and its voltage reference level. for the mobile intel celeron processor both are referenced to v ss . it is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently. overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in table 28 through table 31 . these specifications must not be violated at any time regardless of bus activity or system state. within these specifications are threshold levels that define different allowed pulse durations. provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications, the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications. 3.3.3 overshoot/undershoot pulse duration pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage (maximum overshoot = 1.700 v, maximum undershoot = -0.400 v). the total time could encompass several oscillations above the reference voltage. multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.
251308-002 52 datasheet system bus signal quality specifications note: oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration. 3.3.4 activity factor activity factor (af) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. since the highest frequency of assertion of any signal is every other clock, an af = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. thus, an af = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. for source synchronous signals (address, data, and associated strobes), the activity factor is in reference to the strobe edge, since the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. an af = 1 indicates that the specific overshoot (undershoot) waveform occurs every strobe cycle. the specifications provided in table 28 through table 31 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/ undershoot events of that magnitude only. a platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the af < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if af = 1, then the event occurs at all times and no other events can occur). note: 1: activity factor for agtl+ signals is referenced to bclk[1:0] frequency. note: 2: activity factor for source synchronous (2x) signals is referenced to adstb[1:0]#. note: 3: activity factor for source synchronous (4x) signals is referenced to dstbp[3:0]# and dstbn[3:0]#. 3.3.5 reading overshoot/undershoot specification tables the overshoot/undershoot specification for the mobile intel celeron processor is not a simple single value. instead, many factors are needed to determine what the over/undershoot specification is. in addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot (as measured above v cc ) and the activity factor (af). to determine the allowed overshoot for a particular overshoot event, the following must be done: 1. determine the signal group a particular signal falls into. if the signal is an agtl+ signal operating in the common clock domain, use table 30 . for agtl+ signals operating in the 2x source synchronous domain, use table 29 . for agtl+ signals operating in the 4x source synchronous domain, use table 28 . finally, all other signals reside in the 100mhz domain (asynchronous gtl+, tap, etc.) and are referenced in table 31 . 2. determine the magnitude of the overshoot (relative to v ss ) 3. determine the activity factor (how often does this overshoot occur?) 4. next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed.
251308-002 53 datasheet system bus signal quality specifications 5. compare the specified maximum pulse duration to the signal being measured. if the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. the above procedure is similar for undershoot after the undershoot waveform has been converted to look like an overshoot. undershoot events must be analyzed separately from overshoot events as they are mutually exclusive. 3.3.6 conformance determination to overshoot/undershoot specifications the overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. however, most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, af and magnitude). while each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail. a guideline to ensure a system passes the overshoot and undershoot specifications is shown below. 1. ensure no signal ever exceeds v cc or -0.25 v or 2. if only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables or 3. if multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the af = 1 specifications. if all of these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where af=1), then the system passes. the following notes apply to table 28 through table 31 . notes: 1. absolute maximum overshoot magnitude of 1.70 v must never be exceeded. 2. absolute maximum overshoot is measured relative to v ss , pulse duration of overshoot is measured relative to v cc . 3. absolute maximum undershoot and pulse duration of undershoot is measured relative to v ss . 4. ringback below v cc can not be subtracted from overshoots/undershoots. 5. lesser undershoot does not allocate longer or larger overshoot. 6. oem's are strongly encouraged to follow intel provided layout guidelines. 7. all values specified by design characterization. table 28. source synchronous (400 mhz) agtl+ signal group overshoot/undershoot tolerance absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2 1.700 -0.400 0.11 1.05 5.00 1.650 -0.350 0.24 2.40 5.00 1.600 -0.300 0.53 5.00 5.00 1.550 -0.250 1.19 5.00 5.00 1.500 -0.200 5.00 5.00 5.00
251308-002 54 datasheet system bus signal quality specifications notes: 1. these specifications are measured at the processor core silicon. 2. bclk period is 10 ns. notes: 1. these specifications are measured at the processor core silicon. 2. bclk period is 10 ns. 1.450 -0.150 5.00 5.00 5.00 1.400 -0.100 5.00 5.00 5.00 1.350 -0.050 5.00 5.00 5.00 table 28. source synchronous (400 mhz) agtl+ signal group overshoot/undershoot tolerance absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2 table 29. source synchronous (200 mhz) agtl+ signal group overshoot/undershoot tolerance absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2 1.700 -0.400 0.21 2.10 10.00 1.650 -0.350 0.48 4.80 10.00 1.600 -0.300 1.05 10.00 10.00 1.550 -0.250 2.38 10.00 10.00 1.500 -0.200 10.00 10.00 10.00 1.450 -0.150 10.00 10.00 10.00 1.400 -0.100 10.00 10.00 10.00 1.350 -0.050 10.00 10.00 10.00 table 30. common clock (100 mhz) agtl+ signal group overshoot/undershoot tolerance absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2 1.700 -0.400 0.42 4.20 20.00 1.650 -0.350 0.96 9.60 20.00 1.600 -0.300 2.10 20.00 20.00 1.550 -0.250 4.76 20.00 20.00 1.500 -0.200 20.00 20.00 20.00 1.450 -0.150 20.00 20.00 20.00 1.400 -0.100 20.00 20.00 20.00 1.350 -0.050 20.00 20.00 20.00
251308-002 55 datasheet system bus signal quality specifications notes: 1. these specifications are measured at the processor core silicon. 2. bclk period is 10 ns.
251308-002 56 datasheet system bus signal quality specifications notes: 1. these specifications are measured at the processor core silicon. 2. bclk period is 10 ns. figure 28. maximum acceptable overshoot/undershoot waveform table 31. asynchronous gtl+, pwrgood input, and tap signal groups overshoot/ undershoot tolerance absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2 1.700 -0.400 1.26 12.6 60.00 1.650 -0.350 2.88 28.8 60.00 1.600 -0.300 6.30 60.00 60.00 1.550 -0.250 14.28 60.00 60.00 1.500 -0.200 60.00 60.00 60.00 1.450 -0.150 60.00 60.00 60.00 1.400 -0.100 60.00 60.00 60.00 1.350 -0.050 60.00 60.00 60.00 000588 v cc maximum absolute overshoot maximum absolute undershoot time-de p endent overshoot time-de p endent undershoot gtlref v ol v min v max v ss
251308-002 57 datasheet package mechanical specifications 4 package mechanical specifications the mobile intel celeron processor is packaged in a 478 pin micro-fcpga package. different views of the package are shown in figure 29 through figure 31 . package dimensions are shown in table 32 . figure 29. micro-fcpga package top and bottom isometric views top view bottom view label package keepout die capacitor area
58 251308-002 datasheet package mechanical specifications note: all dimensions in millimeters. values shown are for reference only. figure 30. micro-fcpga package - top and side views 35 (e) 35 (d) pin a1 corner e1 d1 a 1.25 max (a3) ?0.32 (b) 478 places 2.03 0.08 (a1) a2 substrate keepout zone do not contact package inside this line 7 (k1) 8 places 5 (k) 4 places 0.286 0.286
251308-002 59 datasheet package mechanical specifications table 32. micro-fcpga package dimensions notes: 1. all dimensions are preliminary and subject to change. values shown are for reference only. 1. overall height with socket is based on design dimensions of the micro-fcpga package and socket with no thermal solution attached. values were based on design specifications and tolerances. this dimension is subject to change based on socket design, oem motherboard design, or oem smt process. symbol parameter min max unit a overall height, top of die to package seating plane 1.81 2.03 mm - overall height, top of die to pcb surface, including socket(1) 4.69 5.15 mm a1 pin length 1.95 2.11 mm a2 die height 0.854 mm a3 pin-side capacitor height - 1.25 mm b pin diameter 0.28 0.36 mm d package substrate length 34.9 35.1 mm e package substrate width 34.9 35.1 mm d1 die length 11.62 (b0 step) mm e1 die width 11.34 (b0 step) mm e pin pitch 1.27 mm k package edge keep-out 5 mm k1 package corner keep-out 7 mm k3 pin-side capacitor boundary 14 mm - pin tip radial true position <=0.254 mm n pin count 478 each pdie allowable pressure on the die for thermal solution - 689 kpa w package weight 4.5 g package surface flatness 0.286 mm
60 251308-002 datasheet package mechanical specifications figure 31. micro-fcpga package - bottom view note: all dimensions in millimeters. values shown are for reference only. 4.1 processor pin-out figure 32 shows the top view pinout of the mobile intel celeron processor. 1 2 3 4 6 8 1012141618 20 22 24 26 57911 13 15 17 19 21 23 25 a b c e d f g h j k l m n p r t u v w y aa ab ac ad ae af 25x 1.27 (e) 25x 1.27 (e) 14 (k3) 14 (k3)
251308-002 61 datasheet package mechanical specifications figure 32. the coordinates of the processor pins as viewed from the top of the package. vss vssse nse vccse nse testhi 11 nc vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss nc d#[2] vss d#[3] vss ignne# thrmd a vss smi# ferr#/ pbe# vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss d#[0] d#[1] vss d#[6] d#[9] vss tdi vss prochot# thrmdc vss a20m# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc d#[4] vss d#[7] d#[8] vss d#[12] lint0 bpri# vss tck tdo vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vss d#[5] d#[13] vss d#[15] d#[23] vss defer# vss lint1 trst# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc dbi#[0] dstbn# [0] vss d#[17] d#[21] vss rs#[0] vss hit# rs#[2] vss gtlref tms vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc gtlref dstbp# [0] vss d#[19] d#[20] vss d#[22] ads# bnr# vss lock# rs#[1] vss vss d#[10] d#[18] vss dbi#[1] d#[25] vss drdy# req#[4] vss dbsy# br0# d#[11] d#[16] vss d#[26] d#[31] vss req#[0] vss req#[3] req#[2] vss trdy# d#[14] vss dstbp# [1] d#[29] vss dp#[0] a#[6] a#[3] vss a#[4] req#[1] vss vss dstbn# [1] d#[30] vss dp#[1] dp#[2] vss a#[9] a#[7] vss adstb#[0] a#[5] d#[24] d#[28] vss comp[0] dp#[3] vss vss a#[10] a#[11] vss a#[8] d#[27] vss d#[32] d#[35] vss d#[37] a#[12] a#[14] vss a#[15] a#[16] vss vss d#[33] d#[36] vss d#[39] d#[38] comp[1] vss a#[19] a#[20] vss a#[24] d#[34] vss dstbp# [2] d#[41] vss dbi#[2] vss a#[18] a#[21] vss adstb#[1] a#[28] d#[40] dstbn# [2] vss d#[43] d#[42] vss a#[17] a#[22] vss a#[26] a#[30] vss vss d#[46] d#[47] vss d#[45] d#[44] a#[23] vss a#[25] a#[31] vss testhi 8 d#[52] vss d#[50] d#[49] vss d#[48] vss a#[27] a#[32] vss ap#[1] mcerr# dbi#[3] d#[53] vss d#[54] d#[51] vss a#[29] a#[33] vss testhi 9 init# vss vss dstbn#[3] dstbp# [3] vss d#[57] d#[55] a#[34] vss testhi 10 vss bpm#[3] d#[60] vss d#[58] d#[59] vss d#[56] vss testhi1 binit# vss bpm#[4] gtlref vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss itpclkout [0] gtlref d#[62] vss d#[63] d#[61] vss a#[35] rsp# vss bpm#[5] bpm#[1] vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vss itpclkou t[1] pwrgood vss reset# slp# ap#[0] vss ierr# bpm#[2] vss bpm#[0] vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss testhi3 testhi2 vss testhi5 testhi4 vss itp_clk0 vss nc nc vss bsel1 bsel0 vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vcca vss vssa vss testhi 0 dpslp# itp_cl k1 vid4 vid3 vid2 vid1 vid0 vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc nc vss vccio_ pll vss dbr# vss vss vcc nc vccvid vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc bclk[0] bclk[1] nc nc sktoc c# a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1234567891011121314151617181920212223242526 hitm# a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1234567891011121314151617181920212223242526 vss vcc other a#[13] stpclk# thermtrip# top view
62 251308-002 datasheet package mechanical specifications this page intentionally left blank.
pin listing and signal definitions 251308-002 63 datasheet 5 pin listing and signal definitions 5.1 mobile intel celeron processor pin assignments section 5.1 contains the preliminary pin list for the mobile intel celeron processor in table 33 and table 34 . table 33 is a listing of all processor pins ordered alphabetically by pin name. table 34 is also a listing of all processor pins but ordered by pin number.
pin listing and signal definitions 64 251308-002 datasheet table 33. pin listing by pin name pin name pin number signal buffer type direction a#[03] k2 source synch input/output a#[04] k4 source synch input/output a#[05] l6 source synch input/output a#[06] k1 source synch input/output a#[07] l3 source synch input/output a#[08] m6 source synch input/output a#[09] l2 source synch input/output a#[10] m3 source synch input/output a#[11] m4 source synch input/output a#[12] n1 source synch input/output a#[13] m1 source synch input/output a#[14] n2 source synch input/output a#[15] n4 source synch input/output a#[16] n5 source synch input/output a#[17] t1 source synch input/output a#[18] r2 source synch input/output a#[19] p3 source synch input/output a#[20] p4 source synch input/output a#[21] r3 source synch input/output a#[22] t2 source synch input/output a#[23] u1 source synch input/output a#[24] p6 source synch input/output a#[25] u3 source synch input/output a#[26] t4 source synch input/output a#[27] v2 source synch input/output a#[28] r6 source synch input/output a#[29] w1 source synch input/output a#[30] t5 source synch input/output a#[31] u4 source synch input/output a#[32] v3 source synch input/output a#[33] w2 source synch input/output a#[34] y1 source synch input/output a#[35] ab1 source synch input/output a20m# c6 asynch gtl+ input ads# g1 common clock input/output adstb#[0] l5 source synch input/output adstb#[1] r5 source synch input/output ap#[0] ac1 common clock input/output ap#[1] v5 common clock input/output bclk[0] af22 bus clock input bclk[1] af23 bus clock input binit# aa3 common clock input/output bnr# g2 common clock input/output bpm#[0] ac6 common clock input/output bpm#[1] ab5 common clock input/output bpm#[2] ac4 common clock input/output bpm#[3] y6 common clock input/output bpm#[4] aa5 common clock input/output bpm#[5] ab4 common clock input/output bpri# d2 common clock input br0# h6 common clock input/output bsel0 ad6 power/other output bsel1 ad5 power/other output comp[0] l24 power/other input/output comp[1] p1 power/other input/output d#[0] b21 source synch input/output d#[01] b22 source synch input/output d#[02] a23 source synch input/output d#[03] a25 source synch input/output d#[04] c21 source synch input/output d#[05] d22 source synch input/output d#[06] b24 source synch input/output d#[07] c23 source synch input/output d#[08] c24 source synch input/output d#[09] b25 source synch input/output d#[10] g22 source synch input/output d#[11] h21 source synch input/output d#[12] c26 source synch input/output d#[13] d23 source synch input/output d#[14] j21 source synch input/output d#[15] d25 source synch input/output d#[16] h22 source synch input/output d#[17] e24 source synch input/output d#[18] g23 source synch input/output d#[19] f23 source synch input/output d#[20] f24 source synch input/output table 33. pin listing by pin name pin name pin number signal buffer type direction
pin listing and signal definitions 251308-002 65 datasheet d#[21] e25 source synch input/output d#[22] f26 source synch input/output d#[23] d26 source synch input/output d#[24] l21 source synch input/output d#[25] g26 source synch input/output d#[26] h24 source synch input/output d#[27] m21 source synch input/output d#[28] l22 source synch input/output d#[29] j24 source synch input/output d#[30] k23 source synch input/output d#[31] h25 source synch input/output d#[32] m23 source synch input/output d#[33] n22 source synch input/output d#[34] p21 source synch input/output d#[35] m24 source synch input/output d#[36] n23 source synch input/output d#[37] m26 source synch input/output d#[38] n26 source synch input/output d#[39] n25 source synch input/output d#[40] r21 source synch input/output d#[41] p24 source synch input/output d#[42] r25 source synch input/output d#[43] r24 source synch input/output d#[44] t26 source synch input/output d#[45] t25 source synch input/output d#[46] t22 source synch input/output d#[47] t23 source synch input/output d#[48] u26 source synch input/output d#[49] u24 source synch input/output d#[50] u23 source synch input/output d#[51] v25 source synch input/output d#[52] u21 source synch input/output d#[53] v22 source synch input/output d#[54] v24 source synch input/output d#[55] w26 source synch input/output d#[56] y26 source synch input/output d#[57] w25 source synch input/output d#[58] y23 source synch input/output d#[59] y24 source synch input/output table 33. pin listing by pin name pin name pin number signal buffer type direction d#[60] y21 source synch input/output d#[61] aa25 source synch input/output d#[62] aa22 source synch input/output d#[63] aa24 source synch input/output dbi#[0] e21 source synch input/output dbi#[1] g25 source synch input/output dbi#[2] p26 source synch input/output dbi#[3] v21 source synch input/output dbr# ae25 power/other output dbsy# h5 common clock input/output defer# e2 common clock input dp#[0] j26 common clock input/output dp#[1] k25 common clock input/output dp#[2] k26 common clock input/output dp#[3] l25 common clock input/output dpslp# ad25 asynch gtl+ input drdy# h2 common clock input/output dstbn#[0] e22 source synch input/output dstbn#[1] k22 source synch input/output dstbn#[2] r22 source synch input/output dstbn#[3] w22 source synch input/output dstbp#[0] f21 source synch input/output dstbp#[1] j23 source synch input/output dstbp#[2] p23 source synch input/output dstbp#[3] w23 source synch input/output ferr#/pbe# b6 asynch agl+ output gtlref aa21 power/other input gtlref aa6 power/other input gtlref f20 power/other input gtlref f6 power/other input hit# f3 common clock input/output hitm# e3 common clock input/output ierr# ac3 common clock output ignne# b2 asynch gtl+ input init# w5 asynch gtl+ input itpclkout[0] aa20 power/other output itpclkout[1] ab22 power/other output itp_clk0 ac26 tap input itp_clk1 ad26 tap input table 33. pin listing by pin name pin name pin number signal buffer type direction
pin listing and signal definitions 66 251308-002 datasheet lint0 d1 asynch gtl+ input lint1 e5 asynch gtl+ input lock# g4 common clock input/output mcerr# v6 common clock input/output nc a22 nc a7 nc ad2 nc ad3 nc ae21 nc af3 nc af24 nc af25 prochot# c3 asynch gtl+ output pwrgood ab23 power/other input req#[0] j1 source synch input/output req#[1] k5 source synch input/output req#[2] j4 source synch input/output req#[3] j3 source synch input/output req#[4] h3 source synch input/output reset# ab25 common clock input rs#[0] f1 common clock input rs#[1] g5 common clock input rs#[2] f4 common clock input rsp# ab2 common clock input sktocc# af26 power/other output slp# ab26 asynch gtl+ input smi# b5 asynch gtl+ input stpclk# y4 asynch gtl+ input tck d4 tap input tdi c1 tap input tdo d5 tap output testhi0 ad24 power/other input testhi1 aa2 power/other input testhi2 ac21 power/other input testhi3 ac20 power/other input testhi4 ac24 power/other input testhi5 ac23 power/other input testhi8 u6 power/other input testhi9 w4 power/other input table 33. pin listing by pin name pin name pin number signal buffer type direction testhi10 y3 power/other input testhi11 a6 power/other input thermda b3 power/other thermdc c4 power/other thermtrip# a2 asynch gtl+ output tms f7 tap input trdy# j6 common clock input trst# e6 tap input vcc a10 power/other vcc a12 power/other vcc a14 power/other vcc a16 power/other vcc a18 power/other vcc a20 power/other vcc a8 power/other vcc aa10 power/other vcc aa12 power/other vcc aa14 power/other vcc aa16 power/other vcc aa18 power/other vcc aa8 power/other vcc ab11 power/other vcc ab13 power/other vcc ab15 power/other vcc ab17 power/other vcc ab19 power/other vcc ab7 power/other vcc ab9 power/other vcc ac10 power/other vcc ac12 power/other vcc ac14 power/other vcc ac16 power/other vcc ac18 power/other vcc ac8 power/other vcc ad11 power/other vcc ad13 power/other vcc ad15 power/other vcc ad17 power/other vcc ad19 power/other table 33. pin listing by pin name pin name pin number signal buffer type direction
pin listing and signal definitions 251308-002 67 datasheet vcc ad7 power/other vcc ad9 power/other vcc ae10 power/other vcc ae12 power/other vcc ae14 power/other vcc ae16 power/other vcc ae18 power/other vcc ae20 power/other vcc ae6 power/other vcc ae8 power/other vcc af11 power/other vcc af13 power/other vcc af15 power/other vcc af17 power/other vcc af19 power/other vcc af2 power/other vcc af21 power/other vcc af5 power/other vcc af7 power/other vcc af9 power/other vcc b11 power/other vcc b13 power/other vcc b15 power/other vcc b17 power/other vcc b19 power/other vcc b7 power/other vcc b9 power/other vcc c10 power/other vcc c12 power/other vcc c14 power/other vcc c16 power/other vcc c18 power/other vcc c20 power/other vcc c8 power/other vcc d11 power/other vcc d13 power/other vcc d15 power/other vcc d17 power/other vcc d19 power/other table 33. pin listing by pin name pin name pin number signal buffer type direction vcc d7 power/other vcc d9 power/other vcc e10 power/other vcc e12 power/other vcc e14 power/other vcc e16 power/other vcc e18 power/other vcc e20 power/other vcc e8 power/other vcc f11 power/other vcc f13 power/other vcc f15 power/other vcc f17 power/other vcc f19 power/other vcc f9 power/other vcca ad20 power/other vcciopll ae23 power/other vccsense a5 power/other output vccvid af4 power/other input vid0 ae5 power/other output vid1 ae4 power/other output vid2 ae3 power/other output vid3 ae2 power/other output vid4 ae1 power/other output vss a11 power/other vss a13 power/other vss a15 power/other vss a17 power/other vss a19 power/other vss a21 power/other vss a24 power/other vss a26 power/other vss a3 power/other vss a9 power/other vss aa1 power/other vss aa11 power/other vss aa13 power/other vss aa15 power/other vss aa17 power/other table 33. pin listing by pin name pin name pin number signal buffer type direction
pin listing and signal definitions 68 251308-002 datasheet vss aa19 power/other vss aa23 power/other vss aa26 power/other vss aa4 power/other vss aa7 power/other vss aa9 power/other vss ab10 power/other vss ab12 power/other vss ab14 power/other vss ab16 power/other vss ab18 power/other vss ab20 power/other vss ab21 power/other vss ab24 power/other vss ab3 power/other vss ab6 power/other vss ab8 power/other vss ac11 power/other vss ac13 power/other vss ac15 power/other vss ac17 power/other vss ac19 power/other vss ac2 power/other vss ac22 power/other vss ac25 power/other vss ac5 power/other vss ac7 power/other vss ac9 power/other vss ad1 power/other vss ad10 power/other vss ad12 power/other vss ad14 power/other vss ad16 power/other vss ad18 power/other vss ad21 power/other vss ad23 power/other vss ad4 power/other vss ad8 power/other vss ae11 power/other table 33. pin listing by pin name pin name pin number signal buffer type direction vss ae13 power/other vss ae15 power/other vss ae17 power/other vss ae19 power/other vss ae22 power/other vss ae24 power/other vss ae26 power/other vss ae7 power/other vss ae9 power/other vss af1 power/other vss af10 power/other vss af12 power/other vss af14 power/other vss af16 power/other vss af18 power/other vss af20 power/other vss af6 power/other vss af8 power/other vss b10 power/other vss b12 power/other vss b14 power/other vss b16 power/other vss b18 power/other vss b20 power/other vss b23 power/other vss b26 power/other vss b4 power/other vss b8 power/other vss c11 power/other vss c13 power/other vss c15 power/other vss c17 power/other vss c19 power/other vss c2 power/other vss c22 power/other vss c25 power/other vss c5 power/other vss c7 power/other vss c9 power/other table 33. pin listing by pin name pin name pin number signal buffer type direction
pin listing and signal definitions 251308-002 69 datasheet vss d10 power/other vss d12 power/other vss d14 power/other vss d16 power/other vss d18 power/other vss d20 power/other vss d21 power/other vss d24 power/other vss d3 power/other vss d6 power/other vss d8 power/other vss e1 power/other vss e11 power/other vss e13 power/other vss e15 power/other vss e17 power/other vss e19 power/other vss e23 power/other vss e26 power/other vss e4 power/other vss e7 power/other vss e9 power/other vss f10 power/other vss f12 power/other vss f14 power/other vss f16 power/other vss f18 power/other vss f2 power/other vss f22 power/other vss f25 power/other vss f5 power/other vss f8 power/other vss g21 power/other vss g24 power/other vss g3 power/other vss g6 power/other vss h1 power/other vss h23 power/other vss h26 power/other table 33. pin listing by pin name pin name pin number signal buffer type direction vss h4 power/other vss j2 power/other vss j22 power/other vss j25 power/other vss j5 power/other vss k21 power/other vss k24 power/other vss k3 power/other vss k6 power/other vss l1 power/other vss l23 power/other vss l26 power/other vss l4 power/other vss m2 power/other vss m22 power/other vss m25 power/other vss m5 power/other vss n21 power/other vss n24 power/other vss n3 power/other vss n6 power/other vss p2 power/other vss p22 power/other vss p25 power/other vss p5 power/other vss r1 power/other vss r23 power/other vss r26 power/other vss r4 power/other vss t21 power/other vss t24 power/other vss t3 power/other vss t6 power/other vss u2 power/other vss u22 power/other vss u25 power/other vss u5 power/other vss v1 power/other vss v23 power/other table 33. pin listing by pin name pin name pin number signal buffer type direction
pin listing and signal definitions 70 251308-002 datasheet vss v26 power/other vss v4 power/other vss w21 power/other vss w24 power/other vss w3 power/other vss w6 power/other vss y2 power/other vss y22 power/other vss y25 power/other vss y5 power/other vssa ad22 power/other vsssense a4 power/other output table 34. pin listing by pin number pin number pin name signal buffer type direction a2 thermtrip# asynch gtl+ output a3 vss power/other a4 vsssense power/other output a5 vccsense power/other output a6 testhi11 power/other input a7 nc a8 vcc power/other a9 vss power/other a10 vcc power/other a11 vss power/other a12 vcc power/other a13 vss power/other a14 vcc power/other a15 vss power/other a16 vcc power/other a17 vss power/other a18 vcc power/other a19 vss power/other a20 vcc power/other a21 vss power/other a22 nc a23 d#[02] source synch input/output a24 vss power/other table 33. pin listing by pin name pin name pin number signal buffer type direction a25 d#[03] source synch input/output a26 vss power/other aa1 vss power/other aa2 testhi1 power/other input aa3 binit# common clock input/output aa4 vss power/other aa5 bpm#[4] common clock input/output aa6 gtlref power/other input aa7 vss power/other aa8 vcc power/other aa9 vss power/other aa10 vcc power/other aa11 vss power/other aa12 vcc power/other aa13 vss power/other aa14 vcc power/other aa15 vss power/other aa16 vcc power/other aa17 vss power/other aa18 vcc power/other aa19 vss power/other aa20 itpclkout [0] power/other output aa21 gtlref power/other input aa22 d#[62] source synch input/output aa23 vss power/other aa24 d#[63] source synch input/output aa25 d#[61] source synch input/output aa26 vss power/other ab1 a#[35] source synch input/output ab2 rsp# common clock input ab3 vss power/other ab4 bpm#[5] common clock input/output ab5 bpm#[1] common clock input/output ab6 vss power/other ab7 vcc power/other ab8 vss power/other ab9 vcc power/other ab10 vss power/other table 34. pin listing by pin number pin number pin name signal buffer type direction
pin listing and signal definitions 251308-002 71 datasheet ab11 vcc power/other ab12 vss power/other ab13 vcc power/other ab14 vss power/other ab15 vcc power/other ab16 vss power/other ab17 vcc power/other ab18 vss power/other ab19 vcc power/other ab20 vss power/other ab21 vss power/other ab22 itpclkout [1] power/other output ab23 pwrgood power/other input ab24 vss power/other ab25 reset# common clock input ab26 slp# asynch gtl+ input ac1 ap#[0] common clock input/output ac2 vss power/other ac3 ierr# common clock output ac4 bpm#[2] common clock input/output ac5 vss power/other ac6 bpm#[0] common clock input/output ac7 vss power/other ac8 vcc power/other ac9 vss power/other ac10 vcc power/other ac11 vss power/other ac12 vcc power/other ac13 vss power/other ac14 vcc power/other ac15 vss power/other ac16 vcc power/other ac17 vss power/other ac18 vcc power/other ac19 vss power/other ac20 testhi3 power/other input ac21 testhi2 power/other input ac22 vss power/other table 34. pin listing by pin number pin number pin name signal buffer type direction ac23 testhi5 power/other input ac24 testhi4 power/other input ac25 vss power/other ac26 itp_clk0 tap input ad1 vss power/other ad2 nc ad3 nc ad4 vss power/other ad5 bsel1 power/other output ad6 bsel0 power/other output ad7 vcc power/other ad8 vss power/other ad9 vcc power/other ad10 vss power/other ad11 vcc power/other ad12 vss power/other ad13 vcc power/other ad14 vss power/other ad15 vcc power/other ad16 vss power/other ad17 vcc power/other ad18 vss power/other ad19 vcc power/other ad20 vcca power/other ad21 vss power/other ad22 vssa power/other ad23 vss power/other ad24 testhi0 power/other input ad25 dpslp# asynch gtl+ input ad26 itp_clk1 tap input ae1 vid4 power/other output ae2 vid3 power/other output ae3 vid2 power/other output ae4 vid1 power/other output ae5 vid0 power/other output ae6 vcc power/other ae7 vss power/other ae8 vcc power/other ae9 vss power/other table 34. pin listing by pin number pin number pin name signal buffer type direction
pin listing and signal definitions 72 251308-002 datasheet ae10 vcc power/other ae11 vss power/other ae12 vcc power/other ae13 vss power/other ae14 vcc power/other ae15 vss power/other ae16 vcc power/other ae17 vss power/other ae18 vcc power/other ae19 vss power/other ae20 vcc power/other ae21 nc ae22 vss power/other ae23 vcciopll power/other ae24 vss power/other ae25 dbr# asynch gtl+ output ae26 vss power/other af1 vss power/other af2 vcc power/other af3 nc af4 vccvid power/other input af5 vcc power/other af6 vss power/other af7 vcc power/other af8 vss power/other af9 vcc power/other af10 vss power/other af11 vcc power/other af12 vss power/other af13 vcc power/other af14 vss power/other af15 vcc power/other af16 vss power/other af17 vcc power/other af18 vss power/other af19 vcc power/other af20 vss power/other af21 vcc power/other af22 bclk[0] bus clock input table 34. pin listing by pin number pin number pin name signal buffer type direction af23 bclk[1] bus clock input af24 nc af25 nc af26 sktocc# power/other output b2 ignne# asynch gtl+ input b3 thermda power/other b4 vss power/other b5 smi# asynch gtl+ input b6 ferr#/pbe# asynch agl+ output b7 vcc power/other b8 vss power/other b9 vcc power/other b10 vss power/other b11 vcc power/other b12 vss power/other b13 vcc power/other b14 vss power/other b15 vcc power/other b16 vss power/other b17 vcc power/other b18 vss power/other b19 vcc power/other b20 vss power/other b21 d#[0] source synch input/output b22 d#[01] source synch input/output b23 vss power/other b24 d#[06] source synch input/output b25 d#[09] source synch input/output b26 vss power/other c1 tdi tap input c2 vss power/other c3 prochot# asynch gtl+ output c4 thermdc power/other c5 vss power/other c6 a20m# asynch gtl+ input c7 vss power/other c8 vcc power/other c9 vss power/other c10 vcc power/other table 34. pin listing by pin number pin number pin name signal buffer type direction
pin listing and signal definitions 251308-002 73 datasheet c11 vss power/other c12 vcc power/other c13 vss power/other c14 vcc power/other c15 vss power/other c16 vcc power/other c17 vss power/other c18 vcc power/other c19 vss power/other c20 vcc power/other c21 d#[04] source synch input/output c22 vss power/other c23 d#[07] source synch input/output c24 d#[08] source synch input/output c25 vss power/other c26 d#[12] source synch input/output d1 lint0 asynch gtl+ input d2 bpri# common clock input d3 vss power/other d4 tck tap input d5 tdo tap output d6 vss power/other d7 vcc power/other d8 vss power/other d9 vcc power/other d10 vss power/other d11 vcc power/other d12 vss power/other d13 vcc power/other d14 vss power/other d15 vcc power/other d16 vss power/other d17 vcc power/other d18 vss power/other d19 vcc power/other d20 vss power/other d21 vss power/other d22 d#[05] source synch input/output d23 d#[13] source synch input/output table 34. pin listing by pin number pin number pin name signal buffer type direction d24 vss power/other d25 d#[15] source synch input/output d26 d#[23] source synch input/output e1 vss power/other e2 defer# common clock input e3 hitm# common clock input/output e4 vss power/other e5 lint1 asynch gtl+ input e6 trst# tap input e7 vss power/other e8 vcc power/other e9 vss power/other e10 vcc power/other e11 vss power/other e12 vcc power/other e13 vss power/other e14 vcc power/other e15 vss power/other e16 vcc power/other e17 vss power/other e18 vcc power/other e19 vss power/other e20 vcc power/other e21 dbi#[0] source synch input/output e22 dstbn#[0] source synch input/output e23 vss power/other e24 d#[17] source synch input/output e25 d#[21] source synch input/output e26 vss power/other f1 rs#[0] common clock input f2 vss power/other f3 hit# common clock input/output f4 rs#[2] common clock input f5 vss power/other f6 gtlref power/other input f7 tms tap input f8 vss power/other f9 vcc power/other f10 vss power/other table 34. pin listing by pin number pin number pin name signal buffer type direction
pin listing and signal definitions 74 251308-002 datasheet f11 vcc power/other f12 vss power/other f13 vcc power/other f14 vss power/other f15 vcc power/other f16 vss power/other f17 vcc power/other f18 vss power/other f19 vcc power/other f20 gtlref power/other input f21 dstbp#[0] source synch input/output f22 vss power/other f23 d#[19] source synch input/output f24 d#[20] source synch input/output f25 vss power/other f26 d#[22] source synch input/output g1 ads# common clock input/output g2 bnr# common clock input/output g3 vss power/other g4 lock# common clock input/output g5 rs#[1] common clock input g6 vss power/other g21 vss power/other g22 d#[10] source synch input/output g23 d#[18] source synch input/output g24 vss power/other g25 dbi#[1] source synch input/output g26 d#[25] source synch input/output h1 vss power/other h2 drdy# common clock input/output h3 req#[4] source synch input/output h4 vss power/other h5 dbsy# common clock input/output h6 br0# common clock input/output h21 d#[11] source synch input/output h22 d#[16] source synch input/output h23 vss power/other h24 d#[26] source synch input/output h25 d#[31] source synch input/output table 34. pin listing by pin number pin number pin name signal buffer type direction h26 vss power/other j1 req#[0] source synch input/output j2 vss power/other j3 req#[3] source synch input/output j4 req#[2] source synch input/output j5 vss power/other j6 trdy# common clock input j21 d#[14] source synch input/output j22 vss power/other j23 dstbp#[1] source synch input/output j24 d#[29] source synch input/output j25 vss power/other j26 dp#[0] common clock input/output k1 a#[06] source synch input/output k2 a#[03] source synch input/output k3 vss power/other k4 a#[04] source synch input/output k5 req#[1] source synch input/output k6 vss power/other k21 vss power/other k22 dstbn#[1] source synch input/output k23 d#[30] source synch input/output k24 vss power/other k25 dp#[1] common clock input/output k26 dp#[2] common clock input/output l1 vss power/other l2 a#[09] source synch input/output l3 a#[07] source synch input/output l4 vss power/other l5 adstb#[0] source synch input/output l6 a#[05] source synch input/output l21 d#[24] source synch input/output l22 d#[28] source synch input/output l23 vss power/other l24 comp[0] power/other input/output l25 dp#[3] common clock input/output l26 vss power/other m1 a#[13] source synch input/output m2 vss power/other table 34. pin listing by pin number pin number pin name signal buffer type direction
pin listing and signal definitions 251308-002 75 datasheet m3 a#[10] source synch input/output m4 a#[11] source synch input/output m5 vss power/other m6 a#[08] source synch input/output m21 d#[27] source synch input/output m22 vss power/other m23 d#[32] source synch input/output m24 d#[35] source synch input/output m25 vss power/other m26 d#[37] source synch input/output n1 a#[12] source synch input/output n2 a#[14] source synch input/output n3 vss power/other n4 a#[15] source synch input/output n5 a#[16] source synch input/output n6 vss power/other n21 vss power/other n22 d#[33] source synch input/output n23 d#[36] source synch input/output n24 vss power/other n25 d#[39] source synch input/output n26 d#[38] source synch input/output p1 comp[1] power/other input/output p2 vss power/other p3 a#[19] source synch input/output p4 a#[20] source synch input/output p5 vss power/other p6 a#[24] source synch input/output p21 d#[34] source synch input/output p22 vss power/other p23 dstbp#[2] source synch input/output p24 d#[41] source synch input/output p25 vss power/other p26 dbi#[2] source synch input/output r1 vss power/other r2 a#[18] source synch input/output r3 a#[21] source synch input/output r4 vss power/other r5 adstb#[1] source synch input/output table 34. pin listing by pin number pin number pin name signal buffer type direction r6 a#[28] source synch input/output r21 d#[40] source synch input/output r22 dstbn#[2] source synch input/output r23 vss power/other r24 d#[43] source synch input/output r25 d#[42] source synch input/output r26 vss power/other t1 a#[17] source synch input/output t2 a#[22] source synch input/output t3 vss power/other t4 a#[26] source synch input/output t5 a#[30] source synch input/output t6 vss power/other t21 vss power/other t22 d#[46] source synch input/output t23 d#[47] source synch input/output t24 vss power/other t25 d#[45] source synch input/output t26 d#[44] source synch input/output u1 a#[23] source synch input/output u2 vss power/other u3 a#[25] source synch input/output u4 a#[31] source synch input/output u5 vss power/other u6 testhi8 power/other input u21 d#[52] source synch input/output u22 vss power/other u23 d#[50] source synch input/output u24 d#[49] source synch input/output u25 vss power/other u26 d#[48] source synch input/output v1 vss power/other v2 a#[27] source synch input/output v3 a#[32] source synch input/output v4 vss power/other v5 ap#[1] common clock input/output v6 mcerr# common clock input/output v21 dbi#[3] source synch input/output v22 d#[53] source synch input/output table 34. pin listing by pin number pin number pin name signal buffer type direction
pin listing and signal definitions 76 251308-002 datasheet v23 vss power/other v24 d#[54] source synch input/output v25 d#[51] source synch input/output v26 vss power/other w1 a#[29] source synch input/output w2 a#[33] source synch input/output w3 vss power/other w4 testhi9 power/other input w5 init# asynch gtl+ input w6 vss power/other w21 vss power/other w22 dstbn#[3] source synch input/output w23 dstbp#[3] source synch input/output w24 vss power/other w25 d#[57] source synch input/output w26 d#[55] source synch input/output y1 a#[34] source synch input/output y2 vss power/other y3 testhi10 power/other input y4 stpclk# asynch gtl+ input y5 vss power/other y6 bpm#[3] common clock input/output y21 d#[60] source synch input/output y22 vss power/other y23 d#[58] source synch input/output y24 d#[59] source synch input/output y25 vss power/other y26 d#[56] source synch input/output table 34. pin listing by pin number pin number pin name signal buffer type direction
251308-002 77 datasheet pin listing and signal definitions 5.2 alphabetical signals reference table 35. signal description (sheet 1 of 8) name type description a[35:3]# input/ output a[35:3]# (address) define a 2 36 -byte physical memory address space. in sub- phase 1 of the address phase, these pins transmit the address of a transaction. in sub-phase 2, these pins transmit transaction type information. these signals must connect the appropriate pins of all agents on the mobile intel pentium 4 processor-m system bus. a[35:3]# are protected by parity signals ap[1:0]#. a[35:3]# are source synchronous signals and are latched into the receiving buffers by adstb[1:0]#. on the active-to-inactive transition of reset#, the processor samples a subset of the a[35:3]# pins to determine power-on configuration. see section 7.1 for more details. a20m# input if a20m# (address-20 mask) is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/ write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. ads# input/ output ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[35:3]# and req[4:0]# pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# input/ output address strobes are used to latch a[35:3]# and req[4:0]# on their rising and falling edges. strobes are associated with signals as shown below. ap[1:0]# input/ output ap[1:0]# (address parity) are driven by the request initiator along with ads#, a[35:3]#, and the transaction type on the req[4:0]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect the appropriate pins of all mobile intel celeron processor system bus agents. the following table defines the coverage model of these signals. bclk[1:0] input the differential pair bclk (bus clock) determines the system bus frequency. all processor system bus agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are specified with respect to the rising edge of bclk0 crossing v cross . signals associated strobe req[4:0]#, a[16:3]# adstb0# a[35:17]# adstb1# request signals subphase 1 subphase 2 a[35:24]# ap0# ap1# a[23:3]# ap1# ap0# req[4:0]# ap1# ap0#
78 251308-002 datasheet pin listing and signal definitions binit# input/ output binit# (bus initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. if the binit# driver is enabled during power-on configuration, binit# is asserted to signal any bus condition that prevents reliable future operation. if binit# observation is enabled during power-on configuration, and binit# is sampled asserted, symmetric agents reset their bus lock# activity and bus request arbitration state machines. the bus agents do not reset their ioq and transaction tracking state machines upon observation of binit# activation. once the binit# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and ioq entries. if binit# observation is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the error handling architecture of the system. bnr# input/ output bnr# (block next request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. bpm[5:0]# input/ output bpm[5:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpm[5:0]# should connect the appropriate pins of all mobile intel celeron processor system bus agents. bpm4# provides prdy# (probe ready) functionality for the tap port. prdy# is a processor output used by debug tools to determine processor debug readiness. bpm5# provides preq# (probe request) functionality for the tap port. preq# is used by debug tools to request debug operation of the processor. please refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/ 845mz chipset platform design guide for more detailed information. these signals do not have on-die termination and must be terminated on the system board. bpri# input bpri# (bus priority request) is used to arbitrate for ownership of the processor system bus. it must connect the appropriate pins of all processor system bus agents. observing bpri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. br0# input/ output br0# drives the breq0# signal in the system and is used by the processor to request the bus. during power-on configuration this pin is sampled to determine the agent id = 0. this signal does not have on-die termination and must be terminated. bsel[1:0] output bsel[1:0] (bus select) are used to select the processor input clock frequency. ta b l e 5 defines the possible combinations of the signals and the frequency associated with each combination. the required frequency is determined by the processor, chipset and clock synthesizer. all agents must operate at the same frequency. the mobile intel celeron processor operates at a 400-mhz system bus frequency (100-mhz bclk[1:0] frequency). for more information about these pins, including termination recommendations refer to section 2.9 and the appropriate platform design guidelines. comp[1:0] analog comp[1:0] must be terminated on the system board using precision resistors. refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for details on implementation. table 35. signal description (sheet 2 of 8) name type description
251308-002 79 datasheet pin listing and signal definitions d[63:0]# input/ output d[63:0]# (data) are the data signals. these signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. d[63:0]# are latched off the falling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to data strobes and dbi# . furthermore, the dbi# pins determine the polarity of the data signals. each group of 16 data signals corresponds to one dbi# signal. when the dbi# signal is active, the corresponding data group is inverted and therefore sampled active high. dbi[3:0]# input/ output dbi[3:0]# (data bus inversion) are source synchronous and indicate the polarity of the d[63:0]# signals. the dbi[3:0]# signals are activated when the data on the data bus is inverted. the bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. dbr# output dbr# (data bus reset) is used only in processor systems where no debug port is implemented on the system board. dbr# is used by a debug port interposer so that an in-target probe can drive system reset. if a debug port is implemented in the system, dbr# is a no connect in the system. dbr# is not a processor signal. dbsy# input/ output dbsy# (data bus busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all processor system bus agents. defer# input defer# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or input/output agent. this signal must connect the appropriate pins of all processor system bus agents. dp[3:0]# input/ output dp[3:0]# (data parity) provide parity protection for the d[63:0]# signals. they are driven by the agent responsible for driving d[63:0]#, and must connect the appropriate pins of all mobile intel celeron processor system bus agents. dpslp# input dpslp# when asserted on the platform causes the processor to transition from the sleep state to the deep sleep state. in order to return to the sleep state, dpslp# must be deasserted and bclk[1:0] must be running. table 35. signal description (sheet 3 of 8) name type description quad-pumped signal groups data group dstbn#/ dstbp# dbi# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3 dbi[3:0] assignment to data bus bus signal data bus signals dbi3# d[63:48]# dbi2# d[47:32]# dbi1# d[31:16]# dbi0# d[15:0]#
80 251308-002 datasheet pin listing and signal definitions drdy# input/ output drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of all processor system bus agents. dstbn[3:0]# input/ output data strobe used to latch in d[63:0]#. dstbp[3:0]# input/ output data strobe used to latch in d[63:0]#. ferr#/pbe# output ferr#/pbe# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by stpclk#. when stpclk# is not asserted, ferr#/ pbe# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. when stpclk# is not asserted, ferr#/ pbe# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using ms-dos*-type floating-point error reporting. when stpclk# is asserted, an assertion of ferr#/pbe# indicates that the processor has a pending break event waiting for service. the assertion of ferr#/pbe# indicates that the processor should be returned to the normal state. when ferr#/pbe# is asserted, indicating a break event, it will remain asserted until stpclk# is deasserted. for additional information on the pending break event functionality, including the identification of support of the feature and enable/ disable information, refer to volume 3 of the intel architecture software developer's manual and the intel processor identification and the cpuid instruction application note. gtlref input gtlref determines the signal reference level for agtl+ input pins. gtlref should be set at 2/3 v cc . gtlref is used by the agtl+ receivers to determine if a signal is a logical 0 or logical 1. refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for more information. hit# hitm# input/ output input/ output hit# (snoop hit) and hitm# (hit modified) convey transaction snoop operation results. any system bus agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. ierr# output ierr# (internal error) is asserted by a processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the processor system bus. this transaction may optionally be converted to an external error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until the assertion of reset#. this signal does not have on-die termination and must be terminated on the system board. table 35. signal description (sheet 4 of 8) name type description signals associated strobe d[15:0]#, dbi0# dstbn0# d[31:16]#, dbi1# dstbn1# d[47:32]#, dbi2# dstbn2# d[63:48]#, dbi3# dstbn3# signals associated strobe d[15:0]#, dbi0# dstbp0# d[31:16]#, dbi1# dstbp1# d[47:32]#, dbi2# dstbp2# d[63:48]#, dbi3# dstbp3#
251308-002 81 datasheet pin listing and signal definitions ignne# input ignne# (ignore numeric error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. init# input init# (initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. the processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). itpclkout [1:0] output itpclkout[1:0] is an uncompensated differential clock output that is a delayed copy of the bclk[1:0], which is an input to the processor. this clock output can be used as the differential clock into the itp port that is designed onto the motherboard. if itpclkout[1:0] outputs are not used, they must be terminated properly. refer to section 2.5 for additional details and termination requirements. itp_clk[1:0] input itp_clk[1:0] are copies of bclk that are used only in processor systems where no debug port is implemented on the system board. itp_clk[1:0] are used as bclk[1:0] references for a debug port implemented on an interposer. if a debug port is implemented in the system, itp_clk[1:0] are no connects in the system. these are not processor signals. lint[1:0] input lint[1:0] (local apic interrupt) must connect the appropriate pins of all apic bus agents. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# input/ output lock# indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor system bus agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the processor system bus, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. mcerr# input/ output mcerr# (machine check error) is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor system bus agents. mcerr# assertion conditions are configurable at a system level. assertion options are defined by the following options: enabled or disabled. asserted, if configured, for internal errors along with ierr#. asserted, if configured, by the request initiator of a bus transaction after it observes an error. asserted by any bus agent when it observes an error in a bus transaction. for more details regarding machine check architecture, please refer to the ia-32 software developer?s manual, volume 3: system programming guide . table 35. signal description (sheet 5 of 8) name type description
82 251308-002 datasheet pin listing and signal definitions prochot# output the assertion of prochot# (processor hot) indicates that the processor die temperature has reached its thermal limit. see section 6 for more details. pwrgood input pwrgood (power good) is a processor input. the processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. figure 15 illustrates the relationship of pwrgood to the reset# signal. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. it must also meet the minimum pulse width specification in table 20 , and be followed by a 1 to 10 ms reset# pulse. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# input/ output req[4:0]# (request command) must connect the appropriate pins of all processor system bus agents. they are asserted by the current bus owner to define the currently active transaction type. these signals are source synchronous to adstb0#. refer to the ap[1:0]# signal description for details on parity checking of these signals. reset# input asserting the reset# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least one millisecond after v cc and bclk have reached their proper specifications. on observing active reset#, all system bus agents will deassert their outputs within two clocks. reset# must not be kept asserted for more than 10 ms while pwrgood is asserted. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. these configuration options are described in the section 7.1 . this signal does not have on-die termination and must be terminated on the system board. rs[2:0]# input rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. rsp# input rsp# (response parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect to the appropriate pins of all processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. sktocc# output sktocc# (socket occupied) will be pulled to ground by the processor. system board designers may use this pin to determine if the processor is present. slp# input slp# (sleep), when asserted in stop-grant state, causes the processor to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will only recognize the assertion of the reset# signal, deassertion of slp#, and assertion of dpslp# input while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and processor core units. if the bclk input is stopped or if dpslp# is asserted while in the sleep state, the processor will exit the sleep state and transition to the deep sleep state. table 35. signal description (sheet 6 of 8) name type description
251308-002 83 datasheet pin listing and signal definitions smi# input smi# (system management interrupt) is asserted asynchronously by system logic. on accepting a system management interrupt, the processor saves the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. if smi# is asserted during the deassertion of reset# the processor will tristate its outputs. stpclk# input assertion of stpclk# (stop clock) causes the processor to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck input tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi input tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo output tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. testhi[11] testhi[10:8] testhi[5:0] input testhi[11], testhi[10:8], and testhi[5:0] must be connected to a v cc power source through a resistor for proper processor operation. see section 2.5 for more details. thermda other thermal diode anode. see section 6 thermdc other thermal diode cathode. see section 6 thermtrip# output assertion of thermtrip# (thermal trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135 c. upon assertion of thermtrip#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. to protect the processor, its core voltage (vcc) must be removed following the assertion of thermtrip#. see figure 18 and table 20 for the appropriate power down sequence and timing requirements. once activated, thermtrip# remains latched until reset# is asserted. while the assertion of the reset# signal will deassert thermtrip#, if the processor?s junction temperature remains at or above the trip level, thermtrip# will again be asserted. tms input tms (test mode select) is a jtag specification support signal used by debug tools. trdy# input trdy# (target ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of all system bus agents. trst# input trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. this can be done with a 680 ohm pull-down resistor. v cca input v cca provides isolated power for the internal processor core pll?s. refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for complete implementation details. v cciopll input v cciopll provides isolated power for internal processor system bus pll?s. follow the guidelines for v cca , and refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for complete implementation details. table 35. signal description (sheet 7 of 8) name type description
84 251308-002 datasheet pin listing and signal definitions v ccsense output v ccsense is an isolated low impedance connection to processor core power (v cc ). it can be used to sense or measure power near the silicon with little noise. vccvid input independent 1.2-v supply must be routed to vccvid pin for the mobile intel celeron processor?s voltage identification circuit. vid[4:0] output vid[4:0] (voltage id) pins are used to support automatic selection of power supply voltages (vcc). unlike some previous generations of processors, these are open drain signals that are driven by the mobile intel celeron processor and must be pulled up to 3.3 v (max.) with 1-kohm resistors. the voltage supply for these pins must be valid before the vr can supply vcc to the processor. conversely, the vr output must be disabled until the voltage supply for the vid pins becomes valid. the vid pins are needed to support the processor voltage specification variations. see table 3 for definitions of these pins. the vr must supply the voltage that is requested by the pins, or disable itself. v ssa input v ssa is the isolated ground for internal plls. v sssense output v sssense is an isolated low impedance connection to processor core v ss . it can be used to sense or measure ground near the silicon with little noise. table 35. signal description (sheet 8 of 8) name type description
251308-002 85 datasheet thermal specifications and design considerations 6 thermal specifications and design considerations in order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat pipe, or other heat transfer system) must make firm contact to the exposed processor die. the processor die must be clean before the thermal solution is attached or the processor may be damaged. table 36 provides the thermal design power (tdp) dissipation and the minimum and maximum t j temperatures for the mobile intel celeron processor. a thermal solution should be designed to ensure the junction temperature never exceeds the 100c t j specification while operating at the thermal design power. additionally, a secondary failsafe mechanism in hardware would be provided to shutdown the processor under catastrophic thermal conditions, as described in section 2.4.2 . tdp is a thermal design power specification based on the worst case power dissipation of the processor while executing publicly available software under normal operating conditions at nominal voltages. contact your intel field sales representative for further information. table 36. power specifications for the mobile intel celeron processor notes: 1. tdp is defined as the worst case power dissipated by the processor while executing publicly available software under normal operating conditions at nominal voltages that meet the load line specifications. the tdp number shown is a specification based on i cc (maximum) at nominal voltages and indirectly tested by this i cc (maximum) testing. tdp definition is synonymous with the thermal design power (typical) specification referred to in the previous emts. the intel tdp specification is a recommended design point and is not representative of the absolute maximum power the processor may dissipate under worst case conditions. 1. not 100% tested. these power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 1. the maximum junction temperature (t j ) is specified as the hottest location on the die. the thermal monitor?s automatic mode is used to indicate that the maximum t j has been reached. refer to section 6.1.1 for t j measurement guidelines (refer to section 6.1.2 for thermal monitor details). symbol parameter min typ max unit notes tdp thermal design power at 1.80 ghz & 1.30 v 1.70 ghz & 1.30 v 1.60 ghz & 1.30 v 1.50 ghz & 1.30 v 1.40 ghz & 1.30 v 30.0 30.0 30.0 30.0 30.0 w at 100c, note 1 p ah p sgnt p slp auto halt/stop grant/sleep power at 1.30 v 7.5 w at 50c, note 2 p dslp deep sleep power at 1.30 v 5.0 w at 35c, note 2 tj junction temperature 0 100 c note 3
86 251308-002 datasheet thermal specifications and design considerations 6.1 thermal specifications 6.1.1 thermal diode the mobile intel celeron processor incorporates two methods of monitoring die temperature, the thermal monitor and the thermal diode. the thermal monitor (detailed in section 6.1.2 ) must be used to determine when the maximum specified processor junction temperature has been reached. the second method, the thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. the thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but cannot be used to indicate that the maximum t j of the processor has been reached. table 37 and table 38 provide the diode interface and specifications. note: the reading of the thermal sensor connected to the thermal diode does not reflect the temperature of the hottest location on the die (t j ). this is due to inaccuracies in the thermal diode, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature. time based variations can occur since the sampling rate of the sensor is much slower than the die level temperature changes. the offset between the thermal diode based temperature reading and the hottest location of the die (thermal monitor) may be characterized using the thermal monitor?s automatic mode activation of thermal control circuit. this temperature offset must be taken into account when using the processor thermal diode to implement power management events. table 37. thermal diode interface table 38. thermal diode specifications notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. 2. characterized at 100c. 3. not 100% tested. specified by design characterization. 4. the ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: i fw =i s *(e (qv d /nkt) -1) where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). 5. the series resistance, r t , is provided to allow for a more accurate measurement of the diode junction temperature. r t as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. r t can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: signal name pin/ball number signal description thermda b3 thermal diode anode thermdc c4 thermal diode cathode symbol parameter min typ max unit notes i fw forward bias current 5 300 a 1 n diode ideality factor 1.0012 1.0021 1.0030 2, 3, 4 r t series resistance 3.86 ohms 2, 3, 5
251308-002 87 datasheet thermal specifications and design considerations t error = [r t *(n-1)*i fwmin ]/[(nk/q)*ln n] where t error = sensor temperature error, n = sensor current ration, k = boltzmann constant, q = electronic charge. 6.1.2 thermal monitor the thermal monitor feature found in the mobile intel celeron processor allows system designers to design lower cost thermal solutions without compromising system integrity or reliability. by using a factory-tuned, precision on-die thermal sensor, and a fast acting thermal control circuit (tcc), the processor, without the aid of any additional software or hardware, can keep the processor?s die temperature within factory specifications under nearly all conditions. thus, the thermal monitor allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications instead of being designed to the much higher maximum processor power envelopes. thermal monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks. the processor clocks are modulated when the thermal control circuit (tcc) is activated. thermal monitor uses two modes to activate the tcc: automatic mode and on- demand mode. automatic mode is required for the processor to operate within specifications and must first be enabled via bios. once automatic mode is enabled, the tcc will activate only when the internal die temperature is very near the temperature limits of the processor. when tcc is enabled, and a high temperature situation exists (i.e. tcc is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30-50%). cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. once the temperature has returned to a non-critical level, modulation ceases and tcc goes inactive. a small amount of hysteresis has been included to prevent rapid active/ inactive transitions of the tcc when the processor temperature is near the trip point. processor performance will be decreased by approximately the same amount as the duty cycle when the tcc is active, however, with a properly designed and characterized thermal solution, the tcc will only be activated briefly when running the most power intensive applications in a high ambient temperature environment. for automatic mode, the duty cycle is factory configured and cannot be modified. also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. the tcc may also be activated via on-demand mode. if bit 4 of the acpi thermal monitor control register is written to a "1", the tcc will be activated immediately, independent of the processor temperature. when using on-demand mode to activate the tcc, the duty cycle of the clock modulation is programmable via bits 3:1 of the same acpi thermal monitor control register. in automatic mode, the duty cycle is fixed, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. on- demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the tcc via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, the duty cycle of the automatic mode will override the duty cycle selected by the on-demand mode. an external signal, prochot# (processor hot) is asserted when the processor die temperature has reached its thermal limit. if the tcc is enabled (note that the tcc must be enabled for the processor to be operating within spec), tcc will be active when the prochot# signal is active. the temperature at which the thermal control circuit activates is not user configurable and is not software visible. bus snooping and interrupt latching are active while the tcc is active.
88 251308-002 datasheet thermal specifications and design considerations besides the thermal sensor and tcc, the thermal monitor feature also includes one acpi register, performance monitoring logic, bits in three model specific registers (msr), and one i/o pin (prochot#). all are available to monitor and control the state of the thermal monitor feature. thermal monitor can be configured to generate an interrupt upon the assertion or de-assertion of prochot#. if automatic mode is disabled, the processor will be operating out of specification. regardless of enabling of the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 c. at this point the system bus signal thermtrip# will go active and stay active until reset# has been initiated. thermtrip# activation is independent of processor activity and does not generate any bus cycles. if thermtrip# is asserted, processor core voltage (v cc ) must be removed within the timeframe defined in table 20 .
251308-002 89 datasheet configuration and low power features 7 configuration and low power features 7.1 power-on configuration options several configuration options can be configured by hardware. the mobile intel celeron processor samples its hardware configuration at reset, on the active-to-inactive transition of reset#. for specifications on these options, please refer to table 39 . frequency determination functionality will exist on engineering sample processors which means that samples can run at varied frequencies. production material will have the bus to core ratio locked during manufacturing and can only be operated at the rated frequency. the sampled information configures the processor for subsequent operation. these configuration options cannot be changed except by another reset. all resets reconfigure the processor. note: asserting this signal during reset# will select the corresponding option. 7.2 clock control and low power states the use of autohalt, stop-grant, sleep, and deep sleep states is allowed in mobile intel celeron processor based systems to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 33 for a visual representation of the processor low-power states. 7.2.1 normal state this is the normal operating state for the processor. table 39. power-on configuration option pins configuration option pin 1 output tristate smi# execute bist init# in order queue pipelining (set ioq depth to 1) a7# disable mcerr# observation a9# disable binit# observation a10# apic cluster id (0-3) a[12:11]# disable bus parking a15# symmetric agent arbitration id br0#
90 251308-002 datasheet configuration and low power features 7.2.2 autohalt powerdown state autohalt is a low-power state entered when the processor executes the halt instruction. the processor will transition to the normal state upon the occurrence of smi#, binit#, init#, lint[1:0] (nmi, intr), or psb interrupt message. reset# will cause the processor to immediately initialize itself. the return from a system management interrupt (smi) handler can be to either normal mode or the autohalt powerdown state. see the intel architecture software developer's manual, volume iii: system programmer's guide for more information. the system can generate a stpclk# while the processor is in the autohalt powerdown state. when the system deasserts the stpclk# interrupt, the processor will return execution to the halt state. while in autohalt powerdown state, the processor will process bus snoops. 7.2.3 stop-grant state when the stpclk# pin is asserted, the stop-grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued stop grant acknowledge special bus cycle. since the agtl+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to v cc ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the system bus should be driven to the inactive state. binit# will not be serviced while the processor is in stop-grant state. the event will be latched and can be serviced by software upon exit from the stop-grant state. figure 33. clock control states snoop occurs stop grant normal sleep halt/ grant snoop auto halt deep sleep stpclk# asserted slp# asserted slp# de-asserted stpclk# de-asserted snoop serviced hlt instruction snoop serviced snoop occurs dpslp# de-asserted dpslp# asserted stpclk# asserted stpclk# de-asserted halt break v0001-04 halt break - a20m#, binit#, init#, intr, nmi, preq#, reset#, smi#, or apic interrupt
251308-002 91 datasheet configuration and low power features reset# will cause the processor to immediately initialize itself, but the processor will stay in stop-grant state. a transition back to the normal state will occur with the deassertion of the stpclk# signal. when re-entering the stop-grant state from the sleep state, stpclk# should only be deasserted ten or more bus clocks after the deassertion of slp#. a transition to the halt/grant snoop state will occur when the processor detects a snoop on the system bus (see section 7.2.4 ). a transition to the sleep state (see section 7.2.5 ) will occur with the assertion of the slp# signal. while in the stop-grant state, smi#, init#, binit# and lint[1:0] will be latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event will be recognized upon return to the normal state. while in stop-grant state, the processor will process a system bus snoop. 7.2.4 halt/grant snoop state the processor will respond to snoop transactions on the system bus while in stop-grant state or in autohalt power down state. during a snoop transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). after the snoop is serviced, the processor will return to the stop-grant state or autohalt power down state, as appropriate. 7.2.5 sleep state the sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (pll), and has stopped all internal clocks. the sleep state can only be entered from stop-grant state. once in the stop-grant state, the processor will enter the sleep state upon the assertion of the slp# signal. the slp# pin should only be asserted when the processor is in the stop grant state. slp# assertions while the processor is not in the stop-grant state is out of specification and may result in unapproved operation. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behaviour. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp#, dpslp# or reset#) are allowed on the system bus while the processor is in sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behaviour. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, then the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after reset# is asserted to ensure the processor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering an even lower power state, the deep sleep state, by asserting the dpslp# pin. (see section 7.2.6 .) once in the sleep or deep sleep states, the slp# pin must be de-asserted if another asynchronous system bus event needs to occur. the slp# pin has a minimum assertion of one bclk period. when the processor is in sleep state, it will not respond to interrupts or snoop transactions.
92 251308-002 datasheet configuration and low power features 7.2.6 deep sleep state deep sleep state is a very low power state the processor can enter while maintaining context. deep sleep state is entered by asserting the dpslp# pin. the dpslp# pin must be de-asserted to re- enter the sleep state. a period of 30 microseconds (to allow for pll stabilization) must occur before the processor can be considered to be in the sleep state. once in the sleep state, the slp# pin can be deasserted to re-enter the stop-grant state. the clock may be stopped when the processor is in the deep sleep state in order to support the acpi s1 state. the clock may only be stopped after dpslp# is asserted and must be restarted before dpslp# is deasserted. to provide maximum power conservation when stopping the clock during deep sleep, hold the blck0 input at v ol and the bclk1 input at v oh . while in deep sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions of signals are allowed on the system bus while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behaviour.
251308-002 93 datasheet debug tools specifications 8 debug tools specifications please refer to the mobile intel ? pentium ? 4 processor-m and intel ? 845mp/845mz chipset platform design guide for information regarding debug tools specifications. 8.1 logic analyzer interface (lai) intel is working with two logic analyzer vendors to provide logic analyzer interfaces (lais) for use in debugging mobile intel celeron processor systems. tektronix* and agilent* should be contacted to get specific information about their logic analyzer interfaces. the following information is general in nature. specific information must be obtained from the logic analyzer vendor. due to the complexity of mobile intel celeron processor systems, the lai is critical in providing the ability to probe and capture system bus signals. there are two sets of considerations to keep in mind when designing a mobile intel celeron processor system that can make use of an lai: mechanical and electrical. 8.1.1 mechanical considerations the lai is installed between the processor socket and the mobile intel celeron processor. the lai pins plug into the socket, while the mobile intel celeron processor pins plug into a socket on the lai. cabling that is part of the lai egresses the system to allow an electrical connection between the mobile intel celeron processor and a logic analyzer. the maximum volume occupied by the lai, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. system designers must make sure that the keepout volume remains unobstructed inside the system. 8.1.2 electrical considerations the lai will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system. contact the logic analyzer vendor for electrical specifications and load models for the lai solution they provide.

▲Up To Search▲

Price & Availability of RH80532NC029256

	To Download RH80532NC029256 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .