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250 ksps, 12-bit impedance converter, network analyzer AD5934 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features programmable output peak-to-peak excitation voltage to a max frequency of 100 khz programmable frequency sweep capability with serial i 2 c? interface frequency resolution of 27 bits (<0.1 hz) impedance measurement range from 100 to 10 m phase measurement capability system accuracy of 0.5% 2.7 v to 5.5 v power supply operation temperature range ?40c to +125c 16-lead ssop package applications electrochemical analysis bioelectrical impedance analysis impedance spectroscopy complex impedance measurement corrosion monitoring and protection equipment biomedical and automotive sensors proximity sensing nondestructive testing material property analysis fuel/battery cell condition monitoring general description the AD5934 is a high precision impedance converter system solution which combines an on-board frequency generator with a 12-bit, 250 ksps, analog-to-digital converter (adc). the frequency generator allows an external complex impedance to be excited with a known frequency. the response signal from the impedance is sampled by the on-board adc and a discrete fourier transform (dft) is processed by an on-board dsp engine. the dft algorithm returns a real (r) and imaginary (i) data-word at each output frequency. the magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep is easily calculated using the following two equations: 22 ir magnitude += )/( 1 ritanphase ? = table 1. related devices part no. description ad5933 2.7 v to 5.5 v. 1 msps, 12-bit impedance, with internal temperature sensor, 16-lead ssop. functional block diagram adc (12 bits) vdd/2 dds core (27 bits) dac z( ) i 2 c interface imaginary register gain real register 1024-point dft lpf scl s d a dvdd avdd mclk agnd dgnd r out vout AD5934 rfb vin 05325-001 figure 1.
AD5934 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 specifications ..................................................................................... 3 i 2 c serial interface timing characteristics .................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and descriptions .............................................. 7 typical performance characteristics ............................................. 8 ter mi nolo g y .................................................................................... 10 system description ......................................................................... 11 transmit stage ............................................................................. 12 frequency sweep command sequence ................................... 13 receive stage ............................................................................... 13 dft operation ........................................................................... 13 impedance calculation .................................................................. 14 magnitude calculation .............................................................. 14 gain factor calculation ............................................................ 14 impedance calculation using gain factor ............................. 14 gain factor variation with frequency .................................... 14 two-point calibration ............................................................... 15 two-point gain factor calculation ......................................... 15 gain factor setup configuration ............................................. 15 gain factor recalculation ......................................................... 15 gain factor temperature variation......................................... 16 impedance error ........................................................................ 16 performing a frequency sweep .................................................... 18 register map ................................................................................... 19 control register ......................................................................... 19 start frequency register ........................................................... 20 frequency increment register .................................................. 20 number of increments register ............................................... 21 number of settling time cycles register ............................... 21 status register ............................................................................. 22 real and imaginary data registers (16 bits) .......................... 22 serial bus interface ......................................................................... 23 general i 2 c timing .................................................................... 23 writing/reading to the AD5934 .............................................. 24 block write .................................................................................. 24 AD5934 read operations ......................................................... 25 typical applications ....................................................................... 26 biomedical: noninvasive blood impedance measurement .. 26 sensor/complex impedance measurement ............................ 26 electro-impedance spectroscopy ............................................. 27 choosing a reference for the AD5934 ........................................ 28 layout and configuration ............................................................. 29 power supply bypassing and grounding ................................ 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 6/05revision 0: initial version
AD5934 rev. 0 | page 3 of 32 specifications test conditions unless otherwise stated: vdd = 3.3 v, mclk = 16.776 mhz, 2 v p-p output excitation voltage @ 30 khz, 200 k connected between pin 5 and pin 6. feedback resistor = 200 k connected between pin 4 and pin 5. pga gain = 1. table 2. y version 1 parameter min typ max unit test conditions/comments system impedance range 0.001 10 m total system accuracy 0.5 % system impedance error drift 30 ppm/c transmit stage output frequency range 2 1 100 khz output frequency resolution 0.1 hz <0.1 hz resolution achievable using dds techniques. mclk frequency 16.776 mhz max imum system clock frequency. transmit output voltage range 1 ac output excitation voltage 3 1.98 v p-p refer to figure 4 for output voltage distribution. dc bias 4 1.48 v dc bias of the ac excitation signal. see figure 5 . dc output impedance 200 t a = 25c. short-circuit current to ground at vout 5.8 ma t a = 25c. range 2 ac output excitation voltage 3 0.97 v p-p see figure 6 . dc bias 4 0.76 v dc bias of output excitation signal. see figure 7 . dc output impedance 2.4 k short-circuit current to ground at vout 0.25 ma range 3 ac output excitation voltage 3 0.383 v p-p see figure 8 . dc bias 4 0.31 v dc bias of output excitation signal. see figure 9 . dc output impedance 1 k short-circuit current to ground at vout 0.20 ma range 4 ac output excitation voltage 3 0.198 v p-p see figure 10 . dc bias 4 0.173 v dc bias of output excitation signal. see figure 11 . dc output impedance 600 short-circuit current to ground at vout 0.15 ma short-circuit current to ground 0.15 ma system ac characteristics signal-to-noise ratio 60 db total harmonic distortion ?52 db spurious-free dynamic range wide band (0 mhz to 1 mhz) ?56 db narrowband (5 khz) ?85 db
AD5934 rev. 0 | page 4 of 32 y version 1 parameter min typ max unit test conditions/comments receive stage input leakage current 1 na to vin pin. input capacitance 5 0.01 ff pin capacitance between vout and gnd. feedback capacitance c fb 3 pf feedback capacitance around current- to-voltage amplifier; appears in parallel with feedback resistor. analog-to-digital converter 5 resolution 12 bits sampling rate 250 ksps adc throughput rate. logic inputs input high voltage (v ih ) 0.7 vdd input low voltage (v il ) 0.3 vdd input current 6 1 a t a =25c. input capacitance 7 pf t a = 25c. power requirements vdd 2.7 5.5 v idd (normal mode ) 10 15 ma vdd = 3.3 v. 17 25 ma vdd = 5.5 v. idd (standby mode) 7 ma vdd = 3.3 v; see the control register section. 9 ma vdd = 5.5 v. idd (power-down mode) 0.7 5 a vdd = 3.3 v. 1 8 a vdd = 5.5 v. 1 temperature range for y version = ? 40c to +125c, typical at 25c. 2 the lower limit of the output excitation frequency ca n be lowered by scaling the clock supplied to the AD5934. 3 the peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the formula given below. vd d is the supply voltage. vdd voltage itation output exc = 3.3 2 p)-p(v 4 the dc bias value of the output excitation voltage scales with supply voltage according to the formula given below. vdd is the supply voltage. vdd voltage biasn excitatio output = 3.3 2 (v) 5 guaranteed by design or characterization, not production tested . input capacitance at the vout pin is equal to pin capacitance divided by open-loop gain of current- to-voltage amplifier. 6 the accumulation of the currents into pin 8, pin 15, and pin 16.
AD5934 rev. 0 | page 5 of 32 i 2 c serial interface timing characteristics vdd = 2.7 v to 5.5 v. all specifications t min to t max , unless otherwise noted. 1 table 3. parameter 2 limit at t min , t max unit description f scl 400 khz max scl clock frequency t 1 2. 5 s min scl cycle time t 2 0. 6 s min t high , scl high time t 3 1. 3 s min t low , scl low time t 4 0. 6 s min t hd , sta , start/repeated start condition hold time t 5 100 ns min t su , dat , data setup time t 6 3 0. 9 s max t hd , dat , data hold time 0 s min t hd , dat , data hold time t 7 0. 6 s min t su , sta , setup time for repeated start t 8 0. 6 s min t su , sto , stop condition setup time t 9 1. 3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t f , rise time of sda when transmitting 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 300 ns max t f , fall time of scl and sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 250 ns max t f , fall time of sda when receiving 20 + 0.1 c b 4 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line 1 see figure 2. 2 guaranteed by design and characterization, not production tested. 3 a master device must provide a hold time of at least 300 ns fo r the sda signal (referred to v ih min of the scl signal) in order to bridge the undefined scls falling edge. 4 c b is the total capacitance of one bus line in pf. note that t r and t f are measured between 0.3 vdd and 0.7 vdd. 05325-002 scl sda start condition repeated start condition stop condition t 9 t 3 t 10 t 11 t 4 t 4 t 6 t 2 t 5 t 7 t 8 t 1 figure 2. i 2 c interface timing diagram
AD5934 rev. 0 | page 6 of 32 absolute maximum ratings t a = 25c, unless otherwise note table 4. parameter rating dvdd to gnd ?0.3 v to + 7. 0 v avdd1 to gnd ?0.3 v to + 7. 0 v avdd2 to gnd ?0.3 v to + 7. 0 v sda/scl to gnd ?0.3 v to vdd + 0.3 v vout to gnd ?0.3 v to vdd + 0.3 v vin to gnd ?0.3 v to vdd + 0.3 v mclk to gnd ?0.3 v to vdd + 0.3 v operating temperature range extended industrial (y grade) ?40c to +125c storage temperature range ?65c to +160c maximum junction temperature 150c ssop package ja thermal impedance 139c/w jc thermal impedance 136c/w reflow soldering (pb-free) peak temperature 260c time at peak temperature 10 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD5934 rev. 0 | page 7 of 32 pin configuration and descriptions nc 1 nc 2 nc 3 rfb 4 scl 16 sda 15 agnd2 14 agnd1 13 vin 5 vout 6 nc 7 dgnd 12 avdd2 11 avdd1 10 mcl k 8 dvdd 9 nc = no connect AD5934 top view (not to scale) 05325-003 figure 3. pin configuration it is recommended to tie all supply connections (pin 9, pin 10, and pin 11) and run from a single supply between 2.7 v and 5.5 v. it is also recommended to connect all ground signals together (pin 12, pin 13, and pin 14). table 5. pin function descriptions pin no. mnemonic description/comment 1, 2, 3, 7 nc no connect. 4 rfb external feedback resistor. connected from pin 4 to pin 5 and used to set the gain of the current-to-voltage amplifier on the receive side. 5 vin input to receive transimpedance amplifier. presents a virtual earth voltage of vdd/2. 6 vout excitation voltage signal output. 8 mclk master clock for the system. supplied by user. 9 dvdd digital supply voltage. 10 avdd1 analog supply voltage 1. 11 avdd2 analog supply voltage 2. 12 dgnd digital ground. 13 agnd1 analog ground 1. 14 agnd2 analog ground 2. 15 sda i 2 c data input. 16 scl i 2 c clock input.
AD5934 rev. 0 | page 8 of 32 typical performance characteristics 35 0 number of devices 30 25 20 15 10 5 2.06 05325-064 voltage (v) 1.92 1.94 1.96 1.98 2.00 2.02 2.04 mean = 1.9824 sigma = 0.0072 figure 4. range 1: output excitation voltage distribution vdd = 3.3 v 1.30 1.75 05325-072 voltage (v) 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 mean = 1.4807 sigma = 0.0252 0 number of devices 30 25 20 15 10 5 figure 5. range 1: dc bias distribution vdd = 3.3 v 30 0 number of devices 25 20 15 10 5 05325-066 voltage (v) 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 mean = 0.9862 sigma = 0.0041 figure 6. range 2: output excitation voltage distribution vdd = 3.3 v 0.68 0.86 05325-073 voltage (v) 0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84 mean = 0.7543 sigma = 0.0099 30 0 number of devices 25 20 15 10 5 figure 7. range 2: dc bias distribution vdd = 3.3 v 30 0 0.370 0.400 05325-077 voltage (v) number of devices 25 20 15 10 5 0.375 0.380 0.385 0.390 0.395 mean = 0.3827 sigma = 0.00167 figure 8. range 3: output excitation voltage distribution vdd = 3.3 v 0.290 0.320 05325-074 voltage (v) 0.295 0.300 0.305 0.310 0.315 mean = 0.3092 sigma = 0.0014 30 0 number of devices 25 20 15 10 5 figure 9. range 3: dc bias distribution vdd = 3.3 v
AD5934 rev. 0 | page 9 of 32 05325-070 voltage (v) 0.192 0.194 0.196 0.198 0.200 0.202 0.204 0.206 mean = 0.1982 sigma = 0.0008 30 0 number of devices 25 20 15 10 5 figure 10. range 4: output excitation voltage distribution vdd = 3.3 v 0.160 0.205 05325-075 voltage (v) 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 mean = 0.1792 sigma = 0.0024 30 0 number of devices 25 20 15 10 5 figure 11. range 4: dc bias distribution vdd = 3.3 v 15.8 10.8 0 18 05325-088 mclk frequency (mhz) idd (ma) 15.3 14.8 14.3 13.8 13.3 12.8 12.3 11.8 11.3 avdd1, avdd2, dvdd connected together. output excitation frequency = 30khz rfb, z calibration = 100k 246810121416 figure 12. typical supply current vs. AD5934 clock frequency 0.4 ?1.0 0 400 05325-028 phase (degrees) phase error (degrees) 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 50 100 150 200 250 300 350 vdd = 3.3v t a = 25 c f = 32khz figure 13. typical AD5934 phase error
AD5934 rev. 0 | page 10 of 32 terminology tot a l sys te m ac c u r a c y the AD5934 can accurately measure a range of impedance values to less than 0.5% of the correct impedance value for supply voltages between 2.7 v to 5.5 v. spurious-free dynamic range (sfdr) along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a dds device. the spurious-free dynamic range refers to the largest spur or harmonic present in the band of interest. the wideband sfdr gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to nyquist bandwidth. the narrow-band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz, about the fundamental frequency. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental, where v1 is the rms amplitude of the fundamental and v2, v3, v4, v5, and v6 are the rms amplitudes of the second through the sixth harmonics. for the AD5934, thd is defined as 1 6 54 32 v vvvvv thd 2 2222 log20)db( ++++ =
AD5934 rev. 0 | page 11 of 32 system description adc (12 bits) vdd/2 dds core (27 bits) dac z( ) i 2 c interface imaginary register real register mac core (1024 dft) lpf scl sda mclk r out vout AD5934 rfb vin 05325-078 programmable gain amplifier x5 x1 windowing of data cos sin microcontroller mclk figure 14. AD5934 block overview the AD5934 is a high precision impedance converter system solution which combines an on-board frequency generator with a 12-bit, 250 ksps adc. the frequency generator allows an external complex impedance to be excited with a known frequency. the response signal from the impedance is sampled by the on-board adc and dft processed by an on-board dsp engine. the dft algorithm returns both a real (r) and imaginary (i) data-word at each frequency point along the sweep. the impedance magnitude and phase is easily calculated using the following equations: 22 ir magnitude += )/( 1 ritanphase ? = to characterize an impedance profile z( ), generally a frequency sweep is required like that shown in figure 15 . 05325-033 frequency impedance figure 15. the AD5934 permits the user to perform a frequency sweep with a user-defined start frequency, frequency resolution, and number of points in the sweep. in addition, the device allows the user to program the peak-to-peak value of the output sinusoidal signal as an excitation to the external unknown impedance connected between the vout and vin pins. table 6 gives the four possible output peak-to-peak voltages and the corresponding dc bias levels for each range. table 6. output excitation voltage amplitude output dc bias level range 1: 1.98 v p-p 1.48 v range 2: 0.99 v p-p 0.74v range 3: 383 mv p-p 0.31 v range 4: 198 mv p-p 0.179 v the excitation signal for the transmit stage is provided on-chip using dds techniques which permit subhertz resolution. the receive stage receives the input signal current from the unknown impedance, performs signal processing, and digitizes the result. the clock for the dds is generated from an external reference clock which is provided by the user at mclk.
AD5934 rev. 0 | page 12 of 32 transmit stage as shown in figure 16 , the transmit stage of the AD5934 is made up of a 27-bit phase accumulator dds core which provides the output excitation signal at a particular frequency. the input to the phase accumulator is taken from the contents of the start frequency register (see ram locations 82h, 83h, and 84h). although the phase accumulator offers 27 bits of resolution, the start frequency register has the 3 most significant bits (msbs) set to 0 internally; therefore the user has the ability to program only the lower 24 bits of the start frequency register. the AD5934 offers a frequency resolution programmable by the user down to 0.1 hz. the frequency resolution is programmed via a 24-bit word loaded serially over the i 2 c interface to the frequency increment register. the frequency sweep is fully described by the programming of three parameters: the start frequency, the frequency increment, and the number of increments. start frequency this is a 24-bit word that is programmed to the on-board ram at address 82h, address 83h, and address 84h (see the register map section). the required code loaded to the start frequency register is the result of the formula shown in equation 1, based on the master clock frequency and the required start frequency output from the dds. 27 2 16 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mclk frequency start output required code frequency start (1) for example, if the user requires the sweep to begin at 30 khz and has a 16 mhz clock signal connected to mclk. the code that needs to be programmed is given by l hexidecima 3d70a3 27 2 16 mhz16 khz30 ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? code frequency start the user programs 3d hex to register 82 h, 70 hex to register 83 h, and a3 hex to register 84 h. frequency increment this is a 24-bit word that is programmed to the on-board ram at address 85 h, address 86 h, and address 87 h (see the register map section). the required code loaded to the frequency increment register is the result of the formula shown in equation 2, based on the master clock frequency and the required increment frequency output from the dds. 27 2 16 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mclk increment frequency required code increment frequency (2) for example, if the user requires the sweep to have a resolution of 10 hz and has a 16 mhz clock signal connected to mclk, the code that needs to be programmed is given by lhexidecima 00053e 16 mhz16 hz10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = code increment frequency the user programs 00 hex to register 85 h, 05 hex to register 86 h, and finally 3e hex to register 87 h. number of increments this is a 9-bit word that represents the number of frequency points in the sweep. the number is programmed to the on-board ram at address 88 h and address 89 h (see the register map section). the maximum number of points that can be programmed is 511. for example, if the sweep needs 150 points, the user programs 00 hex to register 88 h and 96 hex to register 89 h. once the three parameter values have been programmed, the sweep is initiated by issuing a start frequency sweep command to the control register at address 80 h and address 81 h (see the register map section). bit 2 in the status register (register 8f h) indicates the completion of the frequency measurement for each sweep point. incrementing to the next frequency sweep point is under the control of the user. the measured result is stored in two registers (94 h, 95 h and 96 h, 97 h) which should be read before issuing an increment frequency command to the control register to move to the next sweep point. there is the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the control register . this has the benefit of allowing the user to average successive readings. when the frequency sweep has completed all frequency points, bit 3 in the status register is set, indicating completion of the sweep . once this bit is set further increments are disabled.
AD5934 rev. 0 | page 13 of 32 frequency sweep command sequence the following sequence must be followed to implement a frequency sweep. 1. enter standby mode. prior to issuing a start frequency sweep command, the device must be placed in a standby mode by issuing an enter standby mode command to the control register (register 80 h). in this mode, the vout and vin pins are connected internally to ground so there is no dc bias across the external impedance or between the impedance and ground. 2. enter initialize mode. in general, high q complex circuits require a long time to reach steady state. to facilitate the measurement of such impedances, this mode allows the user full control of the settling time requirement before entering start frequency sweep mode where the impedance measurement takes place. an initialize with start frequency command to the control register enters initialize mode. in this mode the impedance is excited with the programmed start frequency but no measurement takes place. the user times out the required settling time before issuing a start frequency sweep command to the control register to enter the start frequency sweep mode. 3. enter start frequency sweep mode. the user enters this mode by issuing a start frequency sweep command to the control register. in this mode, the adc starts measuring after the programmed number of settling time cycles has elapsed. the user can program an integer number of output frequency cycles (settling time cycles) to register 8a h and register 8b h before beginning the measurement at each frequency point (see figure 28 ). the dds output signal is passed through a programmable gain stage in order to generate the four ranges of peak-to-peak output excitation signals listed in table 6 . the peak-to-peak output excitation voltage is selected by setting bit d10 and bit d9 in the control registersee the control register section and is made available at the vout pin. phase accumulator (27 bits) vout dac r(gain) vbias 05325-034 figure 16. AD5934 transmit stage receive stage the receive stage comprises a currentCto-voltage amplifier, followed by a programmable gain amplifier (pga), antialiasing filter, and adc. the receive stage schematic is shown in figure 17 . the unknown impedance is connected between the vout and vin pins. the first stage current-to-voltage amplifier configuration means that a voltage present at the vin pin is a virtual ground with a dc value set at vdd/2. the signal current that is developed across the unknown impedance flows into the vin pin and develops a voltage signal at the output of the current- to-voltage converter. the gain of the current-to voltage amplifier is determined by a user-selectable feedback resistor connected between pins 4 (rfb) and pin 5 (vin). it is important for the user to choose a feedback resistance value which, in conjunction with the selected gain of the pga stage, maintains the signal within the linear range of the adc (0 v to vdd). the pga allows the user to gain the output of the current-to- voltage amplifier by a factor of 5 or 1 depending upon the status of bit d8 in the control register (see the register map section register 81h). the signal is then low-pass filtered and presented to the input of the 12-bit, 250 ksps adc. 05325-038 5 r r r r c v in vdd/2 rfb adc lpf figure 17. AD5934 receive stage the digital data from the adc is passed directly to the dsp core of the AD5934 which performs a dft on the sampled data. dft operation a dft is calculated for each frequency point in the sweep. the AD5934 dft algorithm is represented by () ))sin())(cos(()( 1023 0 njnnxfx n ? = = where x(f) is the power in the signal at the frequency point f, x(n) is the adc output, with the cos(n) and sin(n) the sampled test vectors provided by the dds core at the frequency f . the multiplication is accumulated over 1024 samples for each frequency point. the result is stored in two, 16-bit registers representing the real and imaginary components of the result. the data is stored in twos complement format.
AD5934 rev. 0 | page 14 of 32 impedance calculation magnitude calculation the first step in impedance calculation for each frequency point is to calculate the magnitude of the dft at that point. the dft magnitude is given by 22 ir magnitude += where r is the real number stored at register address 94 h and register address 95 h and i is the imaginary number stored at register address 96 h and register address 97 h. for example, assume the results in the real and imaginary registers are as follows at a frequency point: real register: = 038b hex = 907 decimal imaginary register: = 0204 hex = 516 decimal 1043.506)516 (907 22 =+= magnitude to convert this number into an impedance, it must be multiplied by a scaling factor called the gain factor. the gain factor is calculated during the calibration of the system with a known impedance connected between the vout and vin pins. once the gain factor has been calculated, it can be used in the calculation of any unknown impedance between the vout and vin pins. gain factor calculation an example of a gain factor calculation follows, with these assumptions: output excitation voltage = 2 v (p-p) calibration impedance value, z calibration = 200 k pga gain = 1 current to voltage amplifier gain resistor = 200 k calibration frequency = 30 khz then typical contents of the real and imaginary register after a frequency point conversion would be real register: = f9c hex = -3996 decimal imaginary register: = 227e hex = 8830 decimal 106.9692)8830(3996( 2 2 =+?= magnitude magnitude impedance 1 code admittance factor gain ? ? ? ? ? ? ? ? = ? ? ? ? ? ? = 12e819.515 106.9692 k 200 1 ? = ? ? ? ? ? ? ? ? ? ? ? ? = factor gain impedance calculation using gain factor the next example illustrates how the calculated gain factor derived previously is used to measure an unknown impedance. for this example, assume that the unknown impedance = 510 k. after measuring the unknown impedance at a frequency of 30 khz, assume that the real and imaginary registers contain the following data: real register: = 0aeb hex = ?1473 decimal imaginary register: = 0db3 hex = 3507 decimal 3802.863)(3507) 1473)(( 2 2 =+?= magnitude then the measured impedance at the frequency point is given by k 509.791 3802.863 12e 515.819273 1 1 = ? = = magnitude factor gain impedance gain factor variation with frequency because the AD5934 has a finite frequency response, the gain factor also shows a variation with frequency. this results in an error in the impedance calculation over a frequency range. figure 18 shows an impedance profile based on a single-point gain factor calculation. to minimize this error, the frequency sweep should be limited to as small a frequency range as possible. 101.5 98.5 54 66 05325-085 frequency (khz) impedance (k ) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 vdd = 3.3v calibration frequency = 60khz t a = 25 c measured calibration impedance = 100k figure 18. impedance profile using a single-point gain factor calculation
AD5934 rev. 0 | page 15 of 32 two-point calibration alternatively it is possible to minimize this error by assuming that the frequency variation is linear and adjusting the gain factor with a 2-point calibration. figure 19 shows an impedance profile based on a 2-point gain factor calculation. 101.5 98.5 54 66 05325-086 frequency (khz) impedance (k ) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 vdd = 3.3v calibration frequency = 60khz t a = 25 c measured calibration impedance = 100k figure 19. impedance profile using a 2-point gain factor calculation two-point gain factor calculation this is an example of a 2-point gain factor calculation assuming the following: output excitation voltage = 2 v (p-p) calibration impedance value, z unknown = 100.0 k pga gain = 1 supply voltage = 3.3 v current to voltage amplifier gain resistor = 100 k calibration frequencies at = 55 khz and 65 khz typical values of the gain factor calculated at the two calibration frequencies read gain factor calculated at 55 khz = 1.031224e-09 gain factor calculated at 65 khz = 1.035682e-09 difference in gain fact or (gf) = 1.035682e-09 ? 1.031224e-09 = 4.458000e-12 frequency span of sweep (f) = 10 khz therefore the gain factor required at 60 khz is given by 09-1.031224e khz 5 khz 10 12-4.458000e + ? ? ? ? ? ? required gain factor = 1.033453e-9 the impedance is calculated as previously described in the impedance calculation section. gain factor setup configuration when calculating the gain factor, it is important that the receive stage is operating in its linear region. this requires careful selection of the excitation signal range, current-to-voltage gain resistor and pga gain. the gain through the system shown in figure 20 is given by gainpga z resistor setting gain range voltage excitation output unknown 05325-089 vin vdd rfb adc lpf z unknown vout current to voltage gain setting resistor pga (x1 or x5) figure 20. AD5934 system voltage gain for this example, assume the following system settings: vdd = 3.3 v gain setting resistor = 200 k z unknown = 200 k pga setting = 1 the peak-to-peak voltage presented to the adc input is 2 v p-p. however had the user chosen a pga gain of 5, the voltage would saturate the adc. gain factor recalculation the gain factor must be recalculated for a change in any of the following parameters: ? current-to-voltage gain setting resistor ? output excitation voltage ? pga gain
AD5934 rev. 0 | page 16 of 32 gain factor temperature variation the typical impedance error variation with temperature is in the order of 30 ppm/c. figure 21 shows an impedance profile with a variation in temperature for 100 k impedance using a 2-point gain factor calibration. 101.5 98.5 54 66 05325-087 frequency (khz) impedance (k ) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 +125 c +25 c ?40 c vdd = 3.3v calibration frequency = 60khz measured calibration impedance = 100k figure 21. impedance profile variation with temperature using a 2-point gain factor calculation impedance error minimizing the impedance range under test optimizes the AD5934 measurement performance. below are examples of the AD5934 performance when operating in the six different impedance ranges. the gain factor is calculated with a precision resistor in each case. range 1 (0.1 k to 1 k) output excitation voltage = 2 v p-p calibration impedance value, z calibration = 100 pga gain = 1 supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 100 7 0 10 05325-079 frequency (khz) % impedance error 6 5 4 3 2 1 35 60 100 rfb = 0.1k calibration impedance = 0.1k t a = 25 c 0.5k 1k figure 22. range 1: typical % impedance error over frequency range 2 (1 k to 10 k) output excitation voltage = 2 v p-p calibration impedance value, z calibration = 1 k pga gain = 1 supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 1 k 2.0 0 10 05325-080 frequency (khz) % impedance error 35 60 100 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 rfb = 1k calibration impedance = 1k t a = 25 c 5k 10k figure 23. range 2: typical % impedance error over frequency range 3 (10 k to 100 k) output excitation voltage = 2 v p-p calibration impedance value, z calibration = 10 k pga gain = 1 supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 10 k 0.3 ?0.3 10 05325-081 frequency (khz) % impedance error 35 60 100 0.2 0.1 0 ?0.1 ?0.2 rfb = 10k calibration impedance = 10k t a = 25 c 50k 100k figure 24. range 3: typical % impedance error over frequency
AD5934 rev. 0 | page 17 of 32 range 4 (100 k to 1 m) output excitation voltage = 2 v p-p calibration impedance value, z calibration = 100 k pga gain = 1 supply voltage = 3.3 v current-to-voltage amplifier gain resistor = 100 k 1.0 ?3.5 10 05325-082 frequency (khz) % impedance error 35 60 100 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 500k 1m rfb = 100k calibration impedance = 100k t a = 25 c figure 25. range 4: typical % impedance error over frequency range 5 (1 m to 2 m) output excitation voltage = 2 v p-p calibration impedance value, z calibration = 100 k pga gain = 1 supply voltage = 3.3 v current to voltage amplifier gain resistor = 100 k 3 ?9 10 05325-083 frequency (khz) % impedance error 35 60 100 1 ?1 ?3 ?5 ?7 rfb = 1m calibration impedance = 1m t a = 25 c 1.5m 2m figure 26. range 5: typical % impedance error over frequency range 6 (9 m to 10 m) output excitation voltage = 2 v p-p calibration impedance value, z calibration = 9 m pga gain = 1 supply voltage = 3.3 v current to voltage amplifier gain resistor = 9 m 4 ?10 10 05325-084 frequency (khz) % impedance error 2 0 ?2 ?4 ?6 ?8 35 60 100 rfb = 10m calibration impedance = 10m t a = 25 c 9.5m 10m figure 27. range 6: typical % impedance error over frequency
AD5934 rev. 0 | page 18 of 32 performing a frequency sweep 05325-047 program the AD5934 into power-down mode. place the AD5934 into standby mode. program frequency sweep parameters into relevant registers (1) start frequency register (2) number of increments register (3) frequency increment register read values from real and imaginary data register. program initialize with start frequency command to the control register. program start frequency sweep command in the control register, after a sufficient amount of settling time has elapsed. poll status register to check if the dft conversion is complete. reset: by issuing a reset command to control register the device is placed in standby mode. program the increment frequency or the repeat frequency command to the control register. y y y n n poll status register to check if frequency sweep is complete. figure 28. frequency sweep flow chart
AD5934 rev. 0 | page 19 of 32 register map table 7. register name register address register data read/write register control 80 h d15 to d8 read/write 81 h d7 to d0 read/write start frequency 82 h d23 to d16 read/write 83 h d15 to d8 read/write 84 h d7 to d0 read/write frequency increment 85 h d23 to d16 read/write 86 h d15 to d8 read/write 87 h d7 to d0 read/write number of increments 88 h d15 to d8 read/write 89 h d7 to d0 read/write number of settling time cycles 8a h d15 to d8 read/write 8b h d7 to d0 read/write status 8f h d7 to d0 read only real data 94 h d15 to d8 read only 95 h d7 to d0 read only imaginary data 96 h d15 to d8 read only 97 h d7 to d0 read only control register table 8. 16-bit register 80 h d15 to d8 read or write 81 h d7 to d0 read or write the control register is a 16-bit register that sets the AD5934 control modes. the 4 msbs of the control register are decoded to provide control functions, such as performing a frequency sweep, powering down the part, and various other control functions defined in the control register map. the user may choose to write only to register location 80 h and not to alter the contents of 81 h. note that the control register should not be written to as part of a block write command. the control register also allows the user to program the excitation voltage and set the system clock. a reset command to the control register does not reset any programmed values associated with the sweep (that is, start frequency, number of increments, frequency increment). after a reset command, an initialize with start frequency command must be issued to the control register to restart the frequency sweep sequence (see figure 28 ). default value upon reset: d15 to d0 reset to a0 00h upon power-up. the AD5934 contains a 16-bit control register (address 80h and 81h) that sets the AD5934 control modes. table 9. control register map bit d15 d14 d13 d12 0 0 0 0 no operation 0 0 0 1 initialize with start frequency 0 0 1 0 start frequency sweep 0 0 1 1 increment frequency 0 1 0 0 repeat frequency 1 0 0 0 no operation 1 0 0 1 no operation 1 0 1 0 power down mode 1 0 1 1 standby mode 1 1 0 0 no operation 1 1 0 1 no operation d11 no operation d10 d9 output voltage range 0 0 range 1 ( 2.0 v p-p typ) 0 1 range 3 (200 mv p-p typ) 1 0 range 4 (400 mv p-p typ) 1 1 range 2 (1.0 v p-p typ) d8 pga gain 0 = 5, 1 = 1 d7 reserved. set to 0. d6 reserved. set to 0. d5 reserved. set to 0. d4 reset d3 1 external system clock. must be set to 1. d2 0 must be set to 0. d1 reserved. set to 0. d0 reserved. set to 0.
AD5934 rev. 0 | page 20 of 32 control register decode initialize with start frequency this command enables the dds to output the programmed start frequency for an indefinite time. it is used is to excite the unknown impedance initially. when the output unknown impedance has settled after a time determined by the user, the user must initiate a start frequency sweep command to begin the frequency sweep. start frequency sweep in this mode the adc starts measuring after the programmed number of settling time cycles has elapsed. the user has the ability to program an integer number of output frequency cycles (settling time cycles) to register 8a h and register 8b h before the commencement of the measurement at each frequency point. see figure 28 . increment frequency the increment frequency command is used to step to the next frequency point in the sweep. this usually happens after data from the previous step has been transferred and verified by the dsp. when the AD5934 receives this command, it waits for the programmed number of settling time cycles before beginning the adc conversion process. repeat frequency there is the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the control register . this has the benefit of allowing the user to average successive readings. power-down the default state on power-up of the AD5934 is power-down mode. the control register contains the code 1010000000000000 (a000h). in this mode both the output and input vout and vin pins are connected internally to gnd. standby mode powers up the part for general operation; in standby mode the vin and vout pins are internally connected to ground. reset a reset command allows the user to interrupt a sweep. the start frequency, number of increments, and frequency increment register contents are not overwritten. an initialize with start frequency command is required to restart the frequency sweep command sequence. output voltage range this allows the user to program the excitation voltage range at vout. pga gain this allows the user to amplify the response signal into the adc by a multiplication factor of 5 or 1. start frequency register table 10. 24-bit register 82 h d23 to d16 read or write 83 h d15 to d8 read or write 84 h d7 to d0 read or write the start frequency register contains the 24-bit digital representation of the frequency from where the subsequent frequency sweep is initiated. for example, if the user requires the sweep to start from frequency 30 khz (using a 16.00 mhz clock), then the user programs 3d hex to register location 82 h, 70 hex to register location 83h, and a3 hex to register location 84 h. this ensures the output frequency starts at 30 khz. the code to be programmed to the start frequency register is lhexidecima 3d70a3 2 16 mhz16 khz30 27 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = code frequency start default value upon reset: d23 to d0 are not reset on power-up. after a reset command the contents of this register are not reset. frequency increment register table 11. 85 h d23 to d16 read or write 86 h d15 to d8 read or write 87 h d7 to d0 read or write the frequency increment register contains a 24-bit representation of the frequency increment between consecutive frequency points along the sweep. for example, if the user requires an increment step of 30 hz using a 16.0 mhz clock, the user should program 00 hex to register location 85 h, 0f hex to register location 86 h and ba hex to register location 87 h. the formula for calculating the increment frequency is given by lhexidecima 00053e 2 16 mhz16 hz10 27 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = code increment frequency the user programs 00 hex to register 85 h, 05 hex to register 86 h, and 3e hex to register 87 h. default value upon reset: d23 to d0 are not reset on power-up. after a reset command, the contents of this register are not reset.
AD5934 rev. 0 | page 21 of 32 number of increments register table 12. 16-bit register bits d15 to d9 = dont care 88 h d15 to d8 read or write bits d8 to d0 = number of frequency increments 89 h d7 to d0 read or write integer number stored in binary format this register determines the number of frequency points in the frequency sweep. the number of points is represented by a 9-bit word, d8 to d0. d9 to d15 are dont care bits. this register in conjunction with the start frequency register and the increment frequency registers determine the frequency sweep range for the sweep operation. the maximum number of increments which can be programmed is 511. default value upon reset: d8 to d0 are not reset on power-up. after a reset command, the contents of this register are not rese t. number of settling time cycles register table 13. 16-bit register d15 to d11 = dont care d10 to d9 = 2-bit decode d8 = msb number of settling time cycles d10 d9 0 0 default 0 1 number cycles 2 1 0 reserved 1 1 number cycles 4 8a h d15 to d8 read or write integer number stored in binary format number of settling time cycles 8b h d7 to d0 read or write this register determines the number of output excitation cycles that are allowed to pass through the unknown impedance, after r eceipt of a start, increment, or repeat frequency command, before the adc is triggered to perform a conversion of the response signal. th e settling time cycles register value determines the delay between a frequency start/increment/repeat command and the time an adc conversion commences. the number of cycles is represented by a 9-bit word, d8 to d0. the value programmed into the settling time cycles register can be increased by a factor of 2 or 4 depending upon the status of bits d10 to d9. the 5 most significant bits, d15 to d11, are dont care bits. the maximum number of output cycles that can be programmed is 511 4 = 2044 cycles. for examp le, consider an excitation signal of 30 khz. the maximum delay between the programming of this frequency and the time that this sig nal is first sampled by the adc is 511 4 33.33 s = 68.126 ms. the adc takes 1024 samples, and the result is stored as real and imaginary data in register 94 h to register 97 h. the conversion process takes approximately 1 ms using a 16.777 mhz clock. default value upon reset: d10 to d0 are not reset on power-up. after a reset command, the contents of this register are not res et.
AD5934 rev. 0 | page 22 of 32 status register table 14. 8-bit register 8f h d7 to d0 read only bits the status register is used to confirm that particular measurement tests have been successfully completed. each of the bits from d7 to d0 indicates the status of specific functionality of the AD5934. d0, and bit d4 to bit d7 are treated as dont care bits, these bits do not indicate the status of any measurement the status of bit d1 indicates the status of a frequency point impedance measurement. this bit is set when the AD5934 has completed the current frequency point impedance measurement. this indicates that there is valid real and imaginary data in register 93 h to register 97 h. this bit is reset on receipt of a start, increment, repeat frequency, or reset command. this bit is also reset on power-up. the status of bit d2 indicates the status of the programmed frequency sweep. this bit is set when all programmed increments to the number of increments register are complete. this bit is reset on power-up and on receipt of a reset command. table 15. status register status register address control word function 8f h 0000 0001 reserved 8f h 0000 0010 valid real/imaginary data 8f h 0000 0100 frequency sweep complete 8f h 0000 1000 reserved 8f h 0001 0000 reserved 8f h 0010 0000 reserved 8f h 0100 0000 reserved 8f h 1000 0000 reserved valid real/imaginary data set when data processing for the current frequency point is finished, indicating real/imaginary data available for reading. reset when a dds start/increment/repeat command is issued. also this bit is reset to 0 when a reset command is issued to the control register. frequency sweep complete set when data processing for the last frequency point in the sweep is complete. reset when a start frequency sweep command is issued to the control register. this bit is also reset when a reset command is issued to the control register. real and imaginary data registers (16 bits) table 16. real data 94 h d15 to d8 read only 95 h d7 to d0 read only twos complement data table 17. imaginary data 96 h d15 to d8 read only 97 h d7 to d0 read only twos complement data these registers contain a digital representation of the real and imaginary components of the impedance measured for the current frequency point. the values are stored in 16-bit, twos complement format. to convert this number to an actual impedance value, the magnitude )imaginary and(real 2 2 must be multiplied by an admittance/code number (called a gain factor) to give the admittance, and the result inverted to give impedance. the gain factor varies for each ac excitation voltage/gain combination. default value upon reset: these registers are not reset on power-up or on receipt of a reset command. note that the data in these registers is only valid if bit d1 in the status register is set, indicating that the processing at the current frequency point is complete.
AD5934 rev. 0 | page 23 of 32 serial bus interface control of the AD5934 is carried out via the 1 2 c-compliant serial interface protocol. the AD5934 is connected to this bus as a slave device under the control of a master device. the AD5934 has a 7-bit serial bus slave address. when the device is powered up, it has a default serial bus address, 0001101 (0d hex) general i 2 c timing the general i 2 c protocol operates as described in this section. figure 29 shows the timing diagram for general read and write operations using the i 2 c-compliant interface. the master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line (sda) while the serial clock line (scl) remains high. this indicates that a data stream follows. the slave responds to the start condition and shifts in the next 8 bits, consisting of a 7-bit slave address (msb first) plus an r/w bit, which determines the direction of the data transferthat is, whether data is written to or read from the slave device (0 = write, 1 = read). the slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is 0, then the master writes to the slave device. if the r/w bit is 1, the master reads from the slave device. data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit, which can be from the master or slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it may be an instruction telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. because data can flow in only one direction as defined by the r/w bit, it is not possible to send a command to a slave device during a read operation. before performing a read operation, it is sometimes necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device releases the sda line during the low period before the ninth clock pulse, but the slave device does not pull it low. this is known as a no acknowledge (nack). the master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. 0001101 r/w d7 d6 d5 d4 d3 d2 d1 d0 start cond by master ack. by AD5934 slave address byte ack. by master/slave scl sda register address 05325-048 figure 29.
AD5934 rev. 0 | page 24 of 32 writing/reading to the AD5934 the interface specification defines several different protocols for different types of read and write operations. this section describes the protocols used in the AD5934. the figures in this section use the following abbreviations: s start p stop r read w write a acknowledge a no acknowledge write byte/command byte user command codes the command codes in tabl e 1 8 are used for reading/writing to the interface. they are further explained in this section, but are grouped here for easy reference. table 18. command code code name code description 1010 0000 block write this command is used when writing multiple bytes to the ram. see the block write section. 1010 0001 block read this command is used when reading multiple bytes from ram/memory. see the block read section. 1011 0000 address pointer this command enables the user to set the address pointer to any location in the memory. the data contains the address of the register where the pointer should be pointing. write byte/command byte in this operation the master device sends a byte of data to the slave device. the write byte can either be a data byte write to a ram location or can be a command operation. to write data to a register the command sequence is as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a register address. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda to end the transaction. s slave address register address register data aw a a p 05325-049 figure 30. writing register data to register address in the AD5934, the write byte protocol is also used to set a pointer to a register location. this is used for a subsequent single-byte read from the same address or block read or write starting at that address. to set a register pointer, the following sequence is applied: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a pointer command code (see table 18 , a pointer command = 1011 0000). 5. the slave asserts ack on sda. 6. the master sends a data byte (a register location where pointer is to point). 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda to end the transaction. s aw a a p pointer command 1011 0000 slave address register location to point to 05325-050 figure 31. setting pointer to register address block write in this operation, the master device writes a block of data to a slave device. the start address for a block write must previously have been set. in the case of the AD5934 this is done by setting a pointer to set the register address. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends an 8-bit command code (1010 0000) that tells the slave device to expect a block write. 5. the slave asserts ack on sda. 6. the master sends a data byte that tells the slave device the number of data bytes to be sent to it. 7. the slave asserts ack on sda. 8. the master sends the data bytes. 9. the slave asserts ack on sda after each data byte. 10. the master asserts a stop condition on sda to end the transaction. aa a a sw a p slave address block write number bytes write byte 0 byte 1 byte 2 05325-051 a figure 32. writing a block write
AD5934 rev. 0 | page 25 of 32 AD5934 read operations the AD5934 uses the following i 2 c read protocols: receive byte in the AD5934, the receive byte protocol is used to read a single byte of data from a register location whose address has previously been set by setting the address pointer. in this operation, the master device receives a single byte from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master asserts nack on sda (slave needs to check that master has received data). 6. the master asserts a stop condition on sda and the transaction ends. sr a a slave address register data 05325-052 p figure 33. reading register data block read in this operation, the master device reads a block of data from a slave device. the start address for a block read must previously have been set by setting a pointer. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code (1010 0001) that tells the slave device to expect a block read. 5. the slave asserts ack on sda. 6. the master sends a byte count data byte that tells the slave how many data bytes to expect. 7. the slave asserts ack on sda. 8. the master asserts a repeat start condition on sda. this is required to set the read bit high. 9. the master sends the 7-bit slave address followed by the read bit (high). 10. the slave asserts ack on sda. 11. the master receives the data bytes. 12. the master asserts ack on sda after each data byte. 13. a nack is generated after the last byte to signal the end of the read. 14. the master asserts a stop condition on sda to end the transaction. number bytes read s slave address wa block read aa slave address r a byte 0 a byte 1 a byte 2 a p 05325-053 s figure 34. performing a block read
AD5934 rev. 0 | page 26 of 32 typical applications this section describes typical applications for the AD5934. biomedical: noninvasive blood impedance measurement when a known strain of a virus is added to a blood sample that already contains a virus, a chemical reaction takes place whereby the impedance of the blood under certain conditions changes. by characterizing th is effect across different frequencies it is possible to detect a specific strain of virus. for example, a strain of the disease exhibits a certain characteristic impedance at one frequency but not at another, therefore the requirement to sweep different frequencies to check for different viruses. th e AD5934, with its 27-bit phase accumulator, allows for sub-hz frequency tuning. the AD5934 can be used to inject a stimulus signal through the blood sample via a probe. the response signal is analyzed and the effective impedance of the blood is tabulated. the AD5934 is ideal for this application because it allows the user to tune to the specific frequency required for each test. probe 2 6 4 adr43x AD5934 top view (not to scale) 10 f 0.1 f 7v aduc702x top view (not to scale) 1 16 2 15 3 14 4 13 5 6 11 7 10 8 9 rfb 12 05325-057 figure 35. measuring a blood sample for a strain of virus sensor/complex impedance measurement the operational principle of a capacitive proximity sensor is based on the change of a capacitance in a rlc resonant circuit. this leads to changes in the resonant frequency of the rlc circuit, which can be evaluated as shown figure 36 . it is first required to tune the rlc circuit to the area of resonance. at the resonant frequency, the impedance of the rlc circuit is at a maximum. therefore, a programmable frequency sweep and tuning capability is required, which is provided by the AD5934. 05325-058 frequency (hz) proximity impedance ( ) resonant frequency change in resonance due to approaching object f o figure 36. detecting a change in resonant frequency an example of the use of this type of sensor is for a train proximity measurement system. the magnetic fields of the train approaching on the track change the resonant frequency to an extent that can be characterized. this information can be sent back to a mainframe system to show the train location on the network. another application for the AD5934 is in parked vehicle detection. the AD5934 is placed in an embedded unit connected to a coil of wire underneath the parking location. the AD5934 outputs a single frequency within the 80 khz to 100 khz frequency range, depending upon the wire composition. the wire can be modeled as a resonant circuit. the coil is calibrated with a known impedance value and at a known frequency. the impedance of the loop is monitored constantly. if a car is parked over the coil, the impedance of the coil changes and the AD5934 detects the presence of the car.
AD5934 rev. 0 | page 27 of 32 electro-impedance spectroscopy the AD5934 has found use in the area of corrosion monitoring. corrosion in a metal such as aluminum, which is used in air craft and ships, requires continuous assessment because the metal is exposed to a wide variety of conditions such as temper- ature and moisture. the AD5934 offers an accurate and compact solution for this type of measurement compared to the large and expensive existing units on the market. mathematically the corrosion of a metal is modeled using a rc network which consists of a resistance,rs, in series with a parallel resistor and capacitor, rp and cp. a system metal would typically have values as follows: rs 10 to 10 k, rp 1 k to 1 m, and cp 5 f to 70 f. the frequency range of interest when monitoring corrosion is 0.1 hz to 100 khz. to ensure that the measurement itself does not introduce a corrosive effect, the metal needs to be excited with minimal voltage, typically in the 200 mv region which the AD5934 is capable of outputting. a nearby processor or control unit like the aduc702x would log a single impedance sweep from 0.1 khz to 100 khz every 10 minutes and download the results back to a control unit. in order to achieve system accuracy from the 0.1 khz to 1 khz region, the system clock needs to be scaled down from the 16.776 mhz nominal clock frequency to 500 khz, typically. the clock scaling can be achieved digitally using an external direct digital synthesizer like the ad9834 as a programmable divider, which supplies a clock signal to mclk and which can be controlled digitally by the nearby microprocessor.
AD5934 rev. 0 | page 28 of 32 choosing a reference for the AD5934 to achieve the best performance from the AD5934, thought should be given to the choice of a precision voltage reference. the AD5934 has three reference inputs: (avdd1, avdd2, and dvdd). it is recommended that the voltage on these reference inputs be run from the same voltage supply. there are four possible sources of error that should be considered when choosing a voltage reference for high accuracy applications: initial accuracy, ppm drift, long-term drift, and output voltage noise. to minimize these errors, a reference with high initial accuracy is preferred. also, choosing a reference with an output trim adjustment, such as a device in the adr43x family, allows a system designer to trim system errors by setting a reference voltage to a voltage other than the nominal. the trim adjustment can also be used at temperature to trim out any error. because the supply current required by the AD5934 is extremely low, the parts are ideal for low supply applications. the adr395 voltage reference is recommended in this case. this requires less than 100 a of quiescent current. it also provides very good noise performance at 8 v p-p in the 0.1 hz to 10 hz range. long-term drift is a measure of how much the reference drifts over time. a reference with a tight long-term drift specification ensures that the overall solution remains stable during its entire lifetime. a reference with a tight temperature coefficient specification should be chosen to reduce temperature dependence of the system output voltage on ambient conditions. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. choosing a reference with as low an output noise voltage as practical for the system noise resolution required is important. precision voltage references such as the adr433 produce low output noise in the 0.1 hz to 10 hz region. examples of some recommended precision references for use as supply to the AD5934 are shown in table 19 . table 19. list of precision references for theAD5934 part no. initial accuracy (mv max) output voltage (v) temp . drift (ppm/c max) 0.1 hz to 10 hz noise (v p-p typ) adr433b 1.4 3. 0 3 3.75 adr433a 4.0 3. 0 10 3.75 adr434b 1.5 4. 096 3 6.25 adr434a 5 4. 096 10 6.25 adr435b 2 5.0 3 8 adr435a 6 5.0 10 8 adr439b 2 4.5 3 7.5 adr439a 5.4 4.5 10 7.5
AD5934 rev. 0 | page 29 of 32 layout and configuration power supply bypassing and grounding when accuracy is important in a circuit, carefully consider the power supply and ground return layout on the board. the printed circuit board containing the AD5934 should have separate analog and digital sections, each having its own area of the board. if the AD5934 is in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the AD5934. the power supply to the AD5934 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi); common ceramic types of capacitors are suitable. the 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
AD5934 rev. 0 | page 30 of 32 outline dimensions 16 9 8 1 6.50 6.20 5.90 8.20 7.80 7.40 seating plane 0.05 min 0.65 bsc 2.00 max 0.25 0.09 0.95 0.75 0.55 0.38 0.22 5.60 5.30 5.00 coplanarity 0.10 8 4 0 1.85 1.75 1.65 pin 1 compliant to jedec standards mo-150-ac figure 37. 16-lead shrink small outline package [ssop] (rs-16) dimensions shown in millimeters ordering guide model temperature range package description package option AD5934yrsz 1 ?40c to +125c 16-lead shrink small outline package (ssop) rs-16 AD5934yrsz-reel7 1 ?40c to +125c 16-lead shrink small outline package (ssop) rs-16 eval-AD5934eb ?40c to +125c evaluation board 1 z = pb-free part.
AD5934 rev. 0 | page 31 of 32 notes
AD5934 rev. 0 | page 32 of 32 t notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05325C0C6/05(0) ttt

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