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256kx18, sync lw, hstl, rev 4.6 1 / 27 august 20, 1998 cxk77b1840gb sony 4a/4/45a/45 4mb late write hstl high speed synchronous sram (256k x 18 organization) description features r-r mode r-l, r-ft modes **dc mode ** ? fast cycle/access time t khkh / t khqv t khkh / t khqv t khkh / t khqv cxk77b1840 -4a 4.0ns / 2.3ns 4.8ns / 4.8ns 4.0ns / 5.2ns -4 4.0ns / 2.3ns 5.3ns / 5.3ns 4.0ns / 5.2ns -45a 4.0ns / 2.3ns 5.3ns / 5.3ns 4.5ns / 6.0ns -45 5.0ns / 2.5ns 6.5ns / 6.5ns 4.5ns / 6.5ns note: contact sony memory marketing for availability of dc mode functionality. ? 4 synchronous modes of operation, selectable by mode pins: register-register; register-latch; register-flow thru; dual clock ? single +3.3v power supply: 3.3v 5% ? dedicated output supply voltage: v ddq (1.5v typical) ? inputs and outputs are hstl / extended hstl compatible. ? differential clock input (k/k , c/c ). ? all inputs (except asynchronous g and zz) and outputs are registered on a single clock edge. ? byte write capability. ? late write scheme to eliminate one dead cycle from read-to-write transitions. ? self-timed write cycles. ? sleep (power down) mode. ? jtag boundary scan (subset of ieee standard 1149.1). ? 119 pin (7x17) plastic ball grid array (pbga) package. the cxk77b1840 is a high speed bicmos synchronous static ram with common i/o pins, organized as 262,144-words by 18-bits. this synchronous sram integrates input registers, high speed ram, output registers/latches, and a one-deep write buffer onto a single monolithic ic. four different read protocols - register-register (r-r), register-latch (r-l), register-flo w thru (r-ft), and dual clock (dc), and an enhanced write protocol - late (delayed) write (lw), are supported, providing a flexible, high-performance user interface. all input signals except g (output enable) and zz (sleep mode) are registered on the positive edge of k clock. read cycles can be controlled in one of four ways - with registered outputs in register-register mode, with latched outputs in register-latch mode, with flow-through outputs in register-flow thru mode, or with registered outputs using a dedicated out- put control clock (c clock) in dual clock mode. the read protocol is user-selectable through external mode pins m1 and m2. write cycles follow a late write protocol, where data is provided to the sram one clock cycle after the address and control signals, eliminating one dead cycle from read-to-write transitions. in this scheme, when a write cycle is initiated, the addres s and data stored in the srams write buffer during the previous write cycle are directed to the srams memory core, while, simultaneously, the address and data from the current write cycle are stored in the srams write buffer. in both register-latch and register-flow thru modes, when sw (global write enable) is driven active, the subsequent positive edge of k clock tri- states the srams output drivers immediately, allowing consecutive read-write-read operations. the write cycle is internally self-timed, which eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. the output drivers are series terminated, and the output impedance is programmable through an external impedance matching resistor rq. by connecting rq between zq and v ss , the output impedance of all 18 dq pins can be precisely controlled. sleep (power down) mode control is provided through the asynchronous zz input. 250 mhz operation is obtained from a single 3.3v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol.
256kx18, sync lw, hstl, rev 4.6 2 / 27 august 20, 1998 sony ? cxk77b1840gb pin configuration (top view) pin description 1234567 a v ddq sa6 sa7 nc sa3 sa2 v ddq b nc nc sa8 nc sa4 nc nc c nc sa12 sa5 v dd sa0 sa13 nc d dq0b nc v ss zq v ss dq8a nc e nc dq1b v ss ss v ss nc dq7a f v ddq nc v ss g v ss dq6a v ddq g nc dq2b sbw bc v ss nc dq5a h dq3b nc v ss cv ss dq4a nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dq4b v ss kv ss nc dq3a l dq5b nc v ss k sbw adq2a nc m v ddq dq6b v ss sw v ss nc v ddq n dq7b nc v ss sa14 v ss dq1a nc p nc dq8b v ss sa11 v ss nc dq0a r nc sa10 m1 v dd m2 sa15 nc t nc sa17 sa9 nc sa1 sa16 zz u v ddq tms tdi tck tdo nc v ddq symbol description symbol description symbol description sa address input (0-17) g async. output enable v ddq output power supply dq data i/o (0-8), bytes a,b zz async. sleep mode v ss ground k,k differential input clocks tck jtag clock (lvttl) v ref input reference voltage c,c differential output control clocks tms jtag mode select (lvttl) zq output impedance control resistor input sw write enable, global tdi jtag data in (lvttl) m1,m2 mode select sbw x write enable, bytes a,b tdo jtag data out (lvttl) nc no connect ss synchronous select v dd +3.3v power supply
256kx18, sync lw, hstl, rev 4.6 3 / 27 august 20, 1998 sony ? cxk77b1840gb add. write pulse 256k x 18 dout din 2:1 mux output latch reg. 2:1 mux input reg. write store reg. read comp. reg. reg. reg. self time write logic output clock mode control sa 0-17 ss sw sbw a-d 4 18 k/k m1 m2 g dq ^ ^ ^ ^ block diagram clock input 2 kint kint kint kint kint c/c 2
256kx18, sync lw, hstl, rev 4.6 4 / 27 august 20, 1998 sony ? cxk77b1840gb ? tr uth tables register - register mode zz ss (t n ) sw (t n ) sbw x (t n ) g mode dq 0-17 (t n ) dq 0-17 (t n+1 ) v dd current h x x x x sleep mode. power down hi - z hi - z i sb l h x x x deselect x hi - z i dd l l h x h read hi - z hi - z i dd l l h x l read x q(t n )i dd l l l l x write all bytes (bits 0-17) x d(t n )i dd l l l x x write bytes with sbw x=l x d(t n )i dd l l l h x abort write x hi - z i dd register - latch and register - flow thru mode zz ss (t n ) sw (t n ) sbw x (t n ) g mode dq 0-17 (t n ) dq 0-17 (t n+1 ) v dd current h x x x x sleep mode. power down hi - z hi - z i sb l h x x x deselect hi - z x i dd l l h x h read hi - z hi - z i dd l l h x l read q(t n )x i dd l l l l x write all bytes (bits 0-17) hi - z d(t n )i dd l l l x x write bytes with sbw x=l hi - z d(t n )i dd l l l h x abort write hi - z x i dd dual clock mode zz ss (t n ) sw (t n ) sbw x (t n ) g mode dq 0-17 (t n ) dq 0-17 (t n+1 ) v dd current h x x x x sleep mode. power down hi - z hi - z i sb l h x x x deselect hi - z x i dd l l h x h read hi - z hi - z i dd l l h x l read q(t n )x i dd l l l l x write all bytes (bits 0-17) hi - z d(t n )i dd l l l x x write bytes with sbw x=l hi - z d(t n )i dd l l l h x abort write hi - z hi - z i dd
256kx18, sync lw, hstl, rev 4.6 5 / 27 august 20, 1998 sony ? cxk77b1840gb ? mode select this device supports four different jedec standard read protocols via mode pins m1 and m2. the mode pins must be set during power-up and cannot change during sram operation. mode select truth table . ? power-up sequence power supplies must power up in the following sequence: v ss , v dd , v ddq , v ref , and inputs. v ddq must never exceed v dd . ? absolute maximum ratings (1) (1) stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. m1 m2 register-register l h register-flow thru l l register-latch h l dual clock h h item symbol rating unit supply voltage v dd -0.5 to +4.6 v output supply voltage v ddq -0.5 to +4.6 v input voltage v in -0.5 to v dd +0.5 (4.6v max.) v output voltage v out -0.5 to v ddq +0.5 (4.6v max.) v operating temperature t a 0 to 70 c junction temperature t j 0 to 110 c storage temperature t stg -55 to 150 c
256kx18, sync lw, hstl, rev 4.6 6 / 27 august 20, 1998 sony ? cxk77b1840gb ? dc recommended operating conditions. ( v ss = 0v , t a = 0 to 70 o c) (1) v ih (max) ac = v dd +1.5 v for pulse width less than 2.0 ns. (2) v il (min) ac = -1.5 v for pulse width less than 2.0 ns. (3) extended v ddq support up to 2.0v is available - please contact marketing. ? i/o capacitance (t a = 25 o c, f = 1 mhz) note: these parameters are sampled and are not 100% tested. ? programmable impedance output drivers this device has programmable impedance output drivers. the output impedance is controlled by an ex- ternal resistor, rq, connected between the srams zq pin and v ss , and is equal to one-fifth the value of this resistor. for output impedance matching within a 7.5% tolerance, rq must be in the range of 175 w to 350 w . for maximum output drive, the zq pin can be connected directly to v ss . for minimum output drive, the zq pin can be left open or connected to v ddq . the output impedance is updated when- ever the drivers are in a hi-z state. at power up, 8192 clock cycles followed by a write or deselect op- eration are required to ensure that the output impedance has reached its desired value. after power up, periodic updates of the output impedance, via a write or deselect operation, are also required. item symbol min typ max unit supply voltage v dd 3.13 3.3 3.47 v output supply voltage v ddq 1.4 --- 1.6 (3) v input reference voltage v ref 0.5 --- 1.0 v input high voltage v ih v ref + 0.2 --- v ddq + 0.3 (1) v input low voltage v il -0.3 (2) --- v ref - 0.2 v input high voltage - test mode v tih 2.0 --- v ddq +0.3 v input low voltage - test mode v til -0.3 --- 0.8 v clock input signal voltage v in -0.3 --- v ddq +0.3 v clock input differential voltage v dif 0.4 --- v ddq +0.6 v clock input common mode voltage v cm 0.5 0.75 1.0 v clock input cross point voltage v x 0.5 0.75 1.0 v output impedance control resistor rq 175 250 350 w item symbol test conditions min max unit input capacitance c in v in = 0v --- 6 pf clock input capacitance c clk v in = 0v --- 6 pf output capacitance c out v out = 0v --- 7 pf
256kx18, sync lw, hstl, rev 4.6 7 / 27 august 20, 1998 sony ? cxk77b1840gb ? dc electrical characteristics (v dd = 3.3v 5%, v ss = 0v, t a = 0 to 70 o c) 1. rq needs to be in the range of 175 w to 350 w for proper control of the value of r out . 1.1 r out 38 w (1.075 * 175 w /5) when rq 175 w 1.2 r out 3 64w (0.925 * 350 w /5) when rq 3 350 w 2. for maximum output drive, zq pin can be tied directly to v ss . the output impedance is as described in note 1.1. 3. for minimum output drive, zq pin can be no connect or tied to v ddq . the output impedance is as described in note 1.2. 4. typical i dd values measured at v dd = 3.3v and t a = 25 o c, with a 75% read / 25% write operation distribution. item symbol test conditions min typ max unit input leakage current i li v in = v ss to v dd -1 --- 1 ua output leakage current i lo v out = v ss to v dd g = v ih -10 --- 10 ua power supply operating current i dd 4 cycle = 6.0ns duty = 100% i out = 0 ma --- 610 --- ma power supply operating current i dd 4 cycle = 5.0ns duty = 100% i out = 0 ma --- 650 --- ma power supply operating current i dd 4 cycle = 4.5ns duty = 100% i out = 0 ma --- 670 --- ma power supply operating current i dd 4 cycle = 4.0ns duty = 100% i out = 0 ma --- 695 --- ma power supply standby current i sb zz 3 v ih --- 60 --- ma output high voltage v oh i oh = -6.0 ma rq=250 w v ddq -0.4 --- --- v output low voltage v ol i ol = 6.0 ma rq = 250 w --- --- 0.4 v output driver impedance r out 1,2,3 v oh = v ddq /2 v ol = v ddq /2 (rq/5)* 0.925 rq/5 (rq/5)* 1.075 w
256kx18, sync lw, hstl, rev 4.6 8 / 27 august 20, 1998 sony ? cxk77b1840gb ? ac electrical characteristics (register-register mode ) 1. all parameters are specified over the range t a = 0 to 70 o c. 2. these parameters are sampled and are not 100% tested. item symbol -4a -4 -45a -45 unit min max min max min max min max cycle time t khkh 4.0 --- 4.0 --- 4.0 --- 5.0 --- ns clock high pulse width t khkl 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns clock low pulse width t klkh 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns address setup time t avkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns address hold time t khax 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns write enables setup time t wvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns write enables hold time t khwx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns synchronous select setup time t svkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns synchronous select hold time t khsx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns data input setup time t dvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns data input hold time t khdx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns clock high to output valid t khqv --- 2.3 --- 2.3 --- 2.3 --- 2.5 ns clock high to output hold t khqx *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns clock high to output low-z t khqx1 *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns clock high to output high-z t khqz *2 --- 2.3 --- 2.3 --- 2.3 --- 2.5 ns output enable low to output valid t glqv --- 2.3 --- 2.3 --- 2.3 --- 2.5 ns output enable low to output low-z t glqx *2 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns output enable high to output high-z t ghqz *2 --- 2.3 --- 2.3 --- 2.3 --- 2.3 ns sleep mode enable time t zze *2 --- 20.0 --- 20.0 --- 20.0 --- 20.0 ns sleep mode recovery time t zzr *2 20.0 --- 20.0 --- 20.0 --- 20.0 ns
256kx18, sync lw, hstl, rev 4.6 9 / 27 august 20, 1998 sony ? cxk77b1840gb ? ac electrical characteristics (register-latch & register-flow thru modes) 1. all parameters are specified over the range t a = 0 to 70 o c. 2. these parameters are sampled and are not 100% tested. 3. for -4a, these parameters are measured from valid v ih /v il levels to the clock mid-point. 4. r-ft mode operation is verified functionally, but associated timing parameters are guaranteed by design only and are not 100 % tested. item symbol -4a -4 -45a -45 unit min max min max min max min max cycle time t khkh 4.8 --- 5.3 --- 5.3 --- 6.5 --- ns clock high pulse width t khkl 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns clock low pulse width t klkh 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns address setup time t avkh 0.4 *3 --- 0.5 --- 0.5 --- 0.5 --- ns address hold time t khax 0.8 *3 --- 1.0 --- 1.0 --- 1.0 --- ns write enables setup time t wvkh 0.4 *3 --- 0.5 --- 0.5 --- 0.5 --- ns write enables hold time t khwx 0.8 *3 --- 1.0 --- 1.0 --- 1.0 --- ns synchronous select setup time t svkh 0.4 *3 --- 0.5 --- 0.5 --- 0.5 --- ns synchronous select hold time t khsx 0.8 *3 --- 1.0 --- 1.0 --- 1.0 --- ns data input setup time t dvkh 0.4 *3 --- 0.5 --- 0.5 --- 0.5 --- ns data input hold time t khdx 0.8 *3 --- 1.0 --- 1.0 --- 1.0 --- ns clock high to output valid t khqv --- 4.8 --- 5.3 --- 5.3 --- 6.5 ns clock high to output hold (r-ft mode only) t khqx *2 2.0 --- 2.0 --- 2.0 --- 2.0 --- ns clock high to output low-z (r-ft mode only) t khqx1 *2 2.5 --- 2.5 --- 2.5 --- 3.0 --- ns clock low to output valid (r-l mode only) t klqv --- 2.2 --- 2.3 --- 2.5 --- 2.5 ns clock low to output hold (r-l mode only) t klqx *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns clock low to output low-z (r-l mode only) t klqx1 *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns clock high to output high-z t khqz *2 --- 2.2 --- 2.3 --- 2.5 --- 2.5 ns output enable low to output valid t glqv --- 2.2 --- 2.3 --- 2.5 --- 2.5 ns output enable low to output low-z t glqx *2 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns output enable high to output high-z t ghqz *2 --- 2.2 --- 2.3 --- 2.3 --- 2.3 ns sleep mode enable time t zze *2 --- 20.0 --- 20.0 --- 20.0 --- 20.0 ns sleep mode recovery time t zzr *2 20.0 --- 20.0 --- 20.0 --- 20.0 --- ns
256kx18, sync lw, hstl, rev 4.6 10 / 27 august 20, 1998 sony ? cxk77b1840gb ? ac electrical characteristics (dual clock mode) 1. all parameters are specified over the range t a = 0 to 70 o c. 2. these parameters are sampled and are not 100% tested. 3. currently, dc mode operation is not verified functionally, and no timing parameters are guaranteed. contact sony memory marketing for availability. item symbol -4a -4 -45a -45 unit min max min max min max min max k clock cycle time t khkh 4.0 --- 4.0 --- 4.5 --- 4.5 --- ns k clock high pulse width t khkl 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns k clock low pulse width t klkh 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns c clock cycle time t chch 4.0 --- 4.0 --- 4.5 --- 4.5 --- ns c clock high pulse width t chcl 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns c clock low pulse width t clch 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns k to c clock delay t khch 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns c to k clock delay t chkh 0.8 --- 0.8 --- 0.8 --- 0.8 --- ns address setup time t avkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns address hold time t khax 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns write enables setup time t wvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns write enables hold time t khwx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns synchronous select setup time t svkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns synchronous select hold time t khsx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns data input setup time t dvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns data input hold time t khdx 0.8 --- 0.8 --- 1.0 --- 1.0 --- ns k clock high to output valid t khqv --- 5.2 --- 5.2 --- 6.0 --- 6.5 ns c clock high to output valid t chqv --- 2.3 --- 2.3 --- 2.5 --- 2.5 ns c clock high to output hold t chqx *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns c clock high to output low-z t chqx1 *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns c clock high to output high-z t chqz *2 --- 2.3 --- 2.3 --- 2.5 --- 2.5 ns output enable low to output valid t glqv --- 2.1 --- 2.1 --- 2.5 --- 2.5 ns output enable low to output low-z t glqx *2 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns output enable high to output high-z t ghqz *2 --- 2.0 --- 2.0 --- 2.3 --- 2.3 ns sleep mode enable time t zze *2 --- 20.0 --- 20.0 --- 20.0 --- 20.0 ns sleep mode recovery time t zzr *2 20.0 --- 20.0 --- 20.0 --- 20.0 --- ns
256kx18, sync lw, hstl, rev 4.6 11 / 27 august 20, 1998 sony ? cxk77b1840gb dq 0.75 v fig. 1: ac test output load (v ddq = 1.5v) 50 w 50 w 5 pf 16.7 w 0.75 v 50 w 50 w 5 pf 16.7 w 16.7 w dq 0.75 v fig. 1: ac test output load (v ddq = 1.5v) 50 w 50 w 5 pf 16.7 w 0.75 v 50 w 50 w 5 pf 16.7 w 16.7 w ? ac test conditions (v ddq = 1.5v) (v dd = 3.3v 5%, t a = 0 to 70 c ) item conditions notes input reference voltage v ref = 0.75v input high level v ih = 1.25v input low level v il = 0.25v input rise & fall time 1v/ns clock input reference level k/k cross; c/c cross input high voltage 1.25v input low voltage 0.25v input rise & fall time 1v/ns output supply voltage v ddq = 1.5v output reference level 0.75v output load conditions fig.1 rq = 250 w
256kx18, sync lw, hstl, rev 4.6 12 / 27 august 20, 1998 sony ? cxk77b1840gb dq 0.95 v fig. 2: ac test output load (v ddq = 1.9v) 50 w 50 w 5 pf 16.7 w 0.95 v 50 w 50 w 5 pf 16.7 w 16.7 w ? ac test conditions (v ddq = 1.9v) .... for extended hstl (for r-l mode only ) (v dd = 3.3v 5%, t a = 0 to 70 c) (v ddq = 1.9v 0.1v, t a = 0 to 70 c) item conditions notes input reference voltage v ref = 0.75v input high level (address / control) v ihca = 1.25v input low level (address / control) v ilca = 0.25v input high level (data) v ihd = 1.25v input low level (data) v ild = 0.25v input rise & fall time 1v/ns clock input reference level k/k cross pecl input high voltage 1.45v pecl input low voltage 0.75v input rise & fall time 1v/ns output supply voltage v ddq = 1.9v output reference level 0.95v output load conditions fig.2 rq = 250 w
256kx18, sync lw, hstl, rev 4.6 13 / 27 august 20, 1998 sony ? cxk77b1840gb register - register mode t svkh t khsx t khqx1 t ghqz t glqv t glqx t khqv qn t khqz sw k k timing diagram of read and deselect operations n qn-1 n+2 sa g dq t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss n+3 qn-2 t khqx timing diagram of write operations g ss sw /sbw x k n n+1 n+2 k sa dn dn+1 dq t khdx t dvkh dn-1 n+3 dn+2
256kx18, sync lw, hstl, rev 4.6 14 / 27 august 20, 1998 sony ? cxk77b1840gb register - register mode sa ss g = v il timing diagram i of read-write-read operations ( ss controlled) k k n n+2 n+3 n+4 n+5 sw /sbw x read n deselect write n+2 read n+3 t khqz dq qn-1 qn dn+2 qn+3 read n+4 sa ss = v il g timing diagram ii of read-write-read operations ( g controlled) k k n n+2 n+3 n+4 n+5 sw /sbw x read n dummy write n+2 read n+3 t ghqz dq qn-1 qn dn+2 qn+3 read n+4 read
256kx18, sync lw, hstl, rev 4.6 15 / 27 august 20, 1998 sony ? cxk77b1840gb register - latch mode t svkh t khsx t klqx t ghqz t glqv t glqx t klqv qn+1 t khqz sw k k timing diagram of read and deselect operations n qn n+1 sa g dq t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss n+3 qn-1 t klqx t klqv t khqv timing diagram of write operations g ss sw /sbw x k n n+1 n+2 k sa dn dn+1 dq t khdx t dvkh dn-1 n+3 dn+2
256kx18, sync lw, hstl, rev 4.6 16 / 27 august 20, 1998 sony ? cxk77b1840gb register - latch mode sa ss g = v il timing diagram of read-write-read operations k k n n+2 n+4 n+5 sw /sbw x read n write n+1 read n+2 deselect t khqz dq qn qn+2 dn+1 qn+4 read n+4 n+1 t khqz
256kx18, sync lw, hstl, rev 4.6 17 / 27 august 20, 1998 sony ? cxk77b1840gb register - flow thru mode t svkh t khsx t ghqz t glqv t glqx qn+1 t khqz sw k k timing diagram of read and deselect operations n qn n+1 sa g dq t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss n+3 qn-1 t khqx t khqv t khqx timing diagram of write operations g ss sw /sbw x k n n+1 n+2 k sa dn dn+1 dq t khdx t dvkh dn-1 n+3 dn+2
256kx18, sync lw, hstl, rev 4.6 18 / 27 august 20, 1998 sony ? cxk77b1840gb register - flow thru mode sa ss g = v il timing diagram of read-write-read operations k k n n+2 n+4 n+5 sw /sbw x read n write n+1 read n+2 deselect t khqz dq qn qn+2 dn+1 qn+4 read n+4 n+1 t khqz
256kx18, sync lw, hstl, rev 4.6 19 / 27 august 20, 1998 sony ? cxk77b1840gb dual clock mode t svkh t khsx t chqx1 t ghqz t glqv t glqx t chqv qn+1 t chqz sw k k timing diagram of read and deselect operations n qn n+1 sa g dq t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss n+3 qn-1 t chqx t chqv t khqv c c t chch t chcl t clch t chkh t khch
256kx18, sync lw, hstl, rev 4.6 20 / 27 august 20, 1998 sony ? cxk77b1840gb dual clock mode timing diagram of write operations g ss sw /sbw x k n n+1 n+2 k sa dn dn+1 dq t khdx t dvkh dn-1 n+3 dn+2 timing diagram i of read-write-read operations ( ss controlled) c c sa ss g = v il k k n n+2 n+3 n+4 n+5 sw /sbw x read n deselect write n+2 read n+3 t chqz dq qn qn+3 dn+2 qn+4 read n+4
256kx18, sync lw, hstl, rev 4.6 21 / 27 august 20, 1998 sony ? cxk77b1840gb dual clock mode timing diagram ii of read-write-read operations ( g controlled) c c sa ss = v il g k k n n+2 n+3 n+4 n+5 sw /sbw x read n dummy write n+2 read n+3 dq read n+4 qn qn+3 dn+2 qn+4 t ghqz read ***note*** note 1: in order to prevent glitches on the data bus during write-read operations, when g is driven active (low) following the rising edge of k, the data bus will remain tri-stated until valid data from the most recent read operation is available. specifically, the data bus will remain tri-stated for the maximum of the following three times: 1.t khqv 2.t khch + t chqv 3.(k high to g low) + t glqv (1)
256kx18, sync lw, hstl, rev 4.6 22 / 27 august 20, 1998 sony ? cxk77b1840gb test mode description functional description the cxk77b1840 provides a jtag boundary scan interface using a limited set of ieee std. 1149.1 functions. the test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller, etc.), srams, other components and the printed circuit board. in conformance with a subset of ieee std. 1149.1, the cxk77b1840 contains a tap controller, instruc- tion register, boundary scan register and bypass register. jtag inputs/outputs are lvttl compatible only. test access port (tap) 4 pins as defined in the pin description table are used to perform jtag functions. the tdi input pin is used to scan test data serially into one of three registers (instruction register, boundary scan register and bypass register). tdo is the output pin used to scan test data serially out. the tdi pin sends the data into lsb of the selected register and the msb of the selected register feeds the data to tdo. the tms input pin controls the state transition of 16 state tap controller as specified in ieee std. 1149.1. inputs on tdi and tms are registered on the rising edge of tck clock. the output data on tdo is presented on the falling edge of tck. tdo driver is in active state only when tap controller is in shift-ir state or in shift-dr state. tck, tms, tdi must be tied low when jtag is not used. tap controller 16 state controller is implemented as specified in ieee std. 1149.1. the controller enters reset state in one of two ways: 1. power up. 2. apply a logic 1 on tms input pin on 5 consecutive tck rising edges. instruction register (3 bits) the jtag instruction register consists of a shift register stage and parallel output latch. the register is 3 bits wide and is encoded as follow: octal msb..........lsb instruction 0 0 0 0 bypass 1 0 0 1 idcode. read device id 2 0 1 0 sample-z. sample inputs and tri-state dqs 3 0 1 1 bypass 4 1 0 0 sample. sample inputs. 5 1 0 1 private. manufacturer use only. 6 1 1 0 bypass 7 1 1 1 bypass
256kx18, sync lw, hstl, rev 4.6 23 / 27 august 20, 1998 sony ? cxk77b1840gb bypass register (1 bit) the bypass register is one bit wide and is connected electrically between tdi and tdo and provides the minimum length serial path between tdi and tdo. id registers (32 bits) the id register is 32 bits wide and is encoded as follows: boundary scan register (51 bits) the boundary scan registers are 51 bits wide and are listed as follows: k/k , c/c inputs are sampled through one differential stage and internally inverted to generate internal k/k , c/c signals for scan registers. place holder are required for some nc pins to maintain 51 bits scan register for different types of the same family sram and for density upgrades. all place holder reg- isters are connected to v ss internally regardless of pin connection externally. id[0} 1 sony id id[11:1] 0000 1110 001 part number id[27:12] 0000 0000 0001 1000 revision number id[31:28] xxxx dq 18 sa 18 sw , sbw x3 ss , g 2 k, k , c, c 4 zz 1 m1, m2 2 zq 1 place holder 2
256kx18, sync lw, hstl, rev 4.6 24 / 27 august 20, 1998 sony ? cxk77b1840gb scan order (order by exit sequence) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 3b - 3a 3c 2c 2a 1d 2e 2g 1h 3g 4d 4e 4g 4h 4m 2k 1l 2m 1n 2p 3t 2r 4n 2t 3r sa v ss sa sa sa sa dqb dqb dqb dqb sbw b zq ss c c sw dqb dqb dqb dqb dqb sa sa sa sa m1 sa v ss sa sa sa sa dqa dqa dqa dqa dqa g k k sbw a dqa dqa dqa dqa zz sa sa sa sa m2 5b - 5a 5c 6c 6a 6d 7e 6f 7g 6h 4f 4k 4l 5l 7k 6l 6n 7p 7t 5t 6r 4p 6t 5r 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
256kx18, sync lw, hstl, rev 4.6 25 / 27 august 20, 1998 sony ? cxk77b1840gb ordering information. note: contact sony memory marketing for availability of dual clock mode functionality. part number speed register - register register - latch/ register - flow thru **dual clock** cxk77b1840gb-4a 4.0ns cycle / 2.3ns access 4.8ns cycle / 4.8ns access 4.0ns cycle / 5.2ns access cxk77b1840gb-4 4.0ns cycle / 2.3ns access 5.3ns cycle / 5.3ns access 4.0ns cycle / 5.2ns access CXK77B1840GB-45a 4.0ns cycle / 2.3ns access 5.3ns cycle / 5.3ns access 4.5ns cycle / 6.0ns access CXK77B1840GB-45 5.0ns cycle / 2.5ns access 6.5ns cycle / 6.5ns access 4.5ns cycle / 6.5ns access sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illu s- trating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circui ts.
256kx18, sync lw, hstl, rev 4.6 26 / 27 august 20, 1998 sony ? cxk77b1840gb revision history rev. # rev. date changes / modifications to data-sheet rev 4.0 8/22/97 initial version, based on ts-2 evaluation rev 4.2 11/21/97 modified ac electrical characteristics: r-r mode: -4.5+ t khkh 5.0ns to 4.5ns -4.5 t ghqz 2.5ns to 2.3ns -4.5 t ghqz 2.5ns to 2.3ns r-l, r-ft modes: -4 t khkh 5.5ns to 5.0ns -4.5+ t khqv 6.5ns to 5.5ns t ghqz 2.5ns to 2.3ns -4.5 t ghqz 2.5ns to 2.3ns -5 t khkh 5.5ns to 6.0ns dc mode: -4 t khqv 5.5ns to 5.3ns t khdx 1.0ns to 0.8ns t glqv 2.3ns to 2.1ns t ghqz 2.3ns to 2.0ns -4.5+ t khqv 6.2ns to 6.0ns t ghqz 2.5ns to 2.3ns -4.5 t ghqz 2.5ns to 2.3ns renamed -4 bin to -40 bin in all modes. renamed -4.5+ bin to -45h bin in all modes. renamed -4.5 bin to -45 bin in all modes. renamed -5 bin to -50 bin in all modes. modified dc recommended operating conditions (page-6) v ih min v ref + 0.1 to v ref + 0.2 v il max v ref - 0.1 to v ref - 0.2 v dif min 0.2v to 0.4v added extended hstl ac test conditions (page-12) provided i dd & i sb typical values (page-7) rev 4.3 01/15/98 modified ac electrical characteristics: added -40a bin to all modes. deleted -40 bin from all modes. deleted -50 bin from all modes. renamed -45h bin to -45a bin in all modes. modified extended hstl ac test conditions (page-12)
256kx18, sync lw, hstl, rev 4.6 27 / 27 august 20, 1998 sony ? cxk77b1840gb rev 4.4 04/14/98 modified ac electrical characteristics deleted -45 bin from all modes. renamed -40a bin to -4a bin in all modes. r-r mode: -4a t khkh 4.5ns to 4.0ns -45a t khkh 4.5ns to 4.0ns t khqv 2.5ns to 2.3ns t khqz 2.5ns to 2.3ns t glqv 2.5ns to 2.3ns r-l, r-ft modes: added r-ft timing parameters guaranteed by design only note for all bins. removed t khqz1 from all bins. -4a t ghqz 2.3ns to 2.2ns dc mode: added dc operation not functionally verified note for all bins. removed t khqx and t khqx1 from all bins. -4a t khqv 5.3ns to 5.2ns modified dc recommended operating conditions (page-6) rq min 200 w to 175 w modified dc electrical characteristics (page-7) r out min (rq/5)*0.9 w to (rq/5)*0.925 w r out max (rq/5)*1.1 w to (rq/5)*1.075 w updated all timing diagrams (page-13 through page-21). added contact sony memory marketing for dc model availability note (page-1 and page-25). removed preliminary from the data sheet rev 4.5 08/12/98 modified ac electrical characteristics r-l, r-ft modes: -4a t khkh 5.0ns to 4.8ns t khqv 5.0ns to 4.8ns -45a t khkh 5.5ns to 5.3ns t khqv 5.5ns to 5.3ns rev 4.6 08/20/98 modified ac electrical characteristics added -4 bin to all modes. added -45 bin to all modes. rev. # rev. date changes / modifications to data-sheet

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