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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit pd4382323, 4382363 8m-bit cmos synchronous fast sram pipelined operation double cycle deselect document no. m15393ej1v0ds00 (1st edition) date published february 2001 ns cp(k) printed in japan data sheet description the pd4382323 is a 262,144-word by 32-bit and the pd4382363 is a 262,144-word by 36-bit synchronous static ram fabricated with advanced cmos technology using n-channel four-transistor memory cell. the pd4382323 and pd4382363 integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as sram core. all input registers are controlled by a positive edge of the single clock input (clk). the pd4382323 and pd4382363 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory. zz has to be set low at the normal operation. when zz is set high, the sram enters power down state (?sleep?). in the ?sleep? state, the sram internal state is preserved. when zz is set low again, the sram resumes normal operation. the pd4382323 and pd4382363 are packaged in 100-pin plastic lqfp with a 1.4 mm package thickness for high density and low capacitive loading. features ? 3.3 v power supply ? synchronous operation ? internally self-timed write control ? burst read / write : interleaved burst and linear burst sequence ? fully registered inputs and outputs for pipelined operation ? double-cycle deselect timing ? all registers triggered off positive clock edge ? 3.3 v lvttl compatible : all inputs and outputs ? fast clock access time : 3.8 ns (150 mhz), 4.0 ns (133 mhz) ? asynchronous output enable : /g ? burst sequence selectable : mode ? sleep mode : zz (zz = open or low : normal operation) ? separate byte write enable : /bw1 - /bw4, /bwe global write enable : /gw ? three chip enables for easy depth expansion ? common i/o using three state outputs
2 data sheet m15393ej1v0ds pd4382323, 4382363 ordering information part number access clock core supply i/o package time frequency voltage interface ns mhz v v pd4382323gf-a67 3.8 150 3.3 0.165 3.3 100-pin plastic lqfp (14 x 20) pd4382323gf-a75 4.0 133 lvttl pd4382363gf-a67 3.8 150 pd4382363gf-a75 4.0 133
3 data sheet m15393ej1v0ds pd4382323, 4382363 pin configuration (marking side) / indicates active low signal. 100-pin plastic lqfp (14 x 20) [ pd4382323gf, pd4382363gf] i/op3, nc i/o17 i/o18 v dd q v ss q i/o19 i/o20 i/o21 i/o22 v ss q v dd q i/o23 i/o24 nc v dd nc v ss i/o25 i/o26 v dd q v ss q i/o27 i/o28 i/o29 i/o30 v ss q v dd q i/o31 i/o32 i/op4, nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/op2, nc i/o16 i/o15 v dd q v ss q i/o14 i/o13 i/o12 i/o11 v ss q v dd q i/o10 i/o9 v ss nc v dd zz i/o8 i/o7 v dd q v ss q i/o6 i/o5 i/o4 i/o3 v ss q v dd q i/o2 i/o1 i/op1, nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 /bw4 /bw3 /bw2 /bw1 /ce2 v dd v ss clk /gw /bwe /g /ac /ap /adv a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc a17 a10 a11 a12 a13 a14 a15 a16 remark refer to package drawing for 1-pin index mark.
4 data sheet m15393ej1v0ds pd4382323, 4382363 pin identification symbol pin no. description a0 - a17 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43 synchronous address input i/o1 - i/o32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 synchronous data in, synchronous / asynchronous data out i/op1, nc note 51 synchronous data in (parity), i/op2, nc note 80 synchronous / asynchronous data out (parity) i/op3, nc note 1 i/op4, nc note 30 /adv 83 synchronous burst address advance input /ap 84 synchronous address status processor input /ac 85 synchronous address status controller input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /bwe1 - /bwe4, /bwe 93, 94, 95, 96, 87 synchronous byte write enable input /gw 88 synchronous global write input /g 86 asynchronous output enable input clk 89 clock input mode 31 asynchronous burst sequence select input do not change state during normal operation zz 64 asynchronous power down state input v dd 15, 41, 65, 91 power supply v ss 17, 40, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 14, 16, 38, 39, 42, 66 no connection note nc (no connection) is used in the pd4382323gf. i/op1 - i/op4 is used in the pd4382363gf.
5 data sheet m15393ej1v0ds pd4382323, 4382363 block diagram address registers binary counter and logic clr q0 q1 byte 1 write register byte 1 write driver 8/9 byte 2 write register byte 2 write driver 8/9 byte 3 write register byte 3 write driver 8/9 byte 4 write register byte 4 write driver 8/9 enable register row and column memory matrix 1,024 rows 256 32 columns (8,388,608 bits) 256 36 columns (9,437,184 bits) output registers output buffers input registers 32/36 16 18 a0, a1 a1 ? a0 ? 32/36 4 32/36 a0 - a17 mode /adv clk /ac /ap /bw1 /bw2 /bw3 /bw4 /bwe /gw /ce ce2 /ce2 /g i/o1 - i/o32 i/op1 - i/op4 zz power down control decoders 18 burst sequence interleaved burst sequence table (mode = open or v dd ) external address a17 - a2, a1, a0 1st burst address a17 - a2, a1, /a0 2nd burst address a17 - a2, /a1, a0 3rd burst address a17 - a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a17 - a2, 0, 0 a17 - a2, 0, 1 a17 - a2, 1, 0 a17 - a2, 1, 1 1st burst address a17 - a2, 0, 1 a17 - a2, 1, 0 a17 - a2, 1, 1 a17 - a2, 0, 0 2nd burst address a17 - a2, 1, 0 a17 - a2, 1, 1 a17 - a2, 0, 0 a17 - a2, 0, 1 3rd burst address a17 - a2, 1, 1 a17 - a2, 0, 0 a17 - a2, 0, 1 a17 - a2, 1, 0
6 data sheet m15393ej1v0ds pd4382323, 4382363 asynchronous truth table operation /g i/o read cycle l dout read cycle h hi-z write cycle hi-z, din deselected hi-z remark : don ? t care synchronous truth table operation /ce ce2 /ce2 /ap /ac /adv /write clk address deselected note h l l h none deselected note ll l l h none deselected note l hl l h none deselected note ll hl l h none deselected note l hhl l h none read cycle / begin burst l h l l l h external read cycle / begin burst l h l h l hl h external read cycle / continue burst hh l l hnext read cycle / continue burst h hl l hnext read cycle / suspend burst hh h l h current read cycle / suspend burst h hh l h current write cycle / begin burst l h l h l ll h external write cycle / continue burst hh l l hnext write cycle / continue burst h hl l hnext write cycle / suspend burst hh h l h current write cycle / suspend burst h hh l h current note deselect status is held until new ? begin burst ? entry. remarks 1. : don ? t care 2. /write = l means any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) and /bwe are low or /gw is low. /write = h means the following two cases. (1) /bwe and /gw are high. (2) /bw1, /bw2, /bw3, /bw4 and /gw are high, and /bwe is low.
7 data sheet m15393ej1v0ds pd4382323, 4382363 partial truth table for write enables operation /gw /bwe /bw1 /bw2 /bw3 /bw4 read cycle h h read cycle h l h h h h write cycle / byte 1 only h l l h h h write cycle / all bytes hlllll write cycle / all bytes l remark : don ? t care pass-through truth table previous cycle present cycle next cycle operation add /write i/o operation add /ces /write /g i/o operation write cycle ak l dn(ak) read cycle am l h l q1(ak) read q1(am) deselected - h hi-z no carry over from previous cycle remarks 1. : don ? t care 2. /write = l means any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) and /bwe are low or /gw is low. /write = h means the following two cases. (1) /bwe and /gw are high. (2) /bw1, /bw2, /bw3, /bw4 and /gw are high, and /bwe is low. /ces = l means /ce is low, /ce2 is low and ce2 is high. /ces = h means /ce is high or /ce2 is high or ce2 is low. zz (sleep) truth table zz chip status 0.2 v active open active v dd ? 0.2 v sleep
8 data sheet m15393ej1v0ds pd4382323, 4382363 electrical specifications absolute maximum ratings parameter symbol conditions min. typ. max. unit note supply voltage v dd ? 0.5 +4.0 v output supply voltage v dd q ? 0.5 v dd v input voltage v in ? 0.5 v dd + 0.5 v 1, 2 input / output voltage v i/o ? 0.5 v dd q + 0.5 v 1, 2 operating ambient temperature t a 070 c storage temperature t stg ? 55 +125 c notes 1. ? 2.0 v (min.) (pulse width : 2 ns) 2. v dd q + 2.3 v (max.) (pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t a = 0 to 70 c) parameter symbol conditions min. typ. max. unit supply voltage v dd 3.135 3.3 3.465 v output supply voltage v dd q 3.135 3.3 3.465 v high level input voltage v ih 2.0 v dd q + 0.3 v low level input voltage v il ? 0.3 note +0.8 v note ? 0.8 v (min.) (pulse width : 2 ns) capacitance (t a = 25 c, f = 1mhz) parameter symbol test conditions min. typ. max. unit input capacitance c in v in = 0 v 4 pf input / output capacitance c i/o v i/o = 0 v 7 pf clock input capacitance c clk v clk = 0 v 4 pf remark these parameters are not 100% tested.
9 data sheet m15393ej1v0ds pd4382323, 4382363 dc characteristics (t a = 0 to 70c, v dd = 3.3 0.165 v) parameter symbol test condition min. typ. max. unit note input leakage current i li v in (except zz, mode) = 0 v to v dd ? 2+2 a i/o leakage current i lo v i/o = 0 v to v dd q, outputs are disabled ? 2+2 a operating supply current i dd device selected, cycle = max. -a67 440 ma v in v il or v in v ih , i i/o = 0 ma -a75 400 i dd1 suspend cycle, cycle = max. 170 /ac, /ap, /adv, /gw, /bwes v ih , v in v il or v in v ih , i i/o = 0 ma standby supply current i sb device deselected, cycle = 0 mhz 30 ma v in v il or v in v ih , all inputs are static i sb1 device deselected, cycle = 0 mhz 10 v in 0.2 v or v in v dd ? 0.2 v, v i/o 0.2 v, all inputs are static i sb2 device deselected, cycle = max. 180 v in v il or v in v ih power down supply current i sbzz zz v dd ? 0.2 v, v i/o v dd q + 0.2 v 10 ma high level output voltage v oh i oh = ? 4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v
10 data sheet m15393ej1v0ds pd4382323, 4382363 ac characteristics (t a = 0 to 70 c, v dd = 3.3 0.165 v) ac test conditions 3.3 v lvttl interface input waveform (rise / fall time 3.0 ns) test ponts v ss 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load condition c l : 30 pf 5 pf (tkhqx1, tkhqx2, tglqx, tghqz, tkhqz) figure1 external load at test i/o (output) v t = +1.5 v 50 ? z o = 50 ? c l remark c l includes capacitances of the probe and jig, and stray capacitances.
11 data sheet m15393ej1v0ds pd4382323, 4382363 read and write cycle parameter symbol -a67 -a75 unit note (150 mhz) (133 mhz) standard alias min. max. min. max. cycle time tkhkh tcyc 6.66 ? 7.5 ? ns clock access time tkhqv tcd ? 3.8 ? 4.0 ns output enable access time tglqv toe ? 3.8 ? 4.0 ns clock high to output active tkhqx1 tdc1 0 ? 0 ? ns clock high to output change tkhqx2 tdc2 1.5 ? 1.5 ? ns output enable to output active tglqx tolz 0 ? 0 ? ns output disable to output high-z tghqz tohz 0 3.5 0 3.5 ns clock high to output high-z tkhqz tcz 1.5 3.8 1.5 4.0 ns clock high pulse width tkhkl tch 2.0 ? 2.0 ? ns clock low pulse width tklkh tcl 2.0 ? 2.0 ? ns setup times address tavkh tas 2.0 ? 2.0 ? ns address status tadsvkh tss data in tdvkh tds write enable twvkh tws address advance tadvvkh ? chip enable tevkh ? hold times address tkhax tah 0.5 ? 0.5 ? ns address status tkhadsx tsh data in tkhdx tdh write enable tkhwx twh address advance tkhadvx ? chip enable tkhex ? power down entry setup tzzes tzzes 5.0 ? 5.0 ? ns 1 power down entry hold tzzeh tzzeh 1.0 ? 1.0 ? ns 1 power down recovery setup tzzrs tzzrs 6.0 ? 6.0 ? ns 1 power down recovery hold tzzrh tzzrh 0 ? 0 ? ns 1 note 1. although zz signal input is asynchronous, the signal must meet specified setup and hold times in order to be recognized.
12 data sheet m15393ej1v0ds pd4382323, 4382363 tkhkh tklkh tkhax twvkh tkhwx tkhex tglqv tglqx tkhqx2 tkhqz q1(a1) q1(a2) q2(a2) q3(a2) q4(a2) hi-z a1 a2 a3 clk /ap /ac address /adv /ces note1 /g data in /bwe /bws tghqz tkhqv tkhkl tkhadsx tadsvkh tavkh tevkh tadsvkh tkhadsx tadvvkh tkhadvx twvkh tkhwx /gw data out read cycle remark qn(a2) refers to output from address a2. q1-q4 refer to outputs according to burst sequence. notes 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. 2. outputs are disabled within two clock cycles after deselect. q1(a2) q1(a3) note2
13 data sheet m15393ej1v0ds pd4382323, 4382363 tkhkh tavkh tkhax tevkh tkhex d1(a1) d1(a2) d2(a2) d2(a2) d3(a2) d4(a2) d1(a3) d2(a3) d3(a3) hi-z tkhkl tklkh a1 a2 a3 tdvkh tkhdx tkhadsx twvkh tkhwx clk /ap /ac address /adv /ces note2 /g data in /bwe note1 /bws /gw note1 data out twvkh tkhadvx tkhwx tadsvkh tkhadsx tadsvkh write cycle notes 2. all bytes write can be initiated by /gw low or /gw high and /bwe, /bw1-/bw4 low. 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. tghqz tadvvkh
14 data sheet m15393ej1v0ds pd4382323, 4382363 tkhkh tklkh tkhkl tavkh tevkh tkhex tkhqv tglqx q1(a1) q1(a3) q2(a3) q3(a3) a1 tghqz tkhqx1 tdvkh tkhdx hi-z d1(a2) tadsvkh tkhadsx tkhax tadsvkh tkhadsx clk /ap /ac address /adv /ces note2 /g data in /bwe note1 /bws /gw note1 data out twvkh tkhwx twvkh tkhwx q4(a3) tadvvkh tkhadvx read / write cycle a2 a3 q1(a2) notes 1. all bytes write can be initiated by /gw low or /gw high and /bwe, /bw1-/bw4 low. 2. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low.
15 data sheet m15393ej1v0ds pd4382323, 4382363 tkhkh tklkh tkhkl tavkh tevkh tkhex tghqz q1(a1) q1(a2) q1(a3) q1(a4) a3 a2 tdvkh tkhdx hi-z tkhax tadsvkh tkhadsx clk /ac address /ces note2 /g data in /bwe note1 /bws /gw note1 data out twvkh notes 2. all bytes write can be initiated by /gw low or /gw high and /bwe, /bw1-/bw4 low. 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. single read / write cycle a4 a5 a6 a7 a1 a8 a9 twvkh tkhwx q1(a7) q1(a8) q1(a9) d1(a5) d1(a6) d1(a7) tglqx tkhqv tglqv tkhqz remark /ap is high and /adv is don't care. tkhwx note3 3. outputs are disabled within two clock cycles after deselect.
16 data sheet m15393ej1v0ds pd4382323, 4382363 tkhkh zz tklkh a1 a2 tzzeh tzzes tzzrh tzzrs power down (i sbzz ) state tkhkl clk /ap /ac address /adv /ces /g /bwe /bws /gw data out power down (zz) cycle q1(a2) q1(a1) hi-z
17 data sheet m15393ej1v0ds pd4382323, 4382363 tkhkh data out tkhkl tklkh a1 a2 power down state (i sb1 ) note q1(a1) q1(a2) data in clk /ap /ac address /adv /ces /g /bwe /bws /gw stop clock cycle hi-z note v in 0.2 v or v in v dd ? 0.2 v, v i/o 0.2 v
18 data sheet m15393ej1v0ds pd4382323, 4382363 package drawing 100-pin plastic lqfp (14x20) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 22.0 0.2 20.0 0.2 0.65 (t.p.) 0.575 j 16.0 0.2 k c 14.0 0.2 i 0.13 1.0 0.2 l 0.5 0.2 f 0.825 n p q 0.10 1.4 0.125 0.075 s100gf-65-8et-1 s 1.7 max. h 0.32 + 0.08 ? 0.07 m 0.17 + 0.06 ? 0.05 r3 + 7 ? 3 m 80 81 51 50 30 31 100 1 s s n j detail of lead end c d a b r k m l p i s q g f h
19 data sheet m15393ej1v0ds pd4382323, 4382363 recommended soldering condition please consult with our sales offices for soldering conditions of the pd4382323 and 4382363. types of surface mount devices pd4382323gf : 100-pin plastic lqfp (14 x 20) pd4382363gf : 100-pin plastic lqfp (14 x 20)
20 data sheet m15393ej1v0ds pd4382323, 4382363 [ memo ]
21 data sheet m15393ej1v0ds pd4382323, 4382363 [ memo ]
22 data sheet m15393ej1v0ds pd4382323, 4382363 [ memo ]
23 data sheet m15393ej1v0ds pd4382323, 4382363 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd4382323, 4382363 m8e 00. 4 the information in this document is current as of february, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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