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rev. 0 adg3249 2.5 v/3.3 v, 2:1 multiplexer/ demultiplexer bus switch information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. features 225 ps propagation delay through the switch 4.5 switch connection between ports data rate 1.244 gbps 2.5 v/3.3 v supply operation selectable level shifting/translation level translation 3.3 v to 2.5 v 3.3 v to 1.8 v 2.5 v to 1.8 v small signal bandwidth 610 mhz 8-lead sot-23 package applications 3.3 v to 1.8 v voltage translation 3.3 v to 2.5 v voltage translation 2.5 v to 1.8 v voltage translation docking stations memory switching analog switch applications functional block diagram en adg3249 a0 a1 b control logic in general description the adg3249 is a 2.5 v or 3.3 v, high performance 2:1 multi- plexer/demultiplexer bus switch. it is designed on a low voltage cmos process, which provides low power dissipation yet gives high switching speed and very low on resistance. this allows the input to be connected to the out put without additional propaga- tion delay or generating additional ground bounce noise. each switch of the adg3249 conducts equally well in both direc- tions when on. the adg3249 exhibits break-before-make switching action, preventing momentary shorting when switch- ing channels. this device is ideal for applications requiring level translation. when operated from a 3.3 v supply, level translation from 3.3 v inputs to 2.5 v outputs is allowed. similarly, if the device is operated from 2.5 v supply and 2.5 v inputs are applied, the device will translate the outputs to 1.8 v. in addition, a level translating pin ( sel ) is included. when sel is low, v cc is reduced internally, allowing for level translating between 3.3 v inputs and 1.8 v outputs. the adg3249 is available in a tiny 8-lead sot-23 package. product highlights 1. 3.3 v or 2.5 v supply operation. 2. extremely low propagation delay through switch. 3. 4.5 ? switches connect inputs to outputs. 4. tiny sot-23 package.
rev. 0 e2e adg3249especifications 1 b version parameter symbol conditions min typ 2 max unit dc electrical characteristics input high voltage v inh v cc = 2.7 v to 3.6 v 2.0 v v inh v cc = 2.3 v to 2.7 v 1.7 v input low voltage v inl v cc = 2.7 v to 3.6 v 0.8 v v inl v cc = 2.3 v to 2.7 v 0.7 v input leakage current i i 0.01 1 a off state leakage current i oz 0 a, b v cc 0.01 1 a on state leakage current 0 a, b v cc 0.01 1 a maximum pass voltage v p v a /v b = v cc = sel = 3.3 v, i o = C C C r on v cc = 3 v, sel = v cc , v a = 0 v, i a = 8 ma 0.1 0.5 v cc = 3 v, sel = 0 v, v a = 0 v, i a = 8 ma 0.1 0.5 power requirements v cc 2.3 3.6 v quiescent power supply current i cc digital inputs = 0 v or v cc ; sel = v cc 0.01 1 a digital inputs = 0 v or v cc ; sel = 0 v 0.1 0.2 ma increase in i cc per input 7 i cc v cc = 3.6 v, en = 3.0 v; sel = v cc ; in = v cc 0.15 8 a notes 1 temperature range is as follows: b version: C
rev. 0 adg3249 e3e absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v cc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . C C C C C ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 206 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . . 300 c ir reflow, peak temperature (<20 sec) . . . . . . . . . . . . 235 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. pin configuration 8-lead sot-23 top view (not to scale) 8 7 6 5 1 2 3 4 adg3249 gnd a1 en in sel v cc a0 b ordering guide model temperature range package description package branding ADG3249BRJ-R2 C C C en n sel nn ll l ls ll ls l l ls l ls sel n en el n n s sel ls s
rev. 0 e4e adg3249 terminology v cc positive power supply voltage. gnd ground (0 v) reference. v inh minimum input voltage for logic 1. v inl maximum input voltage for logic 0. i i input leakage current at the control inputs. i oz off state leakage current. it is the maximum leakage current at the switch pin in the off state. i ol on state leakage current. it is the maximum leakage current at the switch pin in the on state. v p maximum pass voltage. the m aximum pass voltage relates to the clamped output voltage of an nmos device when the switch input voltage is equal to the supply voltage. r on ohmic resistance offered by a switch in the on state. it is measured at a given voltage by forcing a specified amount of current through the switch. r on on resistance match between any two channels, i.e., r on m ax to r on min. c x off off switch capacitance. c x on on switch capacitance. c in , c sel , c en control input capacitance. this consists of in, sel , and en . i cc quiescent power supply current. this current represents the leakage current between the v cc and ground pins. it is measured when all control inputs are at a logic high or low level and the switches are off. i cc extra power supply current component for the en control input when the input is not driven at the supplies. t plh , t phl data propagation delay through the switch in the on state. propagation delay is related to the rc time constant r on c l , where c l is the load capacitance. t pzh , t pzl bus enable times. these are the times taken to cross the v t voltage at the switch output when the switch turns on in response to the control signal, en . t phz , t plz bus disable times. th ese are the time taken to place the switch in the high impedance off state in response to the control signal. they are measured as the time taken for the output voltage to change by v from the original quiescent level, with reference to the logic level transition at the control input. (refer to figure 3 for enable and disable times.) t bbm on or off time. measured between the 90% points of both switches when switching fom one to another. t trans time taken to switch from one channel to the other, measured from 50% of the in signal to 90% of the out signal. max data rate maximum rate at which data can be passed through the switch. channel jitter peak-to-peak value of the sum of the deterministic and random jitter of the switch channel.
rev. 0 t ypical performance characteristicseadg3249 e5e v a /v b (v ) r on ( ) 0 0 0.5 t a = 25 c sel = v cc 5 10 15 20 25 30 35 40 1.5 2.5 3.5 v cc = 3v v cc = 3.3v v cc = 3.6v 3.0 2.0 1.0 tpc 1. on resistance vs. input voltage v a /v b (v) r on ( ) 0 0 0.5 5 10 15 20 1.5 2.0 1.0 25 c 85 c 40 c = 3.3v sel = v cc v cc tpc 4. on resistance vs. input voltage for different temperatures v a /v b (v) v out (v) 0 0 0.5 0.5 1.5 2.5 1.5 2.5 v cc = 2.7v v cc = 2.5v v cc = 2.3v t a = 25 c sel = v cc i o = ? a 2.0 1.0 1.0 2.0 3.0 tpc 7. pass voltage vs. v cc v a /v b (v ) r on ( ) 0 0 0.5 5 10 15 20 25 30 35 40 1.5 2.5 v cc = 2.3v v cc = 2.5v v cc = 2.7v t a = 25 c sel = v cc 3.0 2.0 1.0 tpc 2. on resistance vs. input voltage v a /v b (v) r on ( ) 0 0 0.5 5 10 15 85 c 25 c 1.0 40 c = 2.5v sel = v cc v cc 1.2 tpc 5. on resistance vs. input voltage for different temperatures v a /v b (v) v out (v) 0 0 0.5 0.5 1.5 2.5 1.5 2.5 v cc = 3.6v v cc = 3.3v v cc = 3v 3.5 t a = 25 c sel = 0v i o = ? a 2.0 1.0 1.0 2.0 3.0 tpc 8. pass voltage vs. v cc v a /v b (v ) r on ( ) 0 0 0.5 5 10 15 20 25 30 35 40 1.5 2.5 v cc = 3v v cc = 3.3v v cc = 3.6v 3.5 t a = 25 c sel = 0v 1.0 2.0 3.0 tpc 3. on resistance vs. input voltage v a /v b (v) v out (v) 0 0 0.5 0.5 1.5 2.5 1.5 2.5 3.5 v cc = 3.6v v cc = 3.3v v cc = 3v 3.0 2.0 1.0 1.0 2.0 3.0 t a = 25 c sel = v cc i o = ? a tpc 6. pass voltage vs. v cc 300 0510 15 20 25 30 35 40 45 enable frequency (mhz) i cc ( a) 50 50 100 150 200 250 0 v cc = 3.3v sel = 0v v cc = sel = 3.3v v cc = sel = 2.5v t a = 25 c tpc 9. i cc vs. enable frequency
rev. 0 e6e adg3249 v out (v) 1.5 2.0 2.5 3.0 v cc = 3.3v; sel = 0v v cc = sel = 3.3v t a = 25 c v a = 0v en = 0 v cc = sel = 2.5v i o (a) 0 0.5 1.0 0.02 0.04 0.06 0.08 0.10 0 tpc 10. output low characteristic t a = 25 c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer: r l = r s = 50 0 1 ? ? ? ? 0.03 0.1 1.0 frequency ( mhz ) attenuation (db) 10 100 0 100 ? ? ? ? tpc 13. bandwidth vs. frequency v cc = sel = 3.3v enable enable disable disable v cc = 3.3v, sel = 0v 6 5 ?0 20 0 temperature ( c) time (ns) 20 80 60 40 4 3 2 1 0 tpc 16. enable/disable time vs. temperature i o (a) v out (v) 0 ?.10 0.5 1.0 1.5 2.0 2.5 3.0 t a = 25 c v a = v cc en = 0 v cc = sel = 2.5v v cc = 3.3v; sel = 0v v cc = sel = 3.3v ?.08 0.06 ?.04 0.02 0 tpc 11. output high characteristic t a = 25 c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer: r l = r s = 50 ?0 0 ?0 ?0 ?0 ?0 0.03 0.1 1.0 frequency ( mhz ) attenuation (db) 10 100 0 100 ?0 ?0 ?0 ?00 ?0 tpc 14. crosstalk vs. frequency v cc = sel = 2.5v enable disable 4.0 3.5 3.0 ?0 20 0 temperature ( c) time (ns) 20 80 60 40 2.5 2.0 1.5 1.0 0.5 0 tpc 17. enable/disable time vs. temperature v cc = 2.5v v cc = 3.3v t a = 25 c sel = v cc on = off c l = inf. v a /v b (v) q inj (pc) ?.4 0 ?.2 ?.0 ?.8 ?.6 ?.4 ?.2 0 0.5 1.0 1.5 2.5 2.0 3.0 3. 5 tpc 12. charge injection vs. source voltage t a = 25 c v cc = 3.3v/2.5v sel = v cc v in = 0dbm n/w analyzer: r l = r s = 50 ?0 0 ?0 ?0 ?0 ?0 0.03 0.1 1.0 frequency (mhz) attenuation (db) 10 1000 100 ?0 ?0 ?0 ?00 ?0 tpc 15. off isolation vs. frequency data rate (gbps) jitter (ps p-p) 0.5 60 70 80 90 100 50 40 30 20 10 0 v cc = sel = 3.3v v in = 1.5v p-p 20db attenuation 0.7 0.9 1.1 1.3 1.5 1.7 1.9 tpc 18. jitter vs. data rate; prbs 31
rev. 0 adg3249 e7e data rate (gbps) eye width (%) 0.5 60 70 80 85 90 95 100 75 65 55 50 1.5 1.3 1.1 0.9 0.7 1.7 1.9 v cc = sel = 3.3v v in = 1.5v p-p 20db attenuation % eye width = ((clock period jitter p-p)/clock period) 100% tpc 19. eye width vs. data rate; prbs 31 38.7mv/div 133.7ps/div v cc = 3.3v sel = 3.3v v in = 2v p-p 20db attenuation t a = 25 c tpc 20. eye pattern; 1.244 gbps, v cc = 3.3 v, prbs 31 20mv/div 166.3ps/div v cc = 2.5v sel = 2.5v v in = 1v p-p 20db attenuation t a = 25 c tpc 21. eye pattern; 1 gbps, v cc = 2.5 v, prbs 31
rev. 0 e8e adg3249 for the following load circuit and waveforms, the notation that is used is v in and v out where vv and v v or v v and v v in a out b in b out a ==== control input en 0v t plh v out v t v ih v h v t v l t plh figure 2. propagation delay v cc v in v out c l r l r l sw1 gnd 2 v cc r t dut pulse generator notes pulse generator for all pulses: t r 2.5ns, t f 2.5ns, frequency 10mhz. c l includes board, stray, and load capacitances. r t is the termination resistor, should be equal to z out of the pulse generator. figure 1. load circuit timing measurement information enable disable control input en v in = 0v v in = v cc v out sw1 @ 2v cc v out sw1 @ gnd t plz t pzh t phz t pzl v t 0v v cc v t v h v h ? v l v l + v v cc 0v v t v inh 0v figure 3. enable and disable times table iii. switch position test s1 t plz , t pzl 2 v cc t phz , t pzh gnd test conditions symbol v cc = 3.3 v 0.3 v ( sel sel sel l 300 150 150 mv c l 50 30 30 pf v t 1.5 0.9 0.9 v
rev. 0 adg3249 e9e bus switch applications mixed voltage operation, level translation bus switches can provide an ideal solution for inter facing between mixed voltage systems. the adg3249 is suitable for applications where voltage translation from 3.3 v technology to a lower voltage technology is needed. this device can translate from 2.5 v to 1.8 v, or bidirectionally from 3.3 v directly to 2.5 v. figure 4 shows a block diagram of a typical application in which a user needs to interface between a 3.3 v adc and a 2.5 v microprocessor. the microprocessor may not have 3.3 v toler- ant inputs, therefore placing the adg3249 between the two devices allows the devices to communicate easily. the bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. 3.3v adc 2.5v 3.3v 2.5v microprocessor adg3249 3.3v figure 4. level translation between a 3.3 v adc and a 2.5 v microprocessor 3.3 v to 2.5 v translation when v cc is 3.3 v ( sel = 3.3 v) and the input signal range is 0 v to v cc , the maximum output signal will be clamped to within a voltage threshold below the v cc supply. in this case, the output will be limited to 2.5 v, as shown in f igure 6. this device can be used for translation from 2.5 v to 3.3 v devices and also between two 3.3 v devices. adg3249 2.5v 2.5v 3.3v 2.5v 3.3v figure 5. 3.3 v to 2.5 v voltage translation, sel v in 2.5v v out 0v 3.3v s witch input s witch ou tput 3.3v supply sel = 3.3v figure 6. 3.3 v to 2.5 v voltage translation, sel 2.5 v to 1.8 v translation when v cc is 2.5 v ( sel = 2.5 v) and the input signal range is 0 v to v cc , the maximum output signal will, as before, be clamped to within a voltage threshold below the v cc supply. in this case, the output will be limited to approximately 1.8 v, as shown in figure 8. adg3249 1.8v 2.5v 2.5v figure 7. 2.5 v to 1.8 v voltage translation, sel v in 1.8v v out 0v 2.5v s witch input s witch ou tput 2.5v supply sel = 2.5v figure 8. 2.5 v to 1.8 v voltage translation, sel 3.3 v to 1.8 v translation the adg3249 offers the option of interfacing between a 3.3 v device and a 1.8 v device. this is possible through use of the sel pin. the sel pin is an active low control pin. sel acti- vates internal circuitry in the adg3242 that allows voltage translation betw een 3.3 v devices and 1.8 v devices. when v cc is 3.3 v and the input signal range is 0 v to v cc , the maximum output signal will be clamped to 1.8 v, as shown in figure 9. to do th is, the sel pin must be tied to logic 0. if sel is unused, it should be tied directly to v cc . adg3249 1.8v 3.3v 3.3v figure 9. 3.3 v to 1.8 v voltage translation, sel v in 1.8v v out 0v 3.3v s witch input s witch ou tput 3.3v supply sel = 0v figure 10. 3.3 v to 1.8 v voltage translation, sel
rev. 0 e10e adg3249 analog switching bus switches can be used in many analog switching applications, for example, video graphics. bus switches can have lower on resistance, smaller on and off channel capacitance, and thus improved frequency performance than their analog counterparts. the bus switch channel itself, consisting solely of an nmos switch, limits the operating voltage (see tpc 1 for a typical plot), but in many cases, this does not present an issue. multiplexing many systems, such as docking stations and memory banks, have a large number of common bus signals. common prob- lems faced by designers of these systems include ? large delays caused by capacitive loading of the bus ? noise due to simultaneous switching of the address and data bus signals figure 11 shows an array of memory banks in which each ad- dress and data signal is loaded by the sum of the individual loads. if a bus switch is used as shown in figure 12, the output load on the memory address and data bits is halved. the speed at which the selected bank memory address data memory bank b memory bank c memory bank d memory bank a figure 11. all memory banks are permanently connected to the bus memory address data memory b ank b memory b ank c memory b ank d memory b ank a adg3249 adg3249 figure 12. adg3249 used to reduce both access time and noise
rev. 0 adg3249 e11e outline dimensions 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters 1 3 5 6 2 8 4 7 2.90 bsc pin 1 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.22 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc compliant to jedec standards mo-178ba
c04403?10/03(0) ?2

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