1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 satellite applications flow? (saf) is a trademark of intersil corporation. hs-1840arh-t radiation hardened 16 channel cmos analog multiplexer with high-z analog input protection intersils satellite applications flow tm (saf) devices are fully tested and guaranteed to 100krad total dose. these qml class t devices are processed to a standard ?ow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. the hs-1840arh-t is a radiation hardened, monolithic 16 channel multiplexer constructed with the intersil rad-hard silicon gate, dielectric isolation process. it is designed to provide a high input impedance to the analog source if device power fails (open), or the analog signal voltage inadvertently exceeds the supply by up to 35v, regardless of whether the device is powered on or off. selection of one of sixteen channels is controlled by a 4-bit binary address plus an enable-inhibit input, which conveniently controls the on/off operation of several multiplexers in a system. all inputs have electrostatic discharge protection. speci?cations speci?cations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed below must be used when ordering. detailed electrical speci?cations for the hs-1840arh-t are contained in smd 5962-95630. a hot-link is provided from our website for downloading . www.intersil.com/spacedefense/newsafclasst.asp intersils quality management plan (qm plan), listing all class t screening operations, is also available on our website. www.intersil.com/quality/manuals.asp features ? qml class t, per mil-prf-38535 ? radiation performance - gamma dose ( g ) 1 x 10 5 rad(si) - no latch-up, dielectrically isolated device islands ? improved r ds(on) linearity ? improved access time 1.5 m s (max) over temp and rad ? high analog input impedance 500m w during power loss (open) ? 35v input over voltage protection (power on or off) ? excellent in hi-rel redundant systems ? break-before-make switching pinouts HS1-1840ARH-t (sbdip), cdip2-t28 top view hs9-1840arh-t (flatpack) cdfp3-f28 top view ordering information ordering number part number temp. range ( o c) 5962r9563002txc HS1-1840ARH-t -55 to 125 HS1-1840ARH/proto HS1-1840ARH/proto -55 to 125 5962r9563002tyc hs9-1840arh-t -55 to 125 hs9-1840arh/proto hs9-1840arh/proto -55 to 125 note: minimum order quantity for -t is 150 units through distribution, or 450 units direct. +v s nc nc in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd (+5v s ) v ref addr a3 out in 8 in 7 in 6 in 5 in 3 in 1 enable addr a0 addr a1 addr a2 -v s in 4 in 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +v s nc nc in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd (+5v s ) v ref addr a3 out -v s in 8 in 7 in 6 in 5 in 4 in 3 in 2 in 1 enable addr a0 addr a1 addr a2 data sheet july 1999 file number 4589.1
2 functional diagram truth table a3 a2 a1 a0 en on channel xxxxh none lllll 1 lllhl 2 llhll 3 llhhl 4 lhlll 5 lhlhl 6 lhhll 7 lhhhl 8 hllll 9 hllhl 10 hlhll 11 hlhhl 12 hhlll 13 hhlhl 14 hhhl l 15 hhhhl 16 p en in 1 out in 16 digital address decoders address input buffer and level shifter multiplex switches a0 a1 a2 p a3 1 16 hs-1840arh-t
3 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: (2820 m m x 4080 m m x 483 m m 25.4 m m) 111 x 161 x 19mils 1mil metallization: type: al si cu thickness: 16.0k ? 2k ? substrate potential: unbiased (di) backside finish: silicon passivation: type: nitride (si 3 n 4 ) over silox (s i o 2 ) nitride thickness: 4.0k ? 0.5k ? silox thickness: 12.0k ? 1.3k ? worst case current density: < 2.0e5 a/cm 2 transistor count: 407 process: radiation hardened silicon gate, dielectric isolation metallization mask layout hs-1840arh-t in7 in6 in5 in4 in3 in2 in1 enable a0 a1 a2 a3 v ref gnd in8 -v out +v in16 in15 in14 in13 in12 in11 in10 in9 hs-1840arh-t
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