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? 02.1 2 .06 12345 i 2 c - bus real - time clock ics with battery backup switch - over function r2051 series 12345 rev.1.04 - 1 - n outline the r 20 5 1 is a cmos real - time clock ic connected to the cpu by two signal lines, scl and s da, and configured to perform serial transmission of time and calendar data to the cpu. further, battery backup switchover circuit and a voltage detector. the periodic interrupt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. the 2 alarm interrupt circuits generate interrupt signals at preset times. as the oscillation circuit is driven unde r constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (typ. 0.4 m a at 3 v ). the oscillation halt sensing circuit can be used to judge the validity of internal data in such events as power - on; the supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. the 32 - khz clock output function ( cmos output) is intended to output sub - clock pulses for th e external microcomputer. the oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator. battery backup switchover function is the automatic switchov er circuit between a main power supply and a backup battery of primary or secondary battery. switchover is executed by monitoring the voltage of a main power supply, therefore the voltage of a backup battery voltage is not relevant. this model come s in an ultra - compact ffp12 ( height 0.85mm, 2.0mm 2.0mm ). n features l minimum timekeeping supply voltage typ. 0.75v (max. 1.00v); vdd pin l low power consumption 0.4 m a typ ( 1.0 m a max . ) at vdd=3 v l built - in backup switchover circuit (can be used for a primary battery , a secondary battery, or an electric double layer capacitor) l only two signal lines (scl and s da ) required for connection to the cpu. ( i 2 c - bus interface, 400khz) l time counters (counting hours, minutes, and seconds) and calendar counters (counting yea rs, months, days, and weeks) (in bcd format) l interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to the cpu and provided with an interrupt flag and an interrupt halt l 2 alarm interrupt circuits (a larm_w for week, hour, and minute alarm settings and alarm_d for hour and minute alarm settings) l built - in voltage detector with delay l with power - on flag to prove that the power supply starts from 0v l 32 - khz clock output pin ( cmos output. ? h ? level is always equal to vcc. ) l supply voltage monitoring circuit with two supply voltage monitoring threshold settings l automatic identification of leap years up to the year 2099 l selectable 12 - hour and 24 - hour mode settings l built - in oscillation stabilization capacitor s (cg and cd) l high precision oscillation adjustment circuit l cmos process l ultra - compact ffp12 n pin configuration vdd vcc sda vss top view R2051K(ffp12) vsb /vdcc scl clkout cin oscin oscout /intr 10 11 12 1 2 3 4 7 5 6 9 8
r 20 5 1 series 12345 rev.1.04 - 2 - n block diagram oscout vss vdd /intr cpu power suplly oscin vcc vsb cpu real time clock sda scl c3 battery voltage monitor /vdcc voltage detector sw1 sw2 clkout c2 r1 level shifter delay cin voltage re ference c1 n selection guide in the r2 051xxx series , output voltage and options c an be designated. part number is designated as follows: r2 051k01 - e2 ? part number - - - r2 051abb - cc code description a designation of the package. k: ffp12 s: ssop16 bb serial number of voltage detector se tting etc. cc designation of the taping type. only e2 is available. *) i 2 c - bus is a trademark of philips n.v. purchase of i 2 c - bus components of ricoh company, ltd. conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. part number package - vdet1 R2051K01 - e2 ffp12 2.40(typ .) R2051K02 - e2 ffp12 2.70(typ . )
r 20 5 1 series 12345 rev.1.04 - 3 - n pin description symbol item description scl serial clock line the scl pin is used to input clock pulses synchronizing the input and outpu t of data to and from the sda pin. allows a maximum input voltage of 5.5 volts regardless of supply voltage. sda serial data line the s da pin is used to input or output data intended for writing or reading in synchronization with the scl pin. up to 5.5v beyond vdd may be input. this pin functions as an nch open drain output. /intr interrupt output the /intr pin is used to output alarm interrupt (alarm_w) and alarm interrupt (alarm_d) and output periodic interrupt signals to the cpu signals. disabled at power - on from 0 v . nch. open drain output. clkout 32khz clock output the cl kout pin is used to output 32.768 - khz clock pulses. cmos output. ? h ? level is always equal to vcc. vcc main battery input supply power to the ic. vsb power supply input for bac kup battery connect a primary battery for backup. normally, power is supplied from vcc to the ic. if vcc level is equal or less than ? vdet1, power is supplied from this pin. oscin oscout oscillation circuit input / output the oscin and oscout pins are us ed to connect the 32.768 - khz crystal oscillator (with all other oscillation circuit components built into the R2051K series ). vdd positive power supply input the vdd pin is connected to the power supply. connect a capacitor as much as 0.1 m f between vdd and vss. in the case of using a secondary battery, connecting the secondary battery to this pin is possible. /vdcc vcc power supply monitoring result output while monitoring vcc power supply, if the voltage is equal or lower than ? vdet1, this output l evel is ? l ? . when /vdcc becomes ? l ? , sw1 turns off and sw2 turns on. as a result, power is supplied from vsb pin to the internal real time clock. when vcc is equal to +vdet1 or more, sw1 turns on and sw2 turns off. after t delay passed, /vdcc output becom es off, or ? h ? . nch open - drain output. cin noise bypass pin to stabilize the internal reference, connect a capacitor as much as 0.1uf between this pin and vss. vss negative power supply input the vss pin is grounded.
r 20 5 1 series 12345 rev.1.04 - 4 - n absolute maximum ratings (v ss=0v) symbol item pin name description unit vcc supply voltage 1 vcc - 0.3 to +6. 5 v vdd supply voltage 2 vdd - 0.3 to +6.5 v vsb supply voltage 3 vsb - 0.3 to +6.5 v input voltage 1 scl, sda - 0.3 to +6.5 v vi input voltage 2 cin - 0.3 to vdd+0.3 v output voltage 1 /intr , /vdcc - 0.3 to + 6.5 v vo output voltage 2 clkout - 0.3 to v cc +0.3 v iout maximum output current vdd 10 ma pd power dissipation topt = 25 c 300 mw topt operating temperature - 40 to + 85 c tstg storage temperature - 55 to +125 c n recommended operating conditions ( vss=0v , topt= - 40 to + 85 c ) symbol item pin name min, typ. max. unit v access supply voltage vcc power supply voltage for interfacing with cpu - vdet1 *1) 5.5 v vclk minimum timekeeping voltage cgout,cdout=0 pf *2), *3) 0.75 1.00 v fxt oscillation frequency 32.768 khz vpup pull - up voltage /intr, /vdcc 5.5 v *1) - vdet1 in vaccess specification is guaranteed by design. *2) cgout is connected between oscin and vss, cdout is connected between oscout a nd vss. r2051 series incorporates the capacitors between oscin and vss, between oscout and vss. then normally , cgout and cdout are not necessary. *3) crystal oscillator: cl=6 - 8pf, r1=30k w
r 20 5 1 series 12345 rev.1.04 - 5 - n dc electrical characteristics l R2051K01 (unless otherwise specified : vss=0v,v cc=v sb=3 .0 v, 0.1uf between vdd and vss, cin and vss, topt= - 40 to + 85 c) symbol item pin name conditions min. typ. max. unit vih ? h ? input voltage 0.8 x v cc 5.5 vil ? l ? input voltage scl ,sda - 0.3 0. 2x v cc v ioh ? h ? output curr ent clkout voh=vcc - 0.5v - 0.5 ma iol 1 clkout 0.5 iol2 /intr 2.0 iol4 sda vol=0.4v 3.0 iol3 ? l ? output current /vdcc vdd,vsb,vcc=2.0v vol=0.4v 0.5 ma iil input leakage current scl vi= 5.5 v or vss - 1 .0 1 .0 m a ioz1 output off - state cu rrent 1 sda vo=5.5v or vss - 1.0 1.0 m a ioz 2 output off - state current 2 /intr, /vdcc vo= 5.5 v or vss - 1 .0 1.0 m a isb time keeping current at backup mode vsb vcc=0v, vsb=3.0v, vdd, output=open 0.4 1.0 m a isbl leakage current of backup pin at vcc_on vsb vcc=3.0v, vsb=5.5v or 0v, vdd, output=open - 1.00 1.00 m a vdeth supply voltage monitoring voltage ? h ? v sb topt= 25 c 1.90 2.1 0 2. 30 v vdetl supply voltage monitoring voltage ? l ? vdd topt= 25 c 1. 20 1. 35 1. 50 v - vdet1 detector threshold voltage (falling edge of vcc) vcc topt= 25 c 2.34 2.40 2.46 v +vdet1 detector released voltage (rising edge of vcc) vcc topt= 25 c 2.44 2.52 2.60 v d vdet d topt detector threshold and released voltage temperature coefficient vcc, vsb topt= - 40 to 85 c *1) 100 p pm / c vdd out1 vdd output voltage 1 vdd topt= 25 c, vcc=3.0v, iout=1.0ma vcc - 0.12 vcc - 0.04 v vdd out2 vdd output voltage 2 vdd topt= 25 c, vcc=2.0v, vsb=3.0v, iout=0.1ma vsb - 0.08 vsb - 0.02 v cg internal oscillation capacitance 1 oscin 10 cd i nternal oscillation capacitance 2 oscout 10 pf *1) guaranteed by design.
r 20 5 1 series 12345 rev.1.04 - 6 - l R2051K02 (unless otherwise specified : vss=0v,v cc=v sb=3 .3 v, 0.1uf between vdd and vss, cin and vss, topt= - 40 to + 85 c) symbol item pin name conditions min. typ. max. unit vih ? h ? input voltage 0.8 x v cc 5.5 vil ? l ? input voltage scl ,sda - 0.3 0. 2x v cc v ioh ? h ? output current clkout voh=vcc - 0.5v - 0.5 ma iol 1 clkout 0.5 iol2 /intr 2.0 iol4 sda vol=0.4v 3.0 iol3 ? l ? output current /vdcc vd d,vsb,vcc=2.0v vol=0.4v 0.5 ma iil input leakage current scl vi= 5.5 v or vss - 1 .0 1 .0 m a ioz1 output off - state current 1 sda vo=5.5v or vss - 1.0 1.0 m a ioz 2 output off - state current 2 /intr, /vdcc vo= 5.5 v or vss - 1 .0 1.0 m a isb time keeping curren t at backup mode vsb vcc=0v, vsb=3.0v, vdd, output=open 0.4 1.0 m a isbl leakage current of backup pin at vcc_on vsb vcc=3.3v, vsb=5.5v or 0v, vdd, output=open - 1.00 1.00 m a vdeth supply voltage monitoring voltage ? h ? v sb topt= 25 c 1.90 2.1 0 2. 30 v vdetl supply voltage monitoring voltage ? l ? vdd topt= 25 c 1. 20 1. 35 1. 50 v - vdet1 detector threshold voltage (falling edge of vcc) vcc topt= 25 c 2.73 2.80 2.87 v +vdet1 detector released voltage (rising edge of vcc) vcc topt= 25 c 2.85 2.94 3.03 v d vdet d topt detector threshold and released voltage temperature coefficient vcc, vsb topt= - 40 to 85 c *1) 100 ppm / c vdd out1 vdd output voltage 1 vdd topt= 25 c, vcc=3.3v, iout=1.0ma vcc - 0.12 vcc - 0.04 v vdd out2 vdd output voltage 2 vdd topt= 25 c, vcc=2.0v, vsb=3.3v, iout=0.1ma vsb - 0.08 vsb - 0.02 v cg internal oscillation capacitance 1 oscin 10 cd internal oscillation capacitance 2 oscout 10 pf *1) guaranteed by design.
r 20 5 1 series 12345 rev.1.04 - 7 - n ac electrical characteristics unless otherwise specified: vss=0 v,topt= - 40 to +85 c input and output conditions: vih=0.8 vcc,vil=0.2 vcc,voh=0.8 vcc,vol=0.2 vcc,cl=50pf vcc 3 1.7 v *1) vcc 3 2.5 v *1) sym - bol item condi - tions min. typ. max. min. typ. max. unit f scl scl clock frequency 100 400 khz t low scl cloc k low time 4.7 1.3 m s t high scl clock high time 4.0 0.6 m s t hd;sta start condition hold time 4.0 0.6 m s t su;sto stop condition set up time 4.0 0.6 m s t su;sta start condition set up time 4.7 0.6 m s t su;dat data set up time 250 200 ns t hd;dat data hold time 0 0 ns t pl;dat sda ? l ? stable time after falling of scl 2.0 0.9 m s t pz;dat sda off stable time after falling of scl 2.0 0.9 m s t r rising time of scl and sda (input) 1000 300 n s t f falling time of scl and sda (input) 300 300 n s t sp spike width that can be removed with input filter 50 50 ns t rcv recovery time from stop condition to start condition 62 62 m s t delay output delay time of voltage detector time keeping 100 105 110 100 105 110 ms *1) vcc voltage interfacing with cpu is defined by vaccess (p. 4 n recommended operating conditions ) *) for reading/writing timing, see ? p. 29 n interfacing with the cpu l data transmission under special condition ? . sda(out) scl s sr p t pz ;dat t high t su ;dat t hd ;sta t sp t su ;sto t low t su ;sta sda(in) t hd ;sta t pl ;dat sr p stop condition s start condition repeated start condition t hd ;dat
r 20 5 1 series 12345 rev.1.04 - 8 - /vdcc vcc t delay +vdet1
r 20 5 1 series 12345 rev.1.04 - 9 - n package dimensions l r 20 5 1kxx 9 7 6 4 3 1 10 12 1pin index 2.0 0.1 0.2 0.15 0.35 2.0 0.1 2pin index 0.5 0.3 0.15 0.103 0.25 0.35 1.0max 0.27 0.15 (bottom view) 0.5 0.05 0.17 0.1
r 20 5 1 series 12345 rev.1.04 - 10 - n general description l battery backup switchover function the r2051 series have two power supply input, or vcc and vsb. with monitoring input voltage of vcc pin by internal voltage detector, it is selected which power supply of vcc or vsb is used for the int ernal power source. refer to the next table to see the state of the backup battery and internal power supply ? s state of the ic by each condition. vcc 3 vdet1 vcc < vdet1 vcc ? rtc, vdd /vdcc=off(h) vsb ? rtc, vdd /vdcc=l as a backup battery, not only a primary battery such as cr2025, lr44, or a secondary battery such as ml614, tc616, but also an electric double layered capacitor or an aluminum capacitor can be used. switchover point is judged with the voltage of the main power (vcc), therefore, if the backup vo ltage is higher than main supply voltage, switchover can be realized without extra load to the backup power supply. vdd vsb vcc vss 0.1 m f cpu power supply the case of back - up by primary battery cr2025 etc. vsb vdd vcc vss 0.1 m f cpu power supply ml614 etc. the case of back - up by capacitor or secondary battery (charging voltage is equal to cpu power supply voltage) vsb vdd vcc vss 0.1 m f cpu power supply (3v) 5v double layer capacitor etc. the case of back - up by capacitor or secondary battery (charging voltage is not equal to cpu power supply voltage) l interface with cpu the r 20 5 1 is connected to the cpu by two signa l lines scl and s da , through which it read s and write s data from and to the cpu. since the output of the i/o pin of sda is open drain, data interfacing with a cpu different supply voltage is possible by applying pull - up resistors on the circuit board. the maximum clock frequency of 400khz (at vdd=3v) of scl enables data transfer in i2c - bus fast mode. vcc falls down under - vdet1, the r2051 stops accessing with cpu. l clock and calendar function the r 20 5 1 read s and write s time data from and to the cpu in unit s ranging from seconds to the last two digits of the calendar year. the calendar year will automatically be identified as a leap year when its last two digits are a multiple of 4. consequently, leap years up to the year 2099 can automatically be identifie d as such. *) the year 2000 is a leap year while the year 2100 is not a leap year.
r 20 5 1 series 12345 rev.1.04 - 11 - l alarm function the r 2051 incorporate s the alarm interrupt circuit configured to generate interrupt signals to the cpu at preset times. the alarm interrupt circuit allows two types of alarm settings specified by the alarm_w registers and the alarm_d registers. the alarm_w registers allow week, hour, and minute alarm settings including combinations of multiple day - of - week settings such as "monday, wednesday, and friday" and "saturday and sunday". the alarm_d registers allow hour and minute alarm settings. the alarm_w outputs from /intr pin, and the alarm_d outputs also from /intr pin. each alarm function can be checked from the cpu by using a polling function. l high - precisio n oscillation adjustment function the r 20 5 1 has built - in oscillation stabilization capacitors (cg and cd), that can be connected to an external crystal oscillator to configure an oscillation circuit. two kinds of accuracy for this function are alternatives . to correct deviations in the oscillato r frequency of the crystal, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to 1.5 ppm or 0.5 ppm at 25 c) from the cpu . the maximum range is approximately 189pp m (or 63 ppm) in increments of approximately 3ppm (or 1ppm) . such oscillation frequency adjustment in each system has the following advantages: * allows timekeeping with much higher precision than conventional rtcs while using a crystal oscillator with a wide range of precision variations. * corrects seasonal frequency deviations through seasonal oscillation adjustment. * allows timekeeping with higher precision particularly with a temperature sensing function out of rtc, through oscillation adjustment in tune with temperature fluctuations. l power - on reset, oscillation halt sensing function and supply voltage monitoring function the r2051 has 3 power supply pins (vcc, vsb, vdd), among them, vcc pin and vdd pin have monitoring function of supply v oltage. vcc power supply monitoring circuit makes /vdcc pin ? l ? when vcc power supply pin becomes equal or lower than ? vdet1. at the power - on of vdd, this circuit makes /vdcc pin turn off, or ? h ? after the delay time, tdelay from when the vcc power supply pin becomes equal or more than +vdet1. the r 20 5 1 incorporate s an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt, the oscillation halt sensing circuit , vdd monitoring flag, and power - on reset flag are useful for judging the validity of time data. power on reset function reset the control resisters when the system is powered on from 0v. at the same time, the fact is memorized to the resister as a flag, thereby identifying whether they are po wered on from 0 v or battery backed - up. the r 2051 also incorporate s a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. supply voltage monitoring threshold s ettings can be selected between 2.1 v and 1. 35v through internal register settings. the sampling rate is normally 1s. the oscillation halt sensing circuit is configured to confirm the established invalidation of time data in contrast to the supply voltage m onitoring circuit intended to confirm the potential invalidation of time data. further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring. l periodic interrupt function the r 20 5 1 incorporate s the periodic interrupt c ircuit configured to generate periodic interrupt signals aside from interrupt signals generated by the alarm interrupt circuit for output from the / intr pin. periodic interrupt signals have five selectable frequency settings of 2 hz (once per 0.5 seconds), 1 hz (once per 1 second), 1/60 hz (once per 1 minute), 1/3600 hz (once per 1 hour), and monthly (the first day of every month). further, periodic interrupt signals also have two selectable waveforms , a normal pulse form (with a frequency of 2 hz or 1 hz) and special form adapted to interruption from the cpu in the level mode (with second, minute, hour, and month interrupts). the condition of periodic interrupt signals can be monitored with using a polling function. l 32khz clock output the r 20 5 1 incorporat e s a 32 - khz clock circuit configured to generate clock pulses with the oscillation frequency of a 32.768khz crystal oscillator for output from the cl kout pin ( cmos push - pull output). the 32 - khz clock output is always enabled and the ? h ? level of the clkout pin is same as vcc power supply.
r 20 5 1 series 12345 rev.1.04 - 12 - n a ddress mapping address register name d a t a a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 second counter - *2) s40 s20 s10 s8 s4 s2 s1 1 0 0 0 1 minute counter - m40 m20 m10 m8 m4 m2 m1 2 0 0 1 0 hour counter - - h20 p /a h10 h8 h4 h2 h1 3 0 0 1 1 day - of - week counter - - - - - w4 w2 w1 4 0 1 0 0 day - of - month counter - - d20 d10 d8 d4 d2 d1 5 0 1 0 1 month counter and century bit /19 20 - - m o 10 mo8 mo4 mo2 mo1 6 0 1 1 0 year count er y80 y40 y20 y10 y8 y4 y2 y1 7 0 1 1 1 oscillation adjustment register *3) dev *4) f6 f5 f4 f3 f2 f1 f0 8 1 0 0 0 alarm_w ( minute register ) - wm40 wm20 wm10 wm8 wm4 wm2 wm1 9 1 0 0 1 alarm_w ( hour register ) - - wh20 wp / a wh10 wh8 wh 4 w h2 w h 1 a 1 0 1 0 alarm_w ( day - of - week register ) - ww6 ww5 ww4 ww3 ww2 ww1 ww0 b 1 0 1 1 alarm_d ( minute register ) - dm40 dm20 dm10 dm8 dm4 dm2 dm1 c 1 1 0 0 alarm_d ( hour register ) - - dh20 dp /a dh10 dh8 dh4 dh2 dh1 d 1 1 0 1 - - - - - - - - e 1 1 1 0 contro l register 1 *3) wale dale /12 24 scra tch2 test ct2 ct1 ct0 f 1 1 1 1 control register 2 *3) vdsl vdet /xst pon *5) scra tch1 ctfg wafg dafg notes: * 1) all the data listed above accept both reading and writing. * 2) the data marked with " - " is in valid for writing and reset to 0 for reading. * 3) when the pon bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register, control register 1 and control register 2 excluding the / xst bit. * 4) when de v=0, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to 1.5 ppm . when dev=1, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to or 0.5 ppm . * 5) pon is a power - on - reset flag.
r 20 5 1 series 12345 rev.1.04 - 13 - n register settings l control register 1 (address eh) d7 d6 d5 d4 d3 d2 d1 d0 wale dale /12 24 scra tch2 test ct2 ct1 ct0 ( for writing ) wale dale /12 24 scra tch2 test ct2 ct1 ct0 (for reading) 0 0 0 0 0 0 0 0 default settin gs *) *) default settings: default value means read / written values when the pon bit is set to ? 1 ? due to vdd power - on from 0 volts. (1) w ale, dale alarm_w enable bit, alarm_d enable bit w ale,dale description 0 disabling the ala rm interrupt circuit (under the control of the settings of the alarm_w registers and the alarm_d registers). ( default) 1 enabling the alarm interrupt circuit (under the control of the settings of the alarm_w registers and the alarm_d registers) (2) /12 24 / 12 - 24 - hour mode selection bit /12 24 description 0 selecting the 12 - hour mode with a.m. and p.m. indications. (default) 1 selecting the 24 - hour mode setting the /12 24 bit to 0 and 1 specifies the 12 - hour mode and the 24 - hour mode, respectively. 24 - hour mode 12 - hour mode 24 - hour mode 12 - hour mode 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7 ) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) setting the /12 24 bit should precede writing time data (3) scratch2 scratch bit 2 scratch2 description 0 (default) 1 the s cratch 2 bit is intended for scratching and accepts the reading and writing of 0 and 1. the scratch 2 bit will be set to 0 when the pon bit is set to 1 in the control register 1. (4) test test bit test description 0 normal operation mode. (default) 1 test mode. the test bit is used only for testing in the factory and should normally be set to 0.
r 20 5 1 series 12345 rev.1.04 - 14 - (5) ct2, ct1, and ct0 periodic interrupt selection bits description ct2 ct1 ct0 wave form mode interrupt cycle and falling timing 0 0 0 - off(h) (def ault) 0 0 1 - fixed at ? l ? 0 1 0 pulse mode *1) 2hz (duty50% ) 0 1 1 pulse mode *1) 1hz (duty50%) 1 0 0 level mode *2) once per 1 second (synchronized with second counter increment) 1 0 1 level mode *2) once per 1 minute (at 00 seconds of every min ute) 1 1 0 level mode *2) once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode *2) once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) * 1) pulse mode: 2 - hz and 1 - hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below. /intr pin rewriting of the second counter ctfg bit approx. 9 2 m s ( increment of second counter ) in the pulse mode, the increment of the second counter is delayed by approximately 92 m s from the falling edge of clock pu lses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real - time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the /intr pin low. * 2) level mode: p eriodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of the second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below. ( increment of second counter ) setting ctfg bit to 0 setting ctfg bit to 0 ( increment of second counter ) ( increment of second counter ) ctfg bit /intr pin *1 ), *2) when the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec . or 60sec. as follows: pulse mode: the ?l? period of output pulses will increment or decrement by a maximum of 3.784 ms. for example, 1 - hz clock pulses will have a duty cycle of 50 0.3784%.
r 20 5 1 series 12345 rev.1.04 - 15 - level mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784 ms. l control register 2 (address fh) d7 d6 d5 d4 d3 d2 d1 d0 vdsl vdet /xst pon scra tch1 ctf g wafg dafg ( for writ ing ) vdsl vdet /xst pon scra tch1 ctfg wafg dafg ( for read ing ) 0 0 indefinite 1 0 0 0 0 default settings * ) *) default settings: default value means read / written values when the pon bit is set to ? 1 ? due to vdd power - on from 0 volts. (1) vdsl vdd supply voltage monitoring threshold selection bit vdsl description 0 selecting the vdd supply voltage monitoring threshold setting of 2.1v . (default) 1 selecting the vdd supply voltage monitoring threshold setti ng of 1.35 v . the vdsl bit is intended to select the vdd supply voltage monitoring threshold settings. (2) vdet supply voltage monitoring result indication bit vdet description 0 indicating supply voltage above the supply voltage monitoring threshold settings. (default) 1 indicating supply voltage below the supply voltage monitoring threshold settings. once the vdet bit is set to 1, the supply voltage monitoring circuit will be disabled while the vdet bit will hold the setting of 1. the vdet bit a ccepts only the writing of 0, which restarts the supply voltage monitoring circuit. conversely, setting the vdet bit to 1 causes no event. (3) /xst oscillation halt sensing monitor bit /xst description 0 sensing a halt of oscillation 1 sensing a no rmal condition of oscillation the /xst accepts the reading and writing of 0 and 1. the /xst bit will be set to 0 when the oscillation halt sensing . the / xst bit will hold 0 even after the restart of oscillation. (4) pon power - on - reset flag bit pon description 0 normal condition 1 detecting vdd power - on - reset (default) the pon bit is for sensing power - on reset condition . * the pon bit will be set to 1 when vdd power - on from 0 volts. the pon bit will hold the setting of 1 even after power - on . * when the pon bit is set to 1, all bits will be reset to 0 , in the oscillation adjustment register, control register 1, and control register 2, except /xst and pon. as a result, /intr pin stops outputting . * the pon bit accepts only the writing of 0. conversely, setting the pon bit to 1 causes no event. (5) scratch1 scratch bit 1 scratch1 description 0 (default) 1 the scratch 1 bit is intended for scratching and accepts the reading and writing of 0 and 1. the scratch 1 bit will be set to 0 when the pon bit is set to 1 in the control register 2.
r 20 5 1 series 12345 rev.1.04 - 16 - (6) ctfg periodic interrupt flag bit ctfg description 0 periodic interrupt output = ? h ? (default) 1 periodic interrupt output = ? l ? the ctfg bit is set to 1 when the periodic interrupt signa ls are output from the /intr pin (?l?). the ctfg bit accepts only the writing of 0 in the level mode, which disables (?h?) the /intr pin until it is enabled (?l?) again in the next interrupt cycle. conversely, setting the ctfg bit to 1 causes no event. (7) wafg,dafg alarm_w flag bit and alarm_d flag bit w afg,dafg description 0 indicating a mismatch between current time and preset alarm time (default) 1 indicating a match between current time and preset alarm time the wafg and dafg bits are valid o nly when the wale and dale have the setting of 1, which is caused approximately 61 m s after any match between current time and preset alarm time specified by the alarm_w registers and the alarm_d registers. the wafg (da fg) bit accept s only the writing of 0 . /intr pin outputs off ( ? h ? ) when this bit is set to 0. and /intr pin outputs ?l? again at the next preset alarm time. conversely, setting the wafg and dafg bits to 1 causes no event. the wafg and dafg bits will have the reading of 0 when the alarm in terrupt circuit is disabled with the wale and dale bits set to 0. the settings of the wafg and dafg bits are synchronized with the output of the /intr pin as shown in the timing chart below . /intr pin writing of 0 to wafg(dafg) bit wafg(dafg) bit (match between current time and preset alarm time) approx. 61 m s approx. 61 m s writing of 0 to wafg(dafg) bit (match between current time and preset alarm time) (match between current time and preset alarm time)
r 20 5 1 series 12345 rev.1.04 - 17 - l time counter (address 0 - 2h ) second counter (address 0h) d7 d6 d5 d4 d3 d2 d1 d0 - s40 s20 s10 s8 s4 s2 s1 ( for writing) 0 s40 s20 s10 s8 s4 s2 s1 ( for read ing ) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) minute counter ( add ress 1h) d7 d6 d5 d4 d3 d2 d1 d0 - m40 m20 m10 m8 m4 m2 m1 ( for writ ing ) 0 m40 m20 m10 m8 m4 m2 m1 ( for read ing ) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) hour counter ( address 2h) d7 d6 d5 d4 d3 d2 d1 d0 - - p /a o r h20 h10 h8 h4 h2 h1 ( for writ ing ) 0 0 p /a or h20 h10 h8 h4 h2 h1 ( for read ing ) 0 0 indefinite indefinite indefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / written values when the pon bit is set to ? 1 ? due to vdd power - on from 0 volts. * time digit display (bcd format) as follows: the second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00. the mi nute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00. the hour digits range as shown in " p 13 l control register 1 (address eh) (2) /12 24: / 12 - 24 - hour mode selection bit" and are carried t o the day - of - month and day - of - week digits in transition from pm11 to am12 or from 23 to 00. * any writing to the second counter resets divider units of less than 1 second. * any carry from lower digits with the writing of non - existent time may cause the time counters to malfunction. therefore, such incorrect writing should be replaced with the writing of existent time data. l day - of - week counter (address 3h ) d7 d6 d5 d4 d3 d2 d1 d0 - - - - - w4 w2 w1 ( for writ ing ) 0 0 0 0 0 w4 w2 w1 ( for read ing ) 0 0 0 0 0 indefinite indefinite indefinite default settings *) *) default settings: default value means read / written values when the pon bit is set to ? 1 ? due to vdd power - on from 0 volts. * the day - of - week counter is incremented b y 1 when the day - of - week digits are carried to the day - of - month digits. * day - of - week display (incremented in septimal notation): (w4, w2, w1) = (0, 0, 0) ? (0, 0, 1) ? ? ? (1, 1, 0) ? (0, 0, 0) * correspondences between days of the week and the day - of - wee k digits are user - definable (e.g. sunday = 0, 0, 0) * the writing of (1, 1, 1) to (w4, w2, w1) is prohibited except when days of the week are unused.
r 20 5 1 series 12345 rev.1.04 - 18 - l calendar counter (address 4 - 6h ) day - of - month counter ( address 4h ) d7 d6 d5 d4 d3 d2 d1 d0 - - d20 d10 d8 d4 d2 d1 ( for writ ing ) 0 0 d20 d10 d8 d4 d2 d1 ( for read ing ) 0 0 indefinite indefinite indefinite indefinite indefinite indefinite default settings *) month counter + century bit ( address 5h ) d7 d6 d5 d4 d3 d2 d1 d0 /19 20 - - mo10 mo8 m o4 mo2 mo1 ( for writ ing ) /19 20 0 0 mo10 mo8 mo4 mo2 mo1 ( for read ing ) indefinite 0 0 indefinite indefinite indefinite indefinite indefinite default settings *) year counter ( address 6h) d7 d6 d5 d4 d3 d2 d1 d0 y80 y40 y20 y10 y8 y4 y2 y1 ( for writ in g ) y80 y40 y20 y10 y8 y4 y2 y1 ( for read ing ) indefinite indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / written values when the pon bit is set to ? 1 ? due to vdd power - on from 0 volts. * the calendar counters are configured to display the calendar digits in bcd format by using the automatic calendar function as follows: the day - of - month digits (d20 to d1) range from 1 to 31 for j anuary, march, may, july, august, october, and december; from 1 to 30 for april, june, september, and november; from 1 to 29 for february in leap years; from 1 to 28 for february in ordinary years. the day - of - month digits are carried to the month digits i n reversion from the last day of the month to 1. the month digits (m o 10 to m o 1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. the year digits (y80 to y1) range from 00 to 99 (00, 04, 08, ? , 92, and 96 in leap year s) and are carried to the /19 20 digits in reversion from 99 to 00. the /19 20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits. * any carry from lower digits with the writing of non - existent calendar data may cause the c alendar counters to malfunction. therefore, such incorrect writing should be replaced with the writing of existent calendar data. l oscillation adjustment register (address 7h ) d7 d6 d5 d4 d3 d2 d1 d0 dev f6 f5 f4 f3 f2 f1 f0 ( for writ ing ) dev f6 f5 f 4 f3 f2 f1 f0 ( for read ing) 0 0 0 0 0 0 0 0 default settings *) *) default settings: default value means read / written values when the pon bit is set to ? 1 ? due to vdd power - on from 0 volts. dev bit when dev is set to 0, th e oscillation adjustment circuit operates 00, 20, 40 seconds. when dev is set to 1, the oscillation adjustment circuit operates 00 seconds. f6 to f0 bits the oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register at the timing set by dev .
r 20 5 1 series 12345 rev.1.04 - 19 - * the oscillation adjustment circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the oscillation adjustment re gister. * the f6 bit setting of 0 causes an increment of time counts by ((f5, f4, f3, f2, f1, f0) - 1) x 2. the f6 bit setting of 1 causes a decrement of time counts by ((/f5, /f4, /f3, /f2, /f1, /f0) + 1) x 2. the settings of "*, 0, 0, 0 , 0, 0, *" ("*" representing either "0" or "1") in the f6, f5, f4, f3, f2, f1, and f0 bits cause neither an increment nor decrement of time counts. example: if (dev, f6, f5, f4, f3, f2, f1, f0 ) is set to (0, 0, 0, 0, 0, 1, 1, 1 ), w hen the se cond digits read 00, 20, or 40, an increment of the current time counts of 32768 + (7 - 1) x 2 to 32780 (a current time count loss). if (dev, f6, f5, f4, f3, f2, f1, f0 ) is set to (0, 0, 0, 0, 0, 0, 0, 1 ), w hen the second digits read 00 , 20, 40 , neit her an increment nor a decrement of the current time counts of 32768. if (dev, f6, f5, f4, f3, f2, f1, f0 ) is set to (1, 1, 1, 1, 1, 1, 1, 0), w hen the second digits read 00, a decrement of the current time counts of 32768 + ( - 2) x 2 to 32764 (a c urrent time count gain). an increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 / (32768 x 20 = 3.051 ppm). conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3 ppm. consequently, when dev is set to ? 0 ? , deviations in time counts can be corrected with a precision of 1.5 ppm. in the same way, when dev is set to ? 1 ? , deviations in time counts can be corrected with a precision of 0.5 ppm. note that the oscillat ion adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768 - khz clock pulses. for further details, see " p 33 n configuration of oscillation circuit and correction of time count deviations l oscillation adjustment circuit".
r 20 5 1 series 12345 rev.1.04 - 20 - l alarm_w registers (address 8 - ah ) alarm_w minute register ( address 8h) d7 d6 d5 d4 d3 d2 d1 d0 - wm40 wm20 wm10 wm8 wm4 wm2 wm1 ( for writ ing ) 0 wm40 wm20 wm10 wm8 wm4 wm2 wm1 ( for read ing ) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) alarm_w hour register ( address 9h) d7 d6 d5 d4 d3 d2 d1 d0 - - wh20 wp /a wh10 wh8 wh4 wh2 wh1 ( for writ ing ) 0 0 wh20 wp /a wh10 wh8 wh4 wh2 wh1 ( for read ing ) 0 0 indefinite indefinite indefinite indefinite indefinite indefinite default settings *) alarm_w day - of - week register ( address ah) d7 d6 d5 d4 d3 d2 d1 d0 - ww6 ww5 ww4 ww3 ww2 ww1 ww0 ( for writ ing ) 0 ww6 ww5 ww4 ww3 ww2 ww1 w w0 ( for read ing ) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / written values when the pon bit is set to ? 1 ? due to vdd power - on f rom 0 volts. * the d5 bit of the alarm_w hour r egister represents wp/a when the 12 - hour mode is selected (0 for a.m. and 1 for p.m.) and w h2 0 when the 24 - hour mode is selected (tens in the hour digits). * the alarm_w registers should not have any non - existent alarm time settings. (note that any mismatch between current time and preset alarm time specified by the alarm_w registers may disable the alarm interrupt circuit.) * when the 12 - hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively . (see " p 13 l control register 1 (address eh) ( 2 ) /12 24: 12 - /24 - hour mode selection bit") * ww0 to ww6 correspond to w4, w2, and w1 of the day - of - week counter with settings ranging from (0, 0, 0) to (1, 1, 0). * ww0 to ww6 with respective settings of 0 disable the outputs of the alarm_w registers.
r 20 5 1 series 12345 rev.1.04 - 21 - example of alarm time setting alarm day - of - week 12 - hour mode 24 - hour mode preset alarm time sun. mon. tue. wed. th. fri. sat. 10 hr. 1 hr. 10 min. 1 min. 10 hr. 1 hr. 10 min. 1 min. ww0 ww1 ww2 ww3 ww4 ww5 ww6 00:00 a.m. on all days 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 01:30 a.m. on all days 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 11:59 a.m. on all days 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 00:00 p.m. on mon. to fri. 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 01:30 p.m. on sun. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 11:59 p.m. on mon. ,wed., and fri. 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 note that the correspondence between ww0 to ww6 and the days of the week shown in the above table is only an example and not mandatory. l alarm_d register (address b - c h ) alarm_d minute register ( address b h) d7 d6 d5 d4 d3 d2 d1 d0 - dm40 dm20 dm10 dm8 dm4 dm2 dm1 ( for writing) 0 dm40 dm20 dm10 dm8 dm4 dm2 dm1 ( for read ing ) 0 indefinite indefinite in definite indefinite indefinite indefinite indefinite default settings *) alarm_d hour register ( address c h) d7 d6 d5 d4 d3 d2 d1 d0 - - dh20 dp / a dh10 dh8 dh4 dh2 dh1 ( for writ ing ) 0 0 dh20 dp /a dh10 dh8 dh4 dh2 dh1 ( for read ing ) 0 0 indefinite ind efinite indefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / written values when the pon bit is set to ? 1 ? due to vdd power - on from 0 volts. * the d5 bit represents dp/a wh en the 12 - hour mode is selected (0 for a.m. and 1 for p.m.) and dh2 0 when the 24 - hour mode is selected (tens in the hour digits). * the alarm_d registers should not have any non - existent alarm time settings. (note that any mismatch between current t ime and preset alarm time specified by the alarm_d registers may disable the alarm interrupt circuit.) * when the 12 - hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively . (see " p 13 l control reg ister 1 (address eh) ( 2 ) /12 24: 12 - /24 - hour mode selection bit")
r 20 5 1 series 12345 rev.1.04 - 22 - n interfacing with the cpu the r 2051 employs the i 2 c - bus system to be connected to the cpu via 2 - wires. connection and system of i 2 c - bus are described in the following sections. l connection of i 2 c - bus 2 - wires, scl and sda pins that are connected to i 2 c - bus are used for transmit clock pulses and data respectively. all ics that are connected to these lines are designed that will not be clamped when a voltage beyond supply voltage is applied to input or output pins. open drain pins are used for output. this construction allows communication of signals between ics with different supply voltages by adding a pull - up resistor to each signal line as shown in the figure below. each ic is designed n ot to affect scl and sda signal lines when power to each of these is turned off separately. micro- controller r2051 series other peripheral device vdd1 vdd2 vdd3 vdd4 scl sda * for data interface, the following conditions must be met: vcc4 3 vcc1 vcc4 3 vcc2 vcc4 3 vcc3 * when the master is one, the micro- controller is ready for driving scl to ? h ? and rp of scl may not be required. rp rp cautions on determining rp resistance, (1) dropping voltage at rp due to sum of input current or output current at off conditions on each ic pin connected to the i 2 c - bus shall be adequately small. (2) rising time of each signal be kept short even when all capacity of the bus is driven. (3) current consumed in i 2 c - bus is small compared to the consumption current permitted for the entire system. wh en all ics connected to i 2 c - bus are cmos type, condition (1) may usually be ignored since input current and off - state output current is extremely small for the many cmos type ics. thus the maximum resistance of rp may be determined based on (2), while the minimum on (3) in most cases. in actual cases a resistor may be place between the bus and input/output pins of each ic to improve noise margins in which case the rp minimum value may be determined by the resistance. consumption current in the bus to revie w (3) above may be expressed by the formula below: bus consumption current ? (sum of input current and off state output current of all devices in standby mode ) bus standby duration bus stand - by duration + the bus operation duration + supply voltage bus operation duration 2 rp resistance 2 (bus stand - by duration + bus operation duration) + supply voltage bus capacity charging/discharging times per unit time operation of ? 2 ? in the second member denominator in the above formula is derived from assumption that ? l ? duration of sda and scl pins are the half of bus operation duration. ? 2 ? in the numerator of the same member is because there are two pins of sda and scl. the third member, (charging/discharging times p er unit time) means number of transition from ? h ? to ? l ? of the signal line. calculation example is shown below:
r 20 5 1 series 12345 rev.1.04 - 23 - pull - up resistor (rp) = 10k w , bus capacity = 50pf(both for scl, sda), vcc=3v, in a system with sum of input current and off - state output curr ent of each pin = 0.1 m a, i 2 c - bus is used for 10ms every second while the rest of 990ms in the stand - by mode, in this mode, number of transitions of the scl pin from ? h ? to ? l ? state is 100 while sda 50, every second. bus consumption current ? 0.1 m a 990m sec 990msec + 10msec + 3v 10msec 2 10k w 2 (990msec + 10msec) + 3v 50pf ( 100 + 50 ) ? 0.099 m a + 3.0 m a + 0.0225 m a ? 3.12 m a generally, the second member of the above formula is larger enough than the first and the third members bus consumption current may be determined by the second member is many cases. l transmission system of i 2 c - bus (1) start condition and stop con dition in i 2 c - bus, sda must be kept at a certain state while scl is at the ? h ? state during data transmission as shown below. scl sda tsu ;dat thd ;dat the scl and sda pins are at the ? h ? level when no data transmission is made. changing the sda from ? h ? to ? l ? when the scl and the sda are ? h ? activates the start condition and access is started. changing the sda from ? l ? to ? h ? when the scl is ? h ? activates stop condition and accessing stopped. generation of start and stop conditions are always made by the maste r (see the figure below). scl sda thd ;sta tsu ;sto start condition stop condition (2) data transmission and its acknowledge after start condition is entered, data is transmitted by 1byte (8bits). any bytes of data may be serially transmitted. the receiving side will send an acknowledge sig nal to the transmission side each time 8bit data is transmitted. the acknowledge signal is sent immediately after falling to ? l ? of scl 8bit clock pulses of data is transmitted, by releasing the sda by the transmission side that has asserted the bus at th at time and by turning sda to ? l ? by
r 20 5 1 series 12345 rev.1.04 - 24 - receiving side. when transmission of 1byte data next to preceding 1byte of data is received the receiving side releases the sda pin at falling edge of the scl 9bit of clock pulses or when the receiving side switches to the transmission side it starts data transmission. when the master is receiving side, it generates no acknowledge signal after last 1byte of data from the slave to tell the transmitter that data transmission has completed. the slave side (transmission s ide) continues to release the sda pin so that the master will be able to generate stop condition, after falling edge of the scl 9bit of clock pulses. scl from the master sda from the transmission side sda from the receiving side 1 2 8 9 acknowledge signal start condition (3) data transmission format in i 2 c - bus i 2 c - bus has no chip enable signal line. in p lace of it, each device has a 7bit slave address allocated. the first 1byte is allocated to this 7bit address and to the command (r/w) for which data transmission direction is designated by the data transmission thereafter. 7bit address is sequentially tr ansmitted from the msb and 2 and after bytes are read, when 8bit is ? h ? and when write ? l ? . the slave address of the r2051 is specified at (0110010). at the end of data transmission / receiving , stop condition is generated to complete transmission. howeve r, if start condition is generated without generating stop condition, repeated start condition is met and transmission / receiving data may be continue by setting the slave address again. use this procedure when the transmission direction needs to be chang e during one transmission. s a a data /a p data is written to the slave from the master s 0 a slave address data a a p when data is read from the slave immediately after 7bit addressing from the master master to slave slave to master sr repeated start condition p stop condition a a /a acknowledge signal r/w=1( read ) (0110010) inform read has been completed by not generate an acknowledge signal to the slave side. data r/w=0( write ) (0110010) when the transmission direction is to be changed during transmission. sr 1 0 a a r/w=0( write ) a data r/w=1( read ) (0110010) s 1 a /a p inform read has been completed by not generate an acknowledge signal to the slave side. data s start condition (0110010) slave address salve address slave address data data
r 20 5 1 series 12345 rev.1.04 - 25 - (4) data transmission write format in the r 2051 although the i 2 c - bus standard defines a transmission format for the slave allocated for each ic, transmission method of address information in ic is not defined. the r2051 transmits data the internal address pointer (4bit) and the transmission format register (4bit) at the 1byte next to one which transmitted a slave address and a write command. for write operation only one transmission format is available and (00 00) is set to the transmission format register. the 3byte transmits data to the address specified by the internal address pointer written to the 2byte. internal address pointer setting are automatically incremented for 4byte and after. note that when th e internal address pointer is fh, it will change to 0h on transmitting the next byte. 1 a s 0 a data a data a p example of data writing (when writing to internal address eh to fh) master to slave slave to master s start condition p stop condition a a /a acknowledge signal address pointer ? eh r/w=0( write ) slave address ? (0110010) 1 1 0 0 0 0 0 0 0 0 0 1 1 1 transmission format register ? 0h writing of data to the internal address fh writing of data to the internal address eh
r 20 5 1 series 12345 rev.1.04 - 26 - (5) data transmission read format of the r 2051 the r2051 allows the following three read out method of data an internal register. the first method to reading data from the internal register is to specify an internal address by setting the internal address pointer and the transmission format register described p 25 (4), generate the repeated start condition (see p 24 (3)) to change the data transmission direction to perform reading. the internal address pointer is set to fh when the stop condition is met. therefore, this method of reading allows no insertion of stop co ndition before the repeated start condition. set 0h to the transmission format register when this method used. 1 s 0 a a data /a p example 1 of data read (when data is read from 2h to 4h) master to slave slave to master s start condition sr repeated start condition a a /a acknowledge signal address pointer ? 2h repeated start condition 0 1 0 0 0 1 1 0 0 0 0 0 0 1 transmission format register ? 0h sr 1 0 a slave address ? (0110010) 1 0 0 0 0 1 a data a data reading of data from the internal address 3h r/w=1( read ) r/w=0( write ) p stop condition slave address ? (0110010) reading of data from the internal address 4h reading of data from the internal address 2h
r 20 5 1 series 12345 rev.1.04 - 27 - the second method to reading data from the internal register is to start reading immediately after writing to the internal address pointer and the transmission format register. although this method is not based on i 2 c - bus standard in a strict sense it still effective to shorten read time to ease load to the master. set 4h to the transmission format register when this method u sed. 1 s a a data /a p example 2 of data read (when data is read from internal addresses eh to 1h) master to slave slave to master s start condition a a /a acknowledge signal address pointer ? eh 0 1 1 0 0 0 1 transmission format register ? 4h 1 0 a slave address ? (0110010) 1 0 0 0 0 1 a data a data reading of data from the internal address eh r/w=0( write ) p stop condition data reading of data from the internal address fh reading of data from the internal address 0h reading of data from the internal address 1h
r 20 5 1 series 12345 rev.1.04 - 28 - the third method to reading data from the internal register is to start reading immediately after writing to the slave address and r/w bit. since the internal address pointer is set to fh by default as described in the first m ethod, this method is only effective when reading is started from the internal address fh. s a a data /a p example 3 of data read (when data is read from internal addresses fh to 3h) master to slave slave to master s start condition a a /a acknowledge signal 1 0 a slave address ? (0110010) 1 0 0 1 0 1 a data a data r/w=1( read ) p stop condition data data reading of data from the internal address fh reading of data from the internal address 0h reading of data from the internal address 1h reading of data from the internal address 2h reading of data from the internal address 3h
r 20 5 1 series 12345 rev.1.04 - 29 - l data transmission under special condition the r2051 holds the clock tentatively for duration from start condition to avoid invalid read or wri te clock on carrying clock. when clock carried during this period, which will be adjusted within approx. 61 m s from stop condition. to prevent invalid read or write, clock and calendar data shall be made during one transmission operation (from start condi tion to stop condition). when 0.5 to 1.0 second elapses after start condition, any access to the r2051 is automatically released to release tentative hold of the clock, and access from the cpu is forced to be terminated (the same action as made stop condi tion is received : automatic resume function from i 2 c - bus interface). therefore, one access must be complete within 0.5 seconds. the automatic resume function prevents delay in clock even if scl is stopped from sudden failure of the system during clock re ad operation. also a second start condition after the first start condition and before the stop condition is regarded ? repeated start condition ? . therefore, when 0.5 to 1.0 seconds passed after the first start condition, an access to the r2051 is automa tically released. if access is tried after automatic resume function is activated, no acknowledge signal will be output for writing while ffh will be output for reading. the user shall always be able to access the real - time clock as long as three conditio ns are met. (1) no stop condition shall be generated until clock and calendar data read/write is started and completed. (2) one cycle read/write operation shall be complete within 0.5 seconds. (3) do not make start condition within 61 m s from stop condition. when c lock is carried during the access, which will be adjusted within approx. 61 m s from stop condition. bad example of reading from seconds to hours (invalid read) (start condition) ? (read of seconds) ? (read of minutes) ? (stop condition) ? (start condition) ? (read of hour) ? (stop condition) assuming read was started at 05:59:59 p.m. and while reading seconds and minutes the time advanced to 06:00:00 p.m. at this time second digit is hold so read the read as 05:59:59. then the r2051 confirms (stop conditio n) and carries second digit being hold and the time change to 06:00:00 p.m. then, when the hour digit is read, it changes to 6. the wrong results of 06:59:59 will be read.
r 20 5 1 series 12345 rev.1.04 - 30 - n configuration of oscillation circuit and correction of time count deviations l conf iguration of oscillation circuit 32khz cg cd a oscin oscout oscillator circuit the oscillation circuit is driven at a constant voltage of approximately 1.2 volts relative to the level of the vss pin input. as such, it is configured to generate an oscillating waveform wi th a peak - to - peak voltage on the order of 1.1 volts on the positive side of the vss pin input. < considerations in handling crystal oscillators > generally, crystal oscillators have basic characteristics including an equivalent series resistance (r1) indi cating the ease of their oscillation and a load capacitance (cl) indicating the degree of their center frequency. particularly, crystal oscillators intended for use in the r 2051 are recommended to have a typical r1 value of 30k w and a typical cl value of 6 to 8pf. to confirm these recommended values, contact the manufacturers of crystal oscillators intended for use in these particular models. < considerations in installing components around the oscillation circuit > 1) install the crystal oscillator i n the closest possible vicinity to the real - time clock ics. 2) avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area marked "a" in the above figure). 3) apply the highest possible insulation res istance between the oscin and oscout pins and the printed circuit board. 4) avoid using any long parallel lines to wire the oscin and oscout pins. 5) take extreme care not to cause condensation, which leads to various problems such as oscillation halt. < other relevant considerations > 1) for external input of 32.768 - khz clock pulses to the oscin pin: dc coupling: prohibited due to an input level mismatch. ac coupling: permissible except that the oscillation halt sensing circuit does not guarantee perfect operation because it may cause sensing errors due to such factors as noise. 2) to maintain stable characteristics of the crystal oscillator, avoid driving any other ic through 32.768 - khz clock pulses output from the oscout pin. typical externally - equipped element x?tal : 32.768khz ( r1=30k w typ ) ( cl=6pf to 8pf ) s tandard values of internal elements cg,cd 1 0 pf typ
r 20 5 1 series 12345 rev.1.04 - 31 - l measurement of oscillation frequency frequency counter 32768hz v cc oscin oscout vdd clkout vss * 1) the r 2051 is configured to generate 32.768 - khz clock pulses for output from the clk out pin . * 2) a frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit. l adjustment of oscillation frequency the oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of model r2051 in the s ystem into which they are to be built and on the allowable degree of time count errors. the flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment procedure for the relevant system. start course (b) use 32-khz clock output without regard to its frequency precision no yes use 32-khz clock output? yes no course (c) course (a) course (d) yes yes no no allowable time count precision on order of oscillation frequency variations of crystal oscillator (*1) plus frequency variations of rtc (*2) ? (*3) allowable time count precision on order of oscillation frequency variations of crystal oscillator (*1) plus frequency variations of rtc (*2) ? (*3) * 1) gene rally, crystal oscillators for commercial use are classified in terms of their center frequency depending on their load capacitance (cl) and further divided into ranks on the order of 10, 20, and 50ppm depending on the degree of their oscillation freque ncy variations. * 2) basically, model r 2051 is configured to cause frequency variations on the order of 5 to 10ppm at 25 c . * 3) time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by th e temperature characteristics and other properties of crystal oscillators.
r 20 5 1 series 12345 rev.1.04 - 32 - course (a) when the time count precision of each rtc is not to be adjusted, the crystal oscillator intended for use in that rtc may have any cl value requiring no presetting. th e crystal oscillator may be subject to frequency variations which are selectable within the allowable range of time count precision. several crystal oscillators and rtcs should be used to find the center frequency of the crystal oscillators by the method described in " p 31 l measurement of oscillation frequency" and then calculate an appropriate oscillation adjustment value by the method described in " p 33 l oscillation adjustment circuit" for writing this value to the r2051 . course (b) when the time count precision of each rtc is to be adjusted within the oscillation frequency variations of the crystal oscillator plus the frequency variations of the real - t ime clock ics, it becomes necessary to correct deviations in the time count of each rtc by the method described in " p 33 l oscillation adjustment circuit". such oscillation adjustment provides crystal oscill ators with a wider range of allowable settings of their oscillation frequency variations and their cl values. the real - time clock ic and the crystal oscillator intended for use in that real - time clock ic should be used to find the center frequency of the crystal oscillator by the method described in " p 31 l measurement of oscillation frequency" and then confirm the center frequency thus found to fall within the range adjustable by the oscillation adjust ment circuit before adjusting the oscillation frequency of the oscillation circuit. at normal temperature, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately 0.5ppm. course (c) course (c) together with course (d) requires adjusting the time count precision of each rtc as well as the frequency of 32.768 - khz clock pulses output from the cl kout pin. normally, the oscillation frequency of the crystal oscillator intended for use in the rtcs should be adjusted by adjus ting the oscillation stabilizing capacitors cg and cd connected to both ends of the crystal oscillator. the r 2051 , which incorporate the cg and the cd, require adjusting the oscillation frequency of the crystal oscillator through its cl value. generally , the relationship between the cl value and the cg and cd values can be represented by the following equation: cl = ( cg cd)/(cg + cd ) + cs where "cs" represents the floating capacity of the printed circuit board. the crystal oscillator intended for use in the r 2051 is recommended to have the cl value on the order of 6 to 8pf. its oscillation frequency should be measured by the method described in " p 31 l measurement of oscillation frequency". any c rystal oscillator found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) should be replaced with another one having a smaller and greater cl value, respectively until another one having an optimum c l value is selected. in this case, the bit settings disabling the oscillation adjustment circuit (see " p 33 l oscillation adjustment circuit ") should be written to the oscillation adjustment register. inci dentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external oscillation stabilization capacitor cgout as illustrated in the diagram below. 32khz rd cg cd oscin oscout cg out *1) oscillator circuit course (d) it is necessary to se lect the crystal oscillator in the same manner as in course (c) as well as correct errors in the time count of each rtc in the same manner as in course (b) by the method described in " p 33 l oscillation adjus tment circuit ". *1) the cgout should have a capacitance ranging from 0 to 15 pf .
r 20 5 1 series 12345 rev.1.04 - 33 - l oscillation adjustment circuit the oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1 - second clock pulses once per 20 seconds or 60 seconds . when dev bit in the oscillation adjustment register is set to 0, r2051 varies number of 1 - second clock pulses once per 20 seconds . when dev bit is set to 1, r2051 varies number of 1 - second clock pulses once per 60 seconds . the oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to the f6, f5, f4, f3, f2, f1, and f0 bits in the oscillation adjustment circuit. conversely, when such oscillation adjustment is to be made, an appropriate oscillation adjust ment value can be calculated by the equation below for writing to the oscillation adjustment circuit. (1) when oscillation frequency (* 1) is higher than target frequency (* 2) (causing time count gain) when dev=0: oscillation adjustment value ( * 3) = ( oscillation frequency - target frequency + 0.1) oscillation frequency 3.051 10 - 6 ? ( oscillation frequency ? target frequency) 10 + 1 when dev=1: oscillation adjustment value ( * 3) = (osc illation frequency - target frequency + 0. 0 333) oscillation frequency 1.017 10 - 6 ? ( oscillation frequency ? target frequency) 30 + 1 * 1) oscillation frequency: frequency of clo ck pulse output from the clkout pin at normal temperature in the manner described in " p 31 l measurement of oscillation frequency ". * 2) target frequency: desired frequency to be set. generall y, a 32.768 - khz crystal oscillator has such temperature characteristics as to have the highest oscillation frequency at normal temperature. consequently, the crystal oscillator is recommended to have target frequency settings on the order of 32.768 to 32. 76810 khz (+3.05ppm relative to 32.768 khz). note that the target frequency differs depending on the environment or location where the equipment incorporating the rtc is expected to be operated. * 3) oscillation adjustment value: value that is to be finally written to the f0 to f6 bits in the oscillation adjustment register and is represented in 7 - bit coded decimal notation. (2) when oscillation frequency is equal to target frequency (causing time count neither gain n or loss) o scillation adjustment value = 0 , +1 , - 64 , or ? 63 (3) when oscillation frequency is lower than target frequency (causing time count loss) when dev=0: oscillation adjustment value = (oscillation frequency - target frequency ) oscillation frequency 3.051 10 - 6 ? ( oscillation frequency ? target frequency) 10 when dev=1: oscillation adjustment value = (oscillation frequency - target frequency ) oscillation frequency 1.017 10 - 6 ? ( oscillation frequency ? target frequency) 30 oscillation adjustment value calculations are exemplified below (a) for an oscillation frequency = 32768.85 hz and a target frequency = 32768.05 hz when setting dev bit to 0: oscillation adj ustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 3.051 10 - 6 ) ? (32768.85 - 32768.05) 10 + 1 = 9.001 ? 9 in this instance, write the settings ( dev, f6,f5,f4,f3,f2,f1,f0)=( 0, 0,0,0,1,0,0,1) i n the oscillation adjustment register. thus, an appropriate oscillation adjustment value in the presence of any time count gain represents a distance from 01h.
r 20 5 1 series 12345 rev.1.04 - 34 - when setting dev bit to 1: oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85 1.017 10 - 6 ) ? (32768.85 - 32768.05) 30 + 1 = 23.51 ? 24 in this instance, write the settings ( dev, f6,f5,f4,f3,f2,f1,f0)=( 1, 0,0 ,1,1, 0,0,0) in the oscillation adjustment register. (b) for an oscillation frequency = 3 276 2.22hz and a target frequency = 32768.05 hz when setting dev bit to 0: oscillation adjustment value = (3276 2.22 - 32768.05) / (3276 2.22 3.051 10 - 6 ) ? (3276 2.22 - 32768.05) 10 = - 58.325 ? - 58 to represent an oscillation adjustment value of - 58 in 7 - bit coded decimal notation, subtract 58 ( 3a h) from 128 (80h) to obtain 46 h. in this instance, write the settings of ( dev, f6,f5,f4,f3,f2,f1,f0) = ( 0, 1,0,0,0,1, 1,0) in the oscillation adjustment register. thus, an appropriate oscillation adjustment value in the presence of any time count loss represents a distance from 80h. when setting dev bit to 1: oscillation adjustment value = (3276 2.22 - 32768.05) / (3276 2.22 1.017 10 - 6 ) ? (3276 2.22 - 32768.05) 30 = - 174.97 ? - 175 oscillation adjustment value can be set from - 62 to 63. then, in this case, oscillation adjustment value is out of range. (4) difference between dev=0 and dev=1 difference between dev=0 and dev=1 is following, dev=0 dev=1 maximum valluerange - 189.2ppm to 189.2ppm -- 62ppm to 63ppm minimum resolution 3ppm 1ppm notes: 1) oscillation adjustment does not affect the frequ ency of 32.768 - khz clock pulses output from the clkout pin. 2) oscillation adjustment value range: when the oscillation frequency is higher than the target frequency (causing a time count gain), an appropriate time count gain ranges from - 3.05ppm to - 189 .2ppm with the settings of "0, 0, 0, 0, 0, 1, 0" to "0, 1, 1, 1, 1, 1, 1" written to the f6, f5, f4, f3, f2, f1, and f0 bits in the oscillation adjustment register, thus allowing correction of a time count gain of up to +189.2ppm. conversely, when the osc illation frequency is lower than the target frequency (causing a time count loss), an appropriate time count gain ranges from +3.05ppm to +189.2ppm with the settings of "1, 1, 1, 1, 1, 1, 1" to "1, 0, 0, 0, 0, 1, 0" written to the f6, f5, f4, f3, f2, f1, a nd f0 bits in the oscillation adjustment register, thus allowing correction of a time count loss of up to - 189.2ppm. l how to evaluate the clock gain or loss the o scillato r adjustment c ircuit is configured to change time counts of 1 second on the basis of the settings of the o scillation adjustment r egister once in 20 seconds or 60 seconds . the oscillation adjustment circuit does not e ffect the frequency of 32768hz - clock pulse output from the cl k out pin. therefore, after writing the oscillation adjustment register, we cannot measure the clock error with probing clkout clock pulses. the way to measure the clock error as follows: (1) output a 1hz clock pulse of pulse mode with interrupt pin set (0,0,x,x,0,0,1,1) to control register 1 at address eh.
r 20 5 1 series 12345 rev.1.04 - 35 - (2) afte r setting the oscillation adjustment register, 1hz clock period changes every 20seconds ( or every 60 seconds) like next page figure. 1hz clock pulse t0 t0 t0 t1 1 time 19 times measure the interval of t0 and t1 with frequency counter. a frequency counter with 7 or mor e digits is recommended for the measurement. (3) calculate the typical period from t0 and t1 t = (19 t0+1 t1)/20 calculate the time error from t.
r 20 5 1 series 12345 rev.1.04 - 36 - n power - on reset, oscillation halt sensing, and supply voltage monitoring l pon, /xst, and vdet the power - on re set circuit is configured to reset control register1, 2, and clock adjustment register when vdd power up from 0v. the oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768 - khz clock pulses. the supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.35v. each function has a monitor bit. i.e. the pon bit is for the power - on reset circuit, and /xst bit is for the oscillation halt sensing circuit , and vdet is for the supply voltage monitoring circuit . pon and vdet bits are activated to ? h ? . however, /xst bit is activated to ? l ? . the pon and vdet accept only the writing of 0, but /xst accepts the writing of 0 and 1 . the pon bit is set to 1, when vdd power - u p from 0v, but vdet is set to 0, and /xst is indefinite. the functions of these three monitor bits are shown in the table below. pon /xst vdet function monitoring for the power - on reset function monitoring for the oscillation halt sensing function a dr op in supply voltage below a threshold voltage of 2.1 or 1.35v address d4 in address fh d5 in address fh d6 in address fh activated high low high when vdd power up from 0v 1 indefinite 0 accept the writing 0 only both 0 and 1 0 only the relationship between the pon, / xst , and vdet is shown in the table below. pon /xst vdet conditions of supply voltage and oscillation condition of oscillator , and back - up status 0 0 0 halt on oscillation , but no drop in vdd supply voltage below threshold voltage halt on oscillation cause of condensation etc. 0 0 1 halt on oscillation and drop in vdd supply voltage below threshold voltage , but no drop to 0v halt on oscillation cause of drop in back - up battery voltage 0 1 0 no drop in vdd supply voltage below threshol d voltage and no halt in oscillation normal condition 0 1 1 drop in vdd supply voltage below threshold voltage and no halt on oscillation no halt on oscillation , but drop in back - up battery voltage 1 * * drop in supply voltage to 0v power - up from 0v, 32768 hz oscillation power - on reset flag (pon) oscillation halt sensing flag (/xst) threshold voltage (2.1v or 1.35v) vdd vdd supply voltage monitor flag (vdet) internal initialization period (1 to 2 sec.) vdet ? 0 /xst ? 1 pon ? 0 vdet ? 0 /xst ? 1 pon ? 1 vdet ? 0 /xst ? 1 pon ? 0 internal initialization period (1 to 2 sec.)
r 20 5 1 series 12345 rev.1.04 - 37 - when the pon bit is set to 1 in the control register 2, the dev, f6 to f0, wale, dale, /12 24, scratch2, test, ct2, ct1, ct0, vdsl, vdet, scratch 1 , ctfg, wafg, and dafg bits are reset to 0 in the oscillation adjustment registe r, the control register 1, and the control register 2. the pon bit is also set to 1 at power - on from 0 volts. < considerations in using oscillation halt sensing circuit > be sure to prevent the oscillation halt sensing circuit from malfunctioning by pr eventing the following: 1) instantaneous power - down on the vdd 2) condensation on the crystal oscillator 3) on - board noise to the crystal oscillator 4) applying to individual pins voltage exceeding their respective maximum ratings in particular, note that the / xst bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. further, give special considerations to prevent excessive chattering in the oscillation halt sensin g circuit. vdd
r 20 5 1 series 12345 rev.1.04 - 38 - l voltage monitoring circuit r2051 incorporates two kinds of voltage monitoring function. these are shown in the table below. vcc voltage monitoring circuit vdd voltage monitoring circuit (vdet) purpose cpu reset output back - up battery checker monitoring supply voltage vcc pin vdd pin (supply voltage for the internal rtc circuit) output for result /vdcc pin store in the control register 2 (d6 in address fh) function after falling vcc, /vdcc outputs ? l ? . tdeal y after rising vcc, /vdcc outputs ? h ? (off) below the threshold voltage, sw1 turns off and sw2 turns on. over the threshold voltage, sw1 turns on and sw2 turns off. detector threshold (falling edge of power supply voltage) - vdet1 selecting from vdeth or vdetl by writing to the register (d7 in address fh) detector released voltage (rising edge of power supply voltage) +vdet1 same as falling edge ( no hyster esis) the way to monitor always one time every second the vdd s upply voltage monitoring circui t is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1. 35 v for the vdsl bit setting of 0 (the default setting) or 1, respectively, in the control re gister 2, thus minimizing supply current requirements as illustrated in the timing chart below. this circuit suspends a sampling operation once the vdet bit is set to 1 in the control register 2. the vdd supply voltage monitor is useful for back - up batte ry checking. vdet ( d6 in address fh ) pon vdd 2.1v or 1. 35 v 1s vdet ? 0 7.8 ms sampling timing for vdd supply voltage monitor internal nitiali- zation period (1 to 2sec.) pon ? 0 vdet ? 0
r 20 5 1 series 12345 rev.1.04 - 39 - the vcc supply voltage monitor circuit operates always. when vcc rising over +vdet1, sw1 turns on, and sw2 turns off. and tdelay after rising vcc, /vdcc outputs off(h). but when oscillation is halt, vcc outputs off (h) tdelay after oscillation starting. when vcc falling beyond - vdet1, sw1 turns off, and sw2 turns on. and /vdcc outputs ? l ? . vdd 32768hz oscillation /vdcc +vdet1 vcc sw1 sw2 tdelay tdelay tde lay on on on on on same voltage level as vsb oscillation starting - vdet1 n battery switch over circuit r2051 incorporates three power supply pins, vdd, vcc, and vsb. vdd p in is the power supply pin for internal real time clock circuit. when vcc voltage is lower than vdet1, vsb supplies the power to vdd, and when higher than vdet1, vcc supplies the power to vdd. the timing chart for vcc, vdd, and vsb is shown following. vdd +vdet1 vcc vsb (1) (2) (3) (3) (2) - vdet1 (1) when vsb is 0v and vcc is rising from 0v, vdd follows half of vcc voltage level. after vcc rising over +vdet1, vdd follows vcc voltage level. (2) when vcc is higher than +vdet1, vdd level is equal to vcc. (3) after v cc falling beyond - vdet1, vdd level is equal to vsb.
r 20 5 1 series 12345 rev.1.04 - 40 - n alarm and periodic interrupt the r 2051 incorporate s the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals for out put from the /intr pin as described below. (1) alarm interrupt circuit the alarm interrupt circuit is configured to generate alarm signals for output from the /intr, which is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day - of - week, hour, and minute counters) and alarm time preset by the alarm registers (the alarm_w registers intended for the day - of - week, hour, and minute digit settings and the alarm_d registers intended for the hour and minute dig it settings). (2) periodic interrupt circuit the periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level mode for output from the /intr pin depending on the ct2, ct1, and ct0 bit setti ngs in the control register 1. the above two types of interrupt signals are monitored by the flag bits (i.e. the wafg, dafg, and ctfg bits in the control register 2) and enabled or disabled by the enable bits (i.e. the wale, dale, ct2, ct1, and ct0 bits in the c ontrol register 1) as listed in the table below. flag bits enable bits alarm_w wafg ( d1 at address fh) wale ( d7 at address eh) alarm_d dafg ( d0 at address fh) dale ( d6 at address eh) peridic interrupt ctfg ( d2 at address fh) ct2=ct1=ct0=0 (t hese bit setting of ? 0 ? disable the periodic interrupt) ( d2 to d0 at address eh) * at power - on, when the wale, dale, ct2, ct1, and ct0 bits are set to 0 in the c ontrol register 1, the /intr pin is driven high (disabled). * when two types of inter rupt signals are output simultaneously from the /intr pin, the output from the /intr pin becomes an or waveform of their negative logic. example: combined output to /intr pin under control of /alarm_d and periodic interrupt periodic interrupt /intr / alarm_ d in this event, which type of interrupt signal is output from the /int r pin can be confirmed by reading the dafg, and ctfg bit settings in the control register 2. l alarm interrupt the alarm interrupt circuit is controlled by the enable bits (i.e. the wale and dale bits in the c ontrol r egister 1) and the flag bits (i.e. the wafg and dafg bits in the c ontrol register 2). the enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. when intended for reading, the flag bits can be used to monitor alarm interrupt signals. when intended for w riting, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0. the enable bits will not be affected even when the flag bits are set to 0. in this event, therefore, the alarm interrupt circ uit will continue to function until it is driven low (enabled) upon the next occurrence of a match between current time and preset alarm time.
r 20 5 1 series 12345 rev.1.04 - 41 - the alarm function can be set by presetting desired alarm time in the alarm registers (the alarm_w registers f or the day - of - week digit settings and both the alarm_w registers and the alarm_d registers for the hour and minute digit settings) with the wale and dale bits once set to 0 and then to 1 in the control r egister 1. note that the wale and dale bits should b e once set to 0 in order to disable the alarm interrupt circuit upon the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm function. current time = preset alarm time wale ? 1 (dale) interval (1min . ) during which a match between current time and preset alarm time occurs current time = preset alarm time wafg ? 0 (dafg) /intr wale ? 1 (dale) wale ? 1 (dale) current time = preset alarm time wale ? 0 (dale) current time = preset alarm time /intr after setting wale(dalw) to 0, alarm registers is set to current time, and wale(dale) is set to 1, /intr will be not driven to ? l ? immediately, /intr will be driven to ? l ? at next alarm setting time. l periodic interrupt setting of the periodic selection bits (ct2 to ct0) enables period ic interrupt to the cpu. there are two waveform modes: pulse mode and level mode. in the pulse mode, the output has a waveform duty cycle of around 50%. in the level mode, the output is cyclically driven low and, when the ctfg bit is set to 0, the output is return to high (off) . description ct2 ct1 ct0 wave form mode interrupt cycle and falling timing 0 0 0 - off(h) (default) 0 0 1 - fixed at ? l ? 0 1 0 pulse mode *1) 2hz(duty50% ) 0 1 1 pulse mode *1) 1hz(duty50%) 1 0 0 level mode *2) once pe r 1 second (synchronized with second counter increment) 1 0 1 level mode *2) once per 1 minute (at 00 seconds of every minute) 1 1 0 level mode *2) once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode *2) once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) *1) pulse mode: 2 - hz and 1 - hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below. /intr pin rewriting of the second counter ctfg bit approx. 9 2 m s ( increment of second counter )
r 20 5 1 series 12345 rev.1.04 - 42 - in the pulse mode, the increment of the second counter is delayed by approximately 92 m s from the falling edge of clock pulses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real - time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the /intr pin low. *2) level mode: p eriodic interrupt signals are output with selectable interrupt cy cle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of the second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodic interrupt signals with an interrupt cycle setting of 1 second are outp ut in synchronization with the increment of the second counter as illustrated in the timing chart below. /intr pin ( increment of second counter ) ctfg bit setting ctfg bit to 0 setting ctfg bit to 0 ( increment of second counter ) ( increment of second counter ) *1), *2) when the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec . as fol lows: pulse mode: the ?l? period of output pulses will increment or decrement by a maximum of 3 .784ms. for example, 1 - hz clock pulses will have a duty cycle of 50 0.3784%. level mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784 ms.
r 20 5 1 series 12345 rev.1.04 - 43 - n t ypical a pplications l typical power circuit configurations vdd vsb vcc vss 0.1 m f cpu power supply the case of back - up by primary battery cr2025 etc. vsb vdd vcc vss 0.1 m f cpu power supply ml614 etc. the case of back - up by capacitor or secondary battery (charging voltage is equal to cpu power supply voltage) vsb vdd vcc vss 0.1 m f cpu power supply (3v) 5v double layer capacitor etc. the case of back - up by capacitor or secondary battery (charging voltage is not equal to cpu power supply voltage) vdd pin cannot be connect to any additional heavy load components such as sram. and vdd pin m ust be connected c2, and c 2 should be over 0.1 m f. vdd cpu power supply vcc vsb c3 voltage detector sw1 sw2 c2 r1 cpu vbat - vdet1 rcpu r2051 series when secondary battery or double layer capacitor connects to vdd pin, after cpu power supply turning off, secondray battery discharges through the root above figure. if r1 is much smaller than cpu impedance (rcpu), vcc voltage keeps higher than - vdet1, and sw1 keeps on. therefore r1 must be specified by following formula. r1 > rcpu x (vbat - ( - vdet1)) / ( - vdet1) r1 is specified by back - up battery or double layer capacitor, t oo. please check the data sheet for back - up devices. l connection of cin pin please connect capacitor over 0.1 m f between cin and vss pin.
r 20 5 1 series 12345 rev.1.04 - 44 - l connection of /intr and /vdcc pin the /intr and /vdcc pin s follow the n - channel open drain output logic and contains no protective diode on the power supply side. as such, it can be connected to a pull - up resistor of up to 5.5 volts regardless of supply voltage. v sb oscin oscout /intr or /vdcc *1) 32768hz b a backup power supply system power supply vss * 1 ) depending on whether the /intr and /vdcc pin s are to be used during battery backup, it should be connected to a pull - up resistor at the following differ ent positions: (1) position a in the left diagram when it is not to be used during battery backup. (2) position b in the left diagram when it is to be used during battery backup.
r 20 5 1 series 12345 rev.1.04 - 45 - n typical characteristics l time keeping current (isb) vs. supply voltage (vsb) (topt=25 c) test circuit 0 0.1 0.2 0.3 0.4 0.5 0 1 2 3 4 5 6 vsb(v) time keeping current (ua) 0.1 m f 0.1 m f a vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda l stand - by current (icc) vs. supply voltage (vcc) (topt=25 c) test circuit 0 1 2 3 4 2 3 4 5 6 vcc(v) stand-by current (ua) 0.1 m f 0.1 m f a vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda l time keeping current (isb) vs. operating temperature (topt) (vsb=3v) test circuit 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -50 -25 0 25 50 75 100 operating temperature (celsius) time keeping current (ua) 0.1 m f 0.1 m f a vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda
r 20 5 1 series 12345 rev.1.04 - 46 - l stand - b y current (icc) vs. operating temperature (topt) (vcc=3v) test circuit 0 1 2 3 4 -50 -25 0 25 50 75 100 operating temperature (celsius) stand-by current(ua) 0.1 m f 0.1 m f a vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda l cpu access current vs. scl clock frequency (khz) (topt=25 c) 0 10 20 30 40 0 100 200 300 400 500 scl clock frequency (khz) cpu access current (ua) l oscillation frequency deviation ( d f/f0) vs. operating temperature (topt) (vcc=3v) topt=25 c as standard test circuit -160 -140 -120 -100 -80 -60 -40 -20 0 20 -50 -25 0 25 50 75 100 operating temperature topt(celsius) oscillation frequency deviation df/f0(ppm) 0.1 m f 0.1 m f frequency counter vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda vcc=5v vcc=3v
r 20 5 1 series 12345 rev.1.04 - 47 - l frequency deviation ( d f/f0) vs. supply voltage (vsb/vcc) (topt=25 c) vcc/vsb=3v as standard test circuit -4 -3 -2 -1 0 1 2 0 1 2 3 4 5 6 vcc/vsb(v) frequency deviation d f/f0(ppm) frequency counter 0.1 m f 0.1 m f vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda l frequency deviation ( d f/f0) vs. cgout (topt=25 c, vcc=3v)cgout=0pf a s standard test circuit -40 -30 -20 -10 0 10 0 5 10 15 20 cgout(pf) frequency deviation df/f0(ppm) 0.1 m f 0.1 m f frequency counter vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda l detector threshold voltage (+vdet1/ - vdet1) vs. operating temperature (topt) (vsb=3v) (R2051K01) (R2051K02) 2.3 2.4 2.5 2.6 -50 -25 0 25 50 75 100 perating temperature topt(celsius) detector threshold voltage vdet1(v) 2.7 2.8 2.9 3 -50 -25 0 25 50 75 100 perating temperature topt(celsius) detector threshold voltage vdet1(v) +vdet1 - vdet1 +vdet1 - vdet1
r 20 5 1 series 12345 rev.1.04 - 48 - test circuit 0.1 m f 0.1 m f vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda l vcc - vdd(vddout1) vs. output load current (iout1) (topt=25 c) test circuit -0.5 -0.4 -0.3 -0.2 -0.1 0 0 2 4 6 8 10 output load current iout1(ma) vcc-vdd(v) a 0.1 m f 0.1 m f vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda l vsb - vdd(vddout2) vs. output load current (iout2) (topt=25 c) test circuit -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0 0.5 1 1.5 2 2.5 3 output load current iout2(ma) vsb-vdd(v) a 0.1 m f 0.1 m f vcc vsb vdd cin vss oscin oscout /intr /vdcc clkout scl sda vsb=3v vsb=2v vsb=1v vcc=5v vcc=3v vcc=2.5v
r 20 5 1 series 12345 rev.1.04 - 49 - l vol vs. iol (/vdcc pin) l vol vs. iol (/intr pin) (topt=25 c, vsb=vcc=2v) (topt=25 c) 0 0.2 0.4 0.6 0.8 0 2 4 6 8 10 iol(ma) vol(v) 0 0.1 0.2 0.3 0.4 0 2 4 6 8 10 iol(ma) vol(v) vcc=3v vcc=5v
r 20 5 1 series 12345 rev.1.04 - 50 - n typical software - based operations l initialization at power - on start *1) yes no vdet=0? warning back - up battery run - down set oscillation adjustment register and control register 1 and 2, etc. power - on *2) *4) *3) pon =1? yes no *1) after power - on from 0 volt, the process of internal initialization require a time span on 1sec, so that access should be done after /vdcc turning to off(h) . *2) the pon bit setting of 0 in the c ontrol register 1 indicates power - o n from backup battery and not from 0v. for further details, see " p. 36 n power - on reset, oscillation halt sensing, and supply voltage monitoring l pon, /xst, and vdet ". *3) this step is not required when the supply voltage mon itoring circuit is not used. *4) this step involves ordinary initialization including the oscillation adjustment register and interrupt cycle settings , etc . l writing of time and calendar data write to time counter and calendar counter *2) stop condition *3) start condition *1) *1) when writing to clock and calendar counters, do not insert stop condition until all tim es from second to year have been written to prevent error in writing time. ( detailed in " p. 28 data transmission under special condition ". *2) any writing to the second counter will reset divider units lower than the second digits. *3) take care so that process from start condition to stop condition will be complete within 0.5sec. ( detailed in " p. 28 data transmission under special condition ". the r2051 may also be initialized not at power - on but in the process of writing time and calendar data.
r 20 5 1 series 12345 rev.1.04 - 51 - l reading time and calendar data ( 1) ordinary process of reading time and calendar data read from time counter and calendar counter *2) start condition start condition *1) (2) basic process of reading time and calendar data with periodic interrupt function *2) other interrupt processes set periodic interrupt cycle selection bits ctfg=1? read from time counter and calendar counter yes no control register 2 ? (x 1 x 1x 011) generate interrupt in cpu *1) *3) *1) when writing to clock and calendar counters, do not insert stop condi tion until all times from second to year have been written to prevent error in writing time. ( detailed in " p. 28 data transmission under special condition ". *2) take care so that process from start condition to stop condition will be complete within 0.5sec. ( detailed in " p. 28 data transmission under special condition ". *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step must be completed within 0.5 second. *3) this step is intended to set the ctfg bit to 0 in the co ntrol r egister 2 to cancel an interrupt to the cpu.
r 20 5 1 series 12345 rev.1.04 - 52 - (3) applied process of reading time and calendar data with periodic interrupt function time data need not be read from all the time counters when used for such ordinary purposes as time count indication. this applied process can be used to read time and calendar data with substantial reductions in the load involv ed in such reading. for time indication in "day - of - month, day - of - week, hour, minute, and second" format: *2) other interrupts processes sec. = 00? y es no generate interrupt to cpu *1) *3) ctfg=1? control register 2 ? (x 1 x 1x 011) yes read min.,hr.,day, and day - of - week *4) no control register 1 ? (x xxx0100 ) control register 2 ? (x 1x1x011 ) use previous min.,hr., day, and day - of - week data *1) this ste p is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step must be completed within 0.5 sec. *3) this step is intended to read time data from all the time counters only in the first session of reading ti me data after writing time data. *4) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.
r 20 5 1 series 12345 rev.1.04 - 53 - l interrupt process (1) periodic interrupt *2) other interrupt processes set periodic interrupt cycle selection bits ctfg=1? conduct periodic interrupt yes no control register 2 ? (x 1 x 1x 011) generate interrupt to cpu *1) (2) alarm interrupt *3) other interrupt processes set alarm min., hr., and day - of - week registers wafg or dafg =1? conduct alarm interrupt yes no control register 2 ? (x 1 x 1x10 1) generate interrup t to cpu *1) wale or dale ? 0 *2) wale or dale ? 1 *1) this step is intended to once disable the alarm interrupt circuit by setting the wale or dale bits to 0 in anticipation of the coincidental occurrence of a match be tween current time and preset alarm time in the process of setting the alarm interrupt function. *2) this step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings. *3) this step is intended to once cancel the alarm interrupt function by writing the settings of "x,1,x, 1,x,1,0,1" and "x,1,x,1,x,1,1,0" to the alarm_w registers and the alarm_d registers, respectively. *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.

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