advance information metrolink2t-2? link lay er cyl2t020 1 cypress semiconductor corporation 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-02071 rev. ** revised march 3, 2003 features ? maps two channels of gigabit ethernet (gbe), fibre channel (1x, 1/2x, 1/4x), ficon ? , or escon ? indepen- dently onto a spi-3 interface for transparent transport over sonet/sdh ? oc-48/stm-16, oc-12/stm-4 rates ? compliant to draft recommendation of transparent generic framing procedure (gfp-t) per the itu-t g.7041 (version 0.4, october 2001) supports the following features to enable gfp-t mapping of client payload of gbe, fibre channel, or escon: ? special character mapping ? mapping and demapping into the gfp-t superblock with a user-defined size ? automatic 65b_pad/10b_err character insertion and deletion ? client management frame (cmf) generation and checking register programmable rate adaptation by adding/removal of idle code sequences for: ? gigabit ethernet (ieee 802.3z) ?fibre channel ? escon ?ficon programmable watermarks on each channel?s egress fifo to prevent overflow/underflow conditions by enabling rate adaptation support for programmable interrupt generation on error condition detection 32-bit host interface for register programming and performance monitoring complete performance monitoring using error counters in both egress and ingress directions programmable parity generation and checking on the phy and framer parallel interfaces programmable loopback functions for link verification ? serdes interface loopback ? gfp-t mapper/demapper client-side loopback 1.8v core and 3.3v i/o supplies cypress gfp-t transport solution metrolink2t-2 ? , posic2g ? /posic2gvc ?, and hotlink ii ? provide a complete end-to-end gfp-t solution provides seamless interface to cypress posic2gvc (cy7c9536) and posic2g (cy7c9537) to support: ? gfp-t frame delineation ? chec checking, calculation and scrambling ? payload scrambling ? idle frame insertion and deletion multiplexed cpu bus interface to posic2g/posic2gvc (allows for a single cpu bus interface to both metrolink2t and posic2g/posic2gvc without external muxing) glueless parallel interface to cypress hotlink ii trans- ceivers to support: ? clock and data recovery for gbe, fibre channel, and escon ? word framing ? 8b/10b encoding and decoding ? special character detection and flagging network equipment dwdm transport equipment multiservice provisioning platforms (mspp) sonet/sdh add/drop multiplexers (adm) sonet/sdh digital cross connects (dcs) gbe, ficon, escon, fc two-channel serdes cyp15g0201dx 8-bit data bus, control 8-bit data bus, control spi-3 dual-channel gfp-t mapper cyl2t0201 oc-48/ stm-16 framer cy7c9536 oc-48/ stm-16 phy cys25g0101dx 16-bit hstl to optical modules control cpu cpu interface posic2g/ posic2gvc cpu interface figure 1. metrolink2t-2 application
advance information cyl2t020 1 document #: 38-02071 rev. ** page 2 of 4 block diagram serdes i/f channel a control_a data_a control_b data_b 8 8 gfp-t demapper spi-3 rx i/f data control serdes i/f channel a control_a data_a control_b data_b 8 8 spi-3 tx i/f 32 data channel b channel b control gfp-t mapper cpu i/f cp u i/f framer i/f 32 32 cpu_addr cpu_data cpu_control posic_ control 32 posic_ addr 32 channel a channel b channel a channel b egress ingress cpu interface figure 2. metrolink2t-2 top-level block diagram
advance information cyl2t020 1 document #: 38-02071 rev. ** page 3 of 4 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. overview applications metro service aggregation nodes aggregate client traffic such as gbe, escon, or fibre channel into sonet/sdh payloads for long-haul transport. such nodes require the ability to ensure just the right amount of bandwidth is allocated for the client payload -- which is where virtual concatenation becomes beneficial due to its convenience in specifying payload size. the metrolink2t-2 link-layer device aggregates two channels of gbe, fibre channel, ficon, or escon client traffic onto a single spi-3 bus. the metrolink2t-2 spi-3 interface connects to the posic2gvc/posic2g framer which is used to create the sonet/sdh frame required for network transport. serdes interface the cyl2t0201 metrolink2t-2 gfp-t mapper interface to the two-channel serdes device supports the following functions: error detection and handling egress rate adaptation. the serdes interface allows for a seamless connection to the cy15g0201dx device, as shown in figure 1 . gfp-t engine gfp-t is a version of gfp that provides the benefits of frame- mapped gfp (header error correction/rugged links,? known transport bandwidth/no byte-stuffing) with low latency. the metrolink2t-2 mapping engine follows the itu recom- mendation g.7041 from january 2002. the gfp-t engine in the metrolink2t-2 device supports one or two channels, and contains protocol-specific functions to allow the seamless transport of fibre channel, ficon, escon, or gbe. spi-3 interface the spi-3 interface was designed to support packet-over- sonet/sdh (pos) in the oc-48/stm-16 (2.488 gbps) and below environment. it allows efficient packet transfer between a framer and a link layer device. spi-3 supports multiple ports and has in-band port selection. spi-3 has discrete transmit/receive control signals for start of packet (sop), end of packet (eop), start of transfer, error indications, and other control indications. transmit fifo status flow control is provided by using either a polling or a direct status indication scheme. since the spi-3 interface supports data transfers at clock rates independent of the actual line bit rate, fifos are specified to allow the rate decoupling. the spi-3 interface specifies parity on the data bus. spi-3 also specifies a maximum clock rate of 104 mhz. since the spi-3 interface is a point-to-point interface, the metrolink2t-2 should connect to one framer device, such as a posic2gvc. spi-3 and metrolink2t-2 support variable- length packets. metrolink2t-2 supports the 32-bit-wide packet-level transfer mode of spi-3. in spi-3, the phy port address is inserted in-band with the packet data being transferred on the data bus. spi-3 allows up to 256 ports; since metrolink2t-2 is a two-channel device, only one or two spi-3 ports are supported by metrolink2t-2. escon is a registered trademark, and ficon is a trademark, of ibm corporation. metrolink2t-2, posic2gvc, and posic2g are trademarks of cypress semiconductor. all product and co mpany names mentioned in this document are the trademarks of their respective holders.
advance information cyl2t020 1 document #: 38-02071 rev. ** page 4 of 4 document history page document title: cyl2t0201 metrolink2t-2? link layer document number: 38-02071 rev. ecn no. issue date orig. of change description ** 122359 03/12/03 amv new data sheet
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