 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NJU6821 - 1 - 2002/11/22 82-common x 128rgb-segment, in 256-color stn lcd driver general description the NJU6821 is a stn lcd driver with 82-common x 128rgb-segment in 256-color. it consists of 384(128xrgb)-segment, 82-common drivers, and serial and parallel mpu interface circuits, internal power supply circuits, gradation palettes and 81,920-bit for graphic and 2,048-bit for icon display data ram. each segment driver outputs 8-(for r and g) and 4-(for b) gradation level out of 32-gradation level of gradation palette. since the NJU6821 provides a low operating voltage of 1.7v and low operating current, it is ideally suited for battery-powered handheld applications. in addition, it is possible to drive up to 164 x 128 pixels lcd panel when use two of NJU6821 as a master and slave lsis. features 256-color stn lcd driver lcd drivers 80 and 2-icon commons, 128rgb-segments, 4rgb-icon segments display data ram (ddram) 81,920-bit for graphic display 2,048-bit for icon display color display mode 8-(r and g) or 4-(b) gradation level out of 32-gradation level of gradation palette black & white display mode 82 x 384 pixels in b&w 8/16bit parallel interface directly- connective to 68/80 series mpu programmable 8- or 16-bit data bus length for display data 3-/4-line serial interface programmable duty and bias ratios programmable internal voltage booster (maximum 7-times) programmable contrast control using 128-step evr various instructions display data read/write, display on/off, reverse display on/off, all pixels on/off, column address, row address, n-line inversion, initial display line, initial com line, read-modify-write, gradation mode control, increment control, data bus length, discharge on/off, duty cycle ratio, lcd bias ratio, boost level, evr control, power save on/off, etc low operating current low logic supply voltage 1.7v to 3.3v lcd driving supply voltage 5.0v to 18.0v c-mos process package bumped chip / tcp preliminary package outline NJU6821cj
NJU6821 - 2 - pad location note1) the pads of (l), (r) and (c) are shorted mutually in the lsi. note2) the dmy pads are electrically open. chip center :x= 0 m, y= 0 m chip size :19.91mm x 2.55mm chip thickness :625 m 25 m bump size :100 m x 32 m bump pitch :50 m(min) bump height :14.0~22.5 m (typical 18 m) NJU6821 -3 - pad size v ssa , v ss , v dd , v ssh , v ee , v out pads types 17to19, 21to23, 29to31, 37to39, 43to45, 77to79, 91to93, 109to111, 112to114, 140to142 v ee (r) v ee (c) v ee (l) v ref v ba (r) v ba (l) v reg (r) v reg (l) dmy 2 (l) c 1 +(r) c 1 +(l) v ssh (r) v ssh (c) osc 2 v ssh (l) osc 1 v lcd (l) v lcd (r) v 1 (l) v 1 (r) v 2 (l) v 2 (r) v 3 (l) v 3 (r) v 4 (l) v 4 (r) v ssh (r) v ssh (c) v ssh (l) c 1 -(r) c 1 -(l) c 2 +(r) c 2 +(l) c 2 -(r) c 2 -(l) c 3 +(r) c 3 +(l) c 3 -(r) c 3 -(l) c 4 +(r) c 4 +(l) c 4 -(r) c 4 -(l) c 5 +(r) c 5 +(l) c 5 -(r) c 5 -(l) c 6 +(r) c 6 +(l) c 6 -(r) c 6 -(l) com 39 v out (r) v out (l) v lcd (l) v lcd (r) dmy 1 (l) com 26 dmy 1 (r) dmy 2 (r) com 25 com 0 comi 0 segsa 0 segsc 1 dmy 3 (l) dmy 3 (r) dmy 4 (r) sega 0 dmy 4 (l) segb 0 segc 0 sega 1 segb 1 segc 1 sega 2 segb 2 segc 2 x y x x x 50 50 1 06 1 8 11 8 NJU6821 - 4 - pad coordinates 1 chip size 19910 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) pad no. terminal x ( m) y ( m) 1 dmy 0 (l) -9625 -1068 52 d 10 -2550 -1068 103 c 4 +(l) 6120 -1068 2 dmy 0 (r) -9575 -1068 53 d 11 -2380 -1068 104 c 4 +(r) 6290 -1068 3 com 67 -9525 -1068 54 d 12 -2210 -1068 105 c 4 -(l) 6460 -1068 4 com 68 -9475 -1068 55 d 13 -2040 -1068 106 c 4 -(r) 6630 -1068 5 com 69 -9425 -1068 56 d 14 -1870 -1068 107 c 5 +(l) 6800 -1068 6 com 70 -9375 -1068 57 d 15 -1700 -1068 108 c 5 +(r) 6970 -1068 7 com 71 -9325 -1068 58 v ss (l) -1472 -1068 109 c 5 -(l) 7140 -1068 8 com 72 -9275 -1068 59 v ss (c) -1340 -1068 110 c 5 -(r) 7310 -1068 9 com 73 -9225 -1068 60 v ss (r) -1190 -1068 111 c 6 +(l) 7480 -1068 10 com 74 -9175 -1068 61 cl -1020 -1068 112 c 6 +(r) 7650 -1068 11 com 75 -9125 -1068 62 flm -850 -1068 113 c 6 -(l) 7820 -1068 12 com 76 -9075 -1068 63 fr -680 -1068 114 c 6 -(r) 7990 -1068 13 com 77 -9025 -1068 64 clk -510 -1068 115 v lcd (l) 8160 -1068 14 com 78 -8975 -1068 65 osc 1 -340 -1068 116 v lcd (r) 8330 -1068 15 com 79 -8925 -1068 66 osc 2 -107 -1068 117 v out (l) 8500 -1068 16 comi 1 -8875 -1068 67 v ssh (l) 74 -1068 118 v out (r) 8670 -1068 17 v ssa (l) -8670 -1068 68 v ssh (c) 196 -1068 119 com 39 8875 -1068 18 v ssa (c) -8500 -1068 69 v ssh (r) 318 -1068 120 com 38 8925 -1068 19 v ssa (r) -8330 -1068 70 v lcd (l) 510 -1068 121 com 37 8975 -1068 20 test -8171 -1068 71 v lcd (r) 680 -1068 122 com 36 9025 -1068 21 v dd (l) -7990 -1068 72 v 1 (l) 850 -1068 123 com 35 9075 -1068 22 v dd (c) -7820 -1068 73 v 1 (r) 1020 -1068 124 com 34 9125 -1068 23 v dd (r) -7650 -1068 74 v 2 (l) 1190 -1068 125 com 33 9175 -1068 24 resb -7480 -1068 75 v 2 (r) 1360 -1068 126 com 32 9225 -1068 25 csb -7310 -1068 76 v 3 (l) 1530 -1068 127 com 31 9275 -1068 26 rs -7140 -1068 77 v 3 (r) 1700 -1068 128 com 30 9325 -1068 27 v ss (l) -6970 -1068 78 v 4 (l) 1870 -1068 129 com 29 9375 -1068 28 v ss (c) -6800 -1068 79 v 4 (r) 2040 -1068 130 com 28 9425 -1068 29 v ss (r) -6630 -1068 80 v reg (l) 2210 -1068 131 com 27 9475 -1068 30 m/s -6448 -1068 81 v reg (r) 2380 -1068 132 com 26 9525 -1068 31 v dda -6290 -1068 82 v ba (l) 2550 -1068 133 dmy 1 (l) 9575 -1068 32 p/s -6120 -1068 83 v ba (r) 2693 -1068 134 dmy 1 (r) 9625 -1068 33 sel68 -5950 -1068 84 v ref 2879 -1068 135 dmy 2 (l) 9726 -900 34 v ssa (l) -5780 -1068 85 v ee (l) 3060 -1068 136 dmy 2 (r) 9726 -850 35 v ssa (c) -5610 -1068 86 v ee (c) 3230 -1068 137 com 25 9726 -800 36 v ssa (r) -5440 -1068 87 v ee (r) 3400 -1068 138 com 24 9726 -750 37 wrb -5270 -1068 88 v ssh (l) 3570 -1068 139 com 23 9726 -700 38 rdb -5111 -1068 89 v ssh (c) 3740 -1068 140 com 22 9726 -650 39 v dd (l) -4930 -1068 90 v ssh (r) 3910 -1068 141 com 21 9726 -600 40 v dd (c) -4760 -1068 91 c 1 +(l) 4102 -1068 142 com 20 9726 -550 41 v dd (r) -4590 -1068 92 c 1 +(r) 4250 -1068 143 com 19 9726 -500 42 d 0 /scl -4420 -1068 93 c 1 -(l) 4420 -1068 144 com 18 9726 -450 43 d 1 /sda -4250 -1068 94 c 1 -(r) 4590 -1068 145 com 17 9726 -400 44 d 2 /excs -3995 -1068 95 c 2 +(l) 4760 -1068 146 com 16 9726 -350 45 d 3 /smode -3740 -1068 96 c 2 +(r) 4930 -1068 147 com 15 9726 -300 46 d 4 /spol -3570 -1068 97 c 2 -(l) 5100 -1068 148 com 14 9726 -250 47 d 5 -3400 -1068 98 c 2 -(r) 5270 -1068 149 com 13 9726 -200 48 d 6 -3230 -1068 99 c 3 +(l) 5440 -1068 150 com 12 9726 -150 49 d 7 -3060 -1068 100 c 3 +(r) 5610 -1068 151 com 11 9726 -100 50 d 8 -2890 -1068 101 c 3 -(l) 5780 -1068 152 com 10 9726 -50 51 d 9 -2720 -1068 102 c 3 -(r) 5950 -1068 153 com 9 9726 0 NJU6821 -5 - pad coordinates 2 chip size 19910 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) pad no. terminal x ( m) y ( m) 154 com 8 9726 50 205 segb 10 8025 1068 256 segb 27 5475 1068 155 com 7 9726 100 206 segc 10 7975 1068 257 segc 27 5425 1068 156 com 6 9726 150 207 sega 11 7925 1068 258 sega 28 5375 1068 157 com 5 9726 200 208 segb 11 7875 1068 259 segb 28 5325 1068 158 com 4 9726 250 209 segc 11 7825 1068 260 segc 28 5275 1068 159 com 3 9726 300 210 sega 12 7775 1068 261 sega 29 5225 1068 160 com 2 9726 350 211 segb 12 7725 1068 262 segb 29 5175 1068 161 com 1 9726 400 212 segc 12 7675 1068 263 segc 29 5125 1068 162 com 0 9726 450 213 sega 13 7625 1068 264 sega 30 5075 1068 163 comi 0 9726 500 214 segb 13 7575 1068 265 segb 30 5025 1068 164 segsa 0 9726 550 215 segc 13 7525 1068 266 segc 30 4975 1068 165 segsb 0 9726 600 216 sega 14 7475 1068 267 sega 31 4925 1068 166 segsc 0 9726 650 217 segb 14 7425 1068 268 segb 31 4875 1068 167 segsa 1 9726 700 218 segc 14 7375 1068 269 segc 31 4825 1068 168 segsb 1 9726 750 219 sega 15 7325 1068 270 sega 32 4775 1068 169 segsc 1 9726 800 220 segb 15 7275 1068 271 segb 32 4725 1068 170 dmy 3 (l) 9726 850 221 segc 15 7225 1068 272 segc 32 4675 1068 171 dmy 3 (r) 9726 900 222 sega 16 7175 1068 273 sega 33 4625 1068 172 dmy 4 (l) 9675 1068 223 segb 16 7125 1068 274 segb 33 4575 1068 173 dmy 4 (r) 9625 1068 224 segc 16 7075 1068 275 segc 33 4525 1068 174 sega 0 9575 1068 225 sega 17 7025 1068 276 sega 34 4475 1068 175 segb 0 9525 1068 226 segb 17 6975 1068 277 segb 34 4425 1068 176 segc 0 9475 1068 227 segc 17 6925 1068 278 segc 34 4375 1068 177 sega 1 9425 1068 228 sega 18 6875 1068 279 sega 35 4325 1068 178 segb 1 9375 1068 229 segb 18 6825 1068 280 segb 35 4275 1068 179 segc 1 9325 1068 230 segc 18 6775 1068 281 segc 35 4225 1068 180 sega 2 9275 1068 231 sega 19 6725 1068 282 sega 36 4175 1068 181 segb 2 9225 1068 232 segb 19 6675 1068 283 segb 36 4125 1068 182 segc 2 9175 1068 233 segc 19 6625 1068 284 segc 36 4075 1068 183 sega 3 9125 1068 234 sega 20 6575 1068 285 sega 37 4025 1068 184 segb 3 9075 1068 235 segb 20 6525 1068 286 segb 37 3975 1068 185 segc 3 9025 1068 236 segc 20 6475 1068 287 segc 37 3925 1068 186 sega 4 8975 1068 237 sega 21 6425 1068 288 sega 38 3875 1068 187 segb 4 8925 1068 238 segb 21 6375 1068 289 segb 38 3825 1068 188 segc 4 8875 1068 239 segc 21 6325 1068 290 segc 38 3775 1068 189 sega 5 8825 1068 240 sega 22 6275 1068 291 sega 39 3725 1068 190 segb 5 8775 1068 241 segb 22 6225 1068 292 segb 39 3675 1068 191 segc 5 8725 1068 242 segc 22 6175 1068 293 segc 39 3625 1068 192 sega 6 8675 1068 243 sega 23 6125 1068 294 sega 40 3575 1068 193 segb 6 8625 1068 244 segb 23 6075 1068 295 segb 40 3525 1068 194 segc 6 8575 1068 245 segc 23 6025 1068 296 segc 40 3475 1068 195 sega 7 8525 1068 246 sega 24 5975 1068 297 sega 41 3425 1068 196 segb 7 8475 1068 247 segb 24 5925 1068 298 segb 41 3375 1068 197 segc 7 8425 1068 248 segc 24 5875 1068 299 segc 41 3325 1068 198 sega 8 8375 1068 249 sega 25 5825 1068 300 sega 42 3275 1068 199 segb 8 8325 1068 250 segb 25 5775 1068 301 segb 42 3225 1068 200 segc 8 8275 1068 251 segc 25 5725 1068 302 segc 42 3175 1068 201 sega 9 8225 1068 252 sega 26 5675 1068 303 sega 43 3125 1068 202 segb 9 8175 1068 253 segb 26 5625 1068 304 segb 43 3075 1068 203 segc 9 8125 1068 254 segc 26 5575 1068 305 segc 43 3025 1068 204 sega 10 8075 1068 255 sega 27 5525 1068 306 sega 44 2975 1068 NJU6821 - 6 - pad coordinates 3 chip size 19910 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) pad no. terminal x ( m) y ( m) 307 segb 44 2925 1068 358 segb 61 375 1068 409 segb 78 -2175 1068 308 segc 44 2875 1068 359 segc 61 325 1068 410 segc 78 -2225 1068 309 sega 45 2825 1068 360 sega 62 275 1068 411 sega 79 -2275 1068 310 segb 45 2775 1068 361 segb 62 225 1068 412 segb 79 -2325 1068 311 segc 45 2725 1068 362 segc 62 175 1068 413 segc 79 -2375 1068 312 sega 46 2675 1068 363 sega 63 125 1068 414 sega 80 -2425 1068 313 segb 46 2625 1068 364 segb 63 75 1068 415 segb 80 -2475 1068 314 segc 46 2575 1068 365 segc 63 25 1068 416 segc 80 -2525 1068 315 sega 47 2525 1068 366 sega 64 -25 1068 417 sega 81 -2575 1068 316 segb 47 2475 1068 367 segb 64 -75 1068 418 segb 81 -2625 1068 317 segc 47 2425 1068 368 segc 64 -125 1068 419 segc 81 -2675 1068 318 sega 48 2375 1068 369 sega 65 -175 1068 420 sega 82 -2725 1068 319 segb 48 2325 1068 370 segb 65 -225 1068 421 segb 82 -2775 1068 320 segc 48 2275 1068 371 segc 65 -275 1068 422 segc 82 -2825 1068 321 sega 49 2225 1068 372 sega 66 -325 1068 423 sega 83 -2875 1068 322 segb 49 2175 1068 373 segb 66 -375 1068 424 segb 83 -2925 1068 323 segc 49 2125 1068 374 segc 66 -425 1068 425 segc 83 -2975 1068 324 sega 50 2075 1068 375 sega 67 -475 1068 426 sega 84 -3025 1068 325 segb 50 2025 1068 376 segb 67 -525 1068 427 segb 84 -3075 1068 326 segc 50 1975 1068 377 segc 67 -575 1068 428 segc 84 -3125 1068 327 sega 51 1925 1068 378 sega 68 -625 1068 429 sega 85 -3175 1068 328 segb 51 1875 1068 379 segb 68 -675 1068 430 segb 85 -3225 1068 329 segc 51 1825 1068 380 segc 68 -725 1068 431 segc 85 -3275 1068 330 sega 52 1775 1068 381 sega 69 -775 1068 432 sega 86 -3325 1068 331 segb 52 1725 1068 382 segb 69 -825 1068 433 segb 86 -3375 1068 332 segc 52 1675 1068 383 segc 69 -875 1068 434 segc 86 -3425 1068 333 sega 53 1625 1068 384 sega 70 -925 1068 435 sega 87 -3475 1068 334 segb 53 1575 1068 385 segb 70 -975 1068 436 segb 87 -3525 1068 335 segc 53 1525 1068 386 segc 70 -1025 1068 437 segc 87 -3575 1068 336 sega 54 1475 1068 387 sega 71 -1075 1068 438 sega 88 -3625 1068 337 segb 54 1425 1068 388 segb 71 -1125 1068 439 segb 88 -3675 1068 338 segc 54 1375 1068 389 segc 71 -1175 1068 440 segc 88 -3725 1068 339 sega 55 1325 1068 390 sega 72 -1225 1068 441 sega 89 -3775 1068 340 segb 55 1275 1068 391 segb 72 -1275 1068 442 segb 89 -3825 1068 341 segc 55 1225 1068 392 segc 72 -1325 1068 443 segc 89 -3875 1068 342 sega 56 1175 1068 393 sega 73 -1375 1068 444 sega 90 -3925 1068 343 segb 56 1125 1068 394 segb 73 -1425 1068 445 segb 90 -3975 1068 344 segc 56 1075 1068 395 segc 73 -1475 1068 446 segc 90 -4025 1068 345 sega 57 1025 1068 396 sega 74 -1525 1068 447 sega 91 -4075 1068 346 segb 57 975 1068 397 segb 74 -1575 1068 448 segb 91 -4125 1068 347 segc 57 925 1068 398 segc 74 -1625 1068 449 segc 91 -4175 1068 348 sega 58 875 1068 399 sega 75 -1675 1068 450 sega 92 -4225 1068 349 segb 58 825 1068 400 segb 75 -1725 1068 451 segb 92 -4275 1068 350 segc 58 775 1068 401 segc 75 -1775 1068 452 segc 92 -4325 1068 351 sega 59 725 1068 402 sega 76 -1825 1068 453 sega 93 -4375 1068 352 segb 59 675 1068 403 segb 76 -1875 1068 454 segb 93 -4425 1068 353 segc 59 625 1068 404 segc 76 -1925 1068 455 segc 93 -4475 1068 354 sega 60 575 1068 405 sega 77 -1975 1068 456 sega 94 -4525 1068 355 segb 60 525 1068 406 segb 77 -2025 1068 457 segb 94 -4575 1068 356 segc 60 475 1068 407 segc 77 -2075 1068 458 segc 94 -4625 1068 357 sega 61 425 1068 408 sega 78 -2125 1068 459 sega 95 -4675 1068 NJU6821 -7 - pad coordinates 4 chip size 19910 m x 2550 m (chip center 0 m x 0 m ) pad no. terminal x( m) y( m) pad no. terminal x ( m) y ( m) p ad no. terminal x ( m) y ( m) 460 segb 95 -4725 1068 511 segb 112 -7275 1068 562 segsa 2 -9726 800 461 segc 95 -4775 1068 512 segc 112 -7325 1068 563 segsb 2 -9726 750 462 sega 96 -4825 1068 513 sega 113 -7375 1068 564 segsc 2 -9726 700 463 segb 96 -4875 1068 514 segb 113 -7425 1068 565 segsa 3 -9726 650 464 segc 96 -4925 1068 515 segc 113 -7475 1068 566 segsb 3 -9726 600 465 sega 97 -4975 1068 516 sega 114 -7525 1068 567 segsc 3 -9726 550 466 segb 97 -5025 1068 517 segb 114 -7575 1068 568 com 40 -9726 500 467 segc 97 -5075 1068 518 segc 114 -7625 1068 569 com 41 -9726 450 468 sega 98 -5125 1068 519 sega 115 -7675 1068 570 com 42 -9726 400 469 segb 98 -5175 1068 520 segb 115 -7725 1068 571 com 43 -9726 350 470 segc 98 -5225 1068 521 segc 115 -7775 1068 572 com 44 -9726 300 471 sega 99 -5275 1068 522 sega 116 -7825 1068 573 com 45 -9726 250 472 segb 99 -5325 1068 523 segb 116 -7875 1068 574 com 46 -9726 200 473 segc 99 -5375 1068 524 segc 116 -7925 1068 575 com 47 -9726 150 474 sega 100 -5425 1068 525 sega 117 -7975 1068 576 com 48 -9726 100 475 segb 100 -5475 1068 526 segb 117 -8025 1068 577 com 49 -9726 50 476 segc 100 -5525 1068 527 segc 117 -8075 1068 578 com 50 -9726 0 477 sega 101 -5575 1068 528 sega 118 -8125 1068 579 com 51 -9726 -50 478 segb 101 -5625 1068 529 segb 118 -8175 1068 580 com 52 -9726 -100 479 segc 101 -5675 1068 530 segc 118 -8225 1068 581 com 53 -9726 -150 480 sega 102 -5725 1068 531 sega 119 -8275 1068 582 com 54 -9726 -200 481 segb 102 -5775 1068 532 segb 119 -8325 1068 583 com 55 -9726 -250 482 segc 102 -5825 1068 533 segc 119 -8375 1068 584 com 56 -9726 -300 483 sega 103 -5875 1068 534 sega 120 -8425 1068 585 com 57 -9726 -350 484 segb 103 -5925 1068 535 segb 120 -8475 1068 586 com 58 -9726 -400 485 segc 103 -5975 1068 536 segc 120 -8525 1068 587 com 59 -9726 -450 486 sega 104 -6025 1068 537 sega 121 -8575 1068 588 com 60 -9726 -500 487 segb 104 -6075 1068 538 segb 121 -8625 1068 589 com 61 -9726 -550 488 segc 104 -6125 1068 539 segc 121 -8675 1068 590 com 62 -9726 -600 489 sega 105 -6175 1068 540 sega 122 -8725 1068 591 com 63 -9726 -650 490 segb 105 -6225 1068 541 segb 122 -8775 1068 592 com 64 -9726 -700 491 segc 105 -6275 1068 542 segc 122 -8825 1068 593 com 65 -9726 -750 492 sega 106 -6325 1068 543 sega 123 -8875 1068 594 com 66 -9726 -800 493 segb 106 -6375 1068 544 segb 123 -8925 1068 595 dmy 7 (l) -9726 -850 494 segc 106 -6425 1068 545 segc 123 -8975 1068 596 dmy 7 (r) -9726 -900 495 sega 107 -6475 1068 546 sega 124 -9025 1068 496 segb 107 -6525 1068 547 segb 124 -9075 1068 497 segc 107 -6575 1068 548 segc 124 -9125 1068 498 sega 108 -6625 1068 549 sega 125 -9175 1068 499 segb 108 -6675 1068 550 segb 125 -9225 1068 500 segc 108 -6725 1068 551 segc 125 -9275 1068 501 sega 109 -6775 1068 552 sega 126 -9325 1068 502 segb 109 -6825 1068 553 segb 126 -9375 1068 503 segc 109 -6875 1068 554 segc 126 -9425 1068 504 sega 110 -6925 1068 555 sega 127 -9475 1068 505 segb 110 -6975 1068 556 segb 127 -9525 1068 506 segc 110 -7025 1068 557 segc 127 -9575 1068 507 sega 111 -7075 1068 558 dmy 5 (l) -9625 1068 508 segb 111 -7125 1068 559 dmy 5 (r) -9675 1068 509 segc 111 -7175 1068 560 dmy 6 (l) -9726 900 510 sega 112 -7225 1068 561 dmy 6 (r) -9726 850 NJU6821 - 8 - block diagram rs p/s sel68 csb wrb rdb test resb m/s v ss v dd v lcd , v 1 -v 4 v out v ba v ee mpu interface bus holder internal bus column address decoder display timing generator line counter line address decoder row address decoder display data ram (dd ram) 128x80x(3+3+2)bit icon data ram (pg ram) 128x2x(3+3+2)bit segment driver clk fr flm cl common driver initial display line register 5 c 1 - c 1 + c 2 + c 2 - v ref c 3 + c 3 - c 4 + c 4 - segsa 0 segsb 0 segsc 0 sega 0 segb 0 segc 0 sega 127 segb 127 segc 127 segsa 2 segsb 2 segsc 2 comi 0 com 0 com 79 comi 1 gradation circuit data latch circuit shift register row address register row address counter column address counter column address register d 7 d 4 /spol d 6 d 15 d 14 d 13 d 12 d 5 d 11 d 10 d 9 d 8 d 3 /smode d 0 /scl d 2 /excs d 1 /sda ram interface pole control instruction decoder osc 1 segsa 3 segsb 3 segsc 3 segsa 1 segsb 1 segsc 1 c 5 + c 5 - c 6 + c 6 - register read control oscillator i/o buffer v ssh osc 2 v reg v dda v ssa voltage regulator voltage booster NJU6821 -9 - power supply circuits block diagram v ba v ref v out v ee voltage booster c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v reg + - + - + - + - + - boost level register evr register v 1 v 2 v 3 v 4 v lcd + - gain control (1x-7x) + - voltage regulator reference voltage generator e.v.r. 1/2v re g NJU6821 - 10 - terminal description 1 no. symbol i/o function 21,22,23, 39,40,41 v dd power power supply for logic circuits 27,28,29, 58,59,60 v ss power gnd for logic circuits 67,68,69, 88,89,90 v ssh power gnd for high voltage circuits 31 v dda power this terminal is internally connected to the v dd level. ? this terminal is used to fix the selection terminals to the v dd level. note) do not use this terminal for a main power supply. 17,18,19, 34,35,36 v ssa power this terminal is internally connected to the v ss level. ? this terminal is used to fix the selection terminals to the v ss level. note) do not use this terminal for a main gnd. 7 0,71,115,116 72,73 74,75 76,77 78,79 v lcd v 1 v 2 v 3 v 4 power/o lcd driving voltages ? when the internal voltage booster is not used, external lcd driving voltages (v 1 to v 4 and v lcd ) must be supplied on these terminals. and the external voltages must be maintained in the following relation. v ss NJU6821 - 12 - terminal description 3 no. symbol i/o function mpu interface type selection sel68 h l status 68 series 80 series 33 sel68 i parallel / serial interface mode selection p/s chip select data/instruction data read/write serial clock h csb rs d0~d7 rdb, wrb - l csb rs sda (d1) write only scl (d0) 32 p/s i ? since the d 15 to d 5 terminals are in the high impedance in the serial interface mode (p/s=?0?), they must be fixed to ?1? or ?0?. the rdb and wrb terminals also must be ?1? or ?0?. 20 test i maker test terminal this terminal should be fixed to ?0?. lcd line clock ? this signal is used to count up the line counter and latch the display data into the data latch circuit. ? at the rising edge of the cl signal, the line counter is counted-up and the 384-bit display data, corresponding to the counted-up line address, is latched into the data latch circuit. at the falling edge of the cl signal, the latched data output onto the segment drivers. m/s status cl h master output l slave input 61 cl i/o lcd frame maker signal ? this signal is used to indicate the start of a new display frame. it presets an initial display line address into the line counter when the flm signal becomes ?1?. m/s status flm h master output l slave input 62 flm i/o lcd alternate signal ? this signal is toggled to alternate the crystal polarization of a lcd panel. it can be programmed so that the fr signal will toggle at every frame or once every n frames in the n-line inversion mode. m/s status fr h master output l slave input 63 fr i/o master / slave select m/s status oscillator power supply h master enable enable l slave disable disable 30 m/s i NJU6821 - 13 - terminal description 4 no. symbol i/o function segment output rev mode turn-off turn-on normal 0 1 reverse 1 0 ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and display data. in the b/w mode fr signal display data normal display mode v 2 v lcd v 3 v ss reverse display mode v lcd v 2 v ss v 3 174 ? 557 sega 0 -sega 127 , segb 0 -segb 127 , segc 0 -segc 127 o 164 ? 169, 562 ? 567 segsa 0 -segsa 3 , segsb 0 -segsb 3 , segsc 0 -segsc 3 o icon-segment output ? these terminals are assigned at both edge of normal segment output terminals line for out line frame display. common output ? these terminals output lcd driving waveforms in accordance with the combination of the fr signal and scanning data. data fr output level h h v ss l h v 1 h l v lcd l l v 4 162 ? 137, 132 ? 119, 568 ? 594, 3 ? 15 com 0 -com 79 o 163 comi 0 o icon common output 16 comi 1 o icon common output 65, 66 osc 1 osc 2 i o osc ? when the internal oscillator clock is used in the master mode or when the lsi is used in the slave mode, these terminals must be opened. in these cases, the osc 1 outputs the v ss level. ? when an external oscillator is used, external clock is input to the osc 1 terminal or an external resistor is connected between the osc 1 and osc 2 terminals. display timing synchronous clock ? this signal is used to synchronize the display timing between the master and slave lsis. m/s mode clk h master output l slave input 64 clk i/o (terminal no. 1,2,133,134,135,136,170,171,172,173,558,559,560,561,595, and 596 are dummy.) NJU6821 - 14 - functional description (1) mpu interface (1-1) selection of parallel / serial interface mode the p/s terminal is used to select parallel or serial interface mode as shown in the following table. in the serial interface mode, it is not possible to read out display data from the ddram, and status from the internal registers. table p/s p/s mode csb rs rdb wrb sel68 sda scl data h parallel i/f csb rs rdb wrb sel68 d 7 -d 0 (d 15 -d 0 ) l serial i/f csb rs - - - sda scl - note 1) ? -? : fix to ?1? or ?0?. (1-2) selection of mpu interface type in the parallel interface mode, the sel68 terminal is used to select 80- or 68-series mpu interface type, as shown in the following table. table sel68 mpu type csb rs rdb wrb data h 68 series mpu csb rs e r/w d7-d0 (d15-d0) l 80 series mpu csb rs rdb wrb d7-d0 (d15-d0) (1-3) data distinction in the parallel interface mode, the combination of rs, rdb, and wrb (r/w) signals distinguishes transferred data between the lsi and mpu as instruction or display data, as shown in the following table. table 68 series 80 series rs r/w rdb wrb function h h l h read out instruction data h l h l write instruction data l h l h read out display data l l h l write display data (1-4) selection of serial interface mode in the serial interface mode, the smode terminal is used to select the 3- or 4-line serial interface mode as shown in the following table. table smode serial interface mode h 3-line l 4-line NJU6821 - 15 - (1-5) 4-line serial interface mode in the serial interface mode, when the chip select is active (csb=?0?), the sda and the scl are enabled. when the chip select is not active (csb=?1?), the sda and the scl are disabled, and the internal shift register and the counter are being initialized. the 8-bit serial data on the sda is fetched at the rising edge of the scl signal in order of the d 7 , d 6 ?d 0 , and the fetched data is converted into the 8-bit parallel data at the rising edge of the 8th scl signal. in the 4-line serial interface mode, the transferred data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs signal. table rs data distinction h instruction data l display data since the serial interface operation is sensitive to external noises, the scl should be set to ?0? after data transmissions or during non-access. to release a mal-function caused by the external noises, the chip- selected status should be released (csb=?1?) after each of the 8-bit data transmissions. the following figure illustrates the interface timing for the 4-line serial interface operation. 4-line serial interface timing (1-6) 3-line serial interface mode in the serial interface mode, when the chip select is active (csb=?0?), the sda and scl are enabled. when the chip select is not active (csb=?1?), the sda and scl are disabled and the internal shift register and counter are being initialized. 9-bit serial data on the sda is fetched at the rising edge of the scl signal in order of the rs, d 7 , d 6 ?d 0 , and the fetched data is converted into the 9-bit parallel data at the falling edge of the 9th scl signal. in the 3-line serial interface mode, data on the sda is distinguished as display data or instruction data in accordance with the condition of the rs bit of sda data and the status of the spol, as follows. table spol=l spol=h rs data distinction rs data distinction l display data l instruction data h instruction data h display data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 valid 1 2 3 4 5 6 7 8 csb rs sda scl NJU6821 - 16 - since the serial interface operation is sensitive to external noises, the scl must be set to ?0? after data transmissions or during non-access. to release a malfunction caused by the external noises, the chip- selected status should be released (csb=?1?) after each of 9-bit data transmissions. the following figure illustrates the interface timing of the 3-line serial interface operation. 3-line serial interface timing (1-7) unification of the csb signals (in the serial interface mode) when two of the NJU6821 is used as a master and slave driver in the 3- or 4-line serial interface mode, both of the csb signals can be notified using the excs terminals in order to simplify the control signals. in this time, the master?s excs is assigned to output and slave?s excs is assigned to input. the status of the excs signal is controlled by the ?excs control? instruction. of the master lsi. during both of the excs and csb are ?0?, the slave lsi is enabled to accept instructions from mpu but the master lsi is disabled to accept any instruction except the ?excs control? instruction. during the excs is ?1? and csb is ?0?, the master lsi is enabled and the slave lsi is disabled. 4-line serial interface rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 1 2 3 4 5 6 7 8 csb sda scl d 0 9 excs: extension csb excs=0, csb=0: slave lsi is enabled excs=1,csb=0: master lsi is enabled p/s=0: serial interface p/s=1: parallel interface p/s: parallel/serial interface mode select m/s=0: slave operation m/s=1: master operation m/s: master/slave select smode=0: 4-line serial interface smode=1: 3-line serial interface smode: 3-/4-line serial interface mode select spol=0, rs=0: display data spol=0, rs=1: instruction data spol=1, rs=0: instruction data spol=1, rs=1: display data spol: rs polarity select (in the 3-line serial interface mode) sda csb scl rs m/s p/s smode spol excs (master) sda csb scl rs m/s p/s smode spol excs (slave) csb sda scl rs NJU6821 - 17 - (2) access to the ddram when the csb signal is ?0?, the transferred data from mpu is written into the ddram or instruction register in accordance with the condition of the rs signal. when the rs signal is ?1?, the transferred data is distinguished as display data. after the ?column address? and ?row address? instructions are executed, the display data can be written into the ddram by the ?display data write? instruction. the display data is written at the rising edge of the wrb signal in the 80 series mpu mode, or at the falling edge of the e signal in the 68 series mpu mode. table rs data distinction h display ram data l internal command register in the sequence of the ?display data read? operation, the transferred data from mpu is temporarily held in the internal bus-holder and then transferred to the internal data-bus. when the ?display data read? operation is executed just after the ?column address? and ?row address? instructions or ?display data write? instruction, unexpected data on the bus-holder is read out at the 1st execution, then the data of designated ddram address is read out from the 2nd execution. for this reason, a dummy read cycle must be executed to avoid the unexpected 1st data read. display data write operation display data read operation note) in the 16-bit data bus mode, instruction data must be 16-bit as well as the display data. n n+2 d 0 to d 15 wrb bus holder wrb n n+1 n+2 n+3 n+4 n+1 n+3 n+4 internal d 0 to d 7 (d 0 to d 15 ) rdb n n n+1 n+2 wrb address set n dummy read data read n address data read n+1 address data read n+2 address NJU6821 - 18 - (3) access to the instruction register each of the instruction resisters is assigned to each address between 0 h and f h and content of the instruction register can be read out by the combination of the ?instruction resister address? and ?instruction resister read?. (4) 8-/16-bit data bus length for display data (in the parallel interface mode) the 8- or 16-bit data bus length for display data is determined by the ?wls? of the ?data bus length? instruction. in the 16-bit data bus mode, instruction data must be 16-bit (d 15 to d 0 ) as well as display data. however, for the access to the instruction register, the only lower 8-bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. table wls data bus length mode l 8-bit h 16-bit (5) initial display line register the initial display line resister specifies the line address, corresponding to the initial com line, by the ?initial display line? instruction. the initial com line signifies the common driver, starting scanning the display data in the ddram, and specified by the ?initial com line? instruction. the line address, established in the initial display line resister, is preset into the line counter whenever the flm signal becomes ?1?. at the rising edge of the cl signal, the line counter is counted-up and addressed 384-bit display data, corresponding to the counted-up line address, is latched into the data latch circuit. at the falling edge of the cl signal, the latched data outputs to the segment drivers. d 0 ~d 7 m n wrb instruction resister address set instruction resister read mn rdb instruction resister address set instruction resister read NJU6821 - 19 - (6) ddram mapping the ddram is capable of 1,024-bit (8-bit x 128-segment) for the column address and 82-bit for the row address. in the gradation mode, each pixel for rgb corresponds to the successive 3-segment drivers that consist of 2- segment drivers for 8-gradation and 1-segment driver for 4-gradation, so that the lsi can drive a 256-color display (8-gradation x 8-gradation x 4-gradation) with up to 128x82 pixels. the 8-gradation level is controlled by 3-bit display data in the ddram and 4-gradation level is controlled by 2-bit display data in the ddram respectively. in the b&w mode, only msb data from each 3-bit and 2-bit rgb display data group in the ddram is used. therefore, 384 x 82 pixels in the b&w display is also available. the range of the column address varies depending on data bus length. the range between 00 h and 70f is used in the 8-bit data bus length and the range between 00 h and 3f h is in the 16-bit data bus length. in the 8-bit data bus length mode column-address 0 h 1 h 7e h 7f h 0 h 8bit 8bit 8bit 8bit row- address 51 h 8bit 8bit 8bit 8bit in the 16-bit data bus length mode column-address 0h 3fh 0 h 16bit 16bit row- address 51h 16bit 16bit the ddram is accessing 8-bit or 16-bit unit addressed by column and row address. in the 16-bit data bus length mode, over 40h address setting is prohibited. the increment for the column address and row address are set to the auto-increment mode by programming ?axi? and ?ayi? registers of the ?increment control? instruction. in this mode, the contents of the column address and row address counters automatically increment whenever the ddram is accessed. the column address and row address counters, independent of the line counter. they are used to designate the column address and row address for the display data transferred from mpu. on the other hand, the line counter is used to generate the line address, and output display data to the segment drivers, being synchronized with the display control timing of the flm and cl signals. NJU6821 - 20 - (7) window addressing mode in addition to the above usual ddram addressing, it is possible to access some part of ddram in using the window addressing mode, in which the start and end points are designated. the start point is determined by the ?column address? and ?row address? instructions, and the end point is determined by the ?window end column address ?and ?window end row address? instructions. the setting example of the window addressing is listed, as follows. 1. set win=1, axi=1, and ayi=1 by the ?increment control? instruction 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode in the window addressing mode (win=1, axi=1, ayi=1), the read-modify-write operation is available by setting ?0? to the ?aim? register of the ?increment control? instruction. and in the window addressing mode, the following start and end point must be maintained to abide a malfunction. ax (column address of start point) < ex (column address of end point) < maximum of column address ay (row address of start point) < ey (row address of end point) < maximum of row address column address (x, y) start point end point row address window display area (x, y) whole ddram area (8) reverse display on/off the ?reverse display on/off? function is used to reverse the display data without changing the contents of the ddram. table rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0 (9) segment direction the ?segment direction? function is used to reverse the assignment for the segment drivers and column address, and it is possible to reduce the restrictions for the placement of the lsi on the lcd modules. NJU6821 - 21 - (10) the relationship among the ddram column address, display data and segment drivers in the color mode, and 16-bit data bus mode ref swap column address / bit / segment assign 0 0 x=00h ?????? x=3fh 1 1 x=3fh ?????? x=00h d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ?????? d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 palette a palette b palette c palette a palette b palette c ?????? palette a palette b palette c palette a palette b palette c sega0 segb0 segc0 sega1 segb1 segc1 ?????? sega126 segb126 segc126 sega127 segb127 segc127 ref swap column address / bit / segment assign 0 1 x=00h ?????? x=3fh 1 0 x=3fh ?????? x=00h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ?????? d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 palette c palette b palette a palette c palette b palette a ?????? palette c palette b palette a palette c palette b palette a sega0 segb0 segc0 sega1 segb1 segc1 ?????? sega126 segb126 segc126 sega127 segb127 segc127 in the color mode, and 8-bit data bus mode ref swap column address / bit / segment assign 0 0 x=00h x=01h ?????? x=7eh x=7fh 1 1 x=7fh x=7eh ?????? x=01h x=00h d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 ?????? d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 palette a palette b palette c palette a palette b palette c ?????? palette a palette b palette c palette a palette b palette c sega0 segb0 segc0 sega1 segb1 segc1 ?????? sega126 segb126 segc126 sega127 segb127 segc127 ref swap column address / bit / segment assign 0 1 x=00h x=01h ?????? x=7eh x=7fh 1 0 x=7fh x=7eh ?????? x=01h x=00h d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ?????? d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 palette c palette b palette a palette c palette b palette a ?????? palette c palette b palette a palette c palette b palette a sega0 segb0 segc0 sega1 segb1 segc1 ?????? sega126 segb126 segc126 sega127 segb127 segc127 NJU6821 - 22 - in the b&w mode, and 16-bit data bus mode ref swap column address / bit / segment assign 0 0 x=00h ?????? x=3fh 1 1 x=3fh ?????? x=00h d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ?????? d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 sega0 segb0 segc0 sega1 segb1 segc1 ?????? sega126 segb126 segc126 sega127 segb127 segc127 ref swap column address / bit / segment assign 0 1 x=00h ?????? x=3fh 1 0 x=3fh ?????? x=00h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ?????? d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sega0 segb0 segc0 sega1 segb1 segc1 ?????? sega126 segb126 segc126 sega127 segb127 segc127 in the b&w mode, and 8-bit data bus mode ref swap column address / bit / segment assign 0 0 x=00h x=01h ?????? x=7eh x=7fh 1 1 x=7fh x=7eh ?????? x=01h x=00h d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 ?????? d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 sega0 segb0 segc0 sega1 segb1 segc1 ?????? sega126 segb126 segc126 sega127 segb127 segc127 ref swap column address / bit / segment assign 0 1 x=00h x=01h ?????? x=7eh x=7fh 1 0 x=7fh x=7eh ?????? x=01h x=00h d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ?????? d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sega0 segb0 segc0 sega1 segb1 segc1 ?????? sega126 segb126 segc126 sega127 segb127 segc127 NJU6821 - 23 - bit assignments bitween write and read data (in the 16-bit data bus mode) ref=0, swap=0 write data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 segment data seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10seg11 seg12seg1 3 seg1 4 seg15 read data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ref=0, swap=1 write data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 segment data seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10seg11 seg12seg1 3 seg1 4 seg15 read data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ref=1, swap=0 write data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 segment data seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10seg11 seg12seg1 3 seg1 4 seg15 read data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 ref=1, swap=1 write data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 segment data seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10seg11 seg12seg1 3 seg1 4 seg15 read data d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 NJU6821 - 24 - examples for write and read data (in the 16-bit data bus mode) ref=0, swap=0 d15 d0 write data 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 (e4f2h) d1 5 d0 read data 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 (e4f2h) ref=0, swap=1 d15 d0 write data 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 (e4f2h) d15 d0 read data 0 1 0 0 1 1 1 1 0 0 1 0 0 1 1 1 (4f27h) ref=1, swap=0 d15 d0 write data 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 (e4f2h) d15 d0 read data 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 (e4f2h) ref=1, swap=1 d15 d0 write data 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 (e4f2h) d15 d0 read data 0 1 0 0 1 1 1 1 0 0 1 0 0 1 1 1 (4f27h) NJU6821 - 25 - bit assignments between write and read data (in the 8-bit data bus mode) ref=0, swap=0 write data d0 d1 d2 d3 d4 d5 d6 d7 segment data seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 read data d0 d1 d2 d3 d4 d5 d6 d7 ref=0, swap=1 write data d0 d1 d2 d3 d4 d5 d6 d7 segment data seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 read data d0 d1 d2 d3 d4 d5 d6 d7 ref=1, swap=0 write data d0 d1 d2 d3 d4 d5 d6 d7 segment data seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 read data d0 d1 d2 d3 d4 d5 d6 d7 ref=1, swap=1 write data d0 d1 d2 d3 d4 d5 d6 d7 segment data seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 read data d0 d1 d2 d3 d4 d5 d6 d7 NJU6821 - 26 - examples for write and read data (in the 8-bit data bus mode) ref=0, swap=0 d15 d0 write data 1 1 1 0 0 1 0 0 (e4h) d15 d0 read data 1 1 1 0 0 1 0 0 (e4h) ref=0, swap=1 d15 d0 write data 1 1 1 0 0 1 0 0 (e4h) d15 d0 read data 0 0 1 0 0 1 1 1 (27h) ref=1, swap=0 d15 d0 write data 1 1 1 0 0 1 0 0 (e4h) d15 d0 read data 1 1 1 0 0 1 0 0 (e4h) ref=1, swap=1 d15 d0 write data 1 1 1 0 0 1 0 0 (e4h) d15 d0 read data 0 0 1 0 0 1 1 1 (27h) NJU6821 - 27 - the relationship among the pgram column address, display data and segment drivers in the color mode, and 16-bit data bus mode ref swap column address / bit / segment assign 0 0 x=00h x=01h 1 1 x=01h x=00h d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 palette a palette b palette c palette a palette b palette c palette a palette b palette c palette a palette b palette c segsa0 segsb0 segsc0 segsa1 segsb1 segsc1 segsa2 segsb2 segsc2 segsa3 segsb3 segsc3 ref swap column address / bit / segment assign 0 1 x=00h x=01h 1 0 x=01h x=00h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 palette c palette b palette a palette c palette b palette a palette c palette b palette a palette c palette b palette a segsa0 segsb0 segsc0 segsa1 segsb1 segsc1 segsa2 segsb2 segsc2 segsa3 segsb3 segsc3 in the color mode, and 8-bit data bus mode ref swap column address / bit / segment assign 0 0 x=00h x=01h x=02h x=03h 1 1 x=03h x=02h x=01h x=00h d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 palette a palette b palette c palette a palette b palette c palette a palette b palette c palette a palette b palette c segsa0 segsb0 segsc0 segsa1 segsb1 segsc1 segsa2 segsb2 segsc2 segsa3 segsb3 segsc3 ref swap column address / bit / segment assign 0 1 x=00h x=01h x=02h x=03h 1 0 x=03h x=02h x=01h x=00h d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 palette c palette b palette a palette c palette b palette a palette c palette b palette a palette c palette b palette a segsa0 segsb0 segsc0 segsa1 segsb1 segsc1 segsa2 segsb2 segsc2 segsa3 segsb3 segsc3 NJU6821 - 28 - in the b&w mode, and 16-bit data bus mode ref swap column address / bit / segment assign 0 0 x=00h x=01h 1 1 x=01h x=00h d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 segsa0 segsb0 segsc0 segsa1 segsb1 segsc1 segsa2 segsb2 segsc2 segsa3 segsb3 segsc3 ref swap column address / bit / segment assign 0 1 x=00h x=01h 1 0 x=01h x=00h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 segsa0 segsb0 segsc0 segsa1 segsb1 segsc1 segsa2 segsb2 segsc2 segsa3 segsb3 segsc3 in the b&w mode, and 8-bit data bus mode ref swap column address / bit / segment assign 0 0 x=00h x=01h x=02h x=03h 1 1 x=03h x=02h x=01h x=00h d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 segsa0 segsb0 segsc0 segsa1 segsb1 segsc1 segsa2 segsb2 segsc2 segsa3 segsb3 segsc3 ref swap column address / bit / segment assign 0 1 x=00h x=01h x=02h x=03h 1 0 x=03h x=02h x=01h x=00h d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 segsa0 segsb0 segsc0 segsa1 segsb1 segsc1 segsa2 segsb2 segsc2 segsa3 segsb3 segsc3 NJU6821 - 29 - (11) gradation palette in the gradation mode, each of the gradation palettes aj can select 8-gradation levels out of a palette consisting of 32-gradation levels by setting 5-bit palette value into the ?pa? registers in the ?gradation palette aj? instructions (j=0 to 7). each of the gradation palettes bj and cj can select 8-gradation levels as well as the gradation palette aj. the gradation palettes aj correspond to the segai, the bj to segbj and the cj to segci (j=0 to 7, i=0 to 127). the display data (0,0,0) corresponds to the gradation palettes z0, the data (0,0,1) to the z1, the data (0,1,0) to the z2?the data (1,1,1) to the z7 (z=a, b and c). (12) gradation lsb (glsb) in the graduation mode, each pixel for rgb corresponds to the successive 3-segment drivers that consist of 2- segment drivers for 8-graduation and 1-segment driver for 4-gradietion. the 8-gradation segment drivers can generate 8-gradation levels controlled by 3-bit display data in the ddram. the 4-gradation segment drivers can generate 4-gradation levels by 2-bit in the ddram and 1-bit in the glsb. all of the selected 8-gradation palettes zj (z=a, b and c, j=0 to 7) are available for the 8-gradation segment drivers. however, the only 4-gradation palettes zj (z=a, b and c, j= either 0,2,4,6 or 1,3,5,7) are available for the 4-gradation segment drivers, because the glsb is fixed to either ?0? or ?1? by setting the ?glsb? register in the ?gradation control? instruction and adopted to all of the 4-gradation segment derivers. glsb=0: the lsb of display data is always set to ?0?. display data: (0,0,0), (0,1,0), (1,0,0), (1,1,0) gradation palettes: z0, z2, z4, z6 (z=a, b and c) glsb=1: the lsb of display data is always set to ?1?. display data: (0,0,1), (0,1,1), (1,0,1), (1,1,1) gradation palettes: z1, z3, z5, z7 (z=a, b and c) (13) variable or fixed gradation mode in the gradation mode, either variable or fixed gradation mode is selected by programming the ?pwm? register of the ?gradation control? instruction. pwm=0: variable gradation mode (select 8 gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) NJU6821 - 30 - correspondence between display data and gradation palettes (mon=?0?; gradation mode) (z=a, b and c, j=0 to 7) ( msb ) dis p la y data ( lsb ) gradation p alette z j default p alette value 0 0 0 palette z0 0 0 1 0 0 0 0 1 palette z1 0 0 1 0 1 0 1 0 palette z2 0 1 0 1 0 0 1 1 palette z3 0 1 1 1 0 1 0 0 palette z4 1 0 0 0 1 1 0 1 palette z5 1 0 1 0 1 1 1 0 palette z6 1 1 0 1 0 1 1 1 palette z7 1 1 1 1 1 gradation palette table (variable gradation mode, pwm=?0?, mon=?0?) (z=a, b and c, j=0 to 7) palette value gradation level gradation palette zj palette value gradation level gradation palette zj 0 0 0 0 0 0 palette z0 (default) 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 palette z4 (default) 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 1 0 0 1 1 19/31 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 palette z1 (default) 1 0 1 0 1 21/31 palette z5 (default) 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 1 0 1 1 1 23/31 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 1 1 0 0 1 25/31 0 1 0 1 0 10/31 palette z2 (default) 1 1 0 1 0 26/31 palette z6 (default) 0 1 0 1 1 11/31 1 1 0 1 1 27/31 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 1 1 1 0 1 29/31 0 1 1 1 0 14/31 palette z3 (default) 1 1 1 1 0 30/31 0 1 1 1 1 15/31 1 1 1 1 1 31/31 palette z7 (default) gradation palette table (fixed gradation mode, pwm=?1?, mon=?0?) 8-gradation segment drivers 4-gradation segment drivers display data display data (msb) ddram (lsb) gradation level ddram glsb gradation level 0 0 0 0 0 0 0 0 0 1 1/7 0 0 1 0 0 1 0 2/7 0 1 0 2/7 0 1 1 3/7 0 1 1 3/7 1 0 0 4/7 1 0 0 4/7 1 0 1 5/7 1 0 1 5/7 1 1 0 6/7 1 1 0 1 1 1 7/7 1 1 1 7/7 correspondence between display data and gradation level (b&w mode, mon=?1?) 8-gradation segment drivers 4-gradation segment drivers display data display data (msb) ddram (lsb) gradation level ddram glsb gradation level 0 0 0 0 0 0 * 0 0 0 1 0 0 1 * 0 0 1 0 0 1 0 * 1 0 1 1 0 1 1 * 1 1 0 0 1 *: don?t care 1 0 1 1 1 1 0 1 1 1 1 1 NJU6821 - 31 - (14) gradation control and display data (14-1) gradation mode in the graduation mode, each pixel for rgb corresponds to the successive 3 segment drivers that consist of 2 segment drivers for 8-graduation and 1 segment driver for 4-gradietion, so that NJU6821 can drive a 256-color display (8-gradation x 8-gradation x 4-gradition) with up to 128x82 pixels. the 8-gradation segment drivers can generate 8-gradation levels controlled by using 3-bit of display data in the ddram. the 4-gradation segment drivers can generate 4-gradation levels by using 2-bit in the ddram and 1-bit in the glsb. in addition, the lsi can transfer 8-bit display data for 1-pixel the rgb or 16-bit for 2-pixels rgb to the ddram at one-time access. the data assignment between gradation palettes and segment drivers varies in accordance with the setting for the ?swap? and ?ref? registers of the "display control (2)" instruction. (ref, swap)=(0, 0) or (1, 1) note) ddram column address : 7 h 7f h (ref=?0?) :7f h n h (ref=?1?) (ref, swap)=(0, 1) or (1, 0) note) ddram column address : nh (ref=?0?) : 7f h nh (ref=?1?) segai segbi palette bj 0 0 palette aj 1 0 0 segci palette cj 1 1 1 msb lsb msb lsb msb 0 0 1 0 0 1 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 glsb gradation palette (i=0 to 127) (j=0 to 7) display data from mpu column address: n h gradation control circuit display data in ddram segai segbi 1 1 1 0 0 segci palette aj palette bj palette cj 1 0 0 msb lsb msb lsb msb 0 0 1 0 0 1 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gradation palette (i=0 to 127) (j=0 to 7) display data from mpu column address: n h gradation control circuit display data in ddram 0 glsb NJU6821 - 32 - in the 16-bit data bus mode, the data assignments between the gradation palettes and the segment drivers vary in accordance with setting for the ?swap? and ?ref? bit of the "display control (2)" instruction as well as the assignment in the 8-bit data bus mode. (ref, swap)=(0, 0) or (1, 1) note) ddram column address : n h (ref=?0?) : 3f h n h (ref=?1?) (ref, swap)=(0, 0) or (1, 1) note) ddram column address :n h (ref=?0?) :3f h nh (ref=?1?) segai segbi 0 palette aj segci palette cj msb lsb msb lsb msb glsb gradation palette (i=0 to 126) (j=0 to 7) display data from mpu column address: n h gradation control circuit display data in ddram 0 0 0 0 1 1 1 1 0 1 0 lsb msb lsb msb msb segbi+1 palette bj palette cj palette bj palette aj segai+1 segci+1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 segai segbi 1 palette aj segci palette cj msb lsb msb lsb msb glsb gradation palette (i=0 to 126) (j=0 to 7) display data from mpu column address: n h gradation control circuit display data in ddram 1 0 0 1 1 1 0 0 1 1 0 lsb msb lsb msb msb segbi+1 palette bj palette cj palette bj palette aj segai+1 segci+1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 d 14 d 15 NJU6821 - 33 - (14-2) b&w mode (mon=?1?) in the b&w mode and 8-bit data bus mode, only 3 of msb of each display data is used for the display. in the 16-bit data bus mode, 6 of msb of each display data are used. in the 8-bit data bus mode (similarly 16-bit data bus access) (ref, swap)=(0, 0) or (1, 1) note) ddram column address : n h (ref=?0?) : 7f h n h (ref=?1?) (ref, swap)=(0, 1) or (1, 0) note) ddram column address : n h (ref=?0?) : 7f h n h (ref=?1?) segai segbi palette bj 0 0 palette a j 1 0 0 segci palette cj 1 1 1 msb lsb msb lsb msb 0 0 1 0 0 1 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 glsb gradation palette (i=0 to 127) (j=0 to 7) display data from mpu column address: n h gradation control circuit display data in ddram segci segbi 1 1 1 0 0 segai palette cj palette bj palette aj 1 0 0 msb lsb msb lsb msb 0 0 1 0 0 1 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gradation palette (i=0 to 127) (j=0 to 7) display data from mpu column address: n h gradation control circuit display data in ddram 0 glsb NJU6821 - 34 - (15) display timing generator the display-timing generator creates the timing pulses such as the cl, the flm, the fr and the clk by dividing the oscillation frequency oscillate an external or internal resister mode. the timming pulse terminals and timing generator status is setting by the master/slave (m/s) terminal as described in the following table. the statuses of timing pulse terminal and generator m/s mode cl fr flm clk l slave input input input input h master output output output output (16) lcd line clock (cl) the lcd line clock (cl) is used as a count-up signal for the line counter and a latch signal for the data latch circuit. at the rising edge of the cl signal, the line counter is counted-up and the 384-bit display data, corresponding to this line address, is latched into the data latch circuit. and at the falling edge of the cl signal, this latched data output on the segment drivers. read out timing of the display data, from ddram to the latch circuits, is completely independent of the accsess timing to the mpu. for this reason, the mpu can access to the lsi regardless of an internal operation. (17) lcd alternate signal (fr) and lcd synchronous signal (flm) the fr and flm signals are created from the cl signal. the fr signal is used to alternate the crystal polarization on a lcd panel. it is programmed that the fr signal is toggle on every frame in the default setting or once every n lines in the n-line inversion mode. the flm signal is used to indicate a start line of a new display frame. it presets an initial display line address of the line counter when the flm signal becomes ?1?. when two of NJU6821 is using as a master and slave, the cl, the flm, the fr, and the clk signals should be supplied from master NJU6821 to slave NJU6821 . (18) data latch circuit the data latch circuit is used temporarily store the display data that will output to the segment drivers. the display data in this circuit is updated in synchronization of the cl signal. the ?all pixels on/off?, ?display on/off? and ?reverse display on/off? instructions change the display data in this circuit but do not change the display data of the ddram. NJU6821 - 35 - lcd driving waveforms (in the b&w mode, reverse display off, 1/82 duty) com 1 com 0 seg 1 seg 0 seg 2 com 1 seg 1 seg 0 v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss com 0 v lcd v 1 v 2 v 3 v 4 v ss fr flm cl 82 1 2 4 3 5 82 1 2 4 3 5 82 1 NJU6821 - 36 - (19) common and segment drivers the lsi includes 384-segment drivers and 82-commom drivers for a graphic display. 2 out of 82-common drivers are assigned to the comi 0 and comi 1 for an icon display. the common drivers generate the lcd driving waveforms composed of the v lcd , v 1 , v 4 and v ss in accordance with the fr signal and scanning data. the segment drivers generate the waveforms composed of the v lcd , v 2 , v 3 and v ss in accordance with the fr signal and display data. (20) icon segment drivers the 12-icon-segment drivers: segsak, segsbk and segsck (k=0 to 3) are mainly used for an outer-frame display. 6-icon-segment drivers each are positioned in both sides of the segment drivers? block. the icon segment drivers are controlled by the display data entered in the icon segment registers instead of the ddram. the dummy segment drivers segak correspond to the gradation palette aj, the segsbk to the palette bj and the segsck to the palette cj (k=0 to 3, j=0 to 7). the icon segment registers are capable of 4-byte display data, in which each byte is corresponding to 1-set of the icon segment drivers such as the segsa 0 , segsb 0 and segsc 0 . the icon segment registers are enabled by setting ?1? into the ?dmy? register in the ?icon segment register on/off? instruction and then the ?column address? instruction, where the column address such as 00h, 01h, 02h and 03h are available in the 8-bit data bus mode and the column address such as 00h and 01h in the 16- bit mode. the icon segment drivers are independent of the ?row address set? instruction. 8-bit data bus mode (dmy=?1?) column address 00h: segsa 0 , segsb 0 , segsc 0 01h: segsa 1 , segsb 1 , segsc 1 02h: segsa 2 , segsb 2 , segsc 2 03h: segsa 3 , segsb 3 , segsc 3 16-bit data bus mode (dmy=?1?) column address 00 h : segsa 0 , segsb 0 , segsc 0 , segsa 1 , segsb 1 , segsc 1 01 h : segsa 2 , segsb 2 , segsc 2 , segsa 3 , segsb 3 , segsc 3 the icon segment drivers can support the ?allon? and ?rev? registers in the ?display control (1), (2)? instructions but they cannot support the ?lrev? and ?bt? registers in the ?line inverse control? instruction. as well as the read sequence for the ddram, the sequence for the segment registers also requires the dummy read. 68 series 80 series rs dmy r/w rd wr function 0 0 1 0 1 read data from ddram 0 0 0 1 0 write data into ddram 0 1 1 0 1 read data from icon segment register 0 1 0 1 0 write data into icon segment register NJU6821 - 37 - examples for the icon segment registers (dmy=?1?) (in the 8-bit data bus mode, gradation mode, (ref, swap)=(0,0)) segsa 0 segsb 0 palette aj palette bj 0 0 1 0 0 segsc 0 palette cj 1 1 1 msb lsb msb lsb msb 0 0 1 0 0 1 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 glsb gradation palette (j=0 to 7) display data from mpu gradation control circuit icon segment register column address: 00 h segsa 3 segsb 3 palette aj palette bj 0 0 1 0 0 segsc 3 palette cj 1 1 1 msb lsb msb lsb msb 0 0 1 0 0 1 1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0 glsb gradation palette (j=0 to 7) display data from mpu gradation control circuit icon segment register column address: 03 h NJU6821 - 38 - (21) oscillator the oscillator generates the internal clocks for the display timing and the voltage booster. it is enabled only in the master mode operation by setting the ?m/s? terminal to ?1?. the c and r for the oscillator are on chipped, therefore, there is no c, r required as an external components. use an external r instead of internal r is also available(cks=1), in this time connect the resister between osc 1 and osc 2 terminals. however, when the internal oscillator is not used, an external clock inputs to the osc 1 terminal. in addition, the feed back resister for the oscillator is varied by programming the ?rf? register in the ?frequency control? instruction, so that it is possible to optimize the frame frequency for a lcd panel. setting examples of the mon(b&w /gradation) and the pwm(variable gradation /fixed gradation) are described, as follows. internal oscillation mode (cks=0) symbol ffl mon pwl display mode f 1 1 0 0 f 2 0 0 0 variable gradation mode f 3 1 0 1 f 4 0 0 1 fixed gradation mode f 5 1 1 * f 6 0 1 * b&w mode *: don?t care ? external resistor oscillation mode (cks=1) the internal clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?ffl?, ?mon? and ?pwm? register must be set as well. ? external clock input mode (cks=1) the external clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the ?ffl?, ?mon? and ?pwm? register must be set as well. (22) power supply circuits the internal power supply circuits are composed of the voltage booster, the electrical variable resister (evr), voltage regulator, reference voltage generator and the voltage followers. the condition of the power supply circuits is arranged by programming the ?dcon? and ?ampon? registers on the ?power control? instruction. for this arrangement, some parts of the internal power supply circuits are activated in using an external power supply, as shown in the following table. dcon ampon voltage booster voltage followers voltage regulator evr external voltage note 0 0 disable disable v out , v lcd , v 1 , v 2 , v 3 , v 4 1, 3 0 1 disable enable vout 2, 3 1 1 enable enable ? ? note1) the internal power circuits are not used. the external v out is required and c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, c 6 +, c 6 -, v ref , v reg and v ee terminals must be open. note2) the internal power circuits except the voltage booster are used. the external v out is required and the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, c 6 + and c 6 - terminals must be open. the reference voltage is required to v ref terminal. note3) the relation among the voltages should be maintained as follows. v out v lcd v 1 v 2 v 3 v 4 v ss NJU6821 - 39 - (23) voltage booster the voltage booster generates maximum 7x voltage of the v ee level. it is programmed so that the boost level is selected out of 1x, 2x, 3x, 4x, 5x, 6x and 7x by the ?boost level select? instruction. the boosted voltage v out must not exceed beyond the value of 18.0v, otherwise the voltage stress may cause a permanent damage to the lsi. boosted voltages capacitor connections for the voltage booster 7-time boost 6-time boost 5-time boost 4-time boost 3-time boost 2-time boost 3-time boost 7-time boost v ss =0v v ee =3v v out =9v v out =17.5v v ss =0v v ee =2.5v c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + + c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 4 + c 4 - c 5 + c 5 - c 6 + c 6 - v out + + NJU6821 - 40 - (24) reference voltage generator the reference voltage generator is used to produce the reference voltage (v ba ), which is output from the v ba terminal and should be input to the v ref terminal. v ba = v ee x 0.9 (25) voltage regulator the voltage regulator, composed of the gain control circuit and an operational amplifier, and is used to gain the reference voltage (v ref ) and to create the regulated voltage (v reg ). the v reg is used as an input voltage to the evr circuits, which is programming by the ?vu? register of the ?boost level? instruction. v reg = v ref x n (n: register value for the boost level) (26) electrical variable resister (evr) the evr is variable within 128-step, and is used to fine-tune the lcd driving voltage (v lcd ) by programming the ?dv? register in the ?evr control? instruction, so that it is possible to optimize the contrast level of lcd panels. v lcd = 0.5 x vreg + m (vreg - 0.5 x vreg) / 127 (m: register value for the evr) (27) lcd driving voltage generation circuit lcd driving voltage generation circuit generates the v lcd voltage levels as v lcd , v 1 , v 2 , v 3 and v 4 with internal e.v.r and the bleeder resistors. the bias ratio of the lcd driving voltage is selected out of 1/5, 1/6, 1/7, 1/8, 1/9, and 1/10. in using the internal power supply, the capacitors ca 2 must be connected to the v lcd , v 1 , v 2 , v 3 and v 4 terminals, and the ca 2 value must be determined by the evaluation with actual lcd modules. in using the external power supply, the external lcd driving voltages such as the v lcd , v 1 , v 2 , v 3 and v 4 are supplied and the internal power supply circuits must be set to ?off? by dcon = ampon = "0". in this mode, voltage booster terminals such as c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 +, c 5 -, c 6 +, c 6 -, v ee , v ref and v reg must be opened. in case that the voltage booster is not used but only some parts of internal power supply circuits (voltage followers, voltage regulator and evr) are used, the c 1 +, c 1 -, c 2 +, c 2 -, c 3 +, c 3 -, c 4 +, c 4 -, c 5 + c 5 -, c 6 +, and c 6 - terminals must be opened. and, the external power supply is input to the v out terminal, and the reference voltage to the v ref terminal. the capacitor ca 3 must connect to the v reg terminal for voltage stabilization. NJU6821 - 41 - connections of the capacitors for the voltage booster reference values ca 1 1.0 - 4.7 f ca 2 1.0 - 2.2 f ca 3 0.1 f note1) b grade capacitor is recommended for ca 1 -ca 3 . testing actual samples with an lcd panel is recommended to decide an optimum value of these capacitors. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v lcd , v 1 , v 2 , v 3 and v 4 ) reduces the step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, use the shortest possible wires and place the capacitors to be as close as possible to the lsi. using all of the internal power supply circuits (7-time boost) using only external power supply circuits external power circuit v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 v dd c 5 - c 5 + c 6 - c 6 + NJU6821 v lcd v 1 v 2 v 3 v 4 ca 1 ca 2 ca 2 ca 2 ca 2 ca 1 NJU6821 v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + c 6 - c 6 + ca 1 ca 1 ca 3 v ss v dd c a 1 NJU6821 - 42 - reference values ca 1 1.0 - 4.7 f ca 2 1.0 - 2.2 f ca 3 0.1 f note1) b grade capacitor is recommended for ca 1 -ca 3 . testing actual samples with an lcd panel is recommended to decide an optimum value of these capacitors. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v lcd , v 1 , v 2 , v 3 and v 4 ) reduces the step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, use the shortest possible wires and place the capacitors to be as close as possible to the lsi. using internal power supply circuits without the reference voltage generator (1) (7-time boost) using internal power supply circuits without the reference voltage generator (2) (7-time boost) v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + c 6 - c 6 + ca 1 ca 1 NJU6821 v dd ca 1 thermistor v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 3 v ss ca 1 ca 1 ca 1 ca 1 ca 1 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + c 6 - c 6 + ca 1 ca 1 NJU6821 v dd ca 1 NJU6821 - 43 - reference values ca 1 1.0 - 4.7 f ca 2 1.0 - 2.2 f ca 3 0.1 f note1) b grade capacitor is recommended for ca 1 -ca 3 . testing actual samples with an lcd panel is recommended to decide an optimum value of these capacitors. note2) parasitic resistance on the power supply lines (v dd , v ss , v ee , v ssh , v out , v lcd , v 1 , v 2 , v 3 and v 4 ) reduces the step-up efficiency of the voltage booster, and may have an impact on the lsi?s operation and display quality. to minimize this impact, use the shortest possible wires and place the capacitors to be as close as possible to the lsi. using nternal power supply circuits without the voltage booster external power circuit v dd v ee v ba v ref v reg c 1 - c 1 + c 2 - c 2 + c 3 - c 3 + c 4 - c 4 + v out v lcd v 1 v 2 v 3 v 4 ca 3 v ss v ss ca 2 ca 2 ca 2 ca 2 ca 2 c 5 - c 5 + c 6 - c 6 + NJU6821 ca 3 v ss c a 1 v dd ca 1 NJU6821 - 44 - (28) partial display function the partial display function is used to specify some parts of display area on a lcd panels. by using this function, lcd modules can work in lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. it is usually used to display a time and calendar in the extremely low power consumption. it can be programmed to select the duty cycle ratio (1/17, 1/26, 1/32, 1/38, 1/47, 1/66, 1/77), the lcd bias ratio, the boost level and evr value by the instructions. partial display image normal display partial display partial display sequence - boost level - evr value - lcd bias ratio - duty cycle ratio - initial display line - initial com line - other instructions njrc lcd driver low power and low voltage lcd driver optional status display off (on/off=?0?) internal power supply off (dcon=?0?, ampon=?0?) wait setting for lcd driving voltage-related functions setting for display-related functions internal power supply on (dcon=?1?, ampon=?1?) wait display on (on/off =?1?) partial display status NJU6821 - 45 - (29) discharge circuit discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and v lcd terminals. this circuit is activated by setting ?0? to the ?dis? register of the ?discharge? instruction or by setting the ?resb? terminal to ?0? level. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. (30) reset circuit the reset circuit initializes the lsi into the following default status. it is activated by setting the resb terminal to ?0? level. the resb terminal is usually required to connect to mpu reset terminal in order that the lsi can be initialized at the same timing of the mpu. default status 1. ddram display data :undefined 2. column address :00 h 3. row address :00 h 4. initial display line :0 h (1st line) 5. display on/off :off 6. reverse display on/off :off (normal) 7. duty cycle ratio :1/82 duty 8. n-line inversion on/off :off 9. com scan direction :com 0 com 79 , comi 0 , comi 1 10. increment mode :off 11. reverse seg direction :off (normal) 12. swap mode :off (normal) 13. evr value :(0, 0, 0, 0, 0, 0, 0) 14. internal power supply :off 15. display mode :gradation display mode 16. lcd bias ratio :1/9 bias 17. gradation palette 0 :(0, 0, 0, 0, 0) 18. gradation palette 1 :(0, 0, 1, 0, 1) 19. gradation palette 2 :(0, 1, 0, 1, 0) 20. gradation palette 3 :(0, 1, 1, 1, 0) 21. gradation palette 4 :(1, 0, 0, 0, 1) 22. gradation palette 5 :(1, 0, 1, 0, 1) 23. gradation palette 6 :(1, 1, 0, 1, 0) 24. gradation palette 7 :(1, 1, 1, 1, 1) 25. gradation mode control :variable gradation mode 26. glsb :glsb=0 27. data bus length :8-bit data bus length 28. discharge circuit :off NJU6821 - 46 - (31) power supply on/off sequences the following paragraphs describe power supply on/off sequences, which are to protect the lsi from over current. (31-1) using an external power supply ? power supply on sequence logic voltage (v dd ) must be always input first, and next the lcd driving voltages (v 1 to v 4 and v lcd ) are turned on. in using the external v out , the v dd must be input first, next the reset operation must be performed, and finally the v out can be input. ? power supply off sequence either the reset operation, cutting off the v 1 to v 4 and v lcd from the lsi by the resb terminal or the ?power control? instruction must be performed first, and next the v dd is turned off. it is recommended that a series-resister between 50 ? and 100 ? is added on the v lcd line (or v out line in using only the external v out voltage) in order to protect the lsi from the over current. (31-2) using the internal power supply circuits ? power supply on sequence the v dd must be input first, next the reset operation must be performed, and finally the v 1 to v 4 and v lcd can be turned on by setting ?1? to the ?dcon? and ?ampon? registers of the ?power control? instruction. ? power supply off sequence either the reset operation by the resb terminal or the ?power control? instruction must be performed first, and next the input voltage for the voltage booster (v ee ) and the v dd can be turned off. if the v ee is supplied from different power sources for v dd , the v ee is turned off first, and next the v dd is turned off. NJU6821 - 47 - (32) referential instruction sequences (32-1) initialization in using the internal power supply circuits - evr value - lcd bias ratio - power control (dcon=?1?, ampon=?1?) (32-2) display data writing - initial display line - increment mode - column address - row address v dd , v ee power on wait for power-on stabilization reset input wait setting for lcd driving voltage-related functions end of initialization end of initialization setting for display-related functions display on (on/off =?1?) display data write NJU6821 - 48 - (32-3) power off - all com/seg output v ss level. optional status power save or reset operation v ee , v dd power off wait discharge on NJU6821 - 49 - (33) instruction table instruction table (1) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions display data write 0 0 1 0 0/1 0/1 0/1 write data write display data to ddram display data read 0 0 0 1 0/1 0/1 0/1 read data read display data from ddram column address (lower) [0h] 0 1 1 0 0 0 0 0 0 0 0 ax3 ax2 ax1 ax0 ddram column address column address (upper) [1h] 0 1 1 0 0 0 0 0 0 0 1 * ax6 ax5 ax4 ddram column address row address (lower) [2h] 0 1 1 0 0 0 0 0 0 1 0 ay3 ay2 ay1 ay0 ddram row address row address (upper) [3h] 0 1 1 0 0 0 0 0 0 1 1 * ay6 ay5 ay4 ddram row address initial display line (lower) [4h] 0 1 1 0 0 0 0 0 1 0 0 la3 la2 la1 la0 row address for an initial com line (scan start line) initial display line (upper) [5h] 0 1 1 0 0 0 0 0 1 0 1 * la6 la5 la4 row address for an initial com line (scan start line) n-line inversion (lower) [6h] 0 1 1 0 0 0 0 0 1 1 0 n3 n2 n1 n0 the number of n-line inversion n-line inversion (upper) [7h] 0 1 1 0 0 0 0 0 1 1 1 * n6 n5 n4 the number of n-line inversion display control (1) [8h] 0 1 1 0 0 0 0 1 0 0 0 shi ft mo n all on on/ off shift: common direction mon: gradation or b/w display mode allon: all pixels on/off on/off: display on/off display control (2) [9h] 0 1 1 0 0 0 0 1 0 0 1 re v nl in sw ap re f rev: reverse display on/off nlin: n-line inversion on/off, swap: swap mode on/off ref: segment direction increment control [ah] 0 1 1 0 0 0 0 1 0 1 0 win aim ayi axi win: window addressing mode on/off aim: read-modify-write on/off ayi: row auto-increment mode on/off axi: column auto-increment mode on/off power control [bh] 0 1 1 0 0 0 0 1 0 1 1 amp on ha lt dc on ac l ampon: voltage followers on/off halt: power save on/off dcon: voltage booster on/off acl: reset duty cycle ratio [ch] 0 1 1 0 0 0 0 1 1 0 0 * ds2 ds1 ds0 sets lcd duty cycle ratio boost level [dh] 0 1 1 0 0 0 0 1 1 0 1 * vu2 vu1 vu0 sets boost level lcd bias ratio [eh] 0 1 1 0 0 0 0 1 1 1 0 * b2 b1 b0 sets lcd bias ratio re register [fh] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst0 re2 re1 re0 re flag set note 1) * : don?t care. note 2) [n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6821 - 50 - instruction table (2) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a0 (lower) [0h] 0 1 1 0 0 0 1 0 0 0 0 pa03 pa02 pa01 pa00 sets palette values to gradation palette a0 gradation palette a0 (upper) [1h] 0 1 1 0 0 0 1 0 0 0 1 * * * pa04 sets palette values to gradation palette a0 gradation palette a1 (lower) [2h] 0 1 1 0 0 0 1 0 0 1 0 pa13 pa12 pa11 pa10 sets palette values to gradation palette a1 gradation palette a1 (upper) [3h] 0 1 1 0 0 0 1 0 0 1 1 * * * pa14 sets palette values to gradation palette a1 gradation palette a2 (lower) [4h] 0 1 1 0 0 0 1 0 1 0 0 pa23 pa22 pa21 pa20 sets palette values to gradation palette a2 gradation palette a2 (upper) [5h] 0 1 1 0 0 0 1 0 1 0 1 * * * pa24 sets palette values to gradation palette a2 gradation palette a3 (lower) [6h] 0 1 1 0 0 0 1 0 1 1 0 pa33 pa32 pa31 pa30 sets palette values to gradation palette a3 gradation palette a3 (upper) [7h] 0 1 1 0 0 0 1 0 1 1 1 * * * pa34 sets palette values to gradation palette a3 gradation palette a4 (lower) [8h] 0 1 1 0 0 0 1 1 0 0 0 pa43 pa42 pa41 pa40 sets palette values to gradation palette a4 gradation palette a4 (upper) [9h] 0 1 1 0 0 0 1 1 0 0 1 * * * pa44 sets palette values to gradation palette a4 gradation palette a5 (lower) [ah] 0 1 1 0 0 0 1 1 0 1 0 pa53 pa52 pa51 pa50 sets palette values to gradation palette a5 gradation palette a5 (upper) [bh] 0 1 1 0 0 0 1 1 0 1 1 * * * pa54 sets palette values to gradation palette a5 gradation palette a6 (lower) [ch] 0 1 1 0 0 0 1 1 1 0 0 pa63 pa62 pa61 pa60 sets palette values to gradation palette a6 gradation palette a6 (upper) [dh] 0 1 1 0 0 0 1 1 1 0 1 * * * pa64 sets palette values to gradation palette a6 re register [fh] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst0 re2 re1 re0 re flag set note 1) * : don?t care. note 2) [n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6821 - 51 - instruction table (3) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette a7 (lower) [0h] 0 1 1 0 0 1 0 0 0 0 0 pa73 pa72 pa71 pa70 sets palette values to gradation palette a7 gradation palette a7 (upper) [1h] 0 1 1 0 0 1 0 0 0 0 1 * * * pa74 sets palette values to gradation palette a7 gradation palette b0 (lower) [2h] 0 1 1 0 0 1 0 0 0 1 0 pb03 pb02 pb01 pb00 sets palette values to gradation palette b0 gradation palette b0 (upper) [3h] 0 1 1 0 0 1 0 0 0 1 1 * * * pb04 sets palette values to gradation palette b0 gradation palette b1 (lower) [4h] 0 1 1 0 0 1 0 0 1 0 0 pb13 pb12 pb11 pb10 sets palette values to gradation palette b1 gradation palette b1 (upper) [5h] 0 1 1 0 0 1 0 0 1 0 1 * * * pb14 sets palette values to gradation palette b1 gradation palette b2 (lower) [6h] 0 1 1 0 0 1 0 0 1 1 0 pb23 pb22 pb21 pb20 sets palette values to gradation palette b2 gradation palette b2 (upper) [7h] 0 1 1 0 0 1 0 0 1 1 1 * * * pb24 sets palette values to gradation palette b2 gradation palette b3 (lower) [8h] 0 1 1 0 0 1 0 1 0 0 0 pb33 pb32 pb31 pb30 sets palette values to gradation palette b3 gradation palette b3 (upper) [9h] 0 1 1 0 0 1 0 1 0 0 1 * * * pb34 sets palette values to gradation palette b3 gradation palette b4 (lower) [ah] 0 1 1 0 0 1 0 1 0 1 0 pb43 pb42 pb41 pb40 sets palette values to gradation palette b4 gradation palette b4 (upper) [bh] 0 1 1 0 0 1 0 1 0 1 1 * * * pb44 sets palette values to gradation palette b4 gradation palette b5 (lower) [ch] 0 1 1 0 0 1 0 1 1 0 0 pb53 pb52 pb51 pb50 sets palette values to gradation palette b5 gradation palette b5 (upper) [dh] 0 1 1 0 0 1 0 1 1 0 1 * * * pb54 sets palette values to gradation palette b5 re register [fh] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst0 re2 re1 re0 re flag set note 1) * : don?t care. note 2) [n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6821 - 52 - instruction table (4) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette b6 (lower) [0h] 0 1 1 0 0 1 1 0 0 0 0 pb63 pb62 pb61 pb60 sets palette values to gradation palette b6 gradation palette b6 (upper) [1h] 0 1 1 0 0 1 1 0 0 0 1 * * * pb64 sets palette values to gradation palette b6 gradation palette b7 (lower) [2h] 0 1 1 0 0 1 1 0 0 1 0 pb73 pb72 pb71 pb70 sets palette values to gradation palette b7 gradation palette b7 (upper) [3h] 0 1 1 0 0 1 1 0 0 1 1 * * * pb74 sets palette values to gradation palette b7 gradation palette c0 (lower) [4h] 0 1 1 0 0 1 1 0 1 0 0 pc03 pc02 pc01 pc00 sets palette values to gradation palette c0 gradation palette c0 (upper) [5h] 0 1 1 0 0 1 1 0 1 0 1 * * * pc04 sets palette values to gradation palette c0 gradation palette c1 (lower) [6h] 0 1 1 0 0 1 1 0 1 1 0 pc13 pc12 pc11 pc10 sets palette values to gradation palette c1 gradation palette c1 (upper) [7h] 0 1 1 0 0 1 1 0 1 1 1 * * * pc14 sets palette values to gradation palette c1 gradation palette c2 (lower) [8h] 0 1 1 0 0 1 1 1 0 0 0 pc23 pc22 pc21 pc20 sets palette values to gradation palette c2 gradation palette c2 (upper) [9h] 0 1 1 0 0 1 1 1 0 0 1 * * * pc24 sets palette values to gradation palette c2 gradation palette c3 (lower) [ah] 0 1 1 0 0 1 1 1 0 1 0 pc33 pc32 pc31 pc30 sets palette values to gradation palette c3 gradation palette c3 (upper) [bh] 0 1 1 0 0 1 1 1 0 1 1 * * * pc34 sets palette values to gradation palette c3 gradation palette c4 (lower) [ch] 0 1 1 0 0 1 1 1 1 0 0 pc43 pc42 pc41 pc40 sets palette values to gradation palette c4 gradation palette c4 (upper) [dh] 0 1 1 0 0 1 1 1 1 0 1 * * * pc44 sets palette values to gradation palette c4 re register [fh] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst0 re2 re1 re0 re flag set note 1) * : don?t care. note 2) [n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6821 - 53 - instruction table (5) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions gradation palette c5 (lower) [0h] 0 1 1 0 1 0 0 0 0 0 0 pc53 pc52 pc51 pc50 sets palette values to gradation palette c5 gradation palette c5 (upper) [1h] 0 1 1 0 1 0 0 0 0 0 1 * * * pc54 sets palette values to gradation palette c5 gradation palette c6 (lower) [2h] 0 1 1 0 1 0 0 0 0 1 0 pc63 pc62 pc61 pc60 sets palette values to gradation palette c6 gradation palette c6 (upper) [3h] 0 1 1 0 1 0 0 0 0 1 1 * * * pc64 sets palette values to gradation palette c6 gradation palette c7 (lower) [4h] 0 1 1 0 1 0 0 0 1 0 0 pc73 pc72 pc71 pc70 sets palette values to gradation palette c7 gradation palette c7 (upper) [5h] 0 1 1 0 1 0 0 0 1 0 1 * * * pc74 sets palette values to gradation palette c7 initial com line [6h] 0 1 1 0 1 0 0 0 1 1 0 * sc2 sc1 sc0 sets scan-starting common driver excs control [7h] 0 1 1 0 1 0 0 0 1 1 1 * * * ex cs controls excs signal gradation mode control [8h] 0 1 1 0 1 0 0 1 0 0 0 pw m gl sb * * sets variable or fixed gradation mode data bus length [9h] 0 1 1 0 1 0 0 1 0 0 1 * * cks wl s sets 8- or 16-bit data bus length evr control (lower) [ah] 0 1 1 0 1 0 0 1 0 1 0 dv3 dv2 dv1 dv0 sets evr level (lower bit) evr control (upper) [bh] 0 1 1 0 1 0 0 1 0 1 1 * dv6 dv5 dv4 sets evr level (upper bit) frequency control [dh] 0 1 1 0 1 0 0 1 1 0 1 ffl rf2 rf1 rf0 oscillation frequency discharge on/off [eh] 0 1 1 0 1 0 0 1 1 1 0 * * * dis discharge the electric charge in capacitors on v1 to v4 and vlcd re register [fh] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst0 re2 re1 re0 re flag instruction register address [ch] 0 1 1 0 1 0 0 1 1 0 0 ra3 ra 2 ra 1 ra 0 sets instruction register address instruction register read 0 1 0 1 0/1 0/1 0/1 * * * * read data read out instruction register data note 1) * : don?t care. note 2) [n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. note 4) cks=0: internal oscillation mode (default) cks=1: external oscillation mode NJU6821 - 54 - instruction table (6) code (80 series mpu i/f) code instructions csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 functions window end column address (lower) [0h] 0 1 1 0 1 0 1 0 0 0 0 ex3 ex2 ex1 ex0 sets column address for end point window end column address (upper) [1h] 0 1 1 0 1 0 1 0 0 0 1 * ex6 ex5 ex4 sets column address for end point window end row address (lower) [2h] 0 1 1 0 1 0 1 0 0 1 0 ey3 ey2 ey1 ey0 sets row address for end point window end row address (upper) [3h] 0 1 1 0 1 0 1 0 0 1 1 * ey6 ey5 ey4 sets row address for end point initial reverse line (lower) [4h] 0 1 1 0 1 0 1 0 1 0 0 ls3 ls2 ls1 ls0 sets address for reverse line initial reverse line (upper) [5h] 0 1 1 0 1 0 1 0 1 0 1 * ls6 ls5 ls4 sets address for reverse line last reverse line (lower) [6h] 0 1 1 0 1 0 1 0 1 1 0 le3 le2 le1 le0 sets address for reverse line last reverse line (upper) [7h] 0 1 1 0 1 0 1 0 1 1 1 * le6 le5 le4 sets address for reverse line reverse line display on/off [8h] 0 1 1 0 1 0 1 1 0 0 0 * * bt lr ev controls reverse line display dummy segment register on/off [9h] 0 1 1 0 1 0 1 1 0 0 1 * * * dm y controls icon segment register pwm control [ah] 0 1 1 0 1 0 1 1 0 1 0 pw ms pw ma pw mb pw mc sets pwm mode re register [fh] 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst0 re2 re1 re0 re flag note 1) * : don?t care. note 2) [n h ] : address of instruction register note 3) the dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. the only ?evr control? instruction is enabled after both of the upper and lower bytes are set. NJU6821 - 55 - (34) instruction descriptions this chapter provides detail descriptions and instruction registers. nonexistent instruction codes must not be set into the lsi. (34-1) display data write the ?display data write? instruction is used to write 8-bit display data into the ddram. csb rs rdb wrb re 2 re 1 re 0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0/1 0/1 0/1 display data (34-2) display data read the ?display data read? instruction is used to read out 8-bit display data from the ddram, where the column address and row address must be specified beforehand by the ?column address? and ?row address? instructions. the dummy read is required just after the ?column address? and ?row address? instructions. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0/1 0/1 0/1 display data (34-3) column address the ?column address? instruction is used to specify the column address for display data?s reading and writting operations. it requires dual bytes for lower 4-bit and upper 3-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for the upper 3-bit. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 0 0 ax3 ax2 ax1 ax0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 0 1 * ax6 ax5 ax4 (34-4) row address the ?row address? instruction is used to specify the row address for the display data read and write operations. it requires dual bytes for lower 4-bit and upper 3-bit data. the instruction for the lower 4-bit data must be executed first, next the instruction for upper 3-bit. the row address is specified in between 00 h and 51 h , where the address 50 h and 51 h are assigned to the pgram for the icon display. the setting for the nonexistent row address between 52 h and ff h is prohibited. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 1 0 ay3 ay2 ay1 ay0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 0 1 1 * ay6 ay5 ay4 NJU6821 - 56 - (34-5) initial display line the ?initial display line? instruction is used to specify the line address corresponding to the initial com line. the initial com line specified by the ?initial com line? instruction and indicates the common driver that starts scanning data. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 0 0 la3 la2 la1 la0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 0 1 * la6 la5 la4 la 6 la 5 la 4 la 3 la 2 la 1 la 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : 1 0 0 1 1 1 1 79 (34-6) n-line inversion the ?n-line inversion? instruction is used to control the alternate rates of the liquid crystal direction. it is programmed to select the n value between 2 and 80, and the fr signal toggles once every n lines by setting ?1? into the ?nlin? register of the ?display control (2)? instruction. when the n-line inversion is disabled by setting ?0? into the ?nlin? register, the fr signal toggles by the frame. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 1 0 n 3 n 2 n 1 n 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 0 1 1 1 * n 6 n 5 n 4 n 6 n 5 n 4 n 3 n 2 n 1 n 0 n value 0 0 0 0 0 0 0 inhibited 0 0 0 0 0 0 1 2 : : : : 1 0 0 1 1 1 1 80 NJU6821 - 57 - n-line inversion timing (1/82 duty cycle ratio) n-line inversion off n-line inversion on (34-7) display control (1) the ?display control (1)? instruction is used to control display conditions by setting the ?display on/off?, ?all pixels on/off?, display mode? and ?common direction? registers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 0 0 shift mon allon on/off on/off register on/off=0 : display off (all com/seg output vss level.) on/off=1 : display on all on register the ?all pixels on/off? register is used to turn on all pixels without changing display data of the ddram. the setting for the ?all pixels on/off? register has a priority over the ?reverse display on/off? register. allon=0 : normal allon=1 : all pixels turn on. mon register mon=0 : gradation mode mon=1 : b&w mode shift register shift=0 : com0 com79 shift=1 : com79 com0 cl flm fr 2nd line 82nd line 1st line 3rd line 1st line 81st line cl fr n-line control 2nd line 1st line 1st line 3rd line 2nd line nst line NJU6821 - 58 - (34-8) display control (2) the ?display control (2)? instruction is used to control display conditions by setting the ?segment direction?, ?swap mode on/off?, ?n-line inversion on/off? and ?reverse display on/off? registers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 0 1 rev nlin swap ref ref register the ?ref? register is used to reverse the assignment between segment drivers and column address, and it is possible to reduce restrictions for placement of the lsi on the lcd module. for more information, see (10) ?the relation among the ddram column address, display data and segment drivers?. swap register the ?swap? register is used to reverse the arrangement of the display data in the ddram. swap=0 : swap mode off (normal) swap=1 : swap mode on swap=?0? swap=?1? write data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ram data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 read data d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 nlin register the ?nlin? is used to enable or disable the n-line inversion. nlin=0 : n-line inversion off (the fr signal toggles by the flame.) nlin=1 : n-line inversion on (the fr signal toggles once every n frames.) rev register the ?rev? register is used to enable or disable the reverse display mode that reverses the polarity of the display data without changing the display data of the ddram. rev=0 : reverse display mode off rev=1 : reverse display mode on rev display ddram data display data 0 0 0 normal 1 1 0 1 1 reverse 1 0 NJU6821 - 59 - (34-9) increment control the ?increment control? instruction is used for the increment mode. in using the auto-increment mode, ddram address automatically increment (+1) whenever the ddram is accessed by the ?display data write? or ?display data read? instruction, therefore, once ?display data write? or ?display data read? instruction is established, it is possible to continuously access to the ddram without the ?column address? and ?row address? instructions. the settings for the ?aim?, ?axi? and ?ayi? registers are listed in the following tables. cs rs rd wrb re2 re1 re0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 0 0 0 0 1 0 1 0 win aim ayi axi aim, ayi and axi registers aim increment mode note 0 auto-increment for both of the display data read and write operations - 1 auto-increment for the display write operation (read modify write) - ayi axi increment mode note 0 0 no auto-increment 1 0 1 auto-increment for the column address 2 1 0 auto-increment for the row address 3 1 1 auto-increment for the column address and row address 4 note 1) auto-increment is disabled independent of the ?aim? register. note 2) auto-increment of the column address is enabled in accordance with the ?aim? register. note 3) auto-increment of the row address is enabled in accordance with the ?aim? register. note 4) auto-increment of the column address and row address are enabled. the row address increments whenever the column address reaches to the max h . 00 h max h 51 h 00 h max h 00 h 51 h 00 h column address row address maxh in the 8-bit data bus mode : 7fh maxh in the 16-bit data bus mode : 3fh maxh in the 8-bit data bus mode : 7f h maxh in the 16-bit data bus mode : 3f h NJU6821 - 60 - win register the ?win? register is used to access to the ddram for the window display area, where the start point is determined by the ?column address? and ?row address? instructions, and the end point by the ?window end column address ?and ?window end row address? instructions. the setting sequence for the window display area is listed as follows. for more detail, see (7) ?window addressing mode?. win=0 :window addressing mode off win=1 :window addressing mode on 1. set win=1, axi=1, and ayi=1 by ?increment control? instruction 2. set the start point by the ?column address? and ?row address? instructions 3. set the end point by the ?window end column address? and ?window end row address? instructions 4. enable to access to the ddram in the window addressing mode start address column address row address end address start address end address NJU6821 - 61 - (34-10) power control csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 0 1 1 ampon halt dcon acl acl register the ?acl? register is used to initialize the internal power supply circuits. it is available only in the master mode. acl=0 : initialization off (normal) acl=1 : initialization on when the data of the ?acl register? is read out by the ?instruction register read? instruction, the read-out data is ?1? during the initialization and ?0? after the initialization. this initialization is performed by using the signal produced by 2 clocks on the osc 1 . for this reason, the wait time for 2 clocks of the osc 1 is necessary until next instruction after the initialization by programming ?acl? register. dcon register the ?dcon? register is used to enable or disable the voltage booster. dcon=0 : voltage booster off dcon=1 : voltage booster on halt register the ?halt? register is used to enable or disable the power save mode. it is possible to reduce operating current down to stand-by level. the internal status in the power save mode is listed below. halt=0 : power save off (normal) halt=1 : power save on internal status in the power save mode ? the oscillation circuits and internal power supply circuits are halted. ? all segment and common drivers output vss level. ? the clock input into the osc 1 is inhibited. ? the display data in the ddram is maintained. ? the operational modes before the power save mode are maintained. ? the v 1 to v 4 and v lcd are in the high impedance. as a power save on sequence, the ?display off? must be executed first, next the ?power save on? instruction, and then all common and segment drivers output the vss level. and as power save off sequence, the ?power save off? instruction is executed first, next the ?display on? instruction. if the ?power save off? instruction is executed in the display on status, unexpected pixels may instantly turn on. ampon register the ?ampon? register is used to enable or disable the voltage followers, voltage regulator and evr. ampon=0 : the voltage followers, voltage regulator and the evr off ampon=1 : the voltage followers, voltage regulator and the evr on NJU6821 - 62 - (34-11) duty cycle ratio the ?duty cycle ratio? instruction is used to select lcd duty cycle ratio for the partial display function. the partial display function specifies some parts of display area on a lcd panel in the condition of lower duty cycle ratio, lower lcd bias ratio, lower boost level and lower lcd driving voltage. therefore, it is possible to optimize the lsi?s conditions with extremely low power consumption. it can be also programmed to select not only the duty cycle ratio but also the lcd bias ratio, boost level and evr value by the instructions so that it is possible to optimize the lsi conditions in accordance with the display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 0 0 * ds 2 ds 1 ds 0 ds 2 ds 1 ds 0 duty cycle ratio 0 0 0 1/82 0 0 1 1/77 0 1 0 1/66 0 1 1 1/47 1 0 0 1/32 1 0 1 1/17 1 1 0 1/38 1 1 1 1/26 (34-12) boost level the ?boost level? is used to select the multiple of the voltage booster for the partial display function. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 0 1 * vu 2 vu 1 vu 0 vu 2 vu 1 vu 0 boost level 0 0 0 1-time (no boost) 0 0 1 2-time 0 1 0 3-time 0 1 1 4-time 1 0 0 5-time 1 0 1 6-time 1 1 0 7-time 1 1 1 inhibited NJU6821 - 63 - (34-13) lcd bias ratio the ?lcd bias ratio? is used to select the lcd bias ratio for the partial display function. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 0 1 1 1 0 * b 2 b 1 b 0 b 2 b 1 b 0 lcd bias ratio 0 0 0 1/ 9 0 0 1 1/8 0 1 0 1/7 0 1 1 1/6 1 0 0 1/5 1 0 1 1/10 1 1 0 inhibited 1 1 1 inhibited (34-14) re flag the ?re flag? registers are used to determine the contents for the rf registers (re2, re1 and re0) and it is possible to access to the instruction registers. the data in the ?tst0? register must be ?0?, and it is used only for maker tests only. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0/1 0/1 0/1 1 1 1 1 tst0 re 2 re 1 re 0 NJU6821 - 64 - (34-15) gradation palette a, b and c csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 0 0 pa 03 pa 02 pa 01 pa 00 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 0 1 * * * pa 04 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 1 0 pa 13 pa 12 pa 11 pa 10 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 0 1 1 * * * pa 14 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 0 0 pa 23 pa 22 pa 21 pa 20 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 0 1 * * * pa 24 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 1 0 pa 33 pa 32 pa 31 pa 30 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 0 1 1 1 * * * pa 34 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 0 0 pa 43 pa 42 pa 41 pa 40 NJU6821 - 65 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 0 1 * * * pa 44 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 1 0 pa 53 pa 52 pa 51 pa 50 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 0 1 1 * * * pa54 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 1 0 0 pa 63 pa 62 pa 61 pa 60 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 0 1 1 1 0 1 * * * pa 64 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 0 0 pa 73 pa 72 pa 71 pa 70 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 0 1 * * * pa 74 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 1 0 pb 03 pb 02 pb 01 pb 00 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 0 1 1 * * * pb 04 NJU6821 - 66 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 0 0 pb 13 pb 12 pb 11 pb 10 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 0 1 * * * pb 14 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 1 0 pb 23 pb 22 pb 21 pb 20 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 0 1 1 1 * * * pb 24 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 0 0 pb 33 pb 32 pb 31 pb 30 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 0 1 * * * pb 34 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 1 0 pb 43 pb 42 pb 41 pb 40 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 0 1 1 * * * pb 44 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 1 0 0 pb 53 pb 52 pb 51 pb 50 NJU6821 - 67 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 0 1 1 0 1 * * * pb 54 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 0 0 pb 63 pb 62 pb 61 pb 60 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 0 1 * * * pb64 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 1 0 pb 73 pb 72 pb 71 pb 70 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 0 1 1 * * * pb 74 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 0 0 pc 03 pc 02 pc 01 pc 00 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 0 1 * * * pc 04 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 1 0 pc 13 pc 12 pc 11 pc 10 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 0 1 1 1 * * * pc 14 NJU6821 - 68 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 0 0 pc 23 pc 22 pc 21 pc 20 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 0 1 * * * pc 24 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 1 0 pc 33 pc 32 pc 31 pc 30 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 0 1 1 * * * pc 34 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 1 0 0 pc 43 pc 42 pc 41 pc 40 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 0 1 1 1 1 0 1 * * * pc 44 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 0 0 pc 53 pc 52 pc 51 pc 50 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 0 1 * * * pc 54 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 1 0 pc 63 pc 62 pc 61 pc 60 NJU6821 - 69 - csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 0 1 1 * * * pc 64 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 0 0 pc 73 pc 72 pc 71 pc 70 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 0 1 * * * pc 74 gradation palette table (variable gradation mode, pwm=?0? and mon=?0?) (palette aj, palette bj, palette cj (j=0 to 7)) palette value gradation level gradation palette palette value gradation level gradation palette 0 0 0 0 0 0 palette 0 (default) 1 0 0 0 0 16/31 0 0 0 0 1 1/31 1 0 0 0 1 17/31 palette 4 (default) 0 0 0 1 0 2/31 1 0 0 1 0 18/31 0 0 0 1 1 3/31 1 0 0 1 1 19/31 0 0 1 0 0 4/31 1 0 1 0 0 20/31 0 0 1 0 1 5/31 palette 1 (default) 1 0 1 0 1 21/31 palette 5 (default) 0 0 1 1 0 6/31 1 0 1 1 0 22/31 0 0 1 1 1 7/31 1 0 1 1 1 23/31 0 1 0 0 0 8/31 1 1 0 0 0 24/31 0 1 0 0 1 9/31 1 1 0 0 1 25/31 0 1 0 1 0 10/31 palette 2 (default) 1 1 0 1 0 26/31 palette 6 (default) 0 1 0 1 1 11/31 1 1 0 1 1 27/31 0 1 1 0 0 12/31 1 1 1 0 0 28/31 0 1 1 0 1 13/31 1 1 1 0 1 29/31 0 1 1 1 0 14/31 palette 3 (default) 1 1 1 1 0 30/31 0 1 1 1 1 15/31 1 1 1 1 1 31/31 palette 7 (default) NJU6821 - 70 - (34-16) initial com line the ?initial com line? instruction is used to specify the common driver that starts scanning the display data. the line address, corresponding to the initial com line, is specified by the ?initial display line? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 1 0 * sc 2 sc 1 sc 0 sc2 sc1 sc0 initial com line (shift=0) initial com line (shift=1) 0 0 0 com 0 com 79 0 0 1 com 15 com 64 0 1 0 com 30 com 49 0 1 1 com 45 com 34 1 0 0 com 60 com 19 1 0 1 com 75 com 4 1 1 0 inhibited inhibited 1 1 1 inhibited inhibited shift=0: positive direction (for instance, com 0 com 79 ) shift=1: negative direction (for instance, com 79 com 0 ) (34-17) excs control the ?excs control? instruction is available only in the master mode, where it is used to control the polarity for the excs output. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 0 1 1 1 * * * excs excs=0: output level ?0? excs=1: output level ?1? (34-18) gradation mode control the ?gradation mode control? is used to determine the display data for the glsb and select the gradation mode. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 0 0 pwm glsb * * glsb register glsb=0: glsb ?0? glsb=1: glsb ?1? pwm register pwm=0: variable gradation mode (variable 8-gradation levels out of 32-gradation level of the gradation palette) pwm=1: fixed gradation mode (fixed 8-gradation levels) NJU6821 - 71 - (34-19) data bus length the ?data bus length? instruction is used to select the 8- or 16- bit data bus length and determine the internal or external oscillation. in the 16-bit data bus mode, instruction data must be 16-bit data (d 15 to d 0 ) as well as display data. however, for the access to the instruction registers, the lower 8-bit data (d 7 to d 0 ) of the 16-bit data is valid. for the access to the ddram, all of the 16-bit data (d 15 to d 0 ) is valid. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 0 1 * * cks wls wls register wls =0: 8-bit data bus length wls =1: 16-bit data bus length cks register cks =0: internal oscillation (the osc 1 and osc 2 must be fixed ?1? or ?0?.) cks =1: external oscillation (by the external clock into the osc 1 or external resister between the osc 1 and osc 2 . osc 2 should be open when clock is inputted from osc 1 .) (34-20) evr control the ?evr control? instruction is used to fine-tune the lcd driving voltage (v lcd ) so that it is possible to optimize the contrast level for a lcd panel. this instruction must be programmed by the upper 3-bit data first, next lower 4-bit data. and it becomes enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the v lcd from being generated. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 1 0 dv 3 dv 2 dv 1 dv 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 0 1 1 * dv 6 dv 5 dv 4 dv 6 dv 5 dv 4 dv 3 dv 2 dv 1 dv 0 v lcd 0 0 0 0 0 0 0 low 0 0 0 0 0 0 1 : : : : : 1 1 1 1 1 1 1 high the formula of the v lcd is shown below. vlcd [v] = 0.5 x vreg + m (vreg ? 0.5 x vreg) / 127 v ba = v ee x 0.9 v ba : output voltage of the reference voltage generator v reg = v ref x n v ref : input voltage of the voltage regulator v reg : output voltage of the voltage regulator n : register value for the voltage booster m : register value for the evr NJU6821 - 72 - (34-21) frequency control the ?frequency control? instruction is used to control the frame frequency for a lcd panel. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 0 1 ffl rf2 rf1 rf0 rfx register (x=0, 1, 2) the ?rfx? register is used to determine the feed back resister value for the internal oscillator and it is possible to adjust the frame frequency for the lcd modules. rf 2 rf 1 rf 0 feedback resistor value 0 0 0 reference value 0 0 1 0.8 x reference value 0 1 0 0.9 x reference value 0 1 1 1.1 x reference value 1 0 0 1.2 x reference value 1 0 1 inhibited 1 1 0 inhibited 1 1 1 inhibited ffl register the ?ffl? register is used to select normal or high-speed frame frequency mode. ffl =0: normal (frame frequency: 73hz typical) ffl =1: high-speed mode (frame frequency: 150hz typical) note) the above values for the typical frame frequency are based on the following conditions. variable gradation mode, 1/82 duty cycle ratio, (rf 2 , rf 1 , rf 0 ) = (0,0,0) (34-22) discharge on/off discharge circuit is used to discharge the electric charge of the capacitors on the v 1 to v 4 and the v lcd terminals. the ?discharge on/off? instruction is usually required just after the internal power supply is turned off by setting ?0? into the ?dcon? and ?ampon? registers, or just after the external power supply is turned off. during the discharge operation, the internal or external power supply must not be turned on. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 1 0 * * * dis dis =0: discharge off dis =1: discharge on NJU6821 - 73 - (34-23) instruction register address the ?instruction register address? is used to specify the instruction register address, so that it is possible to read out the contents of the instruction registers in combination with the ?instruction register read? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 0 1 1 0 0 ra 3 ra 2 ra 1 ra 0 (34-24) instruction register read the ?instruction register read? instruction is used to read out the contents of the instruction register in combination with the ?instruction register address? instruction. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0/1 0/1 0/1 * * * * internal register data read (34-25) window end column address the ?window end column address? is used to specify the column address for the window end point. the lower 4-bit data is required to be programmed first and then the upper 3-bit data can be programmed. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 0 0 ex 3 ex 2 ex 1 ex 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 0 1 * ex 6 ex 5 ex 4 (34-26) window end row address set the ?window end row address? is used to specify the row address for the window end point. the lower 4- bit data is required to be programmed first and then the upper 3-bit data can be programmed. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 1 0 ey 3 ey 2 ey 1 ey 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 0 1 1 * ey 6 ey 5 ey 4 NJU6821 - 74 - (34-27) initial reverse line the ?initial reverse line? instruction is used to specify the initial line address for the reverse line display. lower 4-bit data must be programmed first, next upper 3-bit data. it is programmed in between 00 h and 4f h and the line address beyond 4f h is inhibited. the address relation: lsi < lei (i=6 to 0) must be maintained in the reverse line display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 0 0 ls 3 ls 2 ls 1 ls 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 0 1 * ls 6 ls 5 ls 4 (34-28) last reverse line the ?last reverse line? instruction is used to specify the last reverse line address for the reverse line display. lower 4-bit must be programmed first, next upper 3-bit data. it is programmed in between 00 h and 4f h and the line address beyond 4f h is inhibited. the address relation: lsi < lei (i=6 to 0) must be maintained in the reverse line display. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 1 0 le 3 le 2 le 1 le 0 csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 0 1 1 1 * le 6 le 5 le 4 (34-29) reverse line display on/off the ?reverse line display on/off? is used to enable or disable the reverse line display for the blink operation and determine the reverse line display mode. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 0 0 * * bt lrev lrev register the ?lrev? register is used to enable or disable the reverse line display. lrev =0: reverse line display off (normal) lrev =1: reverse line display on NJU6821 - 75 - bt register the ?bt? register is used to determine the reverse line display mode in the reverse line display on (lrev=1) status. bt =0: normal reverse line display bt =1: blink once every 32 frames display examples in the lrev=?1? and bt=?1? njrc lcd driver low power and low voltage njrc lcd driver low power and low voltage (34-30) icon segment register on/off the ?icon segment address on/off? is used to enable or disable to access to the icon segment register. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 0 1 * * * dmy dmy register dmy=0: access to the ddram dmy=1: access to the icon segment register blink once every 32 frames initial reverse line address last reverse line address blink once every 32 frames NJU6821 - 76 - (34-31) pwm control the ?pwm control? is used to determine the pwm type for the segment waveforms, where the type can be specified for each of the segai, segbi and segci (i=0-127) drivers. csb rs rdb wrb re 2 re 1 re 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 0 1 0 1 1 0 1 0 pwms pwma pwmb pwmc pwms register pwms=0: type 1 pwms=1: type 2 pwma, b and c registers the ?pwma, pwmb and pwmc? registers are used to select the type 1-o or type 1-e. pwmz=0 (z=a, b and c): type 1-o pwmz=1 (z=a, b and c): type 1-e pwm type1 (pwms=?0?) pwm type2 (pwms=?1?) odd line even line ?h? ?l? v lcd v 2 v 2 type-o type-e cl seg v lcd ?h? ?l? cl seg v 2 v lcd NJU6821 - 77 - (35) the relationship between common drivers and row addresses row address assignment for common drivers is programmed by the ?shif? register of the ?display control (1), and ?duty cycle ratio?, ?initial display line? and ?initial com line? instructions. the assignment for the comi 0 and comi 1 are independent of these instructions and always fixed. ? when initial display line is ?0? the relation between common drivers and row address of ddram (my) is changing each 15dots unit by the ?duty cycle ratio? and ?initial com line? instructions. if the shift bit is ?0?, the order of common scanning is normal and if it is ?1?, the common scanning order is inversed. when la 0 to la 6 of initial display line setting is ?0?, the ?my? corresponding to the initial com line is also ?0?. and ?my? is increasing. regardless above, comi 0 and comi 1 is fixed to my 80 and my 81 respectively. ? when initial display line is not ?0? the relation between common drivers and row address of ddram (my) is changing each 15dots unit by the ?duty cycle ratio? and ?initial com line? instructions. if the shift bit is ?0?, the order of common scanning is normal and if it is ?1?, the common scanning order is inversed. when la0 to la6 of initial display line setting is not ?0?, the ?my? corresponding to the initial com line is biased by the setting value. during the display, ?my? is increasing up to ?79?. when ?my? over than ?79?, its back to ?0?. and ?my? is increasing from 0 continuously. regardless above, comi 0 and comi 1 is fixed to my 80 and my 81 respectively. NJU6821 - 78 - (35-1) initial display line ?0?, 1/82 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?000? (1/82 duty) ?000? (1/82 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000000? (initial display line 0) ?0000000? (initial display line 0) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 0 65 50 35 20 5 79 64 49 34 19 4 com 1 com 2 com 3 com 4 0 com 5 79 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 79 com 15 0 com 16 com 17 com 18 com 19 0 com 20 79 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 79 com 30 0 com 31 com 32 com 33 com 34 0 com 35 79 com 36 com 37 com 38 com 39 com 40 com 41 com 42 com 43 com 44 79 com 45 0 com 46 com 47 com 48 com 49 0 com 50 79 com 51 com 52 com 53 com 54 com 55 com 56 com 57 com 58 com 59 79 com 60 0 com 61 com 62 com 63 com 64 0 com 65 79 com 66 com 67 com 68 com 69 com 70 com 71 com 72 com 73 com 74 79 com 75 0 com 76 com 77 com 78 com 79 79 64 49 34 19 4 0 65 50 35 20 5 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 79 - (35-2) initial display line ?0?, 1/77 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?001? (1/77 duty) ?001? (1/77 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000000? (initial display line 0) ?0000000? (initial display line 0) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 0 65 50 35 20 5 64 49 34 19 4 com 1 com 2 com 3 com 4 0 com 5 74 com 6 com 7 com 8 com 9 74 com 10 74 com 11 com 12 com 13 com 14 com 15 0 com 16 com 17 com 18 com 19 0 com 20 com 21 com 22 com 23 com 24 74 com 25 74 com 26 com 27 com 28 com 29 com 30 0 com 31 com 32 com 33 com 34 0 com 35 com 36 com 37 com 38 com 39 74 com 40 74 com 41 com 42 com 43 com 44 com 45 0 com 46 com 47 com 48 com 49 0 com 50 com 51 com 52 com 53 com 54 74 com 55 74 com 56 com 57 com 58 com 59 com 60 0 com 61 com 62 com 63 com 64 0 com 65 com 66 com 67 com 68 com 69 74 com 70 74 com 71 com 72 com 73 com 74 74 com 75 0 com 76 com 77 com 78 com 79 64 49 34 19 4 0 65 50 35 20 5 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 80 - (35-3) initial display line ?0?, 1/66 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?010? (1/66 duty) ?010? (1/66 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000000? (initial display line 0) ?0000000? (initial display line 0) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 0 50 35 20 5 49 34 19 4 com 1 63 com 2 com 3 com 4 0 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 63 com 14 com 15 0 com 16 63 com 17 com 18 com 19 0 com 20 com 21 63 com 22 com 23 com 24 com 25 com 26 com 27 com 28 63 com 29 com 30 0 com 31 com 32 com 33 com 34 0 com 35 com 36 63 com 37 com 38 com 39 com 40 com 41 com 42 com 43 63 com 44 com 45 0 com 46 com 47 com 48 com 49 0 com 50 com 51 63 com 52 com 53 com 54 com 55 com 56 com 57 com 58 63 com 59 com 60 0 com 61 com 62 com 63 63 com 64 0 com 65 com 66 63 com 67 com 68 com 69 com 70 com 71 com 72 com 73 com 74 com 75 0 com 76 com 77 com 78 63 com 79 49 34 19 4 0 50 35 20 5 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 81 - (35-4) initial display line ?0?, 1/47 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?011? (1/47 duty) ?011? (1/47 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000000? (initial display line 0) ?0000000? (initial display line 0) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 0 35 20 5 34 19 4 com 1 com 2 com 3 com 4 0 com 5 44 com 6 com 7 com 8 com 9 44 com 10 com 11 com 12 com 13 com 14 com 15 0 com 16 com 17 com 18 com 19 0 com 20 44 com 21 com 22 com 23 com 24 44 com 25 com 26 com 27 com 28 com 29 com 30 0 com 31 com 32 com 33 com 34 0 com 35 44 com 36 com 37 com 38 com 39 44 com 40 44 com 41 com 42 com 43 com 44 44 com 45 0 com 46 com 47 com 48 com 49 0 com 50 com 51 com 52 com 53 com 54 com 55 44 com 56 com 57 com 58 com 59 44 com 60 0 com 61 com 62 com 63 com 64 0 com 65 com 66 com 67 com 68 com 69 com 70 44 com 71 com 72 com 73 com 74 44 com 75 0 com 76 com 77 com 78 com 79 34 19 4 0 35 20 5 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 82 - (35-5) initial display line ?0?, 1/32 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?100? (1/32 duty) ?100? (1/32 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000000? (initial display line 0) ?0000000? (initial display line 0) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 0 20 5 19 4 com 1 com 2 com 3 com 4 0 com 5 29 com 6 com 7 com 8 com 9 29 com 10 com 11 com 12 com 13 com 14 com 15 0 com 16 com 17 com 18 com 19 0 com 20 29 com 21 com 22 com 23 com 24 29 com 25 com 26 com 27 com 28 com 29 29 com 30 0 com 31 com 32 com 33 com 34 0 com 35 29 com 36 com 37 com 38 com 39 com 40 com 41 com 42 com 43 com 44 29 com 45 0 com 46 com 47 com 48 com 49 0 com 50 29 com 51 com 52 com 53 com 54 com 55 29 com 56 com 57 com 58 com 59 29 com 60 0 com 61 com 62 com 63 com 64 0 com 65 com 66 com 67 com 68 com 69 com 70 29 com 71 com 72 com 73 com 74 29 com 75 0 com 76 com 77 com 78 com 79 19 4 0 20 5 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 83 - (35-6) initial display line ?0?, 1/17 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?101? (1/17 duty) ?101? (1/17 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000000? (initial display line 0) ?0000000? (initial display line 0) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 0 5 4 com 1 com 2 com 3 com 4 0 com 5 14 com 6 com 7 com 8 com 9 14 com 10 com 11 com 12 com 13 com 14 14 com 15 0 com 16 com 17 com 18 com 19 0 com 20 14 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 14 com 30 0 com 31 com 32 com 33 com 34 0 com 35 14 com 36 com 37 com 38 com 39 com 40 com 41 com 42 com 43 com 44 14 com 45 0 com 46 com 47 com 48 com 49 0 com 50 14 com 51 com 52 com 53 com 54 com 55 com 56 com 57 com 58 com 59 14 com 60 0 com 61 com 62 com 63 com 64 0 com 65 14 com 66 com 67 com 68 com 69 com 70 14 com 71 com 72 com 73 com 74 14 com 75 0 com 76 com 77 com 78 com 79 4 0 5 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 84 - (35-7) initial display line ?0?, 1/38 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?110? (1/38 duty) ?110? (1/38 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000000? (initial display line 0) ?0000000? (initial display line 0) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 0 35 20 5 34 19 4 com 1 com 2 com 3 com 4 0 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 35 com 15 0 35 com 16 com 17 com 18 com 19 0 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 35 com 30 0 35 com 31 com 32 com 33 com 34 0 com 35 35 com 36 com 37 com 38 com 39 com 40 com 41 com 42 com 43 com 44 35 com 45 0 com 46 com 47 com 48 com 49 0 35 com 50 35 com 51 com 52 com 53 com 54 com 55 com 56 com 57 com 58 com 59 com 60 0 com 61 com 62 com 63 com 64 0 35 com 65 35 com 66 com 67 com 68 com 69 com 70 com 71 com 72 com 73 com 74 com 75 0 com 76 com 77 com 78 com 79 34 19 4 0 35 20 5 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 85 - (35-8) initial display line ?0?, 1/26 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?111? (1/26 duty) ?111? (1/26 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000000? (initial display line 0) ?0000000? (initial display line 0) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 0 20 5 19 4 com 1 com 2 com 3 23 com 4 0 com 5 com 6 com 7 com 8 com 9 com 10 com 11 23 com 12 com 13 com 14 com 15 0 com 16 com 17 com 18 23 com 19 0 com 20 com 21 com 22 com 23 23 com 24 com 25 com 26 23 com 27 com 28 com 29 com 30 0 com 31 com 32 com 33 com 34 0 com 35 com 36 com 37 com 38 23 com 39 com 40 com 41 23 com 42 com 43 com 44 com 45 0 com 46 com 47 com 48 com 49 0 com 50 com 51 com 52 com 53 23 com 54 com 55 com 56 23 com 57 com 58 com 59 com 60 0 com 61 23 com 62 com 63 com 64 0 com 65 com 66 com 67 com 68 23 com 69 com 70 com 71 com 72 com 73 com 74 com 75 0 com 76 23 com 77 com 78 com 79 19 4 0 20 5 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 86 - (35-9) initial display line ?5?, 1/82 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?000? (1/82 duty) ?000? (1/82 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000101? (initial display line 5) ?0000101? (initial display line 5) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 5 70 55 40 25 10 4 69 54 39 24 9 com 1 com 2 com 3 com 4 0 5 com 5 79 com 6 com 7 com 8 com 9 79 0 com 10 0 79 com 11 com 12 com 13 com 14 com 15 5 com 16 com 17 com 18 com 19 5 com 20 com 21 com 22 com 23 com 24 79 0 com 25 0 79 com 26 com 27 com 28 com 29 com 30 5 com 31 com 32 com 33 com 34 5 com 35 com 36 com 37 com 38 com 39 79 0 com 40 0 79 com 41 com 42 com 43 com 44 com 45 5 com 46 com 47 com 48 com 49 5 com 50 com 51 com 52 com 53 com 54 79 0 com 55 0 79 com 56 com 57 com 58 com 59 com 60 5 com 61 com 62 com 63 com 64 5 com 65 com 66 com 67 com 68 com 69 79 0 com 70 0 79 com 71 com 72 com 73 com 74 79 com 75 0 5 com 76 com 77 com 78 com 79 4 69 54 39 24 9 5 70 55 40 25 10 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 87 - (35-10) initial display line ?5?, 1/77 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?001? (1/77 duty) ?001? (1/77 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000101? (initial display line 5) ?0000101? (initial display line 5) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 5 70 55 40 25 10 69 54 39 24 9 com 1 com 2 com 3 com 4 5 com 5 79 com 6 com 7 com 8 com 9 79 com 10 79 com 11 com 12 com 13 com 14 com 15 5 com 16 com 17 com 18 com 19 5 com 20 com 21 com 22 com 23 com 24 79 com 25 79 com 26 com 27 com 28 com 29 com 30 5 com 31 com 32 com 33 com 34 5 com 35 com 36 com 37 com 38 com 39 79 com 40 79 com 41 com 42 com 43 com 44 com 45 5 com 46 com 47 com 48 com 49 5 com 50 com 51 com 52 com 53 com 54 79 com 55 79 com 56 com 57 com 58 com 59 com 60 5 com 61 com 62 com 63 com 64 5 com 65 com 66 com 67 com 68 com 69 79 com 70 79 com 71 com 72 com 73 com 74 79 com 75 5 com 76 com 77 com 78 com 79 69 54 39 24 9 5 70 55 40 25 10 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 88 - (35-11) initial display line ?5?, 1/66 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?010? (1/66 duty) ?010? (1/66 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000101? (initial display line 5) ?0000101? (initial display line 5) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 5 55 40 25 10 54 39 24 9 com 1 68 com 2 com 3 com 4 5 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 68 com 14 com 15 5 com 16 68 com 17 com 18 com 19 5 com 20 com 21 68 com 22 com 23 com 24 com 25 com 26 com 27 com 28 68 com 29 com 30 5 com 31 com 32 com 33 com 34 5 com 35 com 36 68 com 37 com 38 com 39 com 40 com 41 com 42 com 43 68 com 44 com 45 5 com 46 com 47 com 48 com 49 5 com 50 com 51 68 com 52 com 53 com 54 com 55 com 56 com 57 com 58 68 com 59 com 60 5 com 61 com 62 com 63 68 com 64 5 com 65 com 66 68 com 67 com 68 com 69 com 70 com 71 com 72 com 73 com 74 com 75 5 com 76 com 77 com 78 68 com 79 54 39 24 9 5 55 40 25 10 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 89 - (35-12) initial display line ?5?, 1/47 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?011? (1/47 duty) ?011? (1/47 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000101? (initial display line 5) ?0000101? (initial display line 5) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 5 40 25 10 39 24 9 com 1 com 2 com 3 com 4 5 com 5 49 com 6 com 7 com 8 com 9 49 com 10 com 11 com 12 com 13 com 14 com 15 5 com 16 com 17 com 18 com 19 5 com 20 49 com 21 com 22 com 23 com 24 49 com 25 com 26 com 27 com 28 com 29 com 30 5 com 31 com 32 com 33 com 34 5 com 35 49 com 36 com 37 com 38 com 39 49 com 40 49 com 41 com 42 com 43 com 44 49 com 45 5 com 46 com 47 com 48 com 49 5 com 50 com 51 com 52 com 53 com 54 com 55 49 com 56 com 57 com 58 com 59 49 com 60 5 com 61 com 62 com 63 com 64 5 com 65 com 66 com 67 com 68 com 69 com 70 49 com 71 com 72 com 73 com 74 49 com 75 5 com 76 com 77 com 78 com 79 39 24 9 5 40 25 10 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 90 - (35-13) initial display line ?5?, 1/32 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?100? (1/32 duty) ?100? (1/32 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000101? (initial display line 5) ?0000101? (initial display line 5) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 5 25 10 24 9 com 1 com 2 com 3 com 4 5 com 5 34 com 6 com 7 com 8 com 9 34 com 10 com 11 com 12 com 13 com 14 com 15 5 com 16 com 17 com 18 com 19 5 com 20 34 com 21 com 22 com 23 com 24 34 com 25 com 26 com 27 com 28 com 29 34 com 30 5 com 31 com 32 com 33 com 34 5 com 35 34 com 36 com 37 com 38 com 39 com 40 com 41 com 42 com 43 com 44 34 com 45 5 com 46 com 47 com 48 com 49 5 com 50 34 com 51 com 52 com 53 com 54 com 55 34 com 56 com 57 com 58 com 59 34 com 60 5 com 61 com 62 com 63 com 64 5 com 65 com 66 com 67 com 68 com 69 com 70 34 com 71 com 72 com 73 com 74 34 com 75 5 com 76 com 77 com 78 com 79 24 9 5 25 10 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 91 - (35-14) initial display line ?5?, 1/17 duty cycle shift set value shift=?0? (common forward scan) shift=?1? common backward scan) ds 2 ds 1 ds 0 ?101? (1/17 duty) ?101? (1/17 duty) sc 2 sc1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000101? (initial display line 5) ?0000101? (initial display line 5) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 5 10 9 com 1 com 2 com 3 com 4 5 com 5 19 com 6 com 7 com 8 com 9 19 com 10 com 11 com 12 com 13 com 14 19 com 15 5 com 16 com 17 com 18 com 19 5 com 20 19 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 19 com 30 5 com 31 com 32 com 33 com 34 5 com 35 19 com 36 com 37 com 38 com 39 com 40 com 41 com 42 com 43 com 44 19 com 45 5 com 46 com 47 com 48 com 49 5 com 50 19 com 51 com 52 com 53 com 54 com 55 com 56 com 57 com 58 com 59 19 com 60 5 com 61 com 62 com 63 com 64 5 com 65 19 com 66 com 67 com 68 com 69 com 70 19 com 71 com 72 com 73 com 74 19 com 75 5 com 76 com 77 com 78 com 79 9 5 10 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 92 - (35-15) initial display line ?5?, 1/38 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?110? (1/38 duty) ?110? (1/38 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000101? (initial display line 5) ?0000101? (initial display line 5) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 5 40 25 10 39 24 9 com 1 com 2 com 3 com 4 5 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 40 com 15 5 40 com 16 com 17 com 18 com 19 5 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 40 com 30 5 40 com 31 com 32 com 33 com 34 5 com 35 40 com 36 com 37 com 38 com 39 com 40 com 41 com 42 com 43 com 44 40 com 45 5 com 46 com 47 com 48 com 49 5 40 com 50 40 com 51 com 52 com 53 com 54 com 55 com 56 com 57 com 58 com 59 com 60 5 com 61 com 62 com 63 com 64 5 40 com 65 40 com 66 com 67 com 68 com 69 com 70 com 71 com 72 com 73 com 74 com 75 5 com 76 com 77 com 78 com 79 39 24 9 5 40 25 10 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 93 - (35-16) initial display line ?5?, 1/26 duty cycle shift set value shift=?0? (common forward scan) shift=?1? (common backward scan) ds 2 ds 1 ds 0 ?111? (1/26 duty) ?111? (1/26 duty) sc 2 sc 1 sc 0 ?000? ?001? ?010? ?011? ?100? ?101? ?000? ?001? ?010? ?011? ?100? ?101? la 6 !!!!!!!! la 0 ?0000101? (initial display line 5) ?0000101? (initial display line 5) comi 0 80 80 80 80 80 80 80 80 80 80 80 80 com 0 5 25 10 24 9 com 1 com 2 com 3 28 com 4 5 com 5 com 6 com 7 com 8 com 9 com 10 com 11 28 com 12 com 13 com 14 com 15 5 com 16 com 17 com 18 28 com 19 5 com 20 com 21 com 22 com 23 28 com 24 com 25 com 26 28 com 27 com 28 com 29 com 30 5 com 31 com 32 com 33 com 34 5 com 35 com 36 com 37 com 38 28 com 39 com 40 com 41 28 com 42 com 43 com 44 com 45 5 com 46 com 47 com 48 com 49 5 com 50 com 51 com 52 com 53 28 com 54 com 55 com 56 28 com 57 com 58 com 59 com 60 5 com 61 28 com 62 com 63 com 64 5 com 65 com 66 com 67 com 68 28 com 69 com 70 com 71 com 72 com 73 com 74 com 75 5 com 76 28 com 77 com 78 com 79 24 9 5 25 10 comi 1 81 81 81 81 81 81 81 81 81 81 81 81 ds: duty cycle ratio, sc: initial com line, la: initial display line NJU6821 - 94 - absolute maximum ratings parameter symbol condition terminal rating unit supply voltage (1) v dd v dd -0.3 to +4.0 v supply voltage (2) v ee v ee -0.3 to +4.0 v supply voltage (3) v out v out -0.3 to +20.0 v supply voltage (4) v reg v reg -0.3 to +20.0 v supply voltage (5) v lcd v lcd -0.3 to +20.0 v supply voltage (6) v 1 , v 2 , v 3 , v 4 v 1 , v 2 , v 3 , v 4 -0.3 to v lcd + 0.3 v input voltage vi v ss =0v ta = +25 c *1 -0.3 to v dd + 0.3 v storage temperature t stg -45 to +125 c note 1) d 0 to d 15 , csb, rs, m/s, rdb, wrb, osc 1 , cl, flm, fr, clk, resb, test terminals. note 2) to stabilize the voltage booster operation, decoupling capacitors must be connected between the v dd and v ss pins and between the v ee and v ssh pins. recommended operating conditions parameter symbol terminal min typ max unit note v dd1 1.7 3.3 v *1 v dd2 v dd 2.4 3.3 v *2 supply voltage v ee v ee 2.4 3.3 v *3 v lcd v lcd 5 18.0 v *4 v out v out 18.0 v v reg v reg v out 0.9 v operating voltage v ref v ref 2.1 3.3 v *5 operating temperature t opr -30 85 c note1) applies to the condition when the reference voltage generator is not used. note2) applies to the condition when the reference voltage generator is used. note3) applies to the condition when the voltage booster is used. note4) the following relationship among the supply voltages must be maintained. v ss NJU6821 - 96 - parameter symb ol condition min typ max unit note v 2 -100 0 +100 v 3 -100 0 +100 v d12 -30 0 +30 v d34 -30 0 +30 output voltage v d24 -30 0 +30 mv *15 NJU6821 - 97 - clock and frame frequency display duty cycle ratio (1/d) parameter synbol display mode 1/82, 1/77, 1/66 1/47, 1/38, 1/32, 1/26 1/17 note gradation mode f osc / (62xd) f osc / (62xdx2) f osc / (62xdx4) simplified gradation mode f osc / (14xd) f osc / (14xdx2) f osc / (14xdx4) internal clock f osc b&w mode f osc / (2xd) f osc / (2xdx2) f osc / (2xdx4) gradation mode f ck / (62xd) f ck / (62xdx2) f ck / (62xdx4) simplified gradation mode f ck / (14xd) f ck / (14xdx2) f ck / (14xdx4) external clock f ck b&w mode f ck / (2xd) f ck / (2xdx2) f ck / (2xdx4) flm applied terminals and conditions note 1) d 0 -d 15 , csb, rs, m/s, rdb, wrb, p/s, sel68, clk, cl, flm, fr, resb note 2) d 0 -d 15 note 3) cl, flm, fr, clk note 4) csb, rs, m/s, sel68, rdb, wrb, p/s, resb, osc 1 note 5) d 0 -d 15 , cl, flm, fr, clk in the high impedance note 6) sega 0 -sega 127 , segb 0 -segb 127 , segc 0 -segc 127 , com 0 -com 79 , comi 0 , comi 1 - defines the resistance between the com/seg terminals and the power supply terminals (v lcd , v 1 , v 2 , v 3 and v 4 ) at the condition of 0.5v deference and 1/9 lcd bias ratio. note 7) v dd - the oscillator is halted, csb=?1? (disabled), no-load on the com/seg drivers. note 8) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the variable gradation mode. note 9) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,0,0) in the fixed gradation mode. note 10) osc - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(1,0,0) (12khz), - defines the internal oscillation frequency at (rf 2 , rf 1 , rf 0 )=(0,1,1) (24khz), in the black and white mode. note 11) v out - applies to the condition when the internal voltage booster (n=2-7), the internal oscillator and the internal power circuits are used. - v ee =2.4v to 3.3v, evr= (1,1,1,1,1,1,1) - 1/5 to 1/10 lcd bias, 1/82 duty cycle, no-load on the com/seg drivers. - rl=500kohm between v out and v ss , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1? note 12) v dd - applies to the condition using the internal oscillator and internal power circuits, no a ccsess between the lsi and mpu. - evr= (1,1,1,1,1,1,1), all pixels turned-on or checkerboard display in gradation mode. - 1/82 duty cycle, no-load on the com/seg drivers - v dd =v ee , v ref =0.9v ee , ca 1 =ca 2 =1.0uf, ca 3 =0.1uf, dcon=?1?, ampon=?1?, nlin=?0?, 1/82 duty, ta=25 c NJU6821 - 98 - note 13) v reg - applies to the condition that v ba =v ref and voltage booster n= 1. dcon=?0?, v out =13.5v input. note 14) v reg - v ee =2.4v to 3.3v, v ref =0.9vee, v out =18.0v, 1/5 to 1/10 lcd bias ratio, 1/82 duty cycle, evr=(1,1,1,1,1,1,1) - checkerboard display, no-load on the com/seg drivers, the voltage booster n=2 to 7 ca 1 =ca 2 =1.0 uf, ca 3 =0.1 uf, dcon=?0?, ampon=?1?, nlin=?0? note 15) v lcd , v 1 , v 2 , v 3 , v 4 - v ee = 3.0v, v ref = 0.9 v ee , v out =15.0v, bias=1/5~1/10, evr= ?1111111?. display off, no-load on the com/seg drivers, the voltage booster n=5 ca 2 =1.0 f, c a 3 =0.1 f, dcon=?0?, ampon=?1? note 16) v dd =3v, ta=25 c v d12 : (1) ? (2) v d34 : (3) ? (4) v d24 : (2) ? (4) ( 1 ) ( 2 ) ( 3 ) ( 4 ) v l c d v 1 v 2 v 3 v ss v 4 NJU6821 - 99 - ac characteristeristics write operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 90 35 35 ns ns ns wrb data setup time data hold time t ds8 t dh8 30 5 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 160 70 70 ns ns ns wrb data setup time data hold time t ds8 t dh8 40 5 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlw8 t wrhw8 180 80 80 ns ns ns wrb data setup time data hold time t ds8 t dh8 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb wrb rs d 0 d 15 t ah8 t wrlw8 t wrhw8 t ds8 t dh8 t cyc8 NJU6821 - 100 - read operation (80-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 180 80 80 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 60 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah8 t as8 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc8 t wrlr8 t wrhr8 250 120 120 ns ns ns rdb read data delay time read data hold time t rdd8 t rdh8 cl=15pf 0 110 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as8 csb rs d 0 d 15 t rdd8 t rdh8 t cyc8 rdb t wrlr8 t wrhr8 t ah8 NJU6821 - 101 write operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 90 35 35 ns ns ns e data setup time data hold time t ds6 t dh6 40 5 ns ns d 0 to d 15 (v dd =2.4 to 2.7v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns cs rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 160 70 70 ns ns ns e data setup time data hold time t ds6 t dh6 50 5 ns ns d 0 to d 15 (v dd =1.7 to 2.4v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elw6 t ehw6 180 80 80 ns ns ns e data setup time data hold time t ds6 t dh6 70 10 ns ns d 0 to d 15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/wb ( wrb ) d 0 d 15 t ehw6 t elw6 t ds6 t dh6 t cyc6 e ( rdb ) NJU6821 - 102 - read operation (68-type mpu) (v dd =2.5 to 3.3v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =2.2 to 2.5v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr8 180 80 80 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 70 ns ns d 0 to d 15 (v dd =1.7 to 2.2v, ta=-30 to +85 c) prmeter symbol condition min. max. unit terminal address hold time address setup time t ah6 t as6 0 0 ns ns csb rs system cycle time enable ?l? level pulse width enable ?h? level pulse width t cyc6 t elr6 t ehr6 250 120 120 ns ns ns e read data delay time read data hold time t rdd6 t rdh6 cl=15pf 0 110 ns ns d0 d15 note) each timing is specified based on 20% and 80% of v dd . t as6 csb rs t ah6 r/wb (wrb) d 0 d 15 t ehr6 t elr6 t rdd6 t rdh6 t cyc6 e (rdb) NJU6821 - 103 serial interface (v dd =2.5 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 50 20 20 ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =2.2 to 2.5v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 50 20 20 ns ns ns scl address setup time address hold time t ass t ahs 20 20 ns ns rs data setup time data hold time t dss t dhs 20 20 ns ns sda csb ? scl time csb hold time t css t csh 20 20 ns ns csb (v dd =1.7 to 2.2v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal serial clock cycle scl ?h? level pulse width scl ?l? level pulse width t cycs t shw t slw 80 35 35 ns ns ns scl address setup time address hold time t ass t ahs 35 35 ns ns rs data setup time data hold time t dss t dhs 35 35 ns ns sda csb ? scl time csb hold time t css t csh 35 35 ns ns csb note) each timing is specified based on 20% and 80% of v dd . t css csb rs t csh sda t slw t shw t dss t dhs t c y cs scl t a hs t ass NJU6821 - 104 - display control timing NJU6821 - 105 NJU6821 - 106 - input clock timing (v dd =1.7 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal osc 1 ?h? level pulse width (1) t ckhw1 0.525 1.64 s osc 1 osc 1 ?l? level pulse width (1) t cklw1 0.525 1.64 s ? 1 osc 1 ?h? level pulse width (2) t ckhw2 2.45 7.35 s osc 1 osc 1 ?l? level pulse width (2) t cklw2 2.45 7.35 s ? 2 osc 1 ?h? level pulse width (3) t ckhw3 17.2 51.0 s osc 1 osc 1 ?l? level pulse width (3) t cklw3 17.2 51.0 s ? 3 note) each timing is specified based on 20% and 80% of v dd . note *1) applied to the variable gradation mode / mon=?0?, pwm=?0? note *2) applied to the fixed gradation mode / mon=?0?, pwm=?1? note *3) applied to the b&w mode / mon=?1? osc 1 t cklw t ckhw NJU6821 - 107 reset input timing (v dd =2.4 to 3.3v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.0 s resb ?l? level pulse width t rw 10.0 s resb (v dd =1.7 to 2.4v, ta=-30 to +85 c) parameter symbol condition min. max. unit terminal reset time t r 1.5 s resb ?l? level pulse width t rw 10.0 s resb note) each timing is specified based on 20% and 80% of v dd . t rw resb internal circuit status end of reset during reset t r NJU6821 - 108 - application circuit examples mpu connections 80-type mpu interface 68-type mpu interface serial interface a 0 v cc a 1 to a 7 iorqb d 0 to d 7 rdb wrb resb gnd 7 decoder rs csb d 0 to d 7 rdb wrb resb v dd v ss 8 reset in p ut 1.7v to 3.3v (80-type cpu) a 0 v cc a 1 to a 15 vm a d 0 to d 7 e r/w resb gnd 15 decoder rs csb d 0 to d 7 rdb ( e ) wrb ( r/w ) resb v dd v ss 8 reset in p ut 1.7v to 3.3v (68-typecpu) a 0 v cc a 1 to a 7 port 1 port 2 resb gnd 7 decoder rs csb sd a scl resb v dd v ss reset in p ut 1.7v to 3.3v ( cpu ) NJU6821 - 109 master lsi and slave lsi connections a) input interface (parallel interface) (4-line serial interface) (4-line serial interface, excs unification) wrb d 0 to d 7 rdb sel68 p/s m/s rs csb resb ( slave ) wrb d 0 to d 7 rdb sel68 p/s m/s rs csb resb ( master ) v dd resb csb 1 csb 2 rs wrb(r/w) rdb(e) d 0 to d 7 sel68 8 v dd resb csb 1 csb 2 rs sda scl spol excs smode sda scl rdb wrb p/s sel68 ( master ) m/s rs csb resb spol excs smode sda scl rdb wrb p/s sel68 ( slave ) m/s rs csb resb v dd resb csb rs sda scl spol excs smode sda scl rdb wrb p/s sel68 ( master ) m/s rs csb resb spol excs smode sda scl rdb wrb p/s sel68 ( slave ) m/s rs csb resb NJU6821 - 110 - (3-line serial interface) (3-line serial interface, excs unification) v dd resb csb 1 csb 2 sda scl spol excs smode sda scl rdb wrb p/s sel68 ( master ) m/s rs csb resb spol excs smode sda scl rdb wrb p/s sel68 ( slave ) m/s rs csb resb v dd resb csb sda scl spol excs smode sda scl rdb wrb p/s sel68 ( master ) m/s rs csb resb spol excs smode sda scl rdb wrb p/s sel68 ( slave ) m/s rs csb resb NJU6821 - 111 b) lcd driving generation circuit the following paragraphs describes the caution of master/slave operation. 1) display timing is controlled by master chip. the cl, flm, fr, clk signals are stopped when master chip is display off. when ?display off? executions, slave chip must execute ?display off? before master. 2) when ?halt? command is executed in master chip, the voltage booster circuit and voltage regulator circuit is turned off. lcd driver outputs v ss level voltage then display goes to turn off. and v lcd for slave chip goes to stop supply. when ?halt? command is executed in master chip, display off must be executed before. because v lcd for slave chip is stopped. 3) the evr control is valid in only master chip (on this circuit diagram). 4) v out terminal should connect to v lcd to prevent condition of floating. 5) osc 1 terminal and osc 2 in slave chip should be open. v dd v ee v b a v ref c 1 + c 1 - ca 1 c 2 + c 2 - ca 1 c 3 + c 3 - ca 1 c 5 + c 5 - ca 1 v lcd v 1 v 2 v 3 v 4 ca 2 ca 2 ca 2 ca 2 ca 2 v out v reg ca 1 v ss ca 3 v ss clk cl flm fr v lcd v 1 v 2 v 3 v 4 v dd v dd v dd v ee v b a v ref v lcd v 1 v 2 v 3 v 4 v out clk cl flm fr (master) (slave) v reg c 4 + c 4 - ca 1 c 6 + c 6 - ca 1 c 1 + c 1 - c 2 + c 2 - c 3 + c 3 - c 5 + c 5 - c 4 + c 4 - c 6 + c 6 - ca 1 v ss ca 1 v ss ca 1 v ss NJU6821 - 112 - ? typical characteristic parameter symbol min typ max unit basic delay time of gste ta=+25 c, v ss =0v, v dd =3.0v 10 ns ? input output terminal type (a) input circuit1 terminals: csb, rs, rdb, wrb, sel68, m/s p/s, resb (b-1) input/output circuit 1 terminals: flm, cl, fr, clk (b-2) input/output circuit 2 terminals: d 0 ~d 15 v dd i v ss (0v) input signal i/o v dd v ss (0v) input signal v dd v ss (0v) output control signal output signal i/o v dd v ss (0v) input signal v dd v ss (0v) output control signal output signal v ss (0v) input control signal NJU6821 - 113 (c) display output circuit terminals: sega 0 to sega 127 segb 0 to segb 127 segc 0 to segc 127 com 0 to com 79 comi 0 , to comi 1 segsa 0 , to segsa 3 segsb 0 , to segsb 3 segsc 0 , to segsc 3 [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. o v lcd v ss (0v) output control signal 1 v 1 /v 2 v ss (0v) output control signal 3 v lcd v ss (0v) v 3 /v 4 output control signal 2 output control signal 4 v lcd |
Price & Availability of NJU6821
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |