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c at 17 fb a 22 fb b 23 fb c 24 back emf sampler c rt 19 + + 1.5v 750na + 1.5v 750na v dd v dd c rr 21 500na v dd speed fb 20 c vco 15 16 r vco voltage controlled oscillator vco/tach 13 2 4 3 9 10 ha hb hc la lb gating logic & output drivers + speed set 8 5 speed comp 3.9v 1.7v 20khz 6 c t + 1.4v 1 i sense 5 uvlo 12 f/ r + 1.7v v ref 26 c ios 16k ? 8k ? i limit 1-shot 25 brake v dd 4k ? 14 v dd 28 gnd 27 r ref 11 lc reference vco out vco out 18 uv fault 7 v ref a b c d e f r commutation state machine july 2000 ML4426 * bi-directional sensorless bldc motor controller general description the ML4426 pwm motor controller provides all of the functions necessary for starting and controlling the speed of delta or wye wound brushless dc (bldc) motors without hall effect sensors. back emf voltage is sensed from the motor windings to determine the proper commutation phase sequence using a pll. this patented sensing technique will commutate a wide range of 3- phase bldc motors and is insensitive to pwm noise and motor snubbing circuitry. the ML4426 limits the motor current using a constant off- time pwm control loop. the velocity loop is controlled with an onboard amplifier. the ML4426 has circuitry to ensure that there is no shoot-through in directly driven external power mosfets. the timing of the start-up sequence is determined by the selection of three timing capacitors. this allows optimization for a wide range of motors and loads. features motor starts and stops with power to ic bi-directional motor drive for applications requiring forward/ reverse operation on-board start sequence: align ? ramp ? set speed patented back-emf commutation technique provides jitterless torque for minimum ?pin-up?time onboard speed control loop pll used for commutation provides noise immunity from pwm spikes, compared to noise sensitive zero crossing technique pwm control for maximum efficiency direct fet drive for 12v motors; drives high voltage motors with ic buffers from ir, ixys, harris, power integrations, siliconix, etc. (* indicates part is end of life as of july 1, 2000) block diagram (pin configuration shown for 28 pin version) rev. 1.0 10/10/2000
ML4426 2 rev. 1.0 10/10/2000 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 i sense ha hb hc speed comp c t v ref speed set la lb lc f/ r vco/tach v dd gnd r ref c ios brake fb c fb b fb a c rr speed fb c rt uv fault c at r vco c vco top view ML4426 28-pin narrow pdip (p28n) 28-pin soic (s28) fb c fb b fb a c rr speed fb c rt uv fault c at 1 2 3 4 5 6 7 8 9 10111213141516 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 h3 nc speed comp c t v ref speed set la lb lc f/ r vco/tach v dd nc nc c vco r vco hb ha i sense nc gnd r ref c ios brake top view ml4425 32-pin tqfp (h32-7)
ML4426 rev. 1.0 10/10/2000 3 pin name function 1(30) i sense motor current sense input. when i sense exceeds 0.2 ? i limit, the output drivers la, lb, and lc are shut off for a fixed time determined by c ios 2(31) ha active low output driver for the phase a high-side switch 3(32) hb active low output driver for the phase b high-side switch 4(1) hc active low output driver for the phase c high-side switch 5(3) speed comp speed control loop compensation is set by a series resistor and capacitor from speed comp to gnd 6(4) c t a capacitor from c t to gnd sets the pwm oscillator frequency 7(5) v ref 6.9v reference voltage output 8(6) speed set speed loop input which ranges from 0 (stopped) to v ref (maximum speed) 9(7) la active high output driver for the phase a low-side switch 10(8) lb active high output driver for the phase b low-side switch 11(9) lc active high output driver for the phase c low-side switch 12(10) f/ r this ttl level input selects the direction of the motor by changing the sequence of the commutation state machine 13(11) vco/tach this ttl level output corresponds to the signal used to clock the commutation state machine. the output frequency is proportional to the motor speed when the back- emf sensing loop is locked onto the rotor position 14(12) v dd 12v power supply input 15(15) c vco a capacitor to gnd sets the voltage-to-frequency ratio of the vco 16(16) r vco an resistor to gnd sets up a current proportional to the input voltage of the vco pin name function 17(17) c at a capacitor to gnd sets the time that the controller stays in the align mode 18(18) uv fault this output goes low when v dd drops below the uvlo threshold, and indicates that all output drivers have been disabled 19(19) c rt a capacitor to gnd sets the time that the controller stays in the ramp mode 20(20) speed fb output of the back-emf sampling circuit and input to the vco. an rc network connected to speed fb sets the compensation for the pll loop formed by the back-emf sampling circuit, the vco, and the commutation state machine 21(21) c rr a capacitor to between c rr and speed fb sets the ramp rate (acceleration) of the motor when the controller is in ramp mode 22(22) fb a the motor feedback voltage from phase a is monitored through a resistor divider for back-emf sensing at this pin 23(23) fb b the motor feedback voltage from phase b is monitored through a resistor divider for back-emf sensing at this pin 24(24) fb c the motor feedback voltage from phase c is monitored through a resistor divider for back-emf sensing at this pin 25(25) brake a logic low input activates motor braking by shutting off the high- side output drivers and turning on the low-side output drivers 26(26) c ios a capacitor to gnd sets the time that the low-side output drivers remain off after i sense exceeds its threshold 27(27) r ref an 137k ? resistor to gnd sets a current proportional to v ref that is used to set all the internal bias currents except for the vco 28(28) gnd signal and power ground pin description (pin number in parenthesis is for tqfp package)
ML4426 4 rev. 1.0 10/10/2000 electrical characteristics unless otherwise specified,v dd = 12v 10%, r sense = 1 ? , c vco = 10nf, c ios = 100pf, r ref = 137k ? , t a = operating temperature range (notes 1, 2) symbol parameter conditions min typ max units reference v ref total variation line, temp 6.5 6.9 7.5 v pwm oscillator total variation c t = 1nf 28 khz ramp peak 3.9 v ramp valley 1.7 v ramp charging current ? a speed control loop speed set input voltage range 0 v ref v speed fb input voltage range 0 v ref v speed comp output current 5 20 a speed set error amp transconductance v speed set = xv, v speed fb = yv 144 start-up c at charging current c suffix 0.68 0.98 a i suffix 0.5 1.1 a c at threshold voltage 1.4 1.7 v c rt charging current c suffix 0.68 0.98 a i suffix 0.5 1.1 a c rt threshold voltage 1.4 1.7 v voltage controlled oscillator frequency range r vco = 5v, speed fb = 6v 1.5 1.85 2.2 khz frequency vs. speed fb r vco = 5v, 0.5v speed fb 7v 300 hz/v current limit i sense gain 4.5 5.0 5.5 v/v one shot off-time c ios = 100pf c suffix 9 18 s i suffix 9 20 s absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. v dd ........................................................................... 14v logic inputs ( brake , f/ r ) ..................... gnd - 0.3 to 7v all other inputs and outputs . gnd -0.3v to v dd + 0.3v output current (la, lb, lc, ha , hb , hc ) ............ 50ma junction temperature ............................................. 150? storage temperature range ...................... ?5? to 150? lead temperature (soldering 10 sec.) ..................... 260? thermal resistance ( ja ) 28-pin narrow pdip .......................................... 48?/w 28-pin soic ...................................................... 75?/w 32-pin tqfp ...................................................... 80?/w operating conditions temperature range ML4426cx ................................................. 0? to 70? ML4426ix ............................................... ?0? to 85? v dd ......................................................... 10.8v to 13.2v
ML4426 rev. 1.0 10/10/2000 5 electrical characteristics (continued) symbol parameter conditions min typ max units logic inputs ( brake , f/ r ) (note 3) v ih input high voltage 2 v v il input low voltage 0.8 v i ih input high current v ih = 2.4v 2.4 ma i il input low current v il = 0.4v 2.9 ma logic outputs (vco/tach, uv fault ) (note 3) vco/tach output high voltage i out = ?00 a 2.2 v vco/tach output low voltage i out = 400 a 0.6 v uv fault output high voltage i out = ?0 a c suffix 3.4 4.5 5.4 v i suffix 3.2 5.6 v uv fault output low voltage i out = 400 a 0.6 v back-emf sampler speed fb align mode voltage 125 250 mv speed fb ramp mode current c suffix 500 720 na i suffix 500 750 na speed fb run mode current state a, c rt = 5v, c suffix 30 90 a v phb = v dd /3 i suffix 27 90 a state a, c rt = 5v, v phb = v dd /2 ?5 15 a state a, c rt = 5v, c suffix 90 30 a v phb = 2 ? v dd /3 i suffix 90 27 a output drivers high side driver output low current v hx = 2v 0.5 1.2 ma high side driver output high voltage i hx = ?0 av cc ?1.3 v low side driver output low voltage i lx = 1ma 0.2 0.7 v low side driver output high voltage v(i sense ) = 0v c suffix v dd ?2.2 v i suffix v dd ?2.9 v phase c cross-conduction lockout threshold v dd ?3.0 v supply i dd v dd current 32 50 ma uvlo threshold c suffix 8.8 9.5 10.2 v i suffix 8.6 10.3 v uvlo hysteresis 150 mv note 1: limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. note 2: for explanation of states, see figure 4 and table 1. note 3: the brake and uv fault pins each have an internal 4k ? resistor to the internal reference.
ML4426 6 rev. 1.0 10/10/2000 functional description general the ML4426 provides all the circuitry for sensorless speed control of 3-phase brushless dc (bldc) motors. controller functions include start-up circuitry, back-emf commutation control, pulse width modulation (pwm) speed control, fixed off-time current limiting, braking, and undervoltage protection. the start-up circuitry aligns the motor to a known position, then ramps up the motor speed to generate a back-emf signal. a back-emf sampling circuit controls commutation timing by forming a phase locked loop (pll). the commutation control circuitry also outputs a speed feedback (speed fb) signal used in the speed control loop. the speed control loop consists of an error amplifier and pwm comparator that produce a pwm duty cycle for speed regulation. motor current is limited by a fixed off-time pwm shutdown comparator that is controlled by an external sense resistor. commutation control, pwm speed control, and current limiting are combined to produce the output driver signals. six output drivers are used to provide gating signals to an external 3 phase bridge power stage sized for the bldc motor voltage and current requirements. additional functions include a braking function and undervoltage protection circuit to shut down the output drivers in the event of a low voltage condition on v dd of the ML4426. component selection selecting external components for the ML4426 requires calculations based on the motors electrical and mechanical parameters. the following is a list of the motor parameters needed for these calculations : dc motor supply voltage ?v motor (v) maximum operating current ?i max (a) number of magnetic poles ?n back emf constant ?k e (v-s/rad) motor torque constant ?k t (nm/a) (k t = k e in si units) maximum speed of operation rpm max (rpm) moment of inertia of the motor and load ?j (kg-m 2 ) viscous damping factor of the motor and load ? if one or more of the above values is not known, it is still possible to pick components for the ML4426, but some experimentation may be necessary to determine the optimal values. all quantities are in si units unless otherwise specified. the following formulas should be considered as a starting point for optimization. all calculations for capacitors and resistors should be used as the first approximation for selecting the closest standard value. power supply and reference the supply voltage (v dd ) is nominally 12v 10%. a 100nf bypass capacitor to ground should be placed as close as possible to v dd . a 6.9v voltage reference output (v ref ) is provided to set the speed command and current limit of the ML4426. a 137k ? from r ref to gnd is required to set up a reference current for internal functions. output drivers the output drivers la, lb, lc, ha , hb , and hc provide totem pole output drive signals for a 3 phase bridge power stage. all control functions in the ML4426 translate to outputs at these pins. la, lb, and lc provide the low-side drive signals for phases a, b, and c of the 3 phase power stage and are 12v active high signals. ha , hb , and hc provide the high-side signals and are 12v active low signals. motor phase c motor phase b motor phase a v motor 12v r sense dc supply capacitor ha la hb lb hc lc figure 1. using r sense in a 3-phase 12v power stage
ML4426 current limiting in the po wer st a g e the current sense resistor (r sense ) shown in figure 1 regulates the maximum current in the power stage and the bldc motor. current regulation is accomplished by shutting off the output drivers la, lb, and lc for a fixed amount of time if the voltage across r sense exceeds the current limit threshold. r sense the function of r sense is to provide a voltage proportional to the motor current to set the current limit trip point. the default trip voltage across r sense is 460mv, set by the internal i limit divider ratio. the current sense resistor should be a low inductance resistor such as a carbon composition. for resistors in the milliohms range, wire-wound resistors tend to have low values of inductance. r sense should be sized to handle the power dissipation (i max 2 r sense ). i sense filter the i sense rc lowpass filter is placed in series with the current sense signal as shown in figure 2. the purpose of this filter is to remove the diode reverse recovery shootthrough current. this current causes a voltage spike on the leading edge of the current sense signal which may falsely trigger the current limit. the current sense voltage waveform is shown before and after filtering in figure 3. the recommended starting values for this circuit are r = 1k w and c = 330pf. this gives a time constant of 330ns, and will filter out spikes of shorter duration. c can be increased to as much as 2.2nf, but should not exceed a time constant of more than a few microseconds. c ios when i sense exceeds 0.2 i limit , the current limit one- shot is activated, turning off la, lb, and lc for a fixed amount of time (t off ). t off is set by the amount of capacitance connected to c ios . c ios is usually set for a fixed off time equal to or less than the pwm period. for a 25khz pwm frequency, the pwm period is 40s; t off should be between 20s and 40s. the lower limit of t off is dictated by the minimum on time of the power stage; a safe approximation is 5s or less. the equation for finding the c ios capacitance value is as follows: c ta v os off = ? 50 24 m . (1) commut a tion control a 3-phase bldc motor requires electronic commutation to achieve rotational motion. electronic commutation requires the switching on and off of the power switches of a 3-phase half bridge. for torque production to be achieved in one direction, the commutation is dictated by the rotor position. electronic commutation in the ML4426 is achieved by turning on and off, in the proper sequence, functional description (continued) figure 2. current sense circuitry 5 i sense from r sense pwm on/off C + v ref c ios 16k w 2.9v 0v stop 30a start 8k w s r q q f igur e 3. curr ent sense resistor w a v eforms (a) w ithout f iltering, and (b) w ith f iltering (a) 0v 460mv (b) one n output from one phase and one p output from another phase. there are six combinations of n and p outputs (six switching states) that constitute a full commutation cycle. these combinations are illustrated in table 1 and figure 4, and are labeled states a through f. this sequence is programmed into the commutation state machine. clocking of the commutation state machine is provided by a voltage controlled oscillator (vco). forward/reverse control the commutation sequence is reversed by pulling the f/ r pin to gnd. this allows the motor to operate in the opposite direction. this pin should change state only when the motor is at rest. either remove and restore power to the ML4426, or pull the brake pin and c at pin to 0v to stop the motor prior to changing the voltage on f/ r . either method resets the internal commutation state machine, and initiates a new start-up sequence. rev. 1.0 10/10/2000 7
ML4426 o u t p u t s input st a t e l a l b l c h a h b h c sampling r off on off on off on n/a a off off on on off off fb b b off off on off on off fb a c on off off off on off fb c d on off off off off on fb b e off on off off off on fb a f off on off on off off fb c t able 1. commutation state functions (f orw ar d direction) f igur e 4. output commutation sequence t iming diagr am (f orw ar d dir ection) cycle 1 - full commutation, cycle 2 - commutation with 50% pwm duty cycle high side drive outputs ha hb hc low side drive outputs la abcde fabcde f lb lc v oltage contr olled oscillator (vco) the vco provides a ttl compatible clock output on the vco/tach pin proportional to the vco input voltage at the speed fb pin. the proportion of frequency to voltage (vco constant, k v ) is set by an 80.6k w resistor on r vco and a capacitor on c vco as shown in figure 5. r vco sets up a current proportional the vco input voltage at speed fb. this current is used to charge and discharge c vco between the threshold voltages of 2.3v and 4.3v. the resulting triangle wave on c vco corresponds to the clock on vco. k v should be set so that the vco output frequency corresponds to the maximum commutation frequency or maximum motor speed when the vco input is equal to or slightly less than v ref . c vco is calculated using the following equation: c v hz farad v hz rpm nspeed vco max = ?? ? ?? - 6 5 3101 10 005 6 .. . (2) the closest standard value that is equal to or less than the calculated c vco should be used. functional description (continued) rev. 1.0 10/10/2000 8
ML4426 the maximum frequency on the vco pin is found by: fnrpm max max =?? 005. (3) the voltage at the vco/tach pin is equal to the rotor speed. the voltage at speed fb is controlled by the back emf sampler. back emf sampler the input to the voltage controlled oscillator is the back emf sampler. the back emf sense pins fb a, fb b, and fb c inputs to the back emf sampler require a signal from the motor phase leads that is below the v dd of the ML4426. the phase sense input impedance is 8k w . this requires a series resistor res1 from the motor phase lead as shown in figure 6 based on the following equation: res v v v motor 1 670 10 =?- w / 16 (4) the back emf sampler takes the motor phase voltages divided down to signals that are less than v dd (12v nominal) and calculates the neutral point of the motor by the following equation: neutral ph ph ph = ++ 123 3 (5) this allows the ML4426 to compare the back emf signal to the motor's neutral point without the need for bringing out an extra wire on a wye wound motor. for delta wound motors there is no physical neutral to bring out, so this reference point must be calculated in any case. the back emf sampler measures the motor phase that is not driven (i.e. if la and hb are on, then phase a is driven low, phase b is driven high, and phase c is functional description (continued) f igur e 5. external vco component connections c vco c vco 4.3v 0v 5v 2.3v r vco speed fb c vco r vco voltage controlled oscillator vco/tach vco/tach reset (from c at ) from back emf sampler & ramp generator neutral simulator f a + f b + f c 6 multiplexer commutation state machine g m = 1 8k w 4k w 4k w 4k w 4k w 4k w 4k w + C sign changer to speed fb fb a res1 res2 res3 fb b fb c motor f c motor f b motor f a figure 6. back emf sampler detailed block diagram sampled). the sampled phase provides a back emf signal that is compared against the neutral of the motor. the sampler is controlled by the commutation state machine. the sampled back emf is compared to the neutral through an error amplifier. the output of the error amplifier outputs a charging or discharging current to speed fb, which provides the control voltage to the vco. rev. 1.0 10/10/2000 9
ML4426 fb a 22 f/ r 12 fb b 23 fb c 24 back emf sampler v dd 500na speed fb c speedfb1 c speedfb2 r speedfb 20 voltage controlled oscillator phase locked loop vco/tach 13 a b c d e f r commutation state machine b a ck emf sensing pll commut a tion control three blocks form a phase locked loop that locks the commutation clock onto the back emf signal: the commutation state machine, the voltage controlled oscillator, and the back emf sampler. the complete phase locked loop is illustrated in figure 7. the phased locked loop requires a lead lag filter that is set by external components on speed fb. the components are selected as follows: c k m n d f speedfb os vco 1 1 2 2 2 025 100 =?? ? . ln (6a) rm d f nk m speedfb vco so =? ? ? ??- 2 100 1 1 ln 0 5 (6b) cc m speedfb speedfb 21 1 =?- 05 (6c) st a r t -up seq uence when power is first applied to the ML4426 and the motor is at rest, the back emf is equal to zero. the motor needs to be rotating for the back emf sampler to lock onto the rotor position and commutate the motor. the ML4426 uses an open loop start-up technique to bring the rotor from rest up to a speed fast enough to allow back emf sensing. start-up is comprised of three modes: align mode, ramp mode, and run mode. align mode (reset) before the motor can be started, the rotor must be in a known position. when power is first applied to the ML4426, the controller is reset into the align mode. align mode turns on the output drivers lb, ha , and hc which aligns the motor into a position 30 electrical degrees before the center of the first commutation state. this is shown as state r in the commutation states of table 1. align mode must last long enough to allow the motor and its load to settle into this position. the align mode time is set by a capacitor connected to the c at pin as shown in figure 8. c at is charged by a constant 750a current from gnd to 1.5 v until the align comparator trips to end the align mode. a starting point for c at is calculated as follows: c tamp v at s = ?? ? - 75 10 15 7 . . (7) if the align time is not long enough to allow the rotor to settle for reliable starting, then increase c at until the desired performance is achieved. functional description (continued) ramp mode at the end of align mode the controller goes into ramp mode. ramp mode starts commutating through the states a through f as shown in table 1. this ramps up the commutation frequency, and therefore the motor speed, for a fixed length of time. this allows the motor to reach a sufficient speed for the back emf sampler to lock commutation onto the motor's back emf. the amount of time the ML4426 stays in ramp mode is determined by a capacitor connected to the c rt pin as shown in figure 8. c rt is charged by a constant 750a current from gnd to 1.5 v until the ramp comparator trips to end the ramp mode. this gives a fixed ramp time. c rt is calculated as follows: c jampk ik n rt v max t = ?? ? ? ? ??? - 2510 3 7 p (8) the rate at which the ML4426 ramps up the motor speed is determined by a fixed 500a current source on the speed fb pin. the current sources charges up the pll filter components causing the vco frequency to ramp up. during ramp mode, the back emf sampler is disabled to allow control of the ramping to be set only by the 500a current source. the ramp based on the speed fb filter is generally too fast for the motor to keep up, so a capacitor from c rr to speed fb can be added to slow down the ramping rate. the optimal ramp rate is based on the motor and load parameters and is can be adjusted by varying the value of c rr . figure 7. back emf commutation phase locked loop rev. 1.0 10/10/2000 1 0
ML4426 c at c at fb a fb b fb c back emf sampler c rt c rt c rr C + 1.5v 750na C + 1.5v 750na v dd v dd c rr 500na v dd speed fb to speed fb filter c vco r vco voltage controlled oscillator vco/tach to reset input of commutation state machine run mode (back emf sensing) at the end of ramp mode the controller goes into run mode. in run mode, the back emf sensing is enabled and commutation is now under the control of the phase locked loop. motor speed is now regulated by the speed control loop. pwm speed control speed control is accomplished by setting a speed command at speed set with an input voltage from 0 to 6.9v (v ref ). the accuracy of the speed command is determined by the external components r vco and c vco . there are a number of methods that can be used to control the speed command of the ML4426. one is to use a 10k w potentiometer from v ref to ground with the wiper connected to speed set. if speed set is controlled from a microcontroller, one of its dacs can be used with v ref as its input reference. the speed command is compared with the sensed speed from speed fb through a transconductance error amplifier. the output of the speed error amplifier is speed comp. speed comp is clamped between one diode drop above 3.9v (approximately 4.6v) and one diode drop below 1.7v (approximately 1v) to prevent speed loop wind-up. speed loop compensation components are connected to this pin as shown in figure 9. the speed loop compensation components are calculated as follows: c nv c fk mf sc motor vco sb e sb = ?? ? ?+?? 26 9 25 98 696 2 2 . .. t (9a) r fc sc sb sc = ?? 10 2 p (9b) where f sb is the speed loop bandwidth in hz. f igur e 8. ML4426 start-up cir cuitr y for contr olling the align and ramp t imes C + + C speed set speed comp 3.9v 1.7v 10k w 20khz pwm on/off from i limit one-shot from speed fb to gating logic & output drivers c t c t c sc r sc 1.7v v ref the voltage on speed comp is compared with a ramp oscillator to create a pwm duty cycle. the pwm ramp oscillator creates a sawtooth function from 1.7v to 3.9v as shown in figure 9. a negative clamp at one diode drop below 1.7v (approximately 1v) starts the oscillator on power up. the frequency of the ramp oscillator is set by a capacitor to ground c ios and is selected using the following equation: c f a v t pwm = ? 1 50 24 m . (10) where f pwm is the pwm frequency in hz. the pwm duty cycle from the speed control loop is gated the current limit one shot that controls the la, lb, and lc output drivers. figure 9. speed control loop component connections rev. 1.0 10/10/2000 1 1
ML4426 12 rev. 1.0 10/10/2000 cross conduction comparator when the ML4426 goes from align mode into ramp mode, there is a possibility of cross conduction in phase 3 of the bridge power stage. this cross conduction can happen when hc is on in the align mode shown as state r in table 1, and the controller transitions to state a in ramp mode where hc is turned off and lc is turned on. cross conduction can appear due to the differences in turn on and turn off times of the power devices. to solve this problem, the lc output driver is gated off until the hc is equal to v dd 3v as shown in figure 10. braking when the brake pin is pulled below 1.4v, the low side output drivers la, lb, and lc are turned on and the high side output drivers ha, hb, hc are turned off. braking causes rapid deceleration of the motor and current limiting is de-activated, and care should be taken when using the brake pin. brake is has an internal 4k ? pull- up as shown in figure 10, and can be driven by a switch to ground, an open collector or drain logic signal, or a ttl logic signal. undervoltage lockout undervoltage lockout is used to protect the 3-phase bridge power stage from a low v dd condition. undervoltage is triggered at v dd of 9.5v or less and is indicated by a ttl low output on the uv fault pin. undervoltage lockout also turns off all output drivers (la, lb, lc, ha , hb , and hc ). the comparator that triggers undervoltage lockout has 150mv of hystresis. design considerations interfacing to a 3-phase bridge power stage the ML4426 output drivers are configured to drive a 3 phase bridge power stage. for applications with buss voltages from 12v up to 80v, level shifting circuitry can be used to drive higher voltage p-channel mosfets for the high side switches as shown in figure 11. the most flexible configuration is to use high side drivers to control n-channel mosfets (or igbts) which allows applications from less than 12v up to 600v. figure 12 shows the interface between the ML4426 and ir2118 high side drivers from international rectifier. this configuration is capable of driving motors from busses of up to 320v. the brake pin can be pulsed prior to startup with an rc circuit. this charges the bootstrap capacitors (c19, c20, and c21) for the three high side drivers, allowing the reset phase to operate normally. these capacitors must be sized so that they stay sufficiently charged during the align mode. refer to an-43 for additional applications information on the ML4426. functional description (continued) 2 4 3 9 10 ha hb hc la lb gating logic & output drivers ? + 1.4v 9.5v 25 brake v dd 4k ? 14 v dd 28 gnd 27 r ref 11 lc reference 18 uv fault 7 v ref from commutation state machine from speed control loop & current limit + ? figure 10. cross conduction, brake, and uvlo circuits
ML4426 rev. 1.0 10/10/2000 13 r19 80.5k ? brake reverse forward run r10 (res1) r9 (res1) r8 (res1) s1 c16 330pf motor c5 2.2nf r16 10k ? r14 2k ? c17 1nf c9 100nf c12 r18 10k ? r21 787 ? r6 100 ? r5 100 ? r7 100 ? q7 irfr120 q8 irfr120 q9 irfr120 r1 470m ? 2w v buss 24v ? 80v c1 100nf 100v c2 330f 100v r2 10k ? q1 2n6718 c15 470nf 12v q4 irfr9120 r3 10k ? q2 2n6718 q5 irfr9120 r4 10k ? q3 2n6718 r15 1k ? r13 2k ? r12 2k ? q6 irfr9120 c3 1f ml4425 i sense ha hb hc speed comp c t v ref speed set la lb lc f/ r vco/tach v dd gnd r ref c ios brake fb c fb b fb a c rr speed fb c rt uv fault c at r vco c vco r20 137k ? c4 c8 1f c14 r17 10k ? c7 100nf c6 1f c14 1f c13 100nf 12v figure 11. driving lower voltage motors (12 to 80v)
ML4426 14 rev. 1.0 10/10/2000 r16 80.6k ? brake run r13 (res1) r14 (res1) r15 (res1) s1 c14 330pf motor c1 2.2nf r5 10k ? c4 1nf c3 100nf c15 100nf r20 10k ? r19 787 ? r11 100 ? r10 100 ? r9 100 ? d4 d5 d6 (3 1n5819) q2 irf720 q4 ir720 q6 irf720 r12 470m ? 2w v buss 24v ? 80v c9 470nf 12v r6 100 ? q1 irf720 q3 irf720 r1 1k ? q5 irf720 ml4425 r18 137k ? c8 10nf c10 1f c19 2.2f 25v c13* r17 10k ? c11 100nf c12 1f ir2118 v cc in com nc vb ho vs nc c16 100nf 25v d1 mur150 c5 330f 400v c20 2.2f 25v c17 100nf 25v d2 mur150 c21 2.2f 25v c18 100nf 25v d3 mur150 r7 100 ? r8 100 ? ir2118 v cc in com nc vb ho vs nc ir2118 v cc in com nc vb ho vs nc i sense ha hb hc speed comp c t v ref speed set la lb lc f/ r vco/tach v dd gnd r ref c ios brake fb c fb b fb a ramp comp speed fb c rt uv fault c at r vco c vco bootstrap pre-charge capacitor reverse forward c6 1f c7 100nf 12v figure 12. ML4426 high voltage motor drive application circuit
ML4426 rev. 1.0 10/10/2000 15 physical dimensions inches (millimeters 0.048 max (1.20 max) seating plane 0.354 bsc (9.00 bsc) 0.276 bsc (7.00 bsc) 1 0.276 bsc (7.00 bsc) 0.354 bsc (9.00 bsc) 9 25 17 0.032 bsc (0.8 bsc) pin 1 id 0.012 - 0.018 (0.29 - 0.45) 0.037 - 0.041 (0.95 - 1.05) 0.018 - 0.030 (0.45 - 0.75) 0.003 - 0.008 (0.09 - 0.20) 0 o - 8 o package: h32-7 32-pin (7 x 7 x 1mm) tqfp package: p28n 28-pin narrow pdip seating plane 0.280 - 0.296 (7.11 - 7.52) pin 1 id 0.299 - 0.325 (7.60 - 8.26) 1.355 - 1.365 (34.42 - 34.67) 0.015 - 0.021 (0.38 - 0.53) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.020 min (0.51 min) 28 0 o - 15 o 1 0.045 - 0.055 (1.14 - 1.40) 0.180 max (4.57 max) 0.125 - 0.135 (3.18 - 3.43)
ML4426 16 rev. 1.0 10/10/2000 ordering information part number temperature range package ML4426cp (end of life) 0 c to 70 c 28-pin pdip (p28n) ML4426cs (end of life) 0 c to 70 c 28-pin soic (s28) ML4426ch (end of life) 0 c to 70 c 32-pin tqfp (h32-7) ML4426ip (end of life) 40 c to 85 c 28-pin pdip (p28n) ML4426is (end of life) 40 c to 85 c 28-pin soic (s28) ML4426ih (end of life) 40 c to 85 c 32-pin tqfp (h32-7) physical dimensions inches (millimeters) seating plane 0.291 - 0.301 (7.39 - 7.65) pin 1 id 0.398 - 0.412 (10.11 - 10.47) 0.699 - 0.713 (17.75 - 18.11) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.022 - 0.042 (0.56 - 1.07) 0.095 - 0.107 (2.41 - 2.72) 0.005 - 0.013 (0.13 - 0.33) 0.090 - 0.094 (2.28 - 2.39) 28 0.009 - 0.013 (0.22 - 0.33) 0 o - 8 o 1 0.024 - 0.034 (0.61 - 0.86) (4 places) package: s28 28-pin soic life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ?2000 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

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