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OV511 advanced camera to usb bridge omnivision technologies, inc. july 17, 1998 data sheet rev. 1.0 omnivision technologies, inc. reserves the right to make changes without further notice to any product herein to improve reliability, function or design. omnivision does not assume any liability arising out of the application or use of any project, circuit described herein; neither does it convey any license under its patent nor the right of others. this document contains information of a proprietary nature. none of this information shall be divulged to persons other than omnivision technologies, inc. employee authorized by the nature of their duties to receive such information, or individuals or organizations authorized by omnivision technologies, inc. www..net
1 content 1 features ................................ ................................ ................................ ................................ ............ 5 2 architecture ................................ ................................ ................................ ................................ ...... 6 2.1 general description ................................ ................................ ................................ .................. 6 2.2 functional description ................................ ................................ ................................ .............. 7 2.2.1 camera interface ................................ ................................ ................................ ............... 7 2.2.2 dram interface ................................ ................................ ................................ ................ 8 2.2.3 omnice ................................ ................................ ................................ ............................ 9 2.2.4 iso fifo ................................ ................................ ................................ ........................ 10 2.2.5 udc interface ................................ ................................ ................................ ................. 11 2.2.6 system control ................................ ................................ ................................ ................ 11 2.2.7 usb device controller ................................ ................................ ................................ .... 12 2.2.8 i 2 c ................................ ................................ ................................ ................................ .. 12 2.2.9 pio ................................ ................................ ................................ ................................ . 13 2.2.10 custom id ................................ ................................ ................................ ....................... 14 3 pin definition ................................ ................................ ................................ ................................ . 15 3.1 pin assignments ................................ ................................ ................................ ..................... 15 3.2 pin descriptions ................................ ................................ ................................ ...................... 16 4 electrical characteristics ................................ ................................ ................................ ................ 18 5 register table (vendor commands) ................................ ................................ ............................... 19 5.1 camera interface ................................ ................................ ................................ ......... 19 5.2 dram interface ................................ ................................ ................................ .............. 20 5.3 iso fifo ................................ ................................ ................................ ................................ 20 5.4 pio ................................ ................................ ................................ ................................ ......... 21 5.5 i 2 c ................................ ................................ ................................ ................................ .......... 21 5.6 system control ................................ ................................ ................................ ............. 23 5.7 omnice ................................ ................................ ................................ ................................ . 23 6 usb descriptors ................................ ................................ ................................ ............................. 25 6.1 device ................................ ................................ ................................ ................................ ..... 25 6.2 configuration ................................ ................................ ................................ .......................... 25 6.3 interface & endpoint ................................ ................................ ................................ .............. 25 6.3.1 alternate 0 ................................ ................................ ................................ ...................... 26 6.3.2 alternate 1 ................................ ................................ ................................ ...................... 26 6.3.3 alternate 2 ................................ ................................ ................................ ...................... 26 6.3.4 alternate 3 ................................ ................................ ................................ ...................... 27 6.3.5 alternate 4 ................................ ................................ ................................ ...................... 27 6.3.6 alternate 5 ................................ ................................ ................................ ...................... 28 6.3.7 alternate 6 ................................ ................................ ................................ ...................... 28 6.3.8 alternate 7 ................................ ................................ ................................ ...................... 28 7 software package ................................ ................................ ................................ ............................ 30 8 mechanical information ................................ ................................ ................................ ................. 31 9 evb (evaluation board) design reference ................................ ................................ ..................... 32 9.1 evb schematic diagram ................................ ................................ ................................ ........ 32 9.1.1 page 1, OV511 ................................ ................................ ................................ ................ 32 9.1.2 page 2, power and control ................................ ................................ .............................. 33 9.1.3 page 3, camera module ................................ ................................ ................................ ... 34 9.1.4 page 4, custom id ................................ ................................ ................................ ....... 35 9.2 board description ................................ ................................ ................................ ................... 36 9.2.1 power planes ................................ ................................ ................................ ................... 36 9.2.1.1 the power plane of the usb connector, OV511 & dram (5v) ................................ . 36 9.2.1.2 the power plane of the usb transceiver (3.3v) ................................ .......................... 36 9.2.1.3 the power plane of the camera (4.7/5v) ................................ ................................ ..... 37 9.2.1.4 the power plane of oscillators (option) ................................ ................................ ...... 37 www..net
2 9.2.2 clocks ................................ ................................ ................................ ............................. 37 9.2.3 dram ................................ ................................ ................................ ............................ 38 9.2.4 options ................................ ................................ ................................ ........................... 38 9.3 pcb layout ................................ ................................ ................................ ............................ 40 9.3.1 placement ................................ ................................ ................................ ........................ 40 9.3.2 grounding ................................ ................................ ................................ ....................... 40 www..net
3 illustrations figure 1. functional block diagram ................................ ................................ ..................... 6 figure 2. camera int erface yuv - 4:2:2 - 16-bit horizontal timing waveforms .... 7 figure 3. camera int erface vertical ? interlace mode timing waveforms ....... 7 figure 4. camera interface vertical ? progressive mode timing waveforms .. 8 figure 5. memory map ................................ ................................ ................................ ................... 8 figure 6. dram inter face write cycle timing waveforms ................................ .......... 8 figure 7. dram inte rface read cycle timing waveform ................................ .............. 9 figure 8. dram inter face refresh cycle timing waveforms ................................ ..... 9 figure 9. structure of omnice ................................ ................................ ................................ 10 figure 10. sof/eof f ormats ................................ ................................ ................................ ...... 10 figure 11. clock sch eme of OV511 ................................ ................................ ........................ 11 figure 12. usb commu nication flow ................................ ................................ ................... 12 figure 13. a complet e data transfer on i 2 c bus ................................ ........................... 12 figure 14. bit trans fer on the i 2 c bus ................................ ................................ ................ 13 figure 15. pio read cycle timing waveforms ................................ ................................ . 13 figure 16. pio write cycle timing waveforms ................................ ............................... 13 figure 17. 100-pin p qfp package ................................ ................................ .............................. 15 figure 18. power pla nes of the usb camera system ................................ .................... 36 figure 19. the power circuit of the usb connector, OV511, dram & the usb transceiver ................................ ................................ ................................ ............................. 36 figure 20. the power circuit of the camera ................................ ................................ ... 37 figure 21. the power circuit of oscillators (option) ................................ ................ 37 figure 22. circuits of damping resistors & shell grounding ................................ . 38 figure 23. circuits of reset & snapshot bottoms ................................ ........................ 39 www..net
4 tables table 1. capability of camera interface ................................ ................................ .......... 7 table 2. maximum pix el count of one 256kx16 dram ................................ ..................... 7 table 3. parame ters of dram interface timing ................................ .............................. 9 table 4. parameters of pio timing ................................ ................................ ....................... 13 table 5. pin descrip tions ................................ ................................ ................................ .......... 16 table 6. dc electric al characteristics ................................ ................................ .......... 18 table 7. absolute ma ximum ratings ................................ ................................ .................. 18 table 8. recommended operating conditions ................................ ............................... 18 table 9. camera inte rface register list ................................ ................................ ......... 19 table 10. dram inter face register list ................................ ................................ .............. 20 table 11. iso fifo r egister list ................................ ................................ ................................ 20 table 12. pio regist er list ................................ ................................ ................................ ......... 21 table 13. i 2 c register list ................................ ................................ ................................ .......... 21 table 14. system con trol register list ................................ ................................ ............. 23 table 15. omnice reg ister list ................................ ................................ ................................ 23 table 16. device des criptor list ................................ ................................ ............................ 25 table 17. configurat ion descriptor list ................................ ................................ ........... 25 table 18. inte rface descriptor list of alternate 0 ................................ ..................... 26 table 19. endpoint d escriptor list of alternate 0, packet size 992 ....................... 26 table 20. interface descriptor list of alternate 1 ................................ ..................... 26 table 21. endpoint des criptor list of alternate 1, packet size 993 ....................... 26 table 22. interface descriptor list of alternate 2 ................................ ..................... 26 table 23. endpoint d escriptor list of alternate 2, packet size 768 ....................... 27 table 24. interface descriptor list of alternate 3 ................................ ..................... 27 table 25. endpoint d escriptor list of alternate 3, packet size 769 ....................... 27 table 26. interface descriptor list of alternate 4 ................................ ..................... 27 table 27. endpoint d escriptor list of alternate 4, packet size 512 ....................... 27 table 28. interface descriptor list of alternate 5 ................................ ..................... 28 table 29. endpoint d escriptor list of alternate 5, packet size 513 ....................... 28 table 30. interface descriptor list of alternate 6 ................................ ..................... 28 table 31. endpoint d escriptor list of alternate 6, packet size 257 ....................... 28 table 32. interface descri ptor list of alternate 7 ................................ ..................... 28 table 33. endpoint d escriptor list of alternate 7, packet size 0 .......................... 29 www..net
5 1 1 features camera input: 16-bit yuv 4:2:2/rgb raw data formats (two channels) or 8-bit y 4:0:0/rgb raw data formats (one channel only) supports clamping, down-scaling & filtering circuits for different video formats (vga, cif & qcif) supports proprietary real-time compression of up to 7:1 usb camera system: OV511 + 256kx16 5v edo, ras-before-cas refresh, 60ns dram, + usb transceiver supports hardware & software snapshot functions supports suspend / resume function supports usb running at the setting of full speed signaling bit rate supports usb control and isochronous transfers supports 8 alternates of up to 8mbps usb transfer rate supports i 2 c master function running at 100khz (normal mode) supports bus powered function of usb standard supports standard interface of usb transceivers optional single/dual clock inputs, hardware selectable www..net
6 2 2 architecture 2.1 general description the OV511 advanced camera to usb bridge is an usb camera controller that includes a compression function which supports real time image transfer and display in the pc system. a complete usb camera system consists of OV511, a 256kx16 dram, an usb transceiver, and a digital camera such as ov7610. the camera interface generates different image formats by taking either 16-bit yuv 4:2:2/rgb raw data or 8-bit y 4:0:0/rgb raw data inputs. the omnice is a proprietary compression engine. it not only performs 30fps compression rate for cif image, but also allows fast decompression in the host. in order to control camera devices, users can choose either i 2 c or parallel io bus. the i 2 c bus master uses two dedicated pins ?sda? & ?scl?, while the pio shares with y & uv buses. a hardware camera snapshot feature is also implemented in addition to the software snapshot launched by the host. this allows camera to alter formats before taking the shot. the functional blocks of OV511, as shown in the following figure, consist of camera interface, dram interface, omnice, udc interface, iso fifo, system control, i 2 c and pio. figure 1. functional block diagram usb device controller usb xver usb system control camera interface 256kx16 dram dram interface udc interface omnice 8/16 bit bus 16 16 16 iso fifo 27 mhz 48 mhz 8 8 select href vsync pclk www..net
7 2.2 functional description 2.2.1 camera interface the OV511 digital video inputs are either 16-bit yuv 4:2:2/rgb raw data formats (two channels) or 8-bit y 4:0:0/rgb raw data formats (one channel only). clamping, down-scaling & filtering functions are also supported. however, not all input formats can be compressed by omnice. table 1. capability of camera interface channels input formats clamping down-scaling filtering compression (omnice) yuv 4:2:2 available available available available 2, 16-bit (y & uv) 16-bit rgb raw data available available available not available y 4:0:0 available available available available 1, 8-bit (y only) 8-bit rgb raw data available available not available not available if the camera input format is 16-bit yuv 4:2:2 mode, the output of the camera interface can be configured as yuv 4:2:0 or 4:0:0, as well as yuv 4:2:2. the maximum clamped image size is 1024 pixels wide and 1024 lines height in increment of 8, depending on the camera input format. the actual image size is limited by the capability of dram. table 2. maximum pixel count of one 256kx16 dram output formats of camera interface pixel count yuv 4:2:2 256k yuv 4:2:0 344k y 4:0:0 512k the down-scaling feature sub-samples the image in both horizontal & vertical directions by choosing scaling factor 1, 2, 4 or 8. no up-scaling feature is implemented. the anti aliasing filter interploates down-scaling images to improve image resoultion. the camera interface can perform capture of one single frame as well as video, such as vga, cif or qcif easily. figure 2. camera interface yuv - 4:2:2 - 16-bit horizontal timing waveforms figure 3. camera interface vertical ? interlace mode timing waveforms cclk pclk triggers data at rising edge href beginning of an active line end of an active line y0 y1 y2 y3 y636 y637 y638 y639 10h y 10h u0 v0 u2 v2 u636 v636 u638 v638 80h uv 80h vsync fodd href 479 480 1 2 239 240 241 242 www..net
8 figure 4. camera interface vertical ? progressive mode timing waveforms 2.2.2 dram interface dram interface generates dram addresses for write and read cycles based on the configured image size as well as data format. the dram memory is partitioned according to the data formats such as 4:2:2, 4:2:0 or 4:0:0. dram interface also arbitrates the dram access between write request from the camera interface and read request from omnice. it also performs the flow control to avoid image overflow and underflow conditions occur. OV511 supports 5v edo, ras-before-cas refresh, 60ns dram. figure 5. memory map figure 6. dram interface write cycle timing waveforms vsync fodd href 1 2 479 480 00000 y 1ffff 00000 y 2afff 00000 raw 3ffff 20000 u 2ffff 30000 v 3ffff 2b000 u 357ff 35800 u 3ffff 4:2:2 4:2:0 4:0:0 col row ras_ cas_ we_ addr data t rah t rasp t cas t pc t cah t rcd t ds t dh t asc www..net
9 figure 7. dram interface read cycle timing waveform figure 8. dram interface refresh cycle timing waveforms table 3. parameters of dram interface timing symbol parameter min max unit t rasp ras_ pulse width 185 ? ns t rah row address hold time 18.5 ? ns t cas cas_ pulse width 18.5 ? ns t rcd ras_ to cas_ delay time 39 44 ns t asc column address setup time 18.5 ? ns t cah column address hold time 11.5 ? ns t ds data-in setup time 18.5 ? ns t dh data-in hold time 11.5 ? ns t rac access time from ras_ ? 60 ns t cac access time from cas_ ? 15 ns t oez output buffer turnoff delay form oe_ ns t rpc ras_ precharge to cas_ hold time 18.5 ? ns t chr cas_ hold time 55.5 ? ns t csr cas_ setup time 55.5 ? ns t rc random read or write cycle time 185 ? ns t ras ras_ pulse width 111 ? ns t rp ras_ precharge time 74 ? ns 2.2.3 omnice omnice is a proprietary compression engine, constructed by the predictor, the quantizer, as well as encoder along with look-up tables. the predictor predicts image pixels horizontally and vertically. the outstanding look-up table is programmed by the software driver according to calculation of probability. col row ras_ cas_ oe_ addr data t rasp t rah t cas t rcd t pc t cah t asc t oez t off t rac t cac ras_ cas_ t rc t ras t rp t rpc t csr t chr www..net
10 the compression ratio of omnice varies from 4 to 7, depending on image complexity. parameters can be modified dynamically by the software driver to achieve the desired frame rate. it can also be disabled and bypass uncompressed data. figure 9. structure of omnice 2.2.4 iso fifo OV511 implements one isochronous endpoint for video data transfer. the available alternates include packet size of 0, 257, 512, 513, 768, 769, 992 & 993. the corresponding iso fifo size has to be set by the software driver right before the current alternate is set. the size of iso fifo is configurable from 32 to 992 in increment of 32. moreover, in order to assist packet reordering in the host, a packet number inserted at the end of each packet can be turned on. an image frame starts with the sof packet (start of an image frame), as well as ends with the eof packet (end of an image frame). the packet number counts up from 01 to 255 and back to 01. only the sof packet uses the packet number 00. sof/eof packets are indicated by the unique combination which the 1 st to the 8 th byte are all ?0?s and the 9 th byte contains a non-zero header. this header contains image information, such as the operating mode, snapshot flag & even/odd field. in the case of the eof packet, the 10 th and 11 th bytes also contain the image width and height information. figure 10. sof/eof formats predictor input quantizer encoder output look-up table programmed by host 11 video data ...... 1 993,992,768,769,385,384,257,0 packet 1 ... 9 10~11 sof/eof tag 8"0"s 7 6 5 4 3 2 1 0 bit frame header byte, the 9th byte only available for eof 7 - eof 6 - compression enabled 5 - 422/420/400 modes 4 - 422/420/400 modes 3 - 1 2 - snapshot bottom on 1 - snapshot frame 0 - even/odd field packet number sof/eof eof 10th, 11th bytes hor. width ver. width www..net
11 2.2.5 udc interface udc interface performs hand-shaking protocols with usb device controller. its function includes isochronous transfer, responding vendor commands & descriptors, and generating read/write cycles to internal registers. 2.2.6 system control system control unit performs functions of system clock generation, power on reset, software reset scheme, usb reset command, system initialization, snapshot and usb suspend. OV511 takes dual clock inputs, ?clk_48m? & ?clk_27m?. ?clk_48m? takes 48mhz oscillator/crystal input for usb bus, while ?clk_27m? is camera dependent & pin option selectable. 27mhz crystal/oscillator is recommended for vga resolution cameras to perform frame rate of 30fps. if pin ?en_osc27? is pulled up, ?clk_27m? is chosen in support of camera clock. if it?s pulled down, ?clk_48m? is divided by 2 and provides camera clock. figure 11. clock scheme of OV511 there are three kinds of reset scheme supported by OV511. the power-on reset (pin ?resetb?) & usb reset command initialize OV511 & camera circuits. the camera reset (pin ?reset?) toggles as soon as either power-on reset or usb reset is asserted. the software reset allows individual functional blocks to be reset without altering the register contents. software reset is necessary when changing camera formats, iso packet size, compression parameters, etc. according to usb specification, a high-power (> 100ma) function requires staged switching of power. it must first come up in a reduced power state of less than one unit load, which is 100ma. system initialization function stops system clocks as well as sets camera into power down mode by using pin ?pwdn? before bus enumeration. if sufficient power exists in the power budget, the remainder of the function will be powered on by setting register bit ?en_sys? (register 53h). in this case, pin ?en_system? has to be pulled down. if it?s pulled up, the camera system will be high power function right after power-on reset occurs. the snapshot function can be achieved by either setting register bit ?snap[2]? (register 52h) or pushing a bottom (pin ?snapb?) on the system. hardware snapshot function is initiated by setting register bit ?snap[0]? (register 52h). once pushing the bottom, the internal snapshot signal is latched, registers of the camera interface & camera itself are modified to desired formats as well. as soon as OV511 captures one single frame of image and sends to the host, the software driver clears the internal snapshot signal for next snapshot operation by writing a sequence 0-1-0 to register bit ?snap[1]? (register 52h). when usb bus idles for more than 3 msec, OV511 goes into suspend mode and all clocks are stopped by pin ?osc_en?, while all internal registers are remained the same values. the system wakes up when the usb resume condition occurs. suspend function can be disabled by pulling down pin ?en_suspend?, while pin ?osc_en? can be disabled by pulling up pin ?osc_bypass?. 27 mhz 48 mhz en_osc27 core logic m u x % 2 usb device controller OV511 camera www..net
12 2.2.7 usb device controller the camera system constructed by OV511 is defined as a ?high-power, bus-powered? usb device. it means that the camera system draws over one and a maximum of five unit loads from the usb cable. two endpoints are implemented for communication flows between the usb camera device and the usb host. endpoint 0 is an in-out type control endpoint which is the pipe of descriptors, configurations and vendor commands (internal registers). endpoint 1 is an in type isochronous endpoint which is the pipe of video streams. figure 12. usb communication flow the usb descriptors are configured as one configuration, one interface and eight alternates. the packet sizes of eight alternates are 992, 993, 768, 769, 512, 513, 257 & 0. there is no built-in usb transceiver in OV511. therefore, the usb transceiver is required on the camera system. the camera system is defined as a full speed device and needs to be terminated with the pull-up resistor on the d+ line. 2.2.8 i 2 c a built-in i 2 c bus master with two dedicated pins ?scl? & ?sda? controls cameras. pin ?sda? is an open drain i/o, while pin ?scl? is an output only. each pin requires a 4.7k pull-up resistor to 5v. the data rate of the i 2 c bus master is programmable and the maximum data rate is 100k. figure 13. a complete data transfer on i 2 c bus ovt software driver host buffers comm. flows interface pipes usb logic device endpoint 0 endpoint 1 sda scl s p a a a slave id rw sub add data www..net
13 figure 14. bit transfer on the i 2 c bus 2.2.9 pio pio is a parallel i/o port for accessing external sram based devices. it has a standard memory like interface that requires address, data and read/write control signals. these signals share the same buses with the y and uv video channels. when pio is enabled, y channel becomes the pio data bus for both input and output modes, and uv channel becomes address bus and read/write control signals. in this case, video data inputs will be interrupted. the pin assignment of pio control signals is as following, uv [5:0] share with addr [5:0], any arbitrary address can be defined by users as csb uv [6] shares with web uv [7] shares with oeb figure 15. pio read cycle timing waveforms figure 16. pio write cycle timing waveforms table 4. parameters of pio timing symbol parameter min max unit t oe output enable access time 15 ? ns sda scl data stable data change allowed oeb/uv[7] web/uv[6] addr[5:0]/uv[5:0] data[7:0]/y[7:0] addn add0 data0 datan t rc t csa t csx t aa t ax t oez t oe oeb/uv[7] web/uv[6] addr[5:0]/uv[5:0] data[7:0]/y[7:0] add0 addn datan data0 t wc t dh t ds t we t as t ah www..net
14 parameters of pio timing (continued) t oez output enable to z delay 15 ? ns t rc register read cycle time ? 100 ns t csa chip select access time 30 ? ns t csx chip select to data invalid time 15 ? ns t aa address access time 30 ? ns t ax address data invalid time 15 ? ns t wc register write cycle time ? 100 ns t we write enable pulse width ? 50 ns t as write cycle address set up time ? 0 ns t ah write cycle address hold time ? 0 ns t ds write cycle data set up time ? 20 ns t dh write cycle data hold time ? 0 ns 2.2.10 custom id custom id is a specific 8-bit input port which can be pulled up/down to identify company names of manufacturers. the custom id is checked by the software driver and may be requested directly from ovt. if no custom id is applied, pull-up/down resistors are also required to avoid bus floating. www..net
15 3 3 pin definition 3.1 pin assignments figure 17. 100-pin pqfp package 1 v d d 2 v s s 3 y 5 4 y 4 5 y 3 6 y 2 7 y 1 8 y 0 9 e n s y s t e m 1 0 e n s u s p e n d 1 1 s n a p b 1 2 e n o s c 2 7 1 3 c u s t o m i d 7 1 4 v d d 1 5 v s s 1 6 c u s t o m i d 6 1 7 c u s t o m i d 5 1 8 c u s t o m i d 4 1 9 c u s t o m i d 3 2 0 c u s t o m i d 2 2 1 c u s t o m i d 1 2 2 c u s t o m i d 0 2 3 c l k 2 7 m 1 2 4 c l k 2 7 m 2 2 5 r e s e t b 2 6 n c 2 7 o s c e n 2 8 o s c b y p a s s 2 9 c l k 4 8 m 1 3 0 c l k 4 8 m 2 31 txdmns 32 txdpls 33 dmns 34 dpls 35 xverdata 36 txenl 37 clk24k 38 casb 39 vdd 40 vss 41 oeb 42 addr8 43 addr7 44 addr6 45 vdd 46 vss 47 addr5 48 addr4 49 addr3 50 addr2 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 u v 7 n c n c n c v s s v d d d a t a 8 d a t a 9 d a t a 1 0 d a t a 1 1 d a t a 1 2 d a t a 1 3 r a s b w e b v d d v s s d a t a 7 d a t a 6 d a t a 5 d a t a 4 d a t a 3 d a t a 2 d a t a 1 d a t a 0 v d d v s s d a t a 1 5 d a t a 1 4 a d d r 1 a d d r 0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 y6 y7 pwdn reset sda fodd scl href vsync vss vdd pclk cclk uv0 uv1 uv2 uv3 uv4 uv5 uv6 ov 511 www..net
16 3.2 pin descriptions table 5. pin descriptions items/pin # name i/o function camera interface 99, 100, 3~8 y[7:0] i/o camera y data input pio data input/output 80~87 uv[7:0] i/o camera uv data input pio address, read/write control output 89 pclk i camera pixel clock input 93 href i camera horizontal window reference input 92 vsync i camera vertical sync. input 95 fodd i camera even/odd field flag input 88 cclk o camera clock output. software programmable 97 reset o camera hardware reset output 98 pwdn o camera power down output i 2 c interface 96 sda i/o i 2 c serial data. pull-up resistor (4.7k ohm) is required bi-directional with open-drain output 94 scl o i 2 c serial clock output. pull-up resistor (4.7k ohm) is required dram interface 67~74, 57~64 data[15:0] i/o dram 16-bit data 41 oeb o dram oe_ output 54 web o dram we_ output 42~44, 47~52 addr[8:0] o dram address output 38 casb o dram cas_ output 53 rasb o dram ras_ output usb interface 35 xver_data i usb differential receiver data input 33 dmns i d- input 34 dpls i d+ input 36 txenl o output enable for differential driver 31 txdmns o nrzi formatted d- output 32 txdpls o nrzi formatted d+ output clock & misc. 25 resetb i power-on reset input. low-active 29 clk_48m1 i 48mhz oscillator/crystal input 30 clk_48m2 o 48mhz crystal output 23 clk_27m1 i 27mhz oscillator/crystal input 24 clk_27m2 o 27mhz crystal output 27 osc_en o power control for oscillator. 1 for power enabled 28 osc_bypass i osc_en enabled/disabled input. 0 for enabled 11 snapb i snapshot bottom input. cleared by the software driver 9 en_system i hardware system initialization enabled/disabled. 0 for disabled 10 en_suspend i hardware suspend enabled/disabled. 1 for enabled 13, 16~22 custom_id[7:0] i custom id inputs 12 en_osc27 i 27mhz clock input select. 1 for enabled 37 clk_24k o 24khz clock output for switching power supply www..net
17 pin descriptions (continued) items/pin # name i/o function power & ground 1, 14, 39, 45, 55, 65 vdd i power 75, 90 2, 15, 40, 46, 56, 66 vss i ground 76, 91 others 26, 77, 78, 79 nc www..net
18 4 4 electrical characteristics table 6. dc electrical characteristics v dd = 5v + 5%, ta = 0 to 70 o c symbol parameter condition min max unit v ih high level input voltage 2.0 (ttl) ~ 4.0 (cmos schmitt trigger) v v il low level input voltage 0.8~1.0 v i ih high level input current v in = v dd -10 10 ua i il low level input current v in = v ss -10 10 ua v oh high level output voltage 2.4 v v ol low level output voltage 0.4 v i oz tri-state output leakage current v out = v ss or v dd -10 10 ua i dd quiescent supply current v in = v ss or v dd 100 ua table 7. absolute maximum ratings symbol parameter rating unit v d d dc supply voltage -0.3 to 7 v v in dc input voltage -0.3 to v dd + 0.3 v i in dc input current + 10 ma t stg storage temperature -40 to 125 o c table 8. recommended operating conditions symbol parameter rating unit v dd dc supply voltage 5v 4.75 to 5.25 v t a commercial temperature 0 to 70 o c www..net
19 5 5 register table (vendor commands) 5.1 camera interface table 9. camera interface register list register address register name r/w function default value 10h dlym[1:0] rw bit 1~0 : delay modes of video input signals 00 : no delay 01 : delays yuv by one pclk 10 : delays href by one pclk 11 : delays yuv and href by one pclk 00h 11h pem[0] rw bit 0 : edge modes of pclk 0 : pclk negative edge latches video data 1 : pclk positive edge latches video data 01h 12h pxcnt[6:0] rw bit 6~0 : clamped pixel number it defines the clamped pixel number of a horizontal line in increment of 8 pixels. if the pixel number from camera is larger than this number, the spare pixels will be dropped. clamped pixel no. = (pxcnt + 1) * 8 27h 13h lncnt[6:0] rw bit 6~0 : clamped line number it defines the clamped line number in increment of 8 lines. if the line number from camera is larger than this number, the spare lines will be dropped. clamped line no. = (lncnt + 1) * 8 1dh 14h pxdv[1:0] rw bit 1~0 : pixel divisor it defines down sampling frequency in the horizontal pixel direction. 00 : divided by 1 01 : divided by 2 10 : divided by 4 11 : divided by 8 01h 15h lndv[1:0] rw bit 1~0 : line divisor it defines down sampling frequency in the vertical line direction. uses these register bits along with register bit lstr to retain even or odd lines. 00 : divided by 1 01 : divided by 2 10 : divided by 4 11 : divided by 8 01h 16h m400[0] rw bit 0 : 8 bit (y channel only) / 16 bit (y & uv channels) data input select 0 : 8 bit data in y channel (uv channel is ignored) 1 : 16 bit data in both y & uv channels. uses this register bit along with register bit m420 to select 422/420 formats. 01h 17h lstr[0] rw bit 0 : reserved lines for downing sampling 0 : even lines (2, 4, 6, 8, ??) 1 : odd lines (1, 3, 5, 7, ??) 00h 18h m420[1] yfir[0] rw bit 1 : yuv422/420 0 : yuv 4:2:2 1 : yuv 4:2:0 bit 0 : y channel low pass filter 0 : disabled 1 : enabled 00h snapshot operation ? a full set of camera interface registers are duplicated for hardware snapshot operation. these registers replace the normal ones for taking snapshot frame so that the snapshot frame can be different settings from normal frame. the followings are the snapshot registers. www..net
20 camera interface register list (continued) register address register name r/w function default value 19h spdly[7:0] rw bit 7~0 : captured frame for snapshot it defines which frame (one frame only) after snapshot function is triggered will be captured. 00000000 : the first frame 10000001 ~ 11111111 : the 2 nd ~ 128 th frame 00h 1ah snpx[6:0] rw bit 6~0 : clamped pixel number for snapshot 4fh 1bh snln[6:0] rw bit 6~0 : clamped line number for snapshot 1dh 1ch snpd[1:0] rw bit 1~0 : pixel divisor for snapshot 00h 1dh snld[1:0] rw bit 1~0 : line divisor for snapshot 01h 1eh sn400[0] rw bit 0 : 8/16 bit data input for snapshot 01h 1fh snalstr[2] sn420[1] snyfir[0] rw bit 2 : reserved lines for down sampling when snapshot occurs bit 1 : yuv422/420 for snapshot bit 0 : y channel low pass filter for snapshot 04h 5.2 dram interface table 10. dram interface register list register address register name r/w function default value 20h enfc[0] rw bit 0 : image flow control 0 : disabled, doesn?t guarantee a complete image frame 1 : enabled, guarantees a complete image frame 01h 21h arcp[0] rw bit 0 : auto read cycle predictor it predicts the number of read cycles which will be inserted besides write cycles. 0 : disabled, use register bit mrc for manual setting 1 : enabled 01h 22h mrc[3:0] rw bit 3~0 : manual read cycle insertion it defines the number of read cycles which will be inserted besides write cycles. read cycles = mrc + 1 01h 23h rfc[5:0] rw bit 5~0 : refresh counter 1ah 5.3 iso fifo table 11. iso fifo register list register address register name r/w function default value 30h pksz[4:0] rw bit 4~0 : packet size it defines the packet size of iso fifo which is available from 00001 (32 bytes) to 11111 (992 bytes). the packet size must match with the current alternate setting. packet size = (32 * pksz) bytes 08h 31h nzpk[3] enpkno[1] ence[0] rw bit 3 : zero packet inserted after eof (image end of frame flag) 0 : disabled 1 : enabled bit 1 : packet no. insertion it inserts one extra byte at the end of each packet as the packet number. it counts in sequence, but only the packet containing sof (image start of frame flag) uses ?00?. 0 : disabled 1 : enabled bit 0 : compressed data non-zero (01) insertion it inserts ?01? at the 7 th byte of the packet if the 1 st ~8 th incoming compressed data are all ?00?. 0 : enabled 1 : disabled 03h www..net
21 5.4 pio table 12. pio register list register address register name r/w function default value 38h enpio[7] piorw[6] padd[5:0] w bit 7 : parallel io operation 0 : disabled 1 : enabled. uv channel changes to output mode for parallel io operation. register bits padd[5:0] output to pin uv[5:0]. uv[6] performs as oeb, while uv[7] performs as web. y channel is bi-directional. the direction depends on read/write operation of pio. the bus cycle is executed once only after usb host write to this register and enpio = 1. write data has to be placed in register bits pdata[7:0] before launching the pio write cycle. read data is returned in register bits pdata[7:0] after launching the pio read cycle. bit 6 : read/write cycle for pio operation 0 : read cycle 1 : write cycle bit 5~0 : address port of pio operation 00h 39h pdata[7:0] r/w bit 7~0 : data port of pio operation 00h 3eh entp[3] tps[2:0] w bit 3 : bist operation for OV511 0 : disabled 1 : enabled bit 2~0 : bist functions select 00h pio r/w sequence examples write cycles 1. writes to data port (pdata, register 39h) 2. enables pio (enpio, register 38h), sets up address (padd, register 38h), & selects write cycle (piorw, register 38h) 3. disables pio (enpio, register 38h) read cycles 1. enables pio (enpio, register 38h), sets up address (padd, register 38h), & selects read cycle (piorw, register 38h) 2. reads from data port (pdata, register 39h) 5.5 i 2 c table 13. i 2 c register list register address register name r/w function default value 40h tmout[2] noack[1] idle[0] r bit 2 : time out flag for i 2 c operation. sets when timer reaches the value set by register bits tmo[4:0]. bit 1 : no acknowledge on i 2 c bus. it?s valid when register bit idle is set. bit 0 : i 2 c bus idle flag 00h 40h enabort[4] type[2:1] starti2c[0] w bit 4 : aborts i 2 c bus cycle if i 2 c slave doesn?t response (no acknowledge) bit 2~1 : types of i 2 c read/write sequence 00 : 3 byte write cycle, in sequence of slave id (sid), sub address (swa) & i 2 c data (sda) 01 : 2 byte write cycle, in sequence of slave id (sid) & sub address (sma) 1x : 2 byte read cycle, in sequence of slave id (sra) & i 2 c data (sda) bit 0 : launches a new i 2 c bus cycle if set i 2 c won?t launch a new cycle if it doesn?t finish the previous bus cycle. 00h 41h sid[7:0] rw bit 7~0 : i 2 c slave id for 3 or 2 byte write cycles 00h www..net
22 i 2 c register list (continued) register address register name r/w function default value 42h swa[7:0] rw bit 7~0 : sub address for 3 byte write cycles 00h 43h sma[7:0] rw bit 7~0 : sub address for 2 byte write cycles 00h 44h sra[7:0] rw bit 7~0 : slave id for 2 byte read cycles 00h 45h sda[7:0] rw bit 7~0 : i 2 c read/write data port 00h 46h psc[7:0] rw bit 7~0 : i 2 c clock prescaler it defines prescaler values for i 2 c clock. i 2 c bit rate = 93.5 khz / ( psc + 1) 00h 47h tmo[4:0] rw bit 4~0 : time out counter a timer starts to count i 2 c clocks when i 2 c bus cycle is launched. when the timer reaches tmo, tmout is set. 00h snapshot operation - during the period of hardware snapshot operation, OV511 first launches a 3 byte i 2 c write cycle to i 2 c slave device, such as camera, by using register 48h and 49h. it permits i 2 c slave device to modify the internal settings before taking the snapshot. i 2 c register list (continued) register address register name r/w function default value 48h spa[7:0] w bit 7~0 : sub address of the i 2 c write cycle for snapshot operation 00h 49h spd[7:0] w bit 7~0 : data port of the i 2 c write cycle for snapshot operation 00h i 2 c r / w sequence examples setup stage 1. writes to slave id (sid, register 41h) 3 byte write cycles 1. writes to sub address (swa, register 42h) 2. writes to data port (sda, register 45h) 3. writes to control bits to select write cycle and launch i 2 c cycles (type, starti2c, register 40h) 2 byte dummy write cycles (in order to set sub address of i 2 c slave device for the next coming read cycle) 1. writes to sub address (sma, register 43h) 2. writes to control bits to select write cycle and launch i 2 c cycles (type, starti2c, register 40h) 2 byte read cycles 1. writes to sub address (sra, register 44h) 2. writes to control bits to select read cycle and launch i 2 c cycles (type, starti2c, register 40h) 3. reads from status bits (tmout, noack, idle, register 40h) 4. reads from data port (sda, register 45h) www..net
23 5.6 system control table 14. system control register list register address register name r/w function default value 50h rst[6:0] rw bit 0 : software reset for udc bit 1 : software reset for i 2 c bit 2 : software reset for iso fifo bit 3 : software reset for omnice bit 4 : software reset for dram interface bit 5 : software reset for camera interface bit 6 : software reset for OV511 & registers 00h 51h clkdiv[4:0] rw bit 4~0 : camera clock divisor it defines the frequency of camera clock output cclk. cclk is divided down based on external clock inputs clk_48 or clk_27. the maximum frequency of clk_27 that OV511 can handle is 27mhz. if both clk_27 and clk_48 clock inputs are enabled by pulling up pin ?en_osc27?, clk_27 is chosen in support of camera clock. 00000 : no division (clk_27) 11111 : clk_27 divided by 32 if only clk_48 clock input is enabled by pulling down pin ?en_osc27?, clk_48 is divided by 2 and provides camera clock. 00h 52h snap[2:0] rw bit 0 : hardware snapshot 0 : disabled 1 : enabled bit 1 : releases hardware snapshot bottom in sequence of 0,1,0 bit 2 : software snapshot 0 : disabled 1 : enabled 01h 53h en_sys[0] rw bit 0 : software system initialization before system is initialized, system clocks will be stopped to meet the requirement of power consumption for the whole system to be less than 100ma. after that, it can increase to max. 500ma for usb bus powered device. if pin ?en_system? is pulled down, this bit controls system initialization. otherwise, system is initialized right after power-on reset. 0 : system is not initialized 1 : system is initialized 00h 5eh usr[7:0] rw bit 7~0 : user defined read/write register bits 00h 5fh cid[7:0] r bit 7~0 : custom id which links to input pins ?custom_id? it is checked by the software driver to identify company names. it may be requested directly from ovt. the registered custom id can be coded by pulling up or down resistors through pins ?custom id?. if no custom id is applied, pull-up/down resistors are also requested to avoid floating. ~ 5.7 omnice table 15. omnice register list register address register name r/w function default value 70h prh_y[5:0] rw bit 5~0 : predication range in horizontal direction for y channel one horizontal line is divided into horizontal segments for prediction. it defines the number of pixels contained in one horizontal segment of y channel. pixels in the segment except the first one are predicted by the first pixel of this segment. 1fh 71h prh_uv[5:0] rw bit 5~0 : prediction range in horizontal direction for uv channel 05h www..net
24 omnice register list (continued) 72h prv_y[7:0] rw bit 7~0 : predication range in vertical direction for y channel one image frame is divided into vertical segments for prediction. it defines the number of pixels contained in one vertical segment of y channel. pixels in the segment except the first one are predicted by the first pixel of this segment. 06h 73h prv_uv[7:0] rw bit 7~0 : predication range in vertical direction for uv channel 06h 74h qth_y[7:0] rw bit 7~0 : quantization threshold in horizontal direction for y channel 14h 75h qth_uv[7:0] rw bit 7~0 : quantization threshold in horizontal direction for uv channel 03h 76h qtv_y[7:0] rw bit 7~0 : quantization threshold in vertical direction for y channel 04h 77h qtv_uv[7:0] rw bit 7~0 : quantization threshold in vertical direction for uv channel 04h 78h uv_en[2] y_en[1] ce_en[0] rw bit 0 : omnice 0 : disabled 1: enabled bit 1 : y channel operation 0 : disabled 1 : enabled bit 2 : uv channel operation 0 : disabled 1 : enabled 06h 79h lten_uv[1] lten_y[0] rw bit 0 :look-up table for y channel 0 : disabled 1 : enabled bit 1 : look-up table for uv channel 0 : disabled 1 : enabled 00h 80~9fh lt_y rw bit 7~0 : programmable look-up table for y channel ~ a0~bfh lt_uv rw bit 7~0 : programmable look-up table for uv channel ~ www..net
25 6 6 usb descriptors the usb descriptor is a data structure with defined attributes that can respond requests from the usb host. the descriptors of OV511 are hardwire coded inside the chip, and no external eprom is required. 6.1 device the device descriptor describes general information about OV511. there is one device descriptor. table 16. device descriptor list offset field size value (hex) description 0 blength 1 12 size of descriptor in bytes 1 bdescriptortype 1 01 device descriptor type 2 bcdusb 2 0100 usb spec release no. 4 bdeviceclass 1 00 class code 5 bdevicesubclass 1 00 subclass code 6 bdeviceprotocol 1 00 protocol code 7 bmaxpacketsize0 1 08 max. packet size for enpt0 8 idvendor 2 05a9 vendor id 10 idproduct 2 0511 product id 12 bcddevice 2 0100 device release no. 14 imanufacturer 1 00 index of string descriptor describing manufacturer 15 iproduct 1 00 index of string descriptor describing product 16 iserialnumber 1 00 index of string descriptor describing the device's serial no. 17 bnumconfigurations 1 01 number of possible configurations 6.2 configuration the configuration descriptor describes information about a specific device configuration. there is one configuration descriptor. table 17. configuration descriptor list offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 02 configuration 2 wtotallength 2 0089 total length of data returned for this configuration 4 bnuminterfaces 1 01 no. of interfaces supported by this config. 5 bconfigurationvalue 1 01 value to use to set config. to select this config. 6 iconfiguration 1 00 index of string descriptor describing this config. 7 bmattributes 1 80 config. char. bus powered, no remote wakeup 8 maxpower 1 fa max. power consumption, 500 ma 6.3 interface & endpoint the interface descriptor describes a specific interface provided by the associated configuration. there are eight interface descriptors. each one selects one alternate setting and is followed by the corresponding endpoint descriptor. the endpoint descriptor describes the information required by the host to determine the bandwidth requirements of each endpoint. there is no endpoint descriptor for endpoint zero. www..net
26 6.3.1 alternate 0 table 18. interface descriptor list of alternate 0 offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 04 interface 2 binterfacenumber 1 00 no. of interface 3 balternatesetting 1 00 value used to select alternate setting 4 bnumendpoints 1 01 no. of endpoints used by this interface 5 binterfaceclass 1 ff class code 6 binterfacesubclass 1 00 subclass code 7 binterfaceprotocol 1 00 protocol code 8 iinterface 1 00 index of string descriptor describing this interface table 19. endpoint descriptor list of alternate 0, packet size 992 offset field size value (hex) description 0 blength 1 07 size of descriptor in bytes 1 bdescriptortype 1 05 endpoint 2 bendpointaddress 1 81 bit7 1 in enpt, bit 6..4 000, bit 3..0 0001 enpt no. 3 bmattributes 1 01 bit1..0 01 iso 4 wmaxpacketsize 2 03e0 max. packet size 992 6 binterval 1 01 interval for polling enpt for data transfer 6.3.2 alternate 1 table 20. interface descriptor list of alternate 1 offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 04 interface 2 binterfacenumber 1 00 no. of interface 3 balternatesetting 1 01 value used to select alternate setting 4 bnumendpoints 1 01 no. of endpoints used by this interface 5 binterfaceclass 1 ff class code 6 binterfacesubclass 1 00 subclass code 7 binterfaceprotocol 1 00 protocol code 8 iinterface 1 00 index of string descriptor describing this interface table 21. endpoint descriptor list of alternate 1, packet size 993 offset field size value (hex) description 0 blength 1 07 size of descriptor in bytes 1 bdescriptortype 1 05 endpoint 2 bendpointaddress 1 81 bit7 1 in enpt, bit 6..4 000, bit 3..0 0001 enpt no. 3 bmattributes 1 01 bit1..0 01 iso 4 wmaxpacketsize 2 03e1 max. packet size 993 6 binterval 1 01 interval for polling enpt for data transfer 6.3.3 alternate 2 table 22. interface descriptor list of alternate 2 offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 04 interface 2 binterfacenumber 1 00 no. of interface 3 balternatesetting 1 02 value used to select alternate setting 4 bnumendpoints 1 01 no. of endpoints used by this interface 5 binterfaceclass 1 ff class code 6 binterfacesubclass 1 00 subclass code www..net
27 interface descriptor list of alternate 2 (continued) 7 binterfaceprotocol 1 00 protocol code 8 iinterface 1 00 index of string descriptor describing this interface table 23. endpoint descriptor list of alternate 2, packet size 768 offset field size value (hex) description 0 blength 1 07 size of descriptor in bytes 1 bdescriptortype 1 05 endpoint 2 bendpointaddress 1 81 bit7 1 in enpt, bit 6..4 000, bit 3..0 0001 enpt no. 3 bmattributes 1 01 bit1..0 01 iso 4 wmaxpacketsize 2 0300 max. packet size 768 6 binterval 1 01 interval for polling enpt for data transfer 6.3.4 alternate 3 table 24. interface descriptor list of alternate 3 offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 04 interface 2 binterfacenumber 1 00 no. of interface 3 balternatesetting 1 03 value used to select alternate setting 4 bnumendpoints 1 01 no. of endpoints used by this interface 5 binterfaceclass 1 ff class code 6 binterfacesubclass 1 00 subclass code 7 binterfaceprotocol 1 00 protocol code 8 iinterface 1 00 index of string descriptor describing this interface table 25. endpoint descriptor list of alternate 3, packet size 769 offset field size value (hex) description 0 blength 1 07 size of descriptor in bytes 1 bdescriptortype 1 05 endpoint 2 bendpointaddress 1 81 bit7 1 in enpt, bit 6..4 000, bit 3..0 0001 enpt no. 3 bmattributes 1 01 bit1..0 01 iso 4 wmaxpacketsize 2 0301 max. packet size 769 6 binterval 1 01 interval for polling enpt for data transfer 6.3.5 alternate 4 table 26. interface descriptor list of alternate 4 offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 04 interface 2 binterfacenumber 1 00 no. of interface 3 balternatesetting 1 04 value used to select alternate setting 4 bnumendpoints 1 01 no. of endpoints used by this interface 5 binterfaceclass 1 ff class code 6 binterfacesubclass 1 00 subclass code 7 binterfaceprotocol 1 00 protocol code 8 iinterface 1 00 index of string descriptor describing this interface table 27. endpoint descriptor list of alternate 4, packet size 512 offset field size value (hex) description 0 blength 1 07 size of descriptor in bytes 1 bdescriptortype 1 05 endpoint 2 bendpointaddress 1 81 bit7 1 in enpt, bit 6..4 000, bit 3..0 0001 enpt no. 3 bmattributes 1 01 bit1..0 01 iso 4 wmaxpacketsize 2 0200 max. packet size 512 www..net
28 endpoint descriptor list of alternate 4, packet size 512 (continued) 6 binterval 1 01 interval for polling enpt for data transfer 6.3.6 alternate 5 table 28. interface descriptor list of alternate 5 offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 04 interface 2 binterfacenumber 1 00 no. of interface 3 balternatesetting 1 05 value used to select alternate setting 4 bnumendpoints 1 01 no. of endpoints used by this interface 5 binterfaceclass 1 ff class code 6 binterfacesubclass 1 00 subclass code 7 binterfaceprotocol 1 00 protocol code 8 iinterface 1 00 index of string descriptor describing this interface table 29. endpoint descriptor list of alternate 5, packet size 513 offset field size value (hex) description 0 blength 1 07 size of descriptor in bytes 1 bdescriptortype 1 05 endpoint 2 bendpointaddress 1 81 bit7 1 in enpt, bit 6..4 000, bit 3..0 0001 enpt no. 3 bmattributes 1 01 bit1..0 01 iso 4 wmaxpacketsize 2 0201 max. packet size 513 6 binterval 1 01 interval for polling enpt for data transfer 6.3.7 alternate 6 table 30. interface descriptor list of alternate 6 offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 04 interface 2 binterfacenumber 1 00 no. of interface 3 balternatesetting 1 06 value used to select alternate setting 4 bnumendpoints 1 01 no. of endpoints used by this interface 5 binterfaceclass 1 ff class code 6 binterfacesubclass 1 00 subclass code 7 binterfaceprotocol 1 00 protocol code 8 iinterface 1 00 index of string descriptor describing this interface table 31. endpoint descriptor list of alternate 6, packet size 257 offset field size value (hex) description 0 blength 1 07 size of descriptor in bytes 1 bdescriptortype 1 05 endpoint 2 bendpointaddress 1 81 bit7 1 in enpt, bit 6..4 000, bit 3..0 0001 enpt no. 3 bmattributes 1 01 bit1..0 01 iso 4 wmaxpacketsize 2 0101 max. packet size 257 6 binterval 1 01 interval for polling enpt for data transfer 6.3.8 alternate 7 table 32. interface descriptor list of alternate 7 offset field size value (hex) description 0 blength 1 09 size of descriptor in bytes 1 bdescriptortype 1 04 interface www..net
29 interface descriptor list of alternate 7 (continued) 2 binterfacenumber 1 00 no. of interface 3 balternatesetting 1 07 value used to select alternate setting 4 bnumendpoints 1 01 no. of endpoints used by this interface 5 binterfaceclass 1 ff class code 6 binterfacesubclass 1 00 subclass code 7 binterfaceprotocol 1 00 protocol code 8 iinterface 1 00 index of string descriptor describing this interface table 33. endpoint descriptor list of alternate 7, packet size 0 offset field size value (hex) description 0 blength 1 07 size of descriptor in bytes 1 bdescriptortype 1 05 endpoint 2 bendpointaddress 1 81 bit7 1 in enpt, bit 6..4 000, bit 3..0 0001 enpt no. 3 bmattributes 1 01 bit1..0 01 iso 4 wmaxpacketsize 2 0000 max. packet size 0 6 binterval 1 01 interval for polling enpt for data transfer www..net
30 7 7 software package the followings are software drivers that are or will be supported by ovt. stream class minidriver - a wdm (microsoft win32 driver model) stream class driver that supports the ovt usb camera system in the microsoft windows 98 and windows nt 5.0. this driver is the bottom level of the software system, and it completes all actual control actions. video for windows compatible driver - the vfw is the standard interface of microsoft for video capture drivers. package contains a vfw-to-wdm mapper extension dll. it adds some pages in video source property control dialog. this driver allows user control every custom property. twain source control driver - this driver is compatible with microsoft still image architecture in windows 98. it allows standard still image oriented application which use the twain api to use the ovt usb camera system. directshow filter - this software component allows users to control every custom property in directshow graph. installation software - the installation software is responsible for setting up all camera software components. www..net
31 8 8 mechanical information dimensions in milimeters 0.80 + 0.20 0.10max 0.05min 2.65 + 0.10 3.00max 0.80 + 0.20 0~8 o 0.15 +0.10 -0.05 20.00 + 0.20 23.90 + 0.30 14.00 + 0.20 17.90 + 0.30 #1 #100 0.65 0.30 +0.10 -0.05 0.58 0.83 0.15max www..net
32 9 9 evb (evaluation board) design reference 9.1 evb schematic diagram 9.1.1 page 1, OV511 www..net
33 9.1.2 page 2, power and control www..net
34 9.1.3 page 3, camera module www..net
35 9.1.4 page 4, custom id www..net
36 9.2 board description 9.2.1 power planes the usb power through the usb cable is quite noisy such that it may seriously influence the performance of cameras. therefore, the power planes of the usb camera system needs to be separated very carefully. the power planes of the usb camera system can roughly partitioned as three portions, the power plane of the usb connector, OV511 & dram (5v) the power plane of the usb transceiver (3.3v) the power plane of the camera (4.7/5v) figure 18. power planes of the usb camera system figure 19. the power circuit of the usb connector, OV511, dram & the usb transceiver 9.2.1.1 the power plane of the usb connector, OV511 & dram (5v) 5v/vcc 5v, usb bus power from the usb connector. supplies OV511 & dram. x_v 5v, intermediate power between usb bus power and 3.3v. use a lc filter to reduce coupling of usb transition noise. not connected to any active component. 9.2.1.2 the power plane of the usb transceiver (3.3v) 3.3v 3.3v, usb transceiver power. voltage drops from 5v to 3.3v simply by using a led or it may also be generated by a 3.3v power regulator to get cleaner power. 3.3v 5v x_v vcc l1 inductor-.47u u8 led c15 .1u-1206 c14 47u c16 .1u-1206 c17 47u usb connector OV511 dram usb cable usb transceiver camera www..net
37 figure 20. the power circuit of the camera 9.2.1.3 the power plane of the camera (4.7/5v) c_vdd 4.7v/5v, camera power. two options, 1. may use a low dropout voltage regulator, such as toko tk11247 or tk11447, to supply 4.75v or 4.7v to the camera. 2. may use only an inductor to bypass usb bus power if there is any noise reduction circuit for power supply on the camera board. the power plane of the camera has to be as clean as possible. figure 21. the power circuit of oscillators (option) 9.2.1.4 the power plane of oscillators (option) if crystals are installed on the usb camera system, oscillators are not required. vdd 5v, oscillator power controlled by pin ?oscen?. if pin ?oscbp? is pulled down, vdd will be shut down by the power circuit (r11, q2, r10, q1 or simply connected to oe pin of some kinds of oscillator) when suspend occurs. if pin ?oscbp? is pulled up, vdd will never be shut down. 9.2.2 clocks 27mhz input provides clock for camera & camera interface, while 48mhz input provides clock for usb interface. if pin ?enosc27? is pulled up, both 27mhz & 48 mhz inputs are selected. if it is pulled down, only 48 mhz input is selected. in this case, 48 mhz input is divided by 2 to provide 24mhz clock for camera & camera interface. 5v c_vdd 5v c18 .1u-1206 l2 inductor-4.7u c20 10u c19 10u c21 .1u-1206 u9 tk11247ct-nd control 1 gnd 2 bypass 3 vout 4 gnd 5 vin 6 5v 5v vdd oscen vdd clk48m1 clk27m1 r10 4.7k-0603 r11 3.3k-0603 c10 .1u-1206 q2 npn q1 pnp c12 .1u-1206 u6 48mhz-osc vdd 4 oe 1 out 3 gnd 2 u7 27mhz-osc vdd 4 oe 1 out 3 gnd 2 oscen clk27m1 clk48m1 www..net
38 both 27mhz & 48mhz inputs may be allowed to use either crystals or oscillators. oscillator outputs connect to pin 1 of clock buffer (clk27m1 or clk48m1). 9.2.3 dram only 5v edo 256kx16 60ns (or faster) dram is allowed. 9.2.4 options custom id the 8-bit custom id is checked by the software to identify company names. it may be requested directly from ovt. the registered custom id can be coded by pulling up or down resistors. if no custom id is applied, pull-up/down resistors are also requested to avoid floating. enosc27 27mhz clock input select pull-up, both 27mhz & 48 mhz inputs are selected (recommended) pull-down, only 48 mhz input is selected ensuspend hardware suspend enabled/disabled pull-up enable suspend fu nction (recommended) pull-down, disable suspend function ensystem hardware system initialization enabled/disabled pull-up system initialized by hardware pull-down system initialized by software (recommended) oscbp oscen enabled/disabled pull-up enabled pull-down disabled (recommended) figure 22. circuits of damping resistors & shell grounding 3.3v 3.3v vcc * gnd connects to shelll txdpls txdmns r8 1.5k-0603 r4 22-0603 r6 22-0603 r1 22-0603 r2 22-0603 r5 1.5k-0603 u3 pdiusbp11 nc 1 oe# 2 rcv 3 vp 4 vm 5 suspnd 6 gnd 7 vcc 14 nc 8 speed 9 d- 10 d+ 11 vpo 12 vmo 13 r7 22-0603 r3 22-0603 u4 usb_connector vcc 1 dm 2 dp 3 vss 4 txenl dmns xdata dpls www..net
39 damping resistors & shell grounding there are 6 signals connected to the usb transceiver, txenl, xdata, dpls, dmns, txdpls & txdmns. damping resistors may be connected between OV511 & usb transceiver to reduce over-shot & under-shot. shell grounding is necessary for the usb connector. switching power supply clk24k is a 24khz clock output reserved for switching power supply. it is an option to reduce noise of usb transition on the power plane. figure 23. circuits of reset & snapshot bottoms reset bottom pull-up resistor & pull-down capacitor provide rc constant during initialization of the whole system. push reset bottom will reset OV511 as well as the camera. snapshot bottom push snap bottom will trigger hardware snapshot function and capture one single frame of image. 5v resetb r9 10k-0603 c11 .22u-1206 jp2 header 2 1 2 resetb 5v snapb jp3 header 2 1 2 r12 10k-0603 c13 .1u-1206 snapb www..net
40 9.3 pcb layout 9.3.1 placement top view usb connector OV511 usb transceiver n bottom view dram camera connector oscillator 48mhz oscillator 27mhz camera regulator crystal 48mhz crystal 27mhz transistors 9.3.2 grounding camera ground and OV511 & dram ground are separated and both connected to usb ground. shell grounding is necessary for the usb connector. www..net
41 n grounding camera ground usb ground OV511 & dram ground www..net

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