rhea p roduct b rief never stop thinking. mate interface xgmii 10 gigabit interface 4, 8-bit channels at 312.5 mhz (10.0 gbit/s total capacity) automatic pass-through/wrap/ transparent mode communication requires only 1 standard serdes for inter-board communication loss of sync detection with performance counters crc detection microprocessor interface 16-bit, asynchronous interface, up to 100 mhz multiple interrupt reporting send and receive buffers for ips and topology packets electrical/mechanical/thermal 1.5/1.8/3.3 v power supplies 899-pin hyper bga flip chip package -40 c to 85 c operation ~5.18 w other jtag compliant 100 mhz or 200 mhz reference clock hard and soft reset crc generation and checking extensive loopback features for testing key features high speed srp mac up to oc-192 (10 gbit/s) throughput supports srp, pos, native ethernet 1 mb low-priority transit buffer 32 kb high-priority transit buffer giant, runt and short packet filters supports ips and topology discovery 899-pin hyper bga package specifications modes of operation dual ring mode wrap mode pass-through mode transparent mode passive and active sniffer modes operational speeds oc-192 oc-48 packet formats srp pseudo-srp pos (in transparent mode) native ethernet rx/tx framer host interface 64-bits hstl @200 mhz oif spi-4 phase 1 compliant interface giant, runt and short packet filtering with pm counters data and control parity bit checking with pm counters traffic flow monitoring host-side leaky bucket rate limiters - high/low priority data parity fault insertion for system and software test counters for high/low priority unicast/multicast packets and bytes lookup / statistics cam functions 1024 double (source, destination or both) address entries 1024 double address counters cam s/w features: read/write/ probe/reset individual entries 8 coarse multicast address filters accept or reject on match multicast accept/reject capability for individual addresses transit buffer internal source and sink for usage packets internal 1 mb low and 32 kb high priority buffers counters for high/low priority unicast/multicast packets and bytes counters for min, max and average delay in transit buffers rhea resilient ring processor oc-48 / oc-192 srp mac semiconductor solutions for high speed communications and fiber optic applications the in?neon resilient ring processor is a packet opti- mized transport engine designed to enable the ?rst g eneration of resilient packet rings (rpr) for metro- politan area networks. its feature-rich design supports sp atial reuse protocol (srp) at speeds up to 10 gbit/s. it incorporates packet support for both pos and native e thernet with the ?exibility to transport across sonet, d wdm or dark ?ber. the in?neon resilient ring proces- sor is uniquely positioned to enable cost-effective resil- iency and qos for growing, high-speed ip networks.
p roduct b rief how to reach us: http://www.infineon.com infineon technologies na corp. 1730 north first street san jose, ca 95112 usa published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen ? infineon technologies ag 2002. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, de- scriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide. warnings due to technical requirements components may contain danger- ous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life- support devices or systems with the express written approval of infineon technologies, if a failure of such components can rea- sonably be expected to cause the failure of that life-support de- vice or system, or to affect the safety or effectiveness of that de- vice or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reason- able to assume that the health of the user or other persons may be endangered. pu bl i shed by in?neon technologies ag or dering no. b168-h8052 -x-x-7600 printed in germany ps 05022. r&l oc-192 line card oc-192 line card serdes serdes outer rx inner tx outer tx inner rx oc-x line card oc-y line card w est east framer inner forw ard outer forw ard add or r emove tr affic add or r emove tr affic framer 64 64 64 64 64 64 64 64 40 40 40 40 4x2 4x2 oc-192 srp mac l3 engine oc-192 srp mac l3 engine block diagram
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