12-147 HV7022-c 34-channel symmetric row driver device 44 j-lead quad 44 j-lead quad die in 44 j-lead quad ceramic chip carrier plastic chip carrier waffle pack ceramic chip carrier (mil-std-883 processed*) HV7022-c HV7022dj-c HV7022pj-c HV7022x-c rbHV7022dj-c *for hi-rel process flows, refer to page 5-3 of the databook. ordering information features n n processed with hvcmos ? technology n n symmetric row drive (reduces latent imaging in actfel displays) n n output voltages up to 230v n n low-power level shifting n n source/sink current 70ma (min.) n n shift register speed 4mhz n n pin-programmable shift direction n n 44-lead plastic & ceramic surface-mount packages n n hi-rel processing available general description the HV7022-c is a low-voltage serial to high-voltage parallel converter with push-pull outputs. it is especially suited for use as a symmetric row driver in ac thin-film electroluminescent (actfel) displays. the hv70 offers 34 output lines, a direction (dir) pin to give cw or ccw shift register loading, output enable (oe), and polarity (pol) control. after data input is entered (on the falling edge of clock), a logic high will cause the output to swing to v pp if pol is high, or to gnd if pol is low. absolute maximum ratings supply voltage, v dd 1 -0.3v to +15v supply voltage, v pp 1 -0.3v to +250v logic input levels 1 -0.3v to v dd +0.3v ground current 2 1.5a continuous total power dissipation 3 : plastic 1200mw ceramic 1500mw operating temperature range plastic -40 c to +85 c ceramic -55 c to 125 c storage temperature range -65 c to +150 c lead temperature 1.6mm (1/16 inch) 260 c from case for 10 seconds notes: 1. all voltages are referenced to gnd. 2. duty cycle is limited by the total power dissipated in the package. 3. for operation above 25 c ambient derate linearly to maximum operating temperature at 25mw/ c for plastic and at 15mw/ c for ceramic. package options for detailed circuit and application information, please refer to application note an-h3.
12-148 electrical characteristics (over recommended operating conditions of v dd = 12v, t a = 25 c and v pp = 230v unless otherwise noted) symbol parameter min max units conditions i dd v dd supply current 10 ma f clk = 4mhz i pp high voltage supply current 4 ma 1 output high 1 100 m a all outputs low or high-z 750 m a all outputs low or high-z (125 c) i ddq quiescent v dd supply current 100 m a all v in = gnd or v dd v oh high-level output hv out 195 v i o = -70ma (-50ma) 2 data out 11 v i o = -500 m a v ol low-level output hv out 30 v i o = 70ma (+50ma) 2 data out 1 v i o = 500 m a i ih high-level logic input current 1 m av ih = 12v i il low-level logic input current -1 m av il = 0v notes: 1. the total number of on outputs times the duty cycle must not exceed the allowable package power disspation. 2. over military temperature range (-55 c to 125 c). dc characteristics symbol parameter min max units conditions f clk clock frequency 4 mhz t w pulse duration clock high or low 125 ns t sud data set-up time before falling clock 100 ns t hd data hold time after falling clock 100 ns t suc setup time clock low before v pp - or gnd 300 ns t sue setup time enable high before v pp - or gnd 300 ns t sup setup time polarity high or low before v pp - or gnd 300 ns t hc hold time clock high after v pp - or gnd 500 ns t he hold time enable high after v pp - or gnd 300 ns t hp hold time polarity high or low after v pp - or gnd 300 ns t dhl delay time high to low level output from clock 150 ns c l = 10pf t dlh delay time low to high level output from clock 200 ns c l = 10pf t thl transition time high to low level serial output 200 ns c l = 15pf t tlh transition time low to high level serial output 100 ns c l = 15pf t onh high level turn-on time q outputs from enable 500 ns i o = -50 ma,v oh =195v r l = 2 k w to 95v t onl low level turn-on time q outputs from enable 500 ns i o = 50 ma,v oh =130v r l = 2 k w to 30v t offh high level turn-off time q outputs from enable 1000 ns i o = -50 ma,v oh =195v r l = 2 k w to 95v t offl low level turn-off time q outputs from enable 500 ns i o = 50 ma,v oh =130v r l = 2 k w to 30v slew rate, v pp or gnd 45 v/ m s with one active output driving a 4.7 nf load to v pp or gnd ac characteristics (v dd = 12v, t c = 25 c) HV7022-c
12-149 HV7022-c v dd input gnd v pp gnd hv out logic inputs gnd data out logic data output high voltage outputs v dd recommended operating conditions input and output equivalent circuits symbol parameter min max units v dd logic supply voltage 10.8 13.2 v v pp high voltage supply 230 v v ih high-level input voltage v dd = 10.8v 8.1 v v dd = 13.2v 9.9 v il low-level input voltage v dd = 10.8v 2.7 v v dd = 13.2v 3.3 f clk clock frequency 4 mhz t a operating free-air temperature plastic -40 +85 c ceramic -55 +125 c i od allowable pulse current through output diodes 300 ma note: power-up sequence should be the following: 1. connect ground. 2. apply v dd . 3. set all inputs (data, clk, enable, etc.) to a known state. 4. apply v pp . power-down sequence should be the reverse of the above.
12-150 HV7022-c 50% 50% data output (d ioa /d iob ) clock 50% 50% 50% t sud t hd v ih t wl t wh l/f clk t tlh 90% 10% t thl 90% 10% t dlh t dhl data input v ih v il v oh v ol t suc 10% 90% t hc v pp gnd 50% 50% v ih v il 90% pol gnd 10% t sup t hp 50% 50% t sue t he 10% 90% 10% 90% t onl t onh t offl t offh v ih v il v oh v ol v pp oe hv out hv out high impedance high impedance switching waveforms
12-151 HV7022-c hv out 1 oe polarity data in data out gnd s/r clk v dd v pp dir hv out 2 hv out 34 lt lt lt lt = level translator p n notes: h = logic high level, l = logic low level, x = irrelevant, = high-to-low transition, q 1 = hv out 1, q n = hv out (n), etc. * = dependent on previous state and whether an o/p or s/r command occured. inputs outputs i/o relations shift reg hv outputs data out o/p high x x h h h * h o/p off x x l h h * high-z * o/p low x x h l h * l * o/p off x x l l h * high-z * o/p off x x x x l * all o/p high-z * lxx xq n ? q n+1 *q 34 hxx xq n ? q n-1 *q 1 no x x x x * no change no change functional block diagram function table clk dir data pol oe load s/r, set dir
12-152 HV7022-c i (ma) i (ma) volts 0 20406080 180 140 100 60 20 0 100 20 40 60 80 v pp > 40v v dd = 12v & 14 v 100 180 140 100 60 20 volts (v pp - v out ) temp = 25 c temp = 25 c v dd = 14 v dd = 10 v dd = 12 hv out characteristics output n-channel characteristics through fet output p-channel characteristics through fet pin configurations package outline hv70 44 pin j-lead package pin function pin function 1hv out 18/17 23 dir 2hv out 17/18 24 v dd 3hv out 16/19 25 polarity 4hv out 15/20 26 data in 5hv out 14/21 27 v pp 6hv out 13/22 28 n/c 7hv out 12/23 29 hv out 34/1 8hv out 11/24 30 hv out 33/2 9hv out 10/25 31 hv out 32/3 10 hv out 9/26 32 hv out 31/4 11 hv out 8/27 33 hv out 30/5 12 hv out 7/28 34 hv out 29/6 13 hv out 6/29 35 hv out 28/7 14 hv out 5/30 36 hv out 27/8 15 hv out 4/31 37 hv out 26/9 16 hv out 3/32 38 hv out 25/10 17 hv out 2/33 39 hv out 24/11 18 hv out 1/34 40 hv out 23/12 19 data out 41 hv out 22/13 20 output enable 42 hv out 21/14 21 clock 43 hv out 20/15 22 gnd 44 hv out 19/16 note: pin designation for dir l/h example:for dir = l, pin 1 is hv out 18 for dir = h, pin 1 is hv out 17 6 40 41 42 43 44 1 2 3 4 5 39 38 37 36 35 34 33 32 31 30 29 18 28 27 26 25 24 23 22 21 20 19 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin j-lead package
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