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description the opa656 combines a very wideband, unity-gain stable, voltage-feedback op amp with a fet-input stage to offer an ultra high dynamic-range amplifier for adc (analog-to-digital converter) buffering and transimpedance applications. extremely low dc errors give good precision in optical applications. the high unity-gain stable bandwidth and jfet input allows exceptional performance in high-speed, low-noise integrators. the high input impedance and low bias current provided by the fet input is supported by the ultra-low 7nv/ hz input voltage noise to achieve a very low integrated noise in wideband photodiode transimpedance applications. broad transimpedance bandwidths are achievable given the opa656? high 230mhz gain bandwidth product. as shown below, a ?db bandwidth of 1mhz is provided even for a high 1m ? transimpedance gain from a 47pf source capacitance. features 500mhz unity-gain bandwidth low input bias current: 2pa low offset and drift: 0.25mv, 2 v/ c low distortion: 74db sfdr at 5mhz high output current: 70ma low input voltage noise: 7nv/ hz wideband, unity-gain stable, fet-input operational amplifier applications wideband photodiode amplifier sample-and-hold buffer ccd output buffer adc input buffer wideband precision amplifier test and measurement front end frequency 1m ? transimpedance bandwidth 130 120 110 100 90 80 10khz 100khz 1mhz 5mhz transimpedance gain (db) 1mhz bandwidth opa656 wideband photodiode transimpedance amplifier (47pf) v b 499k ? 499k ? v o 1pf opa656 sbos196a january 2002 www.ti.com copyright ? 2001, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. opa656 slew voltage v s bw rate noise device (v) (mhz) (v/ s) (nv/ hz) amplifier description opa355 +5 200 300 5.8 unity-gain stable cmos opa655 5 400 290 6 unity-gain stable fet-input opa657 5 1600 700 4.8 gain of +7 stable fet-input opa627 15 16 55 4.5 unity-gain stable fet-input ths4601 15 180 100 5.4 unity-gain stable fet-input related operational amplifier products production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
opa656 2 sbos196a www.ti.com specified package temperature package ordering transport product package-lead designator (1) range marking number (2) media, quantity opa656u so-8 surface mount d 40 c to +85 c opa656u opa656u rails, 100 """"" opa656u/2k5 tape and reel, 2500 opa656ub so-8 surface mount d 40 c to +85 c opa656ub opa656ub rails, 100 """"" opa656ub/2k5 tape and reel, 2500 opa656n sot23-5 dbv 40 c to +85 c b56 opa656n/250 tape and reel, 250 """"" opa656n/3k tape and reel, 3000 opa656nb sot23-5 dbv 40 c to +85 c b56 opa656nb/250 tape and reel, 250 """"" opa656nb/3k tape and reel, 3000 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. (2) ub and nb are h igh grade, while u and n are standard grade. package/ordering information electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper han- dling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. absolute maximum ratings (1) supply voltage ................................................................................. 6.5v internal power dissipation ........................... see thermal characteristics differential input voltage ..................................................................... v s input voltage range ............................................................................ v s storage temperature range ......................................... 40 c to +125 c lead temperature ......................................................................... +260 c junction temperature (t j ) ........................................................... +175 c esd rating (human body model) .................................................. 2000v (machine model) ............................................................ 200v note: (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. pin configurations top view so-8 top view sot23-5 1 2 3 4 8 7 6 5 nc +v s output nc nc inverting input noninverting input v s 1 2 3 5 4 +v s inverting input output v s noninverting input b56 1 2 3 5 4 pin orientation/package marking
opa656 3 sbos196a www.ti.com electrical characteristics: v s = 5v r f = 250 ? , r l = 100 ? , and g = +2, unless otherwise noted. figure 1 for ac performance. opa656u, n (standard-grade) typ min/max over temperature 0 c to C 40 c to min/ test parameter conditions +25 c +25 c (1) 70 c (2) +85 c (2) units max level (3) ac performance (figure 1) small-signal bandwidth g = +1, v o = 200mvp-p, r f = 0 ? 500 mhz typ c g = +2, v o = 200mvp-p 200 mhz typ c g = +5, v o = 200mvp-p 59 mhz typ c g = +10, v o = 200mvp-p 23 mhz typ c gain-bandwidth product g > +10 230 mhz typ c bandwidth for 0.1db flatness g = +2, v o = 200mvp-p 30 mhz typ c peaking at a gain of +1 v o < 200mvp-p, r f = 0 ? 1.5 db typ c large-signal bandwidth g = +2, v o = 2vp-p 75 mhz typ c slew rate g = +2, 1v step 290 v/ s typ c rise-and-fall time 0.2v step 1.5 ns typ c settling time to 0.02% g = +2, v o = 2v step 21 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd-harmonic r l = 200 ? 71 dbc typ c r l > 500 ? 74 dbc typ c 3rd-harmonic r l = 200 ? 81 dbc typ c r l > 500 ? 100 dbc typ c input voltage noise f > 100khz 7 nv/ hz typ c input current noise f > 100khz 1.3 fa/ hz typ c differential gain g = +2, pal, r l = 150 ? 0.02 % typ c differential phase g = +2, pal, r l = 150 ? 0.05 typ c dc performance (4) open-loop voltage gain (a ol )v o = 0v, r l = 100 ? 65 60 59 58 db min a input offset voltage v cm = 0v 0.25 1.8 2.2 2.6 mv max a average offset voltage drift v cm = 0v 2 12 12 12 v/ cmax a input bias current v cm = 0v 2 20 1800 5000 pa max a input offset current drift v cm = 0v 1 10 900 2500 pa max b input most positive input voltage (5) +2.5 +2.0 +1.9 +1.8 v min a most negative input voltage (5) 4.0 C 3.5 3.4 3.3 v min a common-mode rejection ratio (cmrr) v cm = 0.5v 86 80 78 76 db min a input impedance differential 10 12 || 0.7 ? || pf typ c common-mode 10 12 || 2.8 ? || pf typ c output voltage output swing no load 3.9 3.7 v typ r l = 100 ? 3.5 3.3 3.2 3.1 v min a current output, sourcing +70 56 54 50 ma min a current output, sinking 70 C 56 54 50 ma min a closed-loop output impedance g = +1, f = 0.1mhz 0.01 ? typ c power supply specified operating voltage 5 v typ c maximum operating voltage range 6 6 6vmaxa maximum quiescent current 14 15.8 16 16.1 ma max a minimum quiescent current 14 11.7 11.4 11.1 ma min a power-supply rejection ratio (+psrr) +v s = 4.50v to 5.50v 76 72 70 68 db min a ( psrr) v s = 4.50v to 5.50v 62 56 54 52 db min a temperature range specified operating range: u, n package 40 to 85 c typ thermal resistance, ja junction-to-ambient u: so-8 125 c/w typ n: sot23-5 150 c/w typ notes: (1) junction temperature = ambient for 25 c min/max specifications.(2) junction temperature = ambient at low temperature limit: junction temperature = ambient +20 c at high temperature limit for over temperature min/max specifications. (3) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (4) current is considere d positive out-of-node. v cm is the input common-mode voltage. (5) tested < 3db below minimum specified cmrr at cmir limits.
opa656 4 sbos196a www.ti.com electrical characteristics: v s = 5v: high grade dc specifications (1) r f = 250 ? , r l = 100 ? , and g = +2, unless otherwise noted. opa656ub, nb (high-grade) typ min/max over temperature 0 c to C 40 c to min/ test parameter conditions +25 c +25 c (2) 70 c (3) +85 c (3) units max level (4) input offset voltage v cm = 0v 0.1 0.6 0.85 0.9 mv max a input offset voltage drift v cm = 0v 2 6 6 6 v/ cmax a input bias current v cm = 0v 1 5 450 1250 pa max a input offset current v cm = 0v 0.5 5 450 1250 pa max a common-mode rejection ratio (cmrr) v cm = 0.5v 95 88 86 84 db min a power-supply reje ction ratio (+psrr) +v s = 4.5v to 5.5v 78 74 72 70 db min a ( psrr) v s = 4.5v to 5.5v 68 62 60 58 db min a notes: (1) all other specifications are the same as the standard-grade. (2) junction temperature = ambient for 25 c min/max specifications.(3) junction temperature = ambient at low temperature limit: junction temperature = ambient +20 c at high temperature limit for over temperature min/max specifications. (4) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation.
opa656 5 sbos196a www.ti.com typical characteristics: v s = 5v t a = +25 c, g = +2, r f = 250 ? , r l = 100 ? , unless otherwise noted. noninverting small-signal frequency response 10 0.5 1 500 100 frequency (mhz) normalized gain (db) 6 3 0 3 6 9 12 15 18 see figure 1 g = +2 g = +1 r f = 0 ? g = +5 g = +10 v o = 200mvp-p inverting small-signal frequency response 10 0.5 1 500 100 frequency (mhz) normalized gain (db) 9 6 3 0 3 6 9 12 15 18 21 24 see figure 2 g = 2 g = 1 g = 5 g = 10 v o = 200mvp-p r f = 402 ? noninverting large-signal frequency response 10 0.5 1 500 100 frequency (mhz) gain (db) 9 6 3 0 3 6 9 see figure 1 v o = 0.2vp-p v o = 0.5vp-p v o = 1vp-p v o = 2vp-p g = +2 inverting large-signal frequency response 10 0.5 1 500 100 frequency (mhz) gain (db) 3 0 3 6 9 12 15 18 v o = 0.5vp-p v o = 1vp-p v o = 2vp-p see figure 2 g = 1 noninverting pulse response time (10ns/div) small-signal output voltage (200mv/div) large-signal output voltage (400mv/div) 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 large-signal right scale small-signal left scale see figure 1 g = +2 inverting pulse response time (10ns/div) small-signal output voltage (200mv/div) large-signal output voltage (400mv/div) 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 large-signal right scale small-signal left scale see figure 2 g = 1
opa656 6 sbos196a www.ti.com typical characteristics: v s = 5v (cont.) t a = +25 c, g = +2, r f = 250 ? , r l = 100 ? , unless otherwise noted. harmonic distortion vs load resistance 100 1k resistance ( ? ) harmonic distortion (dbc) 60 65 70 75 80 85 90 95 100 105 110 v o = 2vp-p f = 5mhz see figure 1 2nd harmonic 3rd harmonic harmonic distortion vs frequency 0.1 1 20 10 frequency (mhz) harmonic distortion (dbc) 50 60 70 80 90 100 110 3rd harmonic 2nd harmonic v o = 2vp-p r l = 200 ? see figure 1 harmonic distortion vs noninverting gain 110 gain (v/v) harmonic distortion (dbc) 60 70 80 90 100 110 v o = 2vp-p f = 5mhz r l = 200 ? see figure 1, r g adjusted 2nd harmonic 3rd harmonic harmonic distortion vs inverting gain 1 10 gain (v/v) harmonic distortion (dbc) 60 65 70 75 80 85 90 v o = 2vp-p r f = 604 ? f = 5mhz r l = 200 ? see figure 2, r g and r m adjusted 2nd harmonic 3rd harmonic harmonic distortion vs output voltage (5mhz) 0.5 1 5 output voltage swing (vp-p) harmonic distortion (dbc) 60 65 70 75 80 85 90 95 100 105 f = 5mhz r l = 200 ? 2nd harmonic 3rd harmonic harmonic distortion vs output voltage (1mhz) 0.5 1 5 output voltage swing (vp-p) harmonic distortion (dbc) 70 75 80 85 90 95 100 105 110 f = 1mhz r l = 200 ? see figure 1 2nd harmonic 3rd harmonic
opa656 7 sbos196a www.ti.com typical characteristics: v s = 5v (cont.) t a = +25 c, g = +2, r f = 250 ? , r l = 100 ? , unless otherwise noted. input current and voltage noise density 10 100 1k 10k 100k 1m 10m f (hz) en (nv/ hz) in (fa/ hz) 100 10 1 input voltage noise 7nv/ hz input current noise 1.3fa/ hz common-mode rejection ratio and power-supply rejection ratio vs frequency 1k 100k 1m 10m 10k 100m frequency (hz) cmrr (db) psrr (db) 110 100 90 80 70 60 50 40 30 20 cmrr +psrr psrr open-loop gain and phase 1k 100 100k 1m 10m 10k 1g 100m frequency (hz) open-loop gain (db) open-loop phase (30 /div) 70 60 50 40 30 20 10 0 0 30 60 90 120 150 180 210 20 log(a ol ) < a ol recommended r s vs capacitive load 10 100 1k capacitive load (pf) r s ( ? ) 100 10 1 for maximally flat frequency response frequency response vs capacitive load 1 10 100 500 frequency (mhz) normalized gain to capacitive load (db) 9 6 3 0 3 6 9 12 r s 50 ? 1k ? v i v o c l 250 ? 250 ? opa656 c l = 22pf c l = 100pf c l = 10pf 2-tone, 3rd-order intermodulation spurious 10 8 6 4 24 2 068 single-tone load power (dbm) 3rd-order spurious level (dbc) 60 55 50 45 40 35 30 25 20 50 ? 50 ? 50 ? p i p o 402 ? 402 ? opa656 5mhz 2mhz 15mhz 10mhz
opa656 8 sbos196a www.ti.com typical characteristics: v s = 5v (cont.) t a = +25 c, g = +2, r f = 250 ? , r l = 100 ? , unless otherwise noted. inverting overdrive recovery time (20ns/div) 5 4 3 2 1 0 1 2 3 4 5 r l = 100 ? r f = 402 ? g = 1 see figure 2 output input input and output voltage (v) noninverting input overdrive recovery time (20ns/div) output voltage (v) input voltage (v) 8.0 6.4 4.8 3.2 1.6 0 1.6 3.2 4.8 6.4 8.0 4.0 3.2 2.4 1.6 0.8 0 0.8 1.6 2.4 3.2 4.0 r l = 100 ? g = +2 see figure 1 output voltage left scale input voltage right scale supply and output current vs temperature 50 25 0 25 50 75 100 125 ambient temperature ( c) output current (25ma/div) supply current (3ma/div) 150 125 100 75 50 25 0 18 15 12 9 6 3 0 supply current right scale left scale sourcing current sinking current left scale typical input bias current drift over temperature 50 25 0 25 50 75 100 125 ambient temperature ( c) input bias current (pa) 1000 900 800 700 600 500 400 300 200 100 0 typical input bias current vs common-mode input voltage 3 2 1012 3 common-mode input voltage (v) input bias current (pa) 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 typical input offset voltage drift over temperature 50 25 0 25 50 75 100 125 ambient temperature ( c) input offset voltage (mv) 1.0 0.5 0 0.5 1.0
opa656 9 sbos196a www.ti.com typical characteristics: v s = 5v (cont.) t a = +25 c, g = +2, r f = 250 ? , r l = 100 ? , unless otherwise noted. common-mode rejection ratio vs common-mode input voltage 5 4 3 2 15 4 3 2 1 0 common-mode input voltage (v) cmrr (db) 110 90 70 50 closed-loop output impedance vs frequency 1k 10k 100k 1m 10m 100m frequency (hz) output impedance ( ? ) 10 1 0.1 0.01 output voltage and current limitations 100 80 60 40 20 0 20 40 60 80 100 i o (ma) v o (v) 5 4 3 2 1 0 1 2 3 4 5 1w internal power r l = 100 ? r l = 50 ? r l = 25 ? 1w internal power
opa656 10 sbos196a www.ti.com applications information wideband, noninverting operation the opa656 provides a unique combination of a broadband, unity gain stable, voltage-feedback amplifier with the dc precision of a trimmed jfet-input stage. its very high gain bandwidth product (gbp) of 230mhz can be used to either deliver high signal bandwidths for low-gain buffers, or to deliver broadband, low-noise transimpedance bandwidth to photodiode-detector applications. to achieve the full perfor- mance of the opa656, careful attention to pc board layout and component selection is required as discussed in the remaining sections of this data sheet. figure 1 shows the noninverting gain of +2 circuit used as the basis for most of the typical characteristics. most of the curves were characterized using signal sources with 50 ? driving im- pedance, and with measurement equipment presenting a 50 ? load impedance. in figure 1, the 50 ? shunt resistor at the v i terminal matches the source impedance of the test generator, while the 50 ? series resistor at the v o terminal provides a matching resistor for the measurement equipment load. gener- ally, data sheet voltage swing specifications are at the output pin (v o in figure 1) while output power specifications are at the matched 50 ? load. the total 100 ? load at the output combined with the 500 ? total feedback network load, presents the opa656 with an effective output load of 83 ? for the circuit of figure 1. wideband, inverting gain operation the circuit of figure 2 shows the inverting gain of 1 test circuit used for most of the inverting typical characteristics. in this case, an additional resistor r m is used to achieve the 50 ? input impedance required by the test equipment using in characterization. this input impedance matching is optional in a circuit board environment where the opa656 is used as an inverting amplifier at the output of a prior stage. figure 1. noninverting g = +2 specifications and test circuit. voltage-feedback op amps, unlike current feedback prod- ucts, can use a wide range of resistor values to set their gain. to retain a controlled frequency response for the noninverting voltage amplifier of figure 1, the parallel combination of r f || r g should always < 200 ? . in the noninverting configura- tion, the parallel combination of r f || r g will form a pole with the parasitic input capacitance at the inverting node of the opa656 (including layout parasitics). for best performance, this pole should be at a frequency > than the closed loop bandwidth for the opa656. for this reason, a direct short from output to inverting input is recommended for the unity gain follower application. in this configuration, the output sees the feedback resistor as an additional load in parallel with the 100 ? load used for test. it is often useful to increase the r f value to decrease the loading on the output (improving harmonic distortion) with the constraint that the parallel combination of r f || r g < 200 ? . for higher inverting gains with the dc precision provided by the fet input opa656, consider the higher gain bandwidth product opa657. figure 2 also shows the noninverting input tied directly to ground. often, a bias current canceling resistor to ground is included here to null out the dc errors caused by input bias current effects. this is only useful when the input bias currents are matched. for a jfet part like the opa656, the input bias currents do not match but are so low to begin with (< 5pa) that dc errors due to input bias currents are negligible. hence, no resistor is recommended at the noninverting inputs for the inverting signal path condition. wideband, high sensitivity, transimpedance design the high gbp and low input voltage and current noise for the opa656 make it an ideal wideband transimpedance ampli- fier for low to moderate transimpedance gains. higher transimpedance gains (> 100k ? ) will benefit from the low input noise current of a fet input op amp such as the opa656. one transimpedance design example is shown on the front page of the data sheet. designs that require high bandwidth from a large area detector will benefit from the low input voltage noise for the opa656. this input voltage noise figure 2. inverting g = 1 specifications and test circuit. opa656 +5v 5v v s +v s 50 ? v o v i 50 ? + 0.1 f + 6.8 f 6.8 f r g 250 ? r f 250 ? 50 ? source 50 ? load 0.1 f opa656 +5v 5v +v s v s r m 57.6 ? 50 ? v o v i + 6.8 f 0.1 f + 6.8 f 0.1 f r f 402 ? r g 402 ? 50 ? source 50 ? load
opa656 11 sbos196a www.ti.com is peaked up over frequency by the diode source capaci- tance, and can, in many cases, become the limiting factor to input sensitivity. the key elements to the design are the expected diode capacitance (c d ) with the reverse bias volt- age ( v b ) applied, the desired transimpedance gain, r f , and the gbp for the opa656 (230mhz). figure 3 shows a design from a 25pf source capacitance diode through a 50k ? transimpedance gain. with these 3 variables set (and includ- ing the parasitic input capacitance for the opa656 added to c d ), the feedback capacitor value (c f ) may be set to control the frequency response. where: i eq = equivalent input noise current if the output noise is bandlimited to f < 1/(2 r f c d ). i n = input current noise for the op amp inverting input. e n = input voltage noise for the op amp. c d = diode capacitance. f = bandlimiting frequency in hz (usually a postfilter prior to further signal processing). 4kt = 1.6e 20j at 290 k. evaluating this expression up to the feedback pole frequency at 3.8mhz for the circuit of figure 3, gives an equivalent input noise current of 2.7pa/ hz . this is much higher than the 1.3fa/ hz for just the op amp itself. this result is being dominated by the last term in the equivalent input noise current expression. it is essential in this case to use a low voltage noise op amp. operating suggestions setting resistor values to minimize noise the opa656 provides a very low input noise voltage while requiring a low 14ma quiescent supply current. to take full advantage of this low input noise, a careful attention to the other possible noise contributors is required. figure 4 shows the op amp noise analysis model with all the noise terms included. in this model, all the noise terms are taken to be noise voltage or current density terms in either nv/ hz or pa/ hz . to achieve a maximally flat 2nd-order butterworth frequency response, the feedback pole should be set to: 12 4 /( ) ( /( )) rc gpb rc ff fd = adding the common mode and differential mode input ca- pacitance (0.7 + 2.8)pf to the 25pf diode source capaci- tance of figure 3, and targeting a 50k ? transimpedance gain using the 230mhz gbp for the opa656 will require a feedback pole set to 3.8mhz. this will require a total feed- back capacitance of 0.8pf. typical surface-mount resistors have a parasitic capacitance of 0.2pf leaving the required 0.6pf value shown in figure 3 to get the required feedback pole. this will give an approximate 3db bandwidth set by: f gpb r c hz db f d ? = 3 2 /) the example of figure 3 will give approximately 5.7mhz flat bandwidth using the 0.6pf feedback compensation. if the total output noise is bandlimited to a frequency less than the feedback pole frequency (1/r f c f ), a very simple expression for the equivalent input noise current can be derived as: ii kt r e r ecf eq n f n f nd =+ + ? ? ? ? ? ? + ( ) 2 2 2 4 2 3 figure 3. wideband, low-noise, transimpendance amplifier. figure 4. op amp noise analysis model. the total output spot noise voltage can be computed as the square root of the squared contributing terms to the output noise voltage. this computation is adding all the contributing noise powers at the output by superposition, then taking the square root to get back to a spot noise voltage. equation 1 shows the general form for this output noise voltage using the terms shown in figure 4. (1) e e i r ktr ng i r ktr ng o ni bn ss bi f f =+ ( ) + ? ? ? ? + ( ) + 2 2 2 2 44 r f 50k ? supply decoupling not shown c d 25pf opa656 +5v 5v v b i d v o = i d r f c f 0.6pf 4kt r g r g r f r s opa656 i bi e o i bn 4kt = 1.6e 20j at 290 k e rs e ni 4ktr s 4ktr f * * *
opa656 12 sbos196a www.ti.com dividing this expression by the noise gain (g n = 1+r f /r g ) will give the equivalent input referred spot noise voltage at the noninverting input as shown in equation 2. (2) e e i r ktr ir ng ktr ng nnibn ss bi f f =+ ( ) ++ ? ? ? ? ? ? + 2 2 2 4 4 putting high resistor values into equation 2 can quickly dominate the total equivalent input referred noise. a source impedance on the noninverting input of 3k ? will add a johnson voltage noise term equal to just that for the amplifier itself (7nv/ hz ). while the jfet input of the opa656 is ideal for high source impedance applications, both the overall bandwidth and noise will be limited by higher source imped- ances in the noninverting configuration of figure 1. frequency response control voltage-feedback op amps like the opa656 exhibit decreas- ing signal bandwidth as the signal gain is increased. in theory, this relationship is described by the gbp shown in the electrical characteristics. ideally, dividing gbp by the noninverting signal gain (also called the noise gain, or ng) will predict the closed-loop bandwidth. in practice, this only holds true when the phase margin approaches 90 , as it does in high-gain configurations. at low gains (increased feedback factors), most high-speed amplifiers will exhibit a more com- plex response with lower phase margin. the opa656 is compensated to give a maximally flat 2nd-order butterworth closed loop response at a noninverting gain of +2 (figure 1). this results in a typical gain of +2 bandwidth of 200mhz, far exceeding that predicted by dividing the 230mhz gbp by 2. increasing the gain will cause the phase margin to approach 90 and the bandwidth to more closely approach the pre- dicted value of (gbp/ng). at a gain of +10 the opa656 will show the 23mhz bandwidth predicted using the simple formula and the typical gbp of 230mhz. unity-gain stable op amps like the opa656 can also be bandlimited using a capacitor across the feedback resistor. for the noninverting configuration of figure 1, a capacitor across the feedback resistor will decrease the gain with frequency down to a gain of +1. for instance, to bandlimit the gain of +2 design to 20mhz, a 32pf capacitor can be placed in parallel with the 250 ? feedback resistor. this will, how- ever, only decrease the gain from 2 to 1. using a feedback capacitor to limit the signal bandwidth is more effective in the inverting configuration of figure 2. adding that same capaci- tor to the feedback of figure 2 will set a pole in the signal frequency response at 20mhz, but in this case it will continue to attenuate the signal gain to below 1. however, the output noise contribution due the input voltage noise of the opa656 will still only be reduced to a gain of 1 with the addition of the feedback capacitor. driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an adc including additional external capacitance which may be recommended to im- prove adc linearity. a high-speed, high open-loop gain amplifier like the opa656 can be very susceptible to de- creased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. when the amplifier s open loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. several external solutions to this problem have been suggested. when the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. this does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. the additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. the typical characteristics show the recommended r s ver- sus capacitive load and the resulting frequency response at the load. in this case, a design target of a maximally flat frequency response was used. lower values of r s may be used if some peaking can be tolerated. also, operating at higher gains (than the +2 used in the typical characteristics) will require lower values of r s for a minimally peaked frequency response. parasitic capacitive loads greater than 2pf can begin to degrade the performance of the opa656. long pc board traces, unmatched cables, and connections to multiple devices can easily cause this value to be ex- ceeded. always consider this effect carefully, and add the recommended series resistor as close as possible to the opa656 output pin (see board layout section). distortion performance the opa656 is capable of delivering a low distortion signal at high frequencies over a wide range of gains. the distortion plots in the typical characteristics show the typical distortion under a wide variety of conditions. generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic will dominate the distortion with negligible 3rd-harmonic component. focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. remember that the total load includes the feedback network in the noninverting configura- tion this is sum of r f + r g , while in the inverting configuration this is just r f (see figure 1). increasing output voltage swing increases harmonic distortion directly. a 6db increase in output swing will generally increase the 2nd-harmonic 12db and the 3rd-harmonic 18db. increasing the signal gain will also
opa656 13 sbos196a www.ti.com increase the 2nd-harmonic distortion. again a 6db increase in gain will increase the 2nd- and 3rd-harmonic by about 6db even with a constant output power and frequency. and finally, the distortion increases as the fundamental frequency in- creases due to the rolloff in the loop gain with frequency. conversely, the distortion will improve going to lower frequen- cies down to the dominant open loop pole at approximately 100khz. starting from the 70dbc 2nd-harmonic for a 5mhz, 2vp-p fundamental into a 200 ? load at g = +2 (from the typical characteristics), the 2nd-harmonic distortion for fre- quencies lower than 100khz will be < 105dbc. the opa656 has an extremely low 3rd-order harmonic distortion. this also shows up in the 2-tone 3rd-order inter- modulation spurious (im3) response curves. the 3rd-order spurious levels are extremely low (< 80dbc) at low output power levels. the output stage continues to hold them low even as the fundamental power reaches higher levels. as the typical characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. as the fundamental power level increases, the dy- namic range does not decrease significantly. for 2 tones centered at 10mhz, with 4dbm/tone into a matched 50 ? load (i.e., 1vp-p for each tone at the load, which requires 4vp-p for the overall 2-tone envelope at the output pin), the typical characteristics show a 78dbc difference between the test tone and the 3rd-order intermodulation spurious levels. this exceptional performance improves further when operating at lower frequencies and/or higher load impedances. dc accuracy and offset control the opa656 can provide excellent dc accuracy due to its high open-loop gain, high common-mode rejection, high power-supply rejection, and its trimmed input offset voltage (and drift) along with the negligible errors introduced by the low input bias current. for the best dc precision, a high- grade version (opa656ub or opa656nb) screens the key dc parameters to an even tighter limits. both standard- and high-grade versions take advantage of a new final test technique to 100% test input offset voltage drift over tem- perature. this discussion will use the high-grade typical and min/max electrical characteristics for illustration, however, an identical analysis applies to the standard-grade version. the total output dc offset voltage in any configuration and temperature will be the combination of a number of possible error terms. in a jfet part like the opa656, the input bias current terms are typically quite low but are unmatched. using bias current cancellation techniques, more typical in bipolar input amplifiers, does not improve output dc offset errors. errors due to the input bias current will only become dominant at elevated temperatures. the opa656 shows the typical 2x increase in every 10 c common to jfet-input stage amplifiers. using the 5pa maximum tested value at 25 c, and a 20 c internal self heating (see thermal analysis), the maximum input bias current at 85 c ambient will be 5pa 2 (105 25)/10 = 1280pa. for noninverting configurations, this term only begins to be a significant term versus the input offset voltage for source impedances > 750k ? . this would also be the feedback-resistor value for transimpedance ap- plications (see figure 3) where the output dc error due to inverting input bias current is on the order of that contributed by the input offset voltage. in general, except for these extremely high impedance values, the output dc errors due to the input bias current may be neglected. after the input offset voltage itself, the most significant term contributing to output offset voltage is the psrr for the negative supply. this term is modeled as an input offset voltage shift due to changes in the negative power-supply voltage (and similarly for the +psrr). the high-grade test limit for psrr is 62db. this translates into 1.59mv/v input offset voltage shift = 10 ( 62/20) . in the worst case, a 0.38v ( 7.6%) shift in the negative supply voltage will produce a 0.6mv apparent input offset voltage shift. since this is comparable to the tested limit of 0.6mv input offset voltage, a careful control of the negative supply voltage is required. the +psrr is tested to a minimum value of 74db. this translates into 10 ( 74/20) = 0.2mv/v sensitivity for the input offset voltage to positive power supply changes. as an example, compute the worst-case output dc error for the transimpedance circuit of figure 1 at 25 c and then the shift over the 0 c to 70 c range given the following assump- tions. negative power supply = 5v 0.2v with a 5mv/ c worst-case shift positive power supply = +5v 0.2v with a 5mv/ c worst-case shift initial 25 c output dc error band = 0.3mv (due to the psrr = 1.59mv/v 0.2v) 0.04mv (due to the +psrr = 0.2mv/v 0.2v) 0.6mv input offset voltage total = 0.94mv this would be the worst-case error band in volume produc- tion at 25 c acceptance testing given the conditions stated. over the temperature range of 0 c to 70 c, we can expect the following worst-case shifting from initial value. a 20 c internal junction self heating is assumed here. 0.36mv (opa656 high-grade input offset drift) = 6 v/ c (70 c + 20 c 25 c)) 0.23mv ( psrr of 60db with 5mv (70 c 25 c) supply shift) 0.06mv (+psrr of 72db with 5mv (70 c 25 c) supply shift) total = 0.65mv this would be the worst-case shift from initial offset over a 0 c to 70 c ambient for the conditions stated. typical initial output dc error bands and shifts over temperature will be much lower than these worst-case estimates. in the transimpedance configuration, the cmrr errors can be neglected since the input common mode voltage is held at ground. for noninverting gain configurations ( see fi gure 1), the cmrr term will need to be considered but will typically be far lower than the input offset voltage term. with a tested minimum of 80db (100uv/v), the added apparent dc error will be no more than 0.2mv for a 2v input swing to the circuit of figure 1.
opa656 14 sbos196a www.ti.com power-supply considerations the opa656 is intended for operation on 5v supplies. single-supply operation is allowed with minimal change from the stated specifications and performance from a single supply of +8v to +12v maximum. the limit to lower supply voltage operation is the useable input voltage range for the jfet-input stage. operating from a single supply of +12v can have numerous advantages. with the negative supply at ground, the dc errors due to the psrr term can be minimized. typically, ac performance improves slightly at +12v operation with minimal increase in supply current. thermal analysis the opa656 will not require heatsinking or airflow in most applications. maximum allowed junction temperature will set the maximum allowed internal power dissipation as de- scribed below. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). under this condition p dl = v s 2 /(4 r l ) where r l includes feedback network loading. note that it is the power in the output stage and not into the load that determines internal power dissipation. as a worst-case example, compute the maximum t j using an opa656n (sot23-5 package) in the circuit of figure 1 operating at the maximum specified ambient temperature of +85 c and driving a grounded 100 ? load. p d = 10v 16.1ma + 5 2 /(4 (100 ? || 800 ? )) = 231mw maximum t j = +85 c + (0.23w 150 c/w) = 120 c. all actual applications will be operating at lower internal power and junction temperature. board layout achieving optimum performance with a high-frequency am- plifier like the opa656 requires careful attention to board layout parasitics and external component types. recommen- dations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability on the noninvert- ing input, it can react with the source impedance to cause unintentional bandlimiting. to reduce unwanted capacitance, a window around the signal i/o pins should be opened in all of the ground and power planes around those pins. other- wise, ground and power planes should be unbroken else- where on the board. b) minimize the distance (< 0.25 ) from the power-supply pins to high-frequency 0.1uf decoupling capacitors. at the device pins, the ground and power plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. the power-supply connections should always be decoupled with these capaci- tors. larger (2.2 f to 6.8 f) decoupling capacitors, effective at lower frequency, should also be used on the supply pins. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board. c) careful selection and placement of external components will preserve the high frequency performance of the opa656 . resistors should be a very low reactance type. surface-mount resistors work best and allow a tighter overall layout. metal film and carbon composition axially leaded resistors can also pro- vide good high frequency performance. again, keep their leads and pc board trace length as short as possible. never use wirewound type resistors in a high frequency application. since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. other network components, such as noninverting input termina- tion resistors, should also be placed close to the package. where double side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. good axial metal film or surface-mount resistors have approximately 0.2pf in shunt with the resistor. for resistor values > 1.5k ? , this parasitic capacitance can add a pole and/or zero below 500mhz that can effect circuit operation. keep resistor values as low as possible consistent with load driving considerations. it has been sug- gested here that a good starting point for design would be to keep r f || r g < 250 ? for voltage amplifier applications. doing this will automatically keep the resistor noise terms low, and minimize the effect of their parasitic capacitance. transimpedance applications ( see fi gure 3) can use whatever feedback resistor is required by the application as long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the inverting node. d) connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the plot of recommended r s vs capacitive load. low parasitic capacitive loads (< 5pf) may not need an r s since the opa656 is nominally compensated to operate with a 2pf parasitic load. higher parasitic capacitive loads without an r s are allowed as the signal gain increases (increasing the
opa656 15 sbos196a www.ti.com unloaded phase margin) if a long trace is required, and the 6db signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance trans- mission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 ? environment is normally not necessary onboard, and in fact a higher impedance environment will improve distortion as shown in the distortion versus load plots. with a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the opa656 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device this total effective impedance should be set to match the trace impedance. if the 6db attenuation of a doubly-termi- nated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of recommended r s vs capacitive load. this will not preserve signal integrity as well as a doubly-terminated line. if the input impedance of the destina- tion device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) socketing a high speed part like the opa656 is not recommended. the additional lead length and pin-to-pin ca- pacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impos- sible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa656 onto the board. figure 5. internal esd protection. external pin +v cc v cc internal circuitry input and esd protection the opa656 is built using a very high speed complementary bipolar process. the internal junction breakdown voltages are relatively low for these very small geometry devices. these breakdowns are reflected in the absolute maximum ratings table. all device pins are protected with internal esd protec- tion diodes to the power supplies as shown in figure 5. these diodes provide moderate protection to input overdrive voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g. in systems with 12v supply parts driving into the opa656), current limiting series resistors should be added into the two inputs. keep these resistor values as low as possible since high values degrade both noise performance and frequency response.
opa656 16 sbos196a www.ti.com package drawings msoi002b january 1995 revised september 2001 d (r-pdso-g**) plastic small-outline package 8 pins shown 8 0.197 (5,00) a max a min (4,80) 0.189 0.337 (8,55) (8,75) 0.344 14 0.386 (9,80) (10,00) 0.394 16 dim pins ** 4040047/e 09/01 0.069 (1,75) max seating plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) nom 0 C 8 gage plane a 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
opa656 17 sbos196a www.ti.com package drawings (cont.) mpds018d february 1996 revised january 2001 dbv (r-pdso-g5) plastic small-outline 0,10 m 0,20 0,95 0 C 8 0,25 0,35 0,55 gage plane 0,15 nom 4073253-4/f 10/00 2,60 3,00 0,50 0,30 1,50 1,70 4 5 3 1 2,80 3,00 0,95 1,45 0,05 min seating plane notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. falls within jedec mo-178
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