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this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 a a cmos 180 mhz quadrature digital upconverter preliminary technical information AD9856 features universal low-cost solution for hfc network return-channel tx function up to 70 mhz output bandwidth integrated 12-bit d/a converter programmable sample rate interpolation filter programmable reference clock multiplier internal sinx/x compensation filter >52 db sfdr @40 mhz analog dac out >48 db sfdr @70 mhz analog dac out >80 db narrowband sfdr @ 70 mhz aout +3.3v single supply operation low power: 400 mw@ max. clock speed space-saving surface-mount packaging bi-directional control bus interface supports burst and continuous tx modes 4 stored pin-selectable modulator profiles direct interface to ad8320 pga cable driver applications hfc data, telephony, and video modems wireless and satellite communications spi interface to ad8320 programmable cable driver amplifier 12-bit dac sine cosine dds and control functions ref clock in sinx /x complex data in 5-70 mhz output dac rset bi-directional spi control interface: 32-bit frequency tuning word frequency update interpolation filter coefficients ref clock multiplier coefficients output phase inversion enable cable driver amplifier control reset master tx enable 4x/8x programmable interpolating halfbands 4x/8x programmable interpolating halfbands de-multiplexer & serial-to-parallel converter 1x to 64x programmable interpolator 1x to 64x programmable interpolation dds and control functions profile select 1-2 profile select 3-4 prog. clock multiplier (i/q sync) functional block diagram general description the AD9856 integrates a high-speed direct-digital synthesizer (dds), a high-performance, high-speed 12-bit digital-to-analog converter (dac), clock multiplier circuitry, digital filters, and other dsp functions onto a single chip, to form a complete quadrature digital upconverter device. the AD9856 is primarily intended to function as a universal upstream and downstream i/q modulator for interactive hfc cable network applications, where cost, size, power dissipation, and dynamic performance are critical attributes. the AD9856 is fabricated on an advanced cmos process and it delivers an exceptional level of mixed signal performance. the device provides a precision digital modulation and upconvert function with a direct interface port to the ad8320, digitally- programmable cable driver amplifier. the ad9853/ad8320 chipset forms a highly-integrated, low-power, small footprint, and cost-effective solution for the hfc return-path tx requirement. the AD9856 is available in a space-saving surface mount package and is specified to operate over the extended industrial temperature range of -40 to +85c.
AD9856 preliminary technical information 2 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 absolute maximum ratings 1 maximum junction temp. .................................... +165c storage temperature ............................ -65c to +150c vs ............................................................ +6v operating temp. .................................. -40c to +85c digital inputs ................................ -0.7v to +vs lead temp. (10 sec. soldering) ........................... +300c digital output current ............................... 5ma AD9856 electrical characteristics (vs=+3.3 v 5%, rset=3.9 k w w , reference clock frequency = 8.0 mhz with internal pll enabled @ 20x). parameter temp test level AD9856 min typ max units ref clock input characteristics frequency range pll disabled full vi 180.0 mhz pll enabled @ 20x full vi 9.0 mhz pll enabled @ 4x full vi 45 mhz duty cycle +25c i 50 % input capacitance +25c iv 3 pf input impedance +25c iv 100 m w dac output characteristics resolution 12 bits full scale output current +25c v 5 10 20 ma gain error +25c i -10 +10 %fs output offset +25c i 10 ua differential non-linearity +25c i .5 lsb integral non-linearity +25c i 1 lsb output capacitance +25c i 5 pf phase noise @ 1 khz offset, 40 mhz aout 3 +25c i -100 dbc voltage compliance range +25c i 0 1.5 v wideband sfdr: 1 mhz analog out +25c v 65 dbc 20 mhz analog out +25c v 60 dbc 40 mhz analog out +25c v 55 dbc 65 mhz analog out +25c v 52 dbc 70 mhz analog out +25c v 50 dbc modulator characteristics i/q offset +25c i 48 db error vector magnitude +25c i 1 % pass band amplitude ripple +25c i 0.3 db timing characteristics output latency of profile change 15 fmax cycles wake-up time from full sleep mode 10 us
AD9856 preliminary technical information 3 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 AD9856 electrical characteristics (vs=+3.3v 5%, rset=3.9 k w w , reference clock frequency = 8.0 mhz with internal pll enabled @ 20x). parameter temp test level AD9856 min typ max units cmos logic inputs logic "1" voltage +25c i +2.7 v logic "0" voltage +25c i +0.4 v logic "1" current +25c iv 12 ua logic "0" current +25c iv 12 ua input capacitance +25c v 3 pf power supply +vs current @ full operating conditions +25c i 121 ma p diss @ full operating conditions +25c i 400 mw p diss @ non-bursting +25c i 40 mw p diss @ full power-down mode +25c i 1 mw notes 1 absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. 2 dc to 70 mhz output bandwidth. 3 residual phase noise 4 excluding aliased frequency components explanation of test levels test level i - 100% production tested. iii - sample tested only. iv - parameter is guaranteed by design and characterization testing. v - parameter is a typical value only. vi - all devices are 100% production tested at +25c. 100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices. table i. modulator function description input data format 12-bit parallel, 6-bit nibble, 3-bit nibble - selectable via control bus. input data is assumed to be 4x oversampled when input to the AD9856. input sample rate min: clk/512 ; max: 45 ms/s. programmable via control bus. input reference clock frequency for 5-70 mhz aout operation (160 mhz internal reference clock): w/pll enabled: 8 - 20 mhz, programmable via control bus w/pll disabled: 160 mhz note: for optimum data synchronization, the AD9856 reference clock, and the input data clock, should be derived from the same clock source. internal reference clock pll programmable in integer steps over the range of 4x-20x; enable/disable control via control bus profile select four pin-selectable, pre-programmed, modulator formats interpolating range fixed 4x, programmable 2x, and programmable 64x halfband filters interpolating filters that compensate for cic passband rolloff characteristics tx enable function - burst mode when burst mode is enabled via the control bus, the rising edge of the applied tx enable pulse should be coincident with, and frame, the input data packet. this establishes data sampling synchronization. tx enable function - continuous mode when continuous mode is enabled via the control bus, the tx enable pin becomes the i/q demux control. logic ?1? outputs the demux to the i channel; logic ?0? outputs the demux to the q channel. sinx/x filter pre-compensates for sinx/x roll-off of dac ; user bypassable. i/q channel invert cos - j sin or cos + j sin, selectable via control bus
AD9856 preliminary technical information 4 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 table ii. package lead function assignments (preliminary) pin # pin name pin function pin # pin name pin function 1 tx enable input pulse that frames the burst data stream 25 dac rset r set resistor connection 2 d11 input data 26 dac baseline dac baseline voltage 3 d10 input data 27 avdd analog supply voltage 4 dvdd digital supply voltage 28 agnd analog ground 5 dgnd digital ground 29 ioutb complementary analog current output of the dac 6 d9 input data 30 iout true analog current output of dac 7 d8 input data 31 agnd analog ground 8 d7 input data 32 pll gnd pll ground 9 d6 input data 33 pll filter pll loop filter connection 10 dvdd digital supply voltage 34 pll supply pll voltage supply 11 dgnd digital ground 35 ca enable cable driver amp enable 12 d5 input data 36 ca data cable driver amp data 13 d4 input data 37 ca clk cable driver amp clock 14 d3 input data 38 cs(b) chip select (bar) 15 d2 input data 39 sdo serial data output 16 d1 input data 40 sd i/o serial port i/o 17 d0 input data 41 sclk serial port clock 18 n/c no internal connection 42 i/o reset performs i/o synchronization 19 n/c no internal connection 43 dgnd digital ground 20 dgnd digital ground 44 dvdd digital supply voltage 21 dvdd digital supply voltage 45 ps0 profile select 1 22 n/c no internal connection 46 ps1 profile select 2 23 agnd analog ground 47 ref clk reference clock input 24 ref bypass bypass with .01 m f cap 48 reset master reset
AD9856 preliminary technical information 5 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 table iii. control bus register definitions. bit name width position description profile address (hex) sdo active 1 <7> active high indicates serial port uses dedicated in/out lines. default low configures serial port as single line i/o. n/a 00 lsb first 1 <6> active high indicates serial port access is lsb to msb format. default low indicates msb to lsb format. n/a 00 refclk<4:0> 5 <5:1> reference clock multiplier n/a 00 pd 1 <0> enable automatic power down between bursts n/a 00 moregain 1 <7> this bit adjusts output selection of the cic filters. allows user to gain up the output when interpolation rates are not a power of two. n/a 01 continuous mode 1 <6> continuous mode operation enabled. uses tx enable pin to synchronize i/q data: 1=i, 0=q. operates only in 12-bit parallel word format. n/a 01 sleep 1 <5> active high full sleep mode bit. n/a 01 fsk mode 1 <4> active high fsk mode. dds cosine data output. n/a 01 by pass inverse sinc filter 1 <3> inverse sinc filter bypassed in data path. n/a 01 bpll 1 <2> bypass the refclk pll n/a 01 infmt 2 <1:0> input format select bits: 1x - full word mode, 01 - half-word mode, 00 - quarter word mode. n/a 01 ftw1<31:0> 32 <7:0> <7:0> <7:0> <7:0> 32-bit dds frequency tuning word 1 05, 04, 03, 02 int1<5:0> 6 <7:2> interpolation rate bits: these bits program the interpolation rate of the first interpolator. available rates are 1- 64. 1 06 si1 1 <1> spectral inversion bit: active high enables the spectral inversion capability of the AD9856. 1 06 bphb3 1 <0> bypass third half-band filter 1 06 gs1<7:0> 8 <7:0> ad8320 gain control bits: sets the ad8320 line driver gain control data to be output at the dedicated control bus. 1 07 ftw2<31:0> 32 <7:0> <7:0> <7:0> <7:0> 32-bit frequency tuning word 2 0b, 0a, 09, 08
AD9856 preliminary technical information 6 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 table iii continued. control bus register definitions. bit name width position description profile address (hex) int2<5:0> 6 <7:2> interpolation rate bits: these bits program the interpolation rate of the first interpolator. available rates are 1- 64. 2 0c si2 1 <1> spectral inversion bit: active high enables the spectral inversion capability of the AD9856. 2 0c bphb3 1 <0> bypass third half-band filter 2 0c gs2<7:0> 8 <7:0> ad8320 gain control bits: sets the ad8320 line driver gain control data to be output at the dedicated control bus. 2 0d ftw3<31:0> 32 <7:0> <7:0> <7:0> <7:0> 32-bit frequency tuning word 3 11, 10, 0f, 0e int3<5:0> 6 <7:2> interpolation rate bits: these bits program the interpolation rate of the first interpolator. available rates are 1- 64. 3 12 si3 1 <1> spectral inversion bit: active high enables the spectral inversion capability of the AD9856. 3 12 bphb3 1 <0> bypass third half-band filter 3 12 gs3<7:0> 8 <7:0> ad8320 gain control bits: sets the ad8320 line driver gain control data to be output at the dedicated control bus. 3 13 ftw4<31:0> 32 <7:0> <7:0> <7:0> <7:0> 32-bit frequency tuning word 4 17, 16, 15, 14 int4<5:0> 6 <7:2> interpolation rate bits: these bits program the interpolation rate of the first interpolator. available rates are 1- 64. 4 18 si4 1 <1> spectral inversion bit: active high enables the spectral inversion capability of the AD9856. 4 18 bphb3 1 <0> bypass third half-band filter 4 18 gs4<7:0> 8 <7:0> ad8320 gain control bits: sets the ad8320 line driver gain control data to be output at the dedicated control bus. 4 19
AD9856 preliminary technical information 7 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 figure 1. master reset timing diagram t rs t rh reset ref clk t rr t rl t ol symbol definition min. spec. t rh clk delay after reset rising edge 3.5ns t rl reset falling edge after clk 3.5ns t rs minimum reset width 5 clk cycles
AD9856 preliminary technical information 8 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 serial port operation the AD9856 serial control interface is designed to be compatible with most synchronous transfer formats. the interface allows read/write access to all registers that configure the AD9856. single or multiple byte transfers are supported as well as msb or lsb transfer formats. the AD9856?s serial interface port can be configured as a single pin i/o (sdio) or two unidirectional pins for in/out (sdio/sdo). communicating with the AD9856 occurs in two phases. the first phase of every communication cycle is the writing of an instruction byte. the second phase is the data transfer as specified by the instruction byte. figure 2. using sdio as a read/write transfer sdio cs instruction byte data byte 1 data byte 2 data byte 3 data transfer instruction cycle figure 3. using sdio as an input, sdo as an output sdio cs instruction byte data byte 1 data byte 2 data byte 3 data transfer instruction cycle sdo all data input to the AD9856 is registered on the rising edge of sclk. all data is driven out of the AD9856 on the falling edge of sclk. the instruction byte contains the following information as shown below (see table iv): msb lsb r/w(bar) n1 n0 a4 a3 a2 a1 a0 r/w (bar) - bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. logic high indicates read operation.
AD9856 preliminary technical information 9 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 n1, n2 - bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle of the communications cycle. a4, a3, a2, a1, a0 - bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. for multi-byte transfers, this address is the starting byte address. the remaining register addresses are generated by the AD9856. see the msb/lsb transfer section for details. table iv n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes serial interface port pin description the AD9856 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola 6905/11 spi and intel 8051 ssr protocols. the serial port can be configured as either a 2-wire or 3-wire hardware interface. the 2-wire operation performs read/write operations on the sdio pin. the 3-wire operation performs writes on sdio and reads data out on the sdo pin. definition of serial interface port pins: sclk - serial clock. the serial clock pin is used to synchronize data to and from the AD9856 and to run the internal state machines. sclk maximum frequency is 5 mhz. cs(bar) - chip select (bar). active low input that allows more than one device on the same serial communications lines. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio - serial data i/o. data is always written into the AD9856 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by the reg0<7> bit. reg0<7> defaults to logic zero, which configures the sdio pin as bidirectional. sdo - serial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the AD9856 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. ca clk - output clock pin to the ad8320. if using the ad8320 programmable cable driver amplifier and desire the AD9856 to program its gain control register, connect this pin to the clk input of the ad8320. see the writing the ad8320 gain control register section for details. ca data - output data pin to the ad8320. if using the ad8320 programmable cable driver amplifier and desire the AD9856 to program its gain control register, connect this pin to the sdata input of the ad8320. see the writing the ad8320 gain control register section for details.
AD9856 preliminary technical information 10 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 ca enable - output enable pin to the ad8320. if using the ad8320 programmable cable driver amplifier and desire the AD9856 to program its gain control register, connect this pin to the dataen input of the ad8320. see the writing the ad8320 gain control register section for details. general operation of the serial interface there are two phases to a communication cycle with the AD9856. phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9856, coincident with the first 8 sclk rising edges. the instruction byte provides the AD9856 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer (1-4), and the starting register address for the first byte of the data transfer as previously shown. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the AD9856. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the AD9856 and the system controller. phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. normally, using one communication cycle in a multi-byte transfer is the preferred method. however, single byte communication cycles are useful to reduce cpu overhead when register access requires one byte only. examples of this may be to write the AD9856 sleep bit, or an ad8320 gain control byte. at the completion o any communication cycle, the AD9856 serial port controller expects the next 8 rising sclk edges to be the instruction byte of the next communication cycle. an example of a proper data transfer with the AD9856 is as follows: from initialization, the AD9856 serial port controller expects the first 8 rising sclk edges to synchronously write an instruction byte into the AD9856. notes on serial port operation the AD9856 serial port configuration bits reside in the reg0<7:6> bits. it is important to note that the configuration changes immediately upon writing this register. writing this register may occur during the middle of a communication cycle. the AD9856 serial port controller address can roll from 19h to 0h for certain instruction bytes if the msb first mode is active. the serial port controller address can roll from 0h to 19h for certain instruction bytes if lsb first mode is active. the system must maintain synchronization with the AD9856 or the internal control logic will not be able to recognize further instructions. for example, if the system sends an instruction byte for a two byte write then pulses the sclk pin for a 3-byte write (24 additional sclk rising edges), communication synchronization is lost. in this case, the first 16 sclk rising edges after the instruction cycle will properly write the first two data bytes into the AD9856 but the next 8 rising sclk edges are interpreted as the next instruction byte, not the final byte of the previous communication cycle. in the case where synchronization is lost between the system and the AD9856, the sync i/o pin provides a means to re-establish synchronization without re-initializing the entire chip. the sync i/o pin enables the user to reset the AD9856 state machine to accept the next eight (8) sclk rising edges to be coincident with the instruction phase of a new communication cycle. by applying a ?high? signal to the sync i/o pin, the AD9856 is set to once more begin performing the communication cycle in synchronization with the system. any information that had been written to the AD9856 registers during a valid communication cycle prior to loss of synchronization will remain intact.
AD9856 preliminary technical information 11 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 figure 4. timing diagram for data write to AD9856 t pre t sclk t dsu sclk sdio t sclkpwh t sclkpwl t dhld 1st bit 2nd bit cs symbol definition min spec t pre cs to data set up time 30 ns t sclk period of serial data clock 200 ns t dsu serial data set up time 30 ns t sclkpwh serial data clock pulse width high 80 ns t sclkpwl serial data clock pulse width low 80 ns t dhld serial data hold time 0 ns figure 5. timing diagram for read from AD9856 cs sclk sdio sdo t dv 1st bit 2nd bit symbol definition min spec t dv data valid time 30 ns
AD9856 preliminary technical information 12 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 figure 6. data write cycle, sclk idle high cs sclk sdio i0 i2 i1 i3 i5 i4 i6 i7 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 ir write phase data transfer - two byte write figure 7. data read cycle, 3-wire configuration, sclk idle low cs sclk sdio ir write phase data transfer - two byte read i0 i1 i2 i3 i4 i5 i6 i7 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 sdo msb/lsb transfers the AD9856 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the reg0<6> bit. when reg0<6> is set active high, the AD9856 serial port is in lsb first format. reg0<6> defaults low, to the msb first format. the instruction byte must be written in the format indicated by reg0<6>. that is, if the AD9856 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. multi-byte data transfers in msb format can be completed by writing an instruction byte which includes the register address of the most significant byte. in msb first mode, the serial port internal byte address generator decrements for each byte required of the multi-byte communication cycle. multi-byte data transfers in lsb first format can be completed by writing an instruction byte which includes the register address of the least significant byte. in lsb first
AD9856 preliminary technical information 13 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 mode, the serial port internal byte address generator increments for each byte required of the multi-byte communication cycle. programming/writing the ad8320 cable driver amplifier gain control programming the gain control register of the ad8320 programmable cable driver amplifier can be accomplished via the AD9856 serial port. four 8-bit registers (one per profile) within the AD9856 store the gain value to be written to the ad8320. the ad8320 is written via three dedicated AD9856 output pins that are directly connected to the ad8320?s serial input port. the transfer of data from the AD9856 to the ad8320 will occur upon detection of three conditions. each is described below: 1. power-up reset - the AD9856, upon initial power-up, will write the ad8320 gain control register to all zeros (minimum gain). 2. change in profile selection bits (ps1, ps0) - the AD9856 samples the ps1, ps0 input pins and writes the ad8320 gain control register when a change in profile is determined. the data written to the ad8320 comes from the gain control register associated with the current profile. 3. serial port write of AD9856 registers that contain ad8320 data - the AD9856 will write the ad8320 with data from the gain control register associated with the current profile whenever any AD9856 gain control register is written to. the user does not have to write the AD9856 in any particular order or be concerned with time between writes. if the AD9856 is currently writing the ad8320 while one of the four AD9856 gain control registers is being written, the AD9856 will immediately terminate the ad8320 write sequence (without updating the ad8320) and begin a new ad8320 write sequence. figure 8. programmable cable driver amplifier output control interface timing 8 clock cycles gain transfer (g1) valid data word g1 msb...lsb valid data word g2 gain transfer (g2) ca clk ca data ca enable t ds t ck t wh t es t eh symbol definition min. spec. t d s ca data setup time 6.5 ns t dh ca data hold time 2 ns t wh clock pulse high 9 ns t ck clock period 25 ns t es ca enable setup time 17 ns t eh ca enable hold time 2.0 ns
AD9856 preliminary technical information 14 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 input formatter - clock domains the AD9856 contains programmable phase-locked loop circuitry that multiplies up the external reference clock frequency input (refclk) by integer values, programmable from 4 to 20, to generate the internal reference clock frequency (fmax). the maximum internal clock frequency is 180 mhz. all other internal clock domains are generated from fmax. separate clock domains exist for the halfband filters and input format logic. equations 1-5 relate the clock domains to refclk for profiles that do not bypass the third halfband filter. mult is the programmable 5-bit register value. interprate is the current interpolation rate of the cic filter as selected by the profile bits. fmax = refclk*mult= f5 (eq. 1) f4 = (refclk*mult)/interprate (eq. 2) f3 = f4/2 = (refclk*mult)/(interprate*2 ) (eq. 3) f2 = f3/2= (refclk*mult)/(interprate*4 ) (eq. 4) f1 = f2/2=(refclk*mult)/(interprate*8) (eq. 5) the input data format data rate is a function of the fmax clock rate and the input format mode chosen via the reg1<1:0> bits. if the reg1<1:0> bit is programmed to ?1x?, the input format selected is a 12-bit word (full word mode). for burst operation, in full word mode, the input timing diagram is shown in figure 9. the data rate, related to fmax, is given in equation 6. fin = f2 = (refclk*mult)/(interprate*4) (eq. 6) if the reg1<1:0> bits are programmed to 01, the input format selected is a 6-bit word (half word mode). for burst mode operation in half word mode, the input timing diagram is shown below in figure 10. the data rate, related to fmax is given by equation 7. fin = f3 = (refclk*mult)/(interprate*2) (eq. 7) if the reg1<1:0> bits are programmed to 00, the input format selected is a 3-bit word (quarter mode). for burst mode operation in quarter word mode, the input timing diagram is shown below in figure 11. the data rate, related to fmax, is given by equation 8. fin = f4 = (refclk*mult)/interprate (eq. 8) i/q data synchronization the AD9856 accepts i/q data pairs in 2?s complement numbering system, in three different word length modes. for all input format modes, the AD9856 input formatter logic outputs to the data path circuitry, parallel 12-bit i/q pairs at the data rate f1, as given in equation 5 above. if the bphb3 filter is set, the parallel 12-bit i/q pairs are output at f2 as described in equation 4. programmable input format modes are: 12-bit, 6-bit, or 3-bit, in burst mode operation. in continuous mode operation, only the 12-bit input format is accepted.
AD9856 preliminary technical information 15 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 12-bit input format figures 9-11 show the timing relationship between txenable and d<11:0> inputs. note that the AD9856 expects the 12-bit i data followed by the 12-bit q data. i and q are 2?s complement numbers, the sign bit is d<11> in notation i<11:0>, q<11:0>. figure 9. 12-bit i/q input word format diagram txenable 12-bit input word i0 q0 i1 q1 i2 q2 in qn figure 10. 6-bit i/o input word format diagram txenable 6-bit input word note: in0 (11:6) and in1 (5:0) are combined in i<11:0> (same for q) i00 i01 q00 q01 i10 i11 in0 in1 figure 11. 3-bit i/o input word format diagram txenable 3-bit input word note: in0, in1, and in2 are combined i<11:0> (same for q) i00 i01 i02 q00 q01 q02 qn0 qn1 the AD9856 actually uses the fmax clock rate to sample the d<11:0> inputs. the user only has to provide data, at the proper data rate, synchronous to the rising edge of txenable. the data rate change from fmax to f1 occurs approximately in the middle of each i/q input period. (see timing diagram in figure 12 below).
AD9856 preliminary technical information 16 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 figure 12. input i/q data sampling scheme (12-bit full word mode, interpolation = 5, no halfband filter bypass) fmax clock 1 2 3 4 10 11 19 20 31 30 29 21 24 txenable i 0 q 0 d(11:0) store i d(11:0) at clock #10 store q d(11:0) at clock #30 determing the i/q input sample point for the above setup conditions: for: refclk =10 mhz mult = 18 interp = 5 fmax = 180 mhz f4 = 180/5 = 36 mhz f3 = 36/2 = 18 mhz f2= 18/2 = 9 mhz f1 = 4.5 mhz fin = 9.0 mhz the i/q data period = 180 mhz/9.0 mhz = 20 fmax clock cycles conditions for maximum input data sampling rate the following would be the conditions for achieving the maximum input data sampling rate with the AD9856 device: 12-bit parallel input mode refclk = 10 mhz mult = 18 fmax = 180 mhz interp rate = 2 (halfband3 is bypassed) in this case, halfband2 out rate is 90 mhz halfband1 out rate is 45 mhz the formatted parallel i/q rate is 22.5 mhz the sample rate at the input of the AD9856 is 45 mhz
AD9856 preliminary technical information 17 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 understanding and using pin selectable modulator profiles the AD9856 quadrature digital upconverter is capable of storing four pre-configured modulation modes called ?profiles? that define the following: output frequency - 32-bits (register names: ftw1, ftw2, ftw3, ftw4) interpolation rate - 6 bits (bit names: int1, int2, int3, int4) spectral inversion status - 1 bit (bit names: si1, si2, si3, si4) bypass 3 r d half-band filter - 1 bit (bit names: bphb1, bphb2, bphb3, bphb4) gain control of ad8320 - 8 bits (register names: gs1, gs2, gs3, gs4) output frequency : this attribute consists of four 8-bit words loaded into four register addresses to form a 32-bit frequency tuning word (ftw) for each profile. the lowest register address corresponds to the least significant 8-bit word . ascending addresses correspond to increasingly significant 8-bit words. the output frequency equation is given as : fout = ( ftw*fclk)/2^32. interpolation rate : consists of a 6-bit word representing the allowed interpolation values from 1 to 63. interpolation is the mechanism used to ?up-sample? or multiply the input data rate such that it exactly matches that of the dds sample rate (fmax). this implies that the system clock must be an exact multiple of the symbol rate. this 6-bit word represents the 6 msb?s of the eight bits allocated for that address. the remaining two bits contain the spectral inversion status bit and half-band bypass bit (see below). spectral inversion : consists of a 1-bit word that when at logic 0 the default or ?non-inverted? output from the adder is sent to the following stages. a logic 1 will cause the inverted output to be sent to the following stages. the non-inverted output is described as i* cos (wt) - q*sin(wt). the inverted output is described as i* cos (wt) + q*sin(wt). this bit is located adjacent to the lsb at the same address as the interpolation rate (see above). by-pass third half-band filter : a 1- bit word located in the lsb position of the same address as the interpolation rate (see above). when this bit is logic 0, the third half-band filter (one of three such filters) is engaged and its inherent 2x interpolation rate is applied. when this bit is logic 1, the third half-band filter is by-passed and the 2x interpolation rate is negated. this allows users to input higher data rates - rates that may be too high for the minimum interpolation rate if all three half-band filters with their inherent 2x interpolation rate are engaged. the overall effect is to reduce minimum interpolation rate from x8 to x4. ad8320 gain control : an 8-bit word that controls the gain of an ad8320 programmable gain amplifier connected to the ad9853 with the 3-bit spi interface bus. gain range is from -10 db (00hex) to +26 db ( ffhex). the gain is linear in v/v/lsb and follows the equation : av = .316 + .077 x code. where ?code? is the decimal equivalent of the 8-bit gain word.
AD9856 preliminary technical information 18 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 profile selection : after profiles have been loaded into the appropriate registers, the user may select which profile to use with two input pins: ps1 and ps0, pins 14 and 15. profiles are selected according to the table below. ps1 ps0 profile 0 0 1 0 1 2 1 0 3 1 1 4 except while in fsk mode, it is recommended that users disable the tx enable function by bringing that pin to logic 0 prior to changing from one profile to another and then re-asserting tx enable afterwards. this assures that any discontinuities resulting from register data transfer are not transmitted up or downstream. furthermore, changing interpolation rates ?mid-stream? may create an unrecoverable digital overflow condition that would interrupt transmission until a reset and reloading procedure would be completed. figure 13. basic implementation of AD9856 digital modulator and ad8320 programmable cable driver amplifier in hfc 5-65 mhz return-path application. ad8320 programmable cable driver amplifier 75 ohm lp filter 75 to 75 ohm cable plant control bus data in ciu control processor 75 direct control lines AD9856 quadrature digital upconverter enable and gain control bus 8-20 mhz ref clock in diplexer upstream downstream
AD9856 preliminary technical information 19 this advanced datasheet describes a product which is in the development stage. specifications and pin-out are subject to change without notice. for additional information please contact analog devices, high-speed converter group, 7910 triad center drive, greensboro, nc, 27409 tel: 336/605-4365 rev. 6/2/98 figure 14. mechanical outline 48-lead thin quad flatpack ic package (tqfp) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 1 3 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 - 7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09) for further information on this device contact: jim surber analog devices, inc. 7910 triad center drive greensboro, nc 27410 p 336/605-4365 f 336/605-4187 email jim.surber@analog.com or rick cushing analog devices, inc. 7910 triad center drive greensboro, nc 27410 p 336/605-4258 f 336/605-4187 email rick.cushing@analog.com

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