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| dfe-q v2.1 quad isdn 2b1q echocanceller digital front end pef 24911 version 2.1 data sheet, ds 3, july 2001 wired communications never stop thinking.
edition 2001-07-16 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 7/16/01. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. wired communications data sheet, ds 3, july 2001 never stop thinking. dfe-q v2.1 quad isdn 2b1q echocanceller digital front end pef 24911 version 2.1 for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com pef 24911 revision history: 2001-07-16 ds 3 previous version: data sheet 11.00 ds 2 page subjects (major changes since last revision) page 13 new function: disable super frame marker introduced on pin 16: dsfm page 13 page 13 , page 39 refined description of pin 49: crcon especially, crcon = ?1? selects mfilt= 001 1 0xxx (erroneously, mfilt= 0000 10xx was documented in ds2) page 28 added note: mon-12 read access is impossible in state ?deactivated? page 43 restriction: paca/pace must not be used during local loopback active page 54 c/i-command ltd added (function as in v1.x) page 63 ar0 and arx set uoa = ?1? (before: ar0 and arx set uoa to the same value as the received sai bit) page 95 page 130 refined description ?framer / deframer loopback?: - always transparent - prerequisite is transparent state page 97 bit error rate counter: refined operational description page 103 data through is only test mode, c/i-command = arl must not be applied when pin dt = ?1? page 113 refined description of ?control via mon-2? page 119 removed ?propagation delay measurement?: function not supported page 120 refined description of mode register evaluation timing page 121 removed description opmode.mode1,0: no settings possible page 125 page 127 sai-evaluation / uoa-control: - m4rmask.bit6: only sai-reporting via mon-2 is selected - m4wmask.bit6: in addition to uoa-bit control, also sai-evaluation by the state machine is selected; refined description (see also figure 21 and figure 22 ) page 129 changed test.bit6 = ?1? (not ?0?) page 130 statemachine is put into transparent state by trans=?0? (not ?1?) page 135 refined reset timing description; added 900s internal delay to figure page 136 refined description of fsc / superframe-fsc-timing page 137 table 21 : max. connection resistance specified page 139 removed input capacitance of pin xin (pin xin is not supported) pef 24911 table of contents page data sheet 2001-07-16 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 pinning changes from dfe-q v1.3 to dfe-q v2.1 . . . . . . . . . . . . . . . . . 19 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 iom?-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 iom?-2 interface frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.2 superframe marker function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.3 iom?-2 command/ indicate channel . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.4 iom?-2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.5 mon-12 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 interface to the analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4 general purpose i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6 u-transceiver functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 2b1q frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.8 maintenance channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.8.1 m4 bit reporting to state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.8.2 m4, m5, m6 bit control mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.8.3 start of maintenance bit evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.9 embedded operations channel (eoc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.10 eoc processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.11 cyclic redundancy check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.12 scrambling/ descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.13 encoding/ decoding (2b1q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.14 c/i codes (2b1q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.15 state machine notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.16 lt mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.16.1 inputs to the u-transceiver in lt-mode . . . . . . . . . . . . . . . . . . . . . . . . 58 3.16.2 outputs of the u-transceiver in lt-mode . . . . . . . . . . . . . . . . . . . . . . . 62 3.16.3 lt-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3 layer 1 activation/ deactivation procedures . . . . . . . . . . . . . . . . . . . . . . . 71 pef 24911 table of contents page data sheet 2001-07-16 4.3.1 complete activation initiated by lt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.2 activation with act-bit status ignored by the exchange side . . . . . . . 74 4.3.3 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.3.4 complete deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.3.5 partial activation (u only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.3.6 activation initiated by lt with u active . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.3.7 activation initiated by te with u active . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.3.8 deactivating s/t-interface only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.4 maintenance and test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.4.1 test loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.4.1.1 analog loopback (no.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.4.1.2 loopback no.2 - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.4.1.3 loopback no.2 - complete loopback . . . . . . . . . . . . . . . . . . . . . . . . 91 4.4.1.4 loopback no.2 - single channel loopbacks . . . . . . . . . . . . . . . . . . . 93 4.4.1.5 local loopbacks featured by register loop . . . . . . . . . . . . . . . . . 95 4.4.2 bit error rate counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.4.3 block error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.4.3.1 near-end and far-end block error counter . . . . . . . . . . . . . . . . . . . 97 4.4.3.2 testing block error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.4.4 system measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4.4.1 single-pulses test mode (ssp) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4.4.2 data through test mode (dt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4.4.3 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4.4.4 pulse mask measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.4.4.5 power spectral-density measurement . . . . . . . . . . . . . . . . . . . . . . 104 4.4.4.6 total power measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.4.4.7 return-loss measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.4.4.8 quiet mode measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.4.4.9 insertion loss measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.4.5 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5 monitor commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.1 mon-0 - exchanging eoc information . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.2 mon-2 - exchanging overhead bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3 mon-8 - local functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.1 register summary 118 6.2 reset of u-transceiver functions in state ?deactivated? . . . . . . . . . . . . 120 6.3 mode register evaluation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.4 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.4.1 lp_sel - line port selection register . . . . . . . . . . . . . . . . . . . . . . . . 121 pef 24911 table of contents page data sheet 2001-07-16 6.4.2 opmode - operation mode register . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.4.3 mfilt - m-bit filter options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.4.4 m4rmask - m4 read mask register . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.4.5 m4wmask - m4 write mask register . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.4.6 test - test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.4.7 loop - loop back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.4.8 febe - far end block error counter register . . . . . . . . . . . . . . . . . . 132 6.4.9 nebe - near end block error counter register . . . . . . . . . . . . . . . . . 132 6.4.10 berc - bit error rate counter register . . . . . . . . . . . . . . . . . . . . . . . 132 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7.4.1 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.4.2 iom?-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 7.4.3 interface to the analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.4.4 boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7.5 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.6.1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.6.2 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9 appendix a: standards and specifications . . . . . . . . . . . . . . . . . . . . 141 10 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 pef 24911 list of figures page data sheet 2001-07-16 figure 1 dfe-q/ afe 2nd generation chip set . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3 16-line card application with delic solution. . . . . . . . . . . . . . . . . . . . 5 figure 4 16-line card application with elic ? / idec ? solution . . . . . . . . . . . . . 6 figure 5 connecting two afe/dfe-q chip sets . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6 recommended clocking scheme for more than two dfe-q/afe chip sets 8 figure 7 pin configuration (63 of 64 used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8 block diagram and data flow (dfe-q v2.1 + afe v2.1) . . . . . . . . . . 20 figure 9 clock supply and data exchange between master and slave . . . . . . 21 figure 10 multiplexed frame structure of the iom ? -2 interface . . . . . . . . . . . . . 23 figure 11 superframe marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12 handshake protocol with a 2-byte monitor message/response . . . . . 26 figure 13 abortion of monitor channel transmission . . . . . . . . . . . . . . . . . . . . . 28 figure 14 interface to the analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15 frame structure on sdx/sdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16 u-superframe structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17 u-basic frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18 mon-0/2 - m-bit correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 19 maintenance channel filtering options. . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20 m4 bit report timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21 m4, m5, m6 bit control in transmit direction . . . . . . . . . . . . . . . . . . . 44 figure 22 m4, m5, m6 bit control in receive direction . . . . . . . . . . . . . . . . . . . . 44 figure 23 eoc-procedure in auto- and transparent mode. . . . . . . . . . . . . . . . . 49 figure 24 crc-process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 25 scrambler/ descrambler algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 26 explanation of the state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 27 state transition diagram in lt-mode . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 28 complete activation initiated by lt . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 29 activation with act-bit status ignored by the exchange . . . . . . . . . . 75 figure 30 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 31 complete deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 32 u only activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 33 lt initiated activation with u-interface active . . . . . . . . . . . . . . . . . . . 82 figure 34 te-activation with u active and exchange control (case 1) . . . . . . . . 84 figure 35 te-activation with u active and no exchange control (case 2) . . . . . 86 figure 36 deactivation of s/t only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 37 test loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 38 complete loopback options in the nt . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 39 loopbacks featured by register loop . . . . . . . . . . . . . . . . . . . . . . . 96 figure 40 block error counter test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 41 total power measurement set-up. . . . . . . . . . . . . . . . . . . . . . . . . . . 104 pef 24911 list of figures page data sheet 2001-07-16 figure 42 dfe-q v2.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 43 input/output waveform for ac tests. . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 44 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 45 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 46 boundary scan timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 pef 24911 list of tables page data sheet 2001-07-16 table 1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2 pinning changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3 iom ? -2 data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4 assignments of iom ? channels to time-slots no. on sdx/sdr and line ports no. 30 table 5 2b1q coding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 6 2b1q u-frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 7 overhead bits filter setting by crcon pin . . . . . . . . . . . . . . . . . . . . 40 table 8 supported eoc-commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 9 2b1q coding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 10 command / indicate codes (2b1q). . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 11 timers used in lt-modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 12 u-interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 13 boundary scan cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 14 tap controller instructions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 15 mon-0 functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 16 mon-2 and overhead bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 17 mon-8-local function commands . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 18 register map reference table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 19 iom ? -2 dynamic input characteristics . . . . . . . . . . . . . . . . . . . . . . . 136 table 20 iom ? -2 dynamic output characteristics. . . . . . . . . . . . . . . . . . . . . . 137 table 21 interface signals of afe and dfe-q . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 22 boundary scan dynamic timing requirements . . . . . . . . . . . . . . . . 138 table 23 power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 pef 24911 introduction data sheet 1 2001-07-16 1 introduction the quad isdn 2b1q echocanceller digital front end (dfe-q) is the digital part of an optimized two-chip solution featuring 4x isdn basic rate access and idsl access at 144 kbit/s. the pef 24911 is designed to provide in conjunction with the quad isdn echocanceller analog front end (pef 24902 v2.1) full duplex data transmission at the u-reference point according to ansi t1.601 (1998), etsi ts 102 080 (1998) and itu- t g.961 standards. the dfe-q 2nd generation has been completely reengineered to guarantee the availability of the well proved dfe-q/afe solution over the year 2000. the pef 24911 v2.1 is downwards pin compatible and functionally equivalent to the dfe-q v1.x. thus, line card manufacturers can make use of the most advanced process technology without the need to change their current design (besides the changeover to 3.3 v power supply). no software changes are required if the dfe-q v2.1 is deployed in existing dfe-q v1.x solutions. some new features are provided such as free programmable filtering options for the maintenance bits (m1-6) and enhanced monitoring and test functions. the data rate is programmable from 1 mbit/s to 4 mbit/s. figure 1 dfe-q/ afe 2nd generation chip set the output and input pins are throughout 5 v ttl compatible although the pef 24911 is processed in advanced 3.3 v cmos technology. a power down state with very low power consumption is featured. the pef 24911 comes in a p-mqfp-64 package. dfe-q v2.1 pef 24911 hyb r id hyb r id hyb r id hyb r id 4x u iom ? -2 relay driver/ power controller afe v2.1 pef 24902 15.36mhz chipset.vsd data sheet 2 2001-07-16 type package pef 24911 p-mqfp-64 quad isdn 2b1q echocanceller digital front end dfe-q v2.1 pef 24911 version 2.1 p-mqfp-64 1.1 features u-interface digital part of a two-chip solution featuring full duplex data transmission and reception over two-wire metallic subscriber loops providing 4x isdn basic rate access or idsl access at 144 kbit/s conforms to: ? ansi t1.601 ? 1998 ? etsi ts 102 080 (1998) ? recommendation itu-t g.961 2b1q-block code (2 binary, 1 quaternary) at 80-khz symbol rate lt mode data rate of the system interface programmable activation/ deactivation controller 15 s start-up guard timer (t1) can be disabled for use in repeater applications adaptive echo cancellation and equalization automatic gain control and polarity adaptation clock recovery (frame and bit synchronization) in all applications built-in wake-up unit for activation from power-down state. system interface iom ? -2 interface with programmable data rates (1 mbit/s to 4 mbit/s) sw controlled i/o ports for relay driver and power feeder control ? 4 relay driver pins per port ? 2 status pins per port pef 24911 introduction data sheet 3 2001-07-16 others software compatible to pef 24911 v1.3 (quad iec dfe-q) inputs and outputs 5 v ttl compatible dout (open drain) accepts pull-up to 3.3 v or 5 v +3.3 v 0.3 v power supply advanced low power cmos technology extended temperature range ( ? 40...to 85 c) boundary-scan, jtag ieee 1149.1 add-on features and differences with respect to dfe-q v1.3/v1.2/v1.1 max. iom ? -2 data rate 4 mbit/s (dcl= 8 mhz) +3.3 v instead of +5 v power supply dedicated pins for ssp and dt test modes dout configurable either as open drain or push-pull (tristate) output new mon-12 class features internal register access coefficients retrievable by mon-12 commands instead of mon-8 commands advanced filter options for mon-0 and mon-2 messages bit error rate measurement per port additional digital local loops c/i codes ? ltd ? and ? hi ? are no more supported optimized lt-state machine jtag boundary-scan with dedicated reset line trst (replaces power-on reset functionality) addressed applications isdn line cards for central office isdn line cards for access networks isdn line cards in pbx systems idsl line cards pef 24911 introduction data sheet 4 2001-07-16 1.2 logic symbol figure 2 logic symbol dfe-q v2.1 fsc dcl din dout slot1 cl15 cls0 sdx sdr pdm 0 .. 3 ssp d0a, d0b, d0c, d0d d3a, d3b, d3c, d3d st00, st01 4 4 afe/dfe interface relay driver/ status pins mode settings iom ? -2 interface iom ? -2 mode pins logsym.emf cls1 st30, st31 2 2 4 cls2 cls3 res clocks pup dt +3.3v 0v 4 vdd vss 4 tm s tck tdi tdo trst boundary scan crcon auto slot0 pef 24911 introduction data sheet 5 2001-07-16 1.3 system integration this paragraph shows how the dfe-q v2.1 may be integrated in systems using other infineon isdn devices. the pef 24911 dfe-q is optimized for use in the following applications: ? digital line cards for central office ? digital line cards for access networks (lt mode only) ? pbx applications (lt mode only) figure 3 and figure 4 illustrate line card solutions with various infineon line card controllers. the delic-pb (peb 20571) supersedes the elic ? (peb 20550) and will feature up to 32 hdlc controllers on-chip.the delic controls up to 4 devices of dfe- q v2.1 on a single iom ? -2 interface. in this application an additional clock doubler is necessary to generate the 8.192 mhz dcl clock for the dfe-q derived from the 4.096 mhz bcl clock of the delic. figure 3 16-line card application with delic solution test unit q-ihpc peb 2426 4 3 2 1 afe v2.1 pef 24902 dfe-q v2.1 pef 24911 delic-pb peb 20571 ram c iom-2 pcm hw signalling appl_delic.vsd pef 24911 introduction data sheet 6 2001-07-16 figure 4 16-line card application with elic ? / idec ? solution figure 5 shows how an 8 channel line card application is realized by use of two afe/ dfe-q chip sets: one afe-pll generates the synchronized 15.36 mhz clock and provides the master clock at pin cl15 for the other 3 devices. the internal pll of the first afe synchronizes the 15.36 mhz master clock onto a ptt reference clock of either 8 khz or 2048 khz. infineon recommends to feed the fsc clock input of the dfe-q v2.1 and the pll reference clock input (pin clock) of the afe from the same clock source. the pll of the second afe is deactivated. the 15.36 mhz master clock is applied at pin cl15. cl15 is configured as input if xin is clamped either to vdd or to vss. pin xout has to be left open and clock shall be tied to gnd. pcm highw a y c-bus signalling test unit q-ihpc p eb 2426 4 3 2 1 afe v2.1 pef 24902 dfe-q v2.1 pef 24911 iom ? -2 appl_eli c.vsd idec peb 2075 elic peb 20550 c c165/6 pef 24911 introduction data sheet 7 2001-07-16 figure 5 connecting two afe/dfe-q chip sets the dfe-q devices are supplied by the first afe at pin cl15 with the synchronized 15.36 mhz clock. the iom ? -2 channels the dfe-q devices are assigned to can be programmed by the two slot pins. starting from channel no. 0/4/8/12 always four subsequent channels are occupied. alternatively the clocking scheme as shown in figure 6 may be applied if more than 3 devices are to be clocked (e.g. in a 16-channel line card application). instead to supply the 2nd afe with the master clock at pin cl15, here the 15.36 mhz master clock is input at pin xin. thereby pin cl15 is configured as output and passes the 15.36 mhz clock on to the attached dfe-q. if the clock chain is extended in the same way by another two afe/dfe-q chip sets a 16-channel line card application can be realized with just one single crystal. note that the 15.36 mhz clock is inverted once by the afe if it is input at xin and output at cl15. this way the duty cycle is recovered again. dfe-q v2.1 pef 24911 hyb r id hyb r id hyb r id hyb r id 4x u iom ? -2 afe v2.1 pef 24902 15.36mhz clkchain1.vsd pdm0..3 sdr sdx 15.36mhz dfe-q v2.1 pef 24911 hyb r id hyb r id hyb r id hyb r id 4x u afe v2.1 pef 24902 pdm0..3 sdr sdx 15.36mhz fsc dcl din dout cl15 cl15 cl15 cl15 xin xout clock 8/ 2048khz ptt reference cock xin xout clock n.c. vdd/ vss vss 1-4mbit/s pef 24911 introduction data sheet 8 2001-07-16 figure 6 recommended clocking scheme for more than two dfe-q/afe chip sets dfe-q v2.1 pef 24911 hyb r id hyb r id hyb r id hyb r id 4x u iom ? -2 afe v2.1 pef 24902 15.36mhz c lkc hai n2.vs d pdm0..3 sdr sdx 15.36mhz dfe-q v2.1 pef 24911 hyb r id hyb r id hyb r id hyb r id 4x u afe v2.1 pef 24902 15.36mhz fsc dcl din dout cl15 cl15 cl15 xin xout clock 8/ 2048khz ptt reference cock 1-4mbit/s xin xout clock n.c. vss cl15 pdm0..3 sdr sdx 15.36mhz hyb r id hyb r id hyb r id hyb r id 4x u afe v2.1 pef 24902 15.36mhz xin xout clock n.c. vss cl15 pef 24911 introduction data sheet 9 2001-07-16 1.4 operational overview the dfe-q v2.1 operates always in lt mode. other operating modes known from former versions of the dfe-q are not further supported. system interface configurations the following parameters of the system interface are configurable: open drain/ push-pull mode configured as open drain the output pin dout is floating and a pull-up resistor is required. in push-pull mode the output pin is high impedance outside the active time slots. iom ? -2 channel assignment iom ? -2 channels are always assigned in blocks of four. iom ? -2 data rates send single pulses test mode in test mode ? send single pulses ? +/-3 pulses spaced by 1.5 ms are transmitted on all u lines. the test mode is activated by pin ssp= set to ? 1 ? . the ssp test function can be as well stimulated by c/i= ssp besides the fact that the hw selection impacts all line ports while the sw selection impacts only the chosen line. slot1 slot0 assigned iom ? -2 channels 00 0 .. 3 01 4 .. 7 1 0 8 .. 11 1 1 12 .. 15 dcl frequency [khz] data rate [kbit/s] iom ? -2 channels 2048 1024 4 3072 1536 6 4096 2048 8 6144 3072 12 8192 4096 16 pef 24911 introduction data sheet 10 2001-07-16 data through mode in test mode ? data through ? the u-transceiver is forced to enter the ? transparent ? state and to issue sl3t (see table 12 ) independently of the wake-up protocol. the dt test mode is activated by pin dt= set to ? 1 ? . the dt test function can be as well stimulated by c/i= dt besides the fact that the hw selection impacts all line ports while the sw selection impacts only the chosen line. pef 24911 pin descriptions data sheet 11 2001-07-16 2 pin descriptions 2.1 pin diagram (top view) figure 7 pin configuration (63 of 64 used) trst dt cls3 res auto pbx ssp slot0 vdd lt cls2 d3d d2d crcon vss tck p-mqfp-64 12345 6789101112 141516 13 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 tms tdi tdo cl15 sdr vdd pdm3 pdm2 vss pdm1 pdm0 dcl fsc din dout dsfm pinning.vsd 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 d2a d3a d0b n.c. d1b vdd d2b d3b vss d0c slot1 d3c d0d d1d 44 d1c d2c pup 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 cls1 st21 vss st01 d1a d0a cls0 st00 st10 st11 st30 st31 sdx st20 vdd pef 24911 pin descriptions data sheet 12 2001-07-16 2.2 pin definitions and functions table 1 pin definitions and functions pin no. symbol input (i) output (o) function iom ? -2 interface 13 fsc i frame synchronization clock (8khz) the start of the first b1-channel in time-slot 0 is marked, fsc is expected to be ? 1 ? for at least two dcl periods. 12 dcl i data clock clock rate ranges from 2048 to 8192 khz (1024 to 4096 kbit/s) 14 din i data in input of iom ? -2 data synchronous to dcl clock 15 dout o (od/ pup) data out output of iom ? -2 data synchronous to dcl clock mode selection pins 60 res i reset triggers asynchronous hw reset, schmitt trigger input ? 1 ? = inactive ? 0 ? = active 55 slot0 i iom ? -2 channel slot selection 0 assigns iom ? -2 channels in blocks of 4 slot1, 0: ? 00 ? = iom ? -2 channels 0 to 3 ? 01 ? = iom ? -2 channels 4 to 7 ? 10 ? = iom ? -2 channels 8 to 11 ? 11 ? = iom ? -2 channels 12 to 15 45 slot1 i (pd) iom ? -2 channel slot selection 1 assigns iom ? -2 channels in blocks of 4 pef 24911 pin descriptions data sheet 13 2001-07-16 16 dsfm i (pd) disable super frame marker ? 1 ? = inhibits the evaluation of the super frame marker on fsc. i.e the transmitted super- frame is not affected by an fsc pulse shorter than 2 dcl clock periods. ? 0 ? = the position of the transmitted superframe is synchronized to short fsc pulses. 32 pup i (pd) push pull mode in push pull mode ? 0 ? and ? 1 ? is actively driven during an occupied time slot, outside the active time slots dout is high impedance (tristate) ? 1 ? = configures dout as push/pull output ? 0 ? = configures dout as open drain output 49 crcon i (pd) crc check on/off defines the condition on which mon-2 messages and m4 bit will be passed on, the setting has effect on all ports (see table 7 ). pin crcon is evaluated only after hardware reset. ? 1 ? = crc check on mon-2 messages are not issued and m4-bit are not forwarded to the statemachine if the crc-check of the u-superframe containing m4-bit changes is not ok. (mfilt= 0011 0xxx) ? 0 ? = crc check off mon-2 messages are issued every time a change in at least one of the overhead bits (m4,5,6) of the u-interface is detected, regardless of the crc checksum status. m4-bit are forwarded to the statemachine with triple-last-look filtering (tll). (mfilt= 0000 0xxx) 53 lt i reserved, clamp to high table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) function pef 24911 pin descriptions data sheet 14 2001-07-16 58 pbx i reserved, clamp to low 59 auto i eoc auto mode selects auto or transparent mode for eoc channel processing, the setting has effect on all ports ? 1 ? = eoc auto mode (mfilt= xxxx x100) ? 0 ? = eoc transparent mode (mfilt= xxxx x001) 56 ssp i send single pulses (ssp) test mode ? 1 ? = alternating +/-3 pulses are issued at all line ports in 1.5 ms intervals ? 0 ? = deactivated, clamp to gnd if not used this pin function corresponds to the sw selection by c/i= ssp besides the fact that the hw selection impacts all line ports while the sw selection impacts only the chosen line 62 dt i data through (dt) test mode enables/disables dt test mode ? 1 ? = dt test mode enabled, the u-transceiver is forced on all line ports to enter the ? transparent ? state ? 0 ? = dt test mode disabled this pin function corresponds to the sw selection by c/i= dt besides the fact that the hw selection impacts all line ports while the sw selection impacts only the chosen line interface to the analog front end 4 cl15 i 15.36 mhz master clock input 11 pdm0 i pulse density modulated receive data of line port 0 pulse density modulated bit stream from the pef 24902 quad afe that is output from the second-order sigma-delta adc table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) function pef 24911 pin descriptions data sheet 15 2001-07-16 10 pdm1 i pulse density modulated receive data of line port 1 pulse density modulated bit stream from the pef 24902 quad afe that is output from the second-order sigma-delta adc 8 pdm2 i pulse density modulated receive data of line port 2 pulse density modulated bit stream from the pef 24902 quad afe that is output from the second-order sigma-delta adc 7 pdm3 i pulse density modulated receive data of line port 3 pulse density modulated bit stream from the pef 24902 quad afe that is output from the second-order sigma-delta adc 5 sdr i serial data receive line interface signal from the pef 24902 quad afe that transports level detect information for the wake-up recognition of all 4 lines by use of tdm 17 sdx o serial data transmit line interface to the pef 24902 quad afe for the transmit and control data. transmission is based on clock cl15 (15.36 mbit/s). for each line port the following bits are exchanged: td0, td1: transmit data range: range select loop: analog loopback switch pdow: power down/power up synchronization information table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) function pef 24911 pin descriptions data sheet 16 2001-07-16 relay driver/ status pins 30, 35, 42, 47 d0a d0b d0c d0d o relay driver pins of line port 0 addressable via mon-8 command in iom ? -2 channel 0/4/8/12. the logic values of the bit positions a,b,c, d of the mon-8 command ? setd ? determine the output setting. default value after pin-reset is low. c/i-code reset does not affect the current status. 31, 37, 43, 48 d1a d1b d1c d1d o relay driver pins of line port 1 addressable via mon-8 command in iom ? -2 channel 1/5/9/13. the logic values of the bit positions a,b,c, d of the mon-8 command ? setd ? determine the output setting. default value after pin-reset is low. c/i-code reset does not affect the current status. 33, 39, 44, 50 d2a d2b d2c d2d o relay driver pins of line port 2 addressable via mon-8 command in iom ? -2 channel 2/6/10/14. the logic values of the bit positions a,b,c, d of the mon-8 command ? setd ? determine the output setting. default value after pin-reset is low. c/i-code reset does not affect the current status. 34, 40, 46, 51 d3a d3b d3c d3d o relay driver pins of line port 3 addressable via mon-8 command in iom ? -2 channel 3/7/11/15. the logic values of the bit positions a,b,c, d of the mon-8 command ? setd ? determine the output setting. default value after pin-reset is low. c/i-code reset does not affect the current status. 28, 27 st00 st01 i status pin of line port 0 change of status is passed to iom ? -2 channel 0/4/8/12 via mon-8 message ? ast ? at bit positions s 0, s 1 . connect to either vdd or vss if not used. table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) function pef 24911 pin descriptions data sheet 17 2001-07-16 26, 24 st10 st11 i status pin of line port 1 change of status is passed to iom ? -2 channel 1/5/9/13 via mon-8 message ? ast ? at bit positions s 0, s 1 . connect to either vdd or vss if not used. 23, 21 st20 st21 i status pin of line port 2 change of status is passed to iom ? -2 channel 2/6/10/14 via mon-8 message ? ast ? at bit positions s 0, s 1 . connect to either vdd or vss if not used. 19, 18 st30 st31 i status pin of line port3 change of status is passed to iom ? -2 channel 3/7/11/15 via mon-8 message ? ast ? at bit positions s 0, s 1 . connect to either vdd or vss if not used. test pins 29 cls0 o 12 msec clock synchronized to the received superframe of port 0 can be used for monitoring and test purposes note: the delay between both signals may vary from activation to activation. 20 cls1 o 12 msec clock synchronized to the received superframe of port 1 can be used for monitoring and test purposes note: the delay between both signals may vary from activation to activation. 52 cls2 o 12 msec clock synchronized to the received superframe of port 2 can be used for monitoring and test purposes note: the delay between both signals may vary from activation to activation. table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) function pef 24911 pin descriptions data sheet 18 2001-07-16 od: open drain pup: push pull pd: internal pull down (e.g.. 10 to 20 kohms) pu: internal pull up (e.g.. 10 to 20 kohms) 61 cls3 o 12 msec clock synchronized to the received superframe of port 3 can be used for monitoring and test purposes note: the delay between both signals may vary from activation to activation. jtag boundary scan 64 tck i test clock 1tmsi (pu) test mode select internal pullup resistor (160 k ? ) 2tdii (pu) test data input internal pullup resistor (160 k ? ) 3 tdo o test data output 63 trst i (pu) jtag boundary scan disable resets the tap controller state machine (asynchronous reset), active low, internal pullup (160 k ? ). clamp trst to gnd if the boundary scan logic is not used ? 1 ? = reset inactive ? 0 ? = reset active power supply pins 6, 22, 38, 54 vdd 3.3v 0.3v supply voltage 9, 25, 41, 57 vss 0v ground table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) function pef 24911 pin descriptions data sheet 19 2001-07-16 2.3 pinning changes from dfe-q v1.3 to dfe-q v2.1 table 2 pinning changes pin no. v2.1 v1.3 comment 16 dsfm tpd new function for suppression of short fsc evaluation 32 pup n.c. additional push-pull mode for pin dout eases interface adaptation 36 n.c. dsync obsolete 45 slot1 n.c. increased max data rate requires additional slot pin 49 crcon crcon see page 39 53 lt lt dedicated lt mode pin is obsolete 55 slot0 slot renamed 56 ssp tsp dedicated pin for ? send single pulses ? test mode 58 pbx pbx function removed 62 dt tp dedicated pin for ? data through ? test mode 63 trst tp1 bscan power-on-reset is replaced by a dedicated reset line pef 24911 functional description data sheet 20 2001-07-16 3 functional description 3.1 functional overview a functional overview of the dfe-q v2.1 is given in figure 8 . besides the signal processing and frame formatting blocks the pef 24911 features an on-chip activation/ deactivation controller and programmable general purpose i/o pins for the control of test relays and power feeding circuits. an application specific dsp core services the four u- lines and cuts chip size to a minimum. figure 8 block diagram and data flow (dfe-q v2.1 + afe v2.1) clock generation mode setting iom-2 ? dsp ge ne r a l purpose i/os mode pins clocks 4x u level detection for wake up a g c equalizer pdm filt er + adc activation/de activation controller u protocol processing unit hybrid siu dac liu dfe-q v2.1 dataflow.vsd i/o control bandgap, bia s, refer. afe v2.1 de - scram ble r u de - fram ing 2b1q decoder system inte rface un it ec h o canceller timing recovery scram ble r u fr am in g 2b1q encoder pef 24911 functional description data sheet 21 2001-07-16 3.2 iom ? -2 interface the iom ? -2 interface is a four-wire serial interface providing a symmetrical full-duplex communication link to layer-1 and layer-2 backplane devices. it transports user data, control/programming and status information via dedicated time multiplexed channels. the structure used follows the 2b + 1 d-channel structure of isdn. the isdn-user data rate of 144 kbit/s (b1 + b2 + d) on the u-interface is transmitted transparently in both directions (u <=> iom ? ) over the interface. figure 9 clock supply and data exchange between master and slave the frame sync signal fsc is a 8 khz signal delimiting the frames. this signal is used to determine the start of a frame. the data is clocked by a data clock (dcl) which operates at twice the data rate. the data clock is a square wave signal with a duty cycle ratio of typically 1:1. incoming data is sampled on the falling edge of the dcl-clock. data is carried over data upstream (du) and data downstream (dd) signals. the upstream and downstream directions are always defined with respect to the exchange: downstream refers to information flowing from the exchange to the subscriber, upstream is defined vice versa. the output line is operating either as open drain or push-pull output. both modes are selected by signal ? pup ? . in open drain mode an external pull-up resistor is required. the absence of a pull-up resistor is not automatically recognized (i.e. no push-pull detection). dcl fsc du dd iomif.emf fsc dcl du dd iom ? -2 master iom ? -2 slave last bit of frame 1. bit of frame 2. bit of frame 3. bit of frame pef 24911 functional description data sheet 22 2001-07-16 within one fsc-period, 128 to 512 bit are transmitted, corresponding to dcl- frequencies ranging from 2048 khz up to 8192 khz. the following table shows possible operating frequencies of the iom ? -2-interface. table 3 iom ? -2 data rates 3.2.1 iom ? -2 interface frame structure the typical iom ? -2 line card application comprises a dcl-frequency of 4096 khz with a nominal bit rate of 2048 kbit/s. therefore eight channels are available, each consisting of the basic frame with a nominal data rate of 256 kbit/s. the downstream data (dd) is transferred on signal din, the upstream data (du) on signal dout. the iom ? -2 channel assignment is programmable by pin strapping (slot1,0). the basic iom ? -2 frame and clocking structure consists of: two 64-kbit/s channels b1 and b2 the monitor channel for transferring maintenance information between layer-1 and layer-2 devices two bits for the 16-kbit/s d-channel four command / indication (c/i) bits for controlling of layer-1 functions (activation/ deactivation and additional control functions) by the layer-2 controller two bits mr and mx for handling the monitor channel dcl frequency [khz] data rate [kbit/s] iom ? -2 channels 2048 1024 4 3072 1536 6 4096 2048 8 6144 3072 12 8192 4096 16 channel bits b1 b2 monitor d command / indicate mr mx 888 24 11 pef 24911 functional description data sheet 23 2001-07-16 figure 10 multiplexed frame structure of the iom ? -2 interface 3.2.2 superframe marker function the start of a new superframe is programmed by a fsc high-phase lasting for one single dcl-period. a fsc high-phase of two (or more) dcl-periods is transmitted for all other iom ? -2-frame starts. it is optional to include superframe markers in every 96th ? frame synchronization ? signal. the remaining 95 fsc-clocks must be of at least two dcl-periods duration. if no superframe marker is to be used all fsc high-phases need to be of at least two dcl- periods duration. with the sf function enabled the next outgoing basic frame on u defines the start of the u superframe by an inverted sync word (see figure 11 ). this way the positions of the iom ? -2 and the u superframe are no more arbitrary but definite within a tolerance of 1.5 ms. pef 24911 functional description data sheet 24 2001-07-16 figure 11 superframe marker if no superframe marker is to be used, all fsc high-phases need to be of at least two dcl-periods duration. the relationship between the iom ? -2-superframe on the lt-side, the u-frame and the iom ? -2-superframe on the nt-side is fixed after activation of the u-interface. i.e. data inserted on lt-side in the first b1-channel after the iom ? -2-slave superframe marker will always appear on nt-side with a fixed offset, e.g. in the 5th b1-channel after the master superframe marker. after a new activation this relationship (offset) may be different. note: the evaluation of short fsc by the dfe-q v2.1 can be suppressed by pin dsfm (see page 13 ). 3.2.3 iom ? -2 command/ indicate channel the command/indication (c/i) channel carries real-time control and status information between the dfe-q v2.1 and a layer-1 control device. a new c/i code must be applied in six consecutive iom ? -2 frames to be considered valid, unconditional commands (i.e. res, ssp, dt and commands in the states ? test ? and ? reset ? ) must be applied up to 2 ms before they are recognized. an indication is issued permanently by the dfe-q v2.1 on dout until a new indication needs to be forwarded. the c/i code is 4 bit wide and located at bit positions 27 ? 30 in each time-slot. a listing and explanation of the u-transceiver c/i codes can be found on page 3-54. 3.2.4 iom ? -2 monitor channel the monitor channel represents a second method of initiating and reading u-transceiver specific information. features of the monitor channel are supplementary to the command/indicate channel. unlike the command/indicate channel with an emphasis on status control, the monitor channel provides access to internal bits (maintenance, overhead) and test functions (local loop-backs, block error counter etc.). iom-2 frame (1) fsc iom-2 frame (12) 2b+d m bits isw sw m bits 2b+d du/ dd u fixed chip internal delay u superframe start sf_pos.emf pef 24911 functional description data sheet 25 2001-07-16 besides the known mon-0/2/8 commands a new mon class, mon-12 is introduced in the dfe-q v2.1: new mon-12 class by use of mon-12 commands the dfe-q v2.1 provides the ability to address parts of the device internal register map and thus to address functions that have been added with version 2.1. mon-12 commands are always prioritized and processed first if other monitor commands are outstanding. see chapter 3.2.5 for the details. this means that monitor commands are split into four categories. each category derives its name from the first nibble (4 bits) of the two byte long message. these are: mon-12(internal register map) mon-0(transparent channel) mon-2(overhead bits) mon-8(local functions) the order of the list above corresponds to the priority attributed to each category. mon- 12 commands are always processed first. mon-0 messages will be transmitted before mon-2 messages in case several messages are initiated simultaneously. the various mon-0, mon-2 and mon-8-commands are discussed in detail in chapter 5 , ? monitor commands ? on page 110 . structure the structure of the monitor channel is 8 bit wide, located at bit position 17 ? 24 in every time-slot. monitor commands/messages sent to/from the u-transceiver are always 2 bytes long. transmission of multiple monitor bytes is specified by iom ? -2 (see next section ? handshake procedure ? for details). for handshake control in multiple byte transfers, bit 31, monitor read ? mr ? , and bit 32, monitor transmit ? mx ? , of every time-slot are used. verification a double last-look criterion is implemented for the monitor channel. if the monitor message that was received consecutively after a change has been detected is not identical to the message that was received before the message will be aborted. handshake procedure iom ? -2 provides a sophisticated handshake procedure for the transfer of monitor messages. for handshake control two bits, mx and mr, are assigned to each iom ? -2 frame (on din and dout). the monitor transmit bit (mx) indicates when a new byte has been issued in the monitor channel (active low). the transmitter postpones transmitting the next information until the correct reception has been confirmed. a correct reception will be confirmed by setting the monitor read bit (mr) to low. pef 24911 functional description data sheet 26 2001-07-16 the monitor channel is full duplex and operates on a pseudo-asynchronous base, i.e. while data transfer on the bus takes place synchronized to frame synchronization, the flow of monitor data is controlled by the mr- and mx-bits. monitor data will be transmitted repeatedly until its reception is acknowledged. figure 12 illustrates a monitor transfer at maximum speed. the transmission of a 2-byte monitor command followed by a 2-byte response requires a minimum of 15 iom ? -2 frames (reception 7 frames + transmission 8 frames = 1.875 ms). in case the controller is able to confirm the receipt of first response byte in the frame immediately following the mx-transition on dout from high to low (i.e. in frame no. 9), 1 byte may be saved (7 frames + 7 frames). transmission and reception of monitor messages can be performed simultaneously by the u-transceiver. in the procedure depicted in figure 12 it would be possible for the u- transceiver to transmit monitor data in frames 1 ? 5 (excluding eom-indication) and receive monitor data from frame 8 onwards. m 1/2:monitor message 1. and 2. byte r 1/2:monitor response 1. and 2. byte figure 12 handshake protocol with a 2-byte monitor message/response idle state after the bits mr and mx have been held inactive (i.e. high) for two or more successive iom ? -frames, the channel is considered idle in this direction. pef 24911 functional description data sheet 27 2001-07-16 standard transmission procedure 1. the first byte of monitor data is placed by the external controller on the din line of the dfe-q v2.1 and mx is activated (low; frame no. 1). 2. the dfe-q v2.1 reads the data of the monitor channel and acknowledges by setting the mr-bit of dout active if the transmitted bytes are identical in two received frames (frame no. 2 because data are already read and compared while the mx-bit is not activated). 3. the second byte of monitor data is placed by the controller on din and the mx-bit is set inactive for one single iom ? -frame. this is performed at a time convenient to the controller. 4. the dfe-q v2.1 reads the new data byte in the monitor channel after the rising edge of mx has been detected. in the frame immediately following the mx-transition active- to-inactive, the mr-bit of dout is set inactive. the mr-transition inactive-to-active exactly one iom ? -frame later is regarded as acknowledgment by the external controller (frame no. 4 ? 5). the acknowledgement by the dfe-q v2.1 will always be sent two iom ? -frames after the activation of a new data byte. 5. after both monitor data bytes have been transferred to the dfe-q v2.1, the controller transmits ? end of message ? (eom) by setting the mx-bit inactive for two or more iom ? -frames (frame no. 5 ? 6). 6. in the frame following the transition of the mx-bit from active to inactive, the dfe-q v2.1 sets the mr-bit inactive (as was the case in step 4). as it detects eom, it keeps the mr-bit inactive (frame no. 6). the transmission of the monitor command by the controller is complete. 7. if the dfe-q v2.1 is requested to return an answer it will commence with the response as soon as possible. figure 12 illustrates the case where the response can be sent immediately. the procedure for the response is similar to that described in points 1 ? 6 except for the transmission direction. it is assumed that the controller does not latch monitor data. for this reason one additional frame will be required for acknowledgement. transmission of the 2nd monitor byte will be started by the dfe-q v2.1 in the frame immediately following the acknowledgment of the first byte. the u-transceiver does not delay the monitor transfer. transmission abortion if no eom is detected after the first two monitor bytes, or received bytes are not identical in the first two received frames, transmission will be aborted through receiver by setting the mr-bit inactive for two or more iom ? -2-frames. the controller reacts with eom. this situation is illustrated in figure 13 . pef 24911 functional description data sheet 28 2001-07-16 figure 13 abortion of monitor channel transmission 3.2.5 mon-12 protocol mon-12 commands feature direct access to the device internal register map via the monitor channel. this means, although the dfe-q v2.1 features no microcontroller interface, internal register functions can be directly addressed by use of mon-12 commands. a mon-12 read request command must be first acknowledged by the dfe-q v2.1 before a subsequent read request can be triggered. in case of a failure condition the dfe-q v2.1 repeats the last outstanding mon-12 answer. mon-12 commands are prioritized over the other mon classes. note: register read access via mon-12 commands is not possible in state 'deactivated'. however, register read access via mon-12 commands is still possible in state 'reset' and all active states except 'deactivated'. if u-interface functions are addressed, the value of register lp_sel determines the register bank of the channel that is referred to. as a result the desired line port number must be programmed first in register lp_sel before any u-interface register can be accessed. for this reason mon-12 commands may not be issued simultaneously on different iom ? -2 channels, but must be issued consecutively if they address u-interface functions. for registers that are addressable by mon-12 commands please refer to the ? detailed register description ? on page 121 . mon-12 commands are of the following format: a mon-12 write command comprises 3 bytes, the first byte contains the mon-12 header, the second byte the register address, the third byte the register value. pef 24911 functional description data sheet 29 2001-07-16 a mon-12 read request command comprises 2 bytes, the first byte contains the mon-12 header, the second byte the register address of the data that is requested. after a read request the dfe-q v2.1 reacts with a 3-byte message. a mon-12 read answer comprises 3 bytes, the first byte contains the mon-12 header, the second byte the register address, the third byte the register value. 1. byte 2. byte 3. byte 1100 w=1 0 0 0 a a a a a a a a d d d d d d d d mon-12 register address register value 1. byte 2. byte 1100 r=0 0 0 0 a a a a a a a a mon-12 register address 1. byte 2. byte 3. byte 1100 r=0 0 0 0 a a a a a a a a d d d d d d d d mon-12 register address register value pef 24911 functional description data sheet 30 2001-07-16 3.3 interface to the analog front end the interface to the pef 24902 afe v2.1 is a 6-wire interface (see figure 14 ). on sdx and sdr transmit and receive data is exchanged as well as control information for the start-up procedure by means of time division multiplexing. on sdx transmit data, power-up/down information, range function and analog loopback requests are transferred. on sdr level status information is received for all line ports. on pdm0..pdm3 the adc output data from the afe is transferred to the dfe-q v2.1. the timing of all signals is based on the 15.36 mhz master clock which is provided by the afe. figure 14 interface to the analog front end the 192 available bits (related to the 15.36 mhz clock) on sdr/sdx during a 80 khz period are divided into 9 time-slots. 8 time-slots are 21 bits long and are reserved for data transmission, 1 time-slot is 24 bits long and used for synchronization purposes. the dfe-q v2.1 uses four of them, time-slots no. 1, 3, 5 and 7. table 4 shows the assignment of the iom ? -2 channels to the time-slots on sdx/sdr and the assignment of the time-slots to the line ports. table 4 assignments of iom ? channels to time-slots no. on sdx/sdr and line ports no. iom ? -2 channel no. time-slot no. line port no. 0/4/8/12 1 0 1/5/9/13 3 1 2/6/10/14 5 2 3/7/11/15 7 3 dfe-q v2.1 pef 24911 afe v2.1 pef 24902 dfe_afe_i f.vsd sdx sdr pdm0 pdm2 pdm1 pdm3 pef 24911 functional description data sheet 31 2001-07-16 the status on sdr is synchronized to sdx. each time-slot on sdr carries the corresponding ld bit during the last 20 bits of the slot. figure 15 frame structure on sdx/sdr the data on sdx is interpreted as follows: the 2b1q data is coded with the bits td2, td1, td0: nop : the no-operation-bit is set to ? 0 ? if none of the control bits (pdow, range and loop) shall be changed. the values of the control bits of the assigned line port is latched. the states of the control bits on sdx are ignored, they should be set to ? 0 ? to reduce any digital cross-talk to the analog signals. the nopq bit is set to ? 1 ? if at least one of the control bits shall be changed. in this case all control bits are transmitted with their current values. pdow: if the pdow bit is set to ? 1 ? , the assigned line port is switched to power- down. otherwise it is switched to power-up. range: range activates the range function which attenuates the received u- signal ? 1 ? = range function is activated (short line) ? 0 ? = range function is deactivated (long line) loop: loop = ? 1 ? activates the loop function, i.e. the loop is closed. otherwise the line port is in normal operation. sy: first bit of the time-slots with transmission data. for synchronization and bit allocation on sdx, sy is set to ? 1 ? on sdx and ? 0 ? on sdr. "0": reserved bit. reserved bits are currently not defined and shall be set to ? 0 ? . some of these bits may be used for test purposes or can be assigned to a function in later versions. pef 24911 functional description data sheet 32 2001-07-16 the data on sdr is interpreted as follows: table 5 2b1q coding table 2b1q data td2 td1 td0 0 1 don t care don t care ? 3000 ? 1001 + 3010 + 1011 ld: the level detect information is communicated to the dfe-q v2.1 on sdr. if the signal amplitude reaches the wake-up level, the ld bit toggles with the signal frequency. if the input signal at the u-interface is below the wake-up level, the ld bit is tied to either low or high. sy: first bit of the time-slots with transmission data. for synchronization and bit allocation on sdx, sy is set to ? 1 ? on sdx and ? 0 ? on sdr. pef 24911 functional description data sheet 33 2001-07-16 3.4 general purpose i/os the dfe-q v2.1 features 6 general purpose i/o pins per line port. this way transparent control of test relays and power feeding circuits is possible via the iom ? -2 monitor channel. four of the six pins are outputs, two are inputs. setting relay driver pins four relay driver output pins dij (where i = 0, 1, 2, 3 denotes the line port no. and j = a, b, c, d specifies the pin) are available per line port. the logic state of the four relay driver outputs which are assigned to the same line port can be set by a single mon-8 command, called ? setd ? . the value is latched as long as no other setd command with different relay driver settings is received. the state of the relay driver pins is not affected by any software reset (c/i= res). the state of all relay driver pins after hardware reset is ? low ? . reading status pins each line port owns two status pins st ij (where i = 0,1, 2, 3 denotes the line port no. and j = 0, 1 specifies the pin) whose logical value is reported in the associated monitor channel. any signal change at one of the status pins st1..4 causes automatically the issue of a two-byte mon-8 message ? ast ? whose two least significant bits reflect the status of pin stij. however, this automatic mechanism is only enabled again, if the previous status pin message has been transferred and acknowledged correctly according to the monitor channel handshake protocol. it takes the dfe-q v2.1 at least 8x iom ? -2 frames (1 ms) to transmit the 2-byte mon-8 message. thus, repeated changes within periods shorter than 8x iom ? -2 frames will overwrite the status pin register information. for this reason only the value of the last recent status change will be reported. note that the mon-8 transfer time depends also on the reaction time (acknowledge by mr-bit) of the dfe-q counterpart. besides this automatic report the dfe-q v2.1 will issue the status pin monitor message ? ast ? upon the mon-8 request ? rst ? . the st ij pins have to be tied to either vdd or gnd, if they are not used. pef 24911 functional description data sheet 34 2001-07-16 3.5 clock generation the u-transceiver has to synchronize onto an externally provided ptt-master clock. a phase locked loop (pll) is integrated in the afe (pef 24902) to generate the 15.36 mhz system clock. a synchronized system clock guarantees that u-interface transmission will be synchronous to the ptt-master clock. the afe is able to synchronize onto a 8 khz or a 2048 khz system clock. infineon recommends however to feed the fsc clock input of the dfe-q v2.1 and the pll reference clock input (pin clock) of the afe from the same clock source. please refer to the pef 24902 data sheet for further details on the pll. for the connection of the afe clock output line with the dfe-q v2.1 clock input line (cl15) please refer to figure 5 and figure 6 . 3.6 u-transceiver functions the u-interface establishes the direct link between the exchange and the terminal side. it consists of two copper wires. the quad iec afe uses four differential outputs (aout, bout) and four differential inputs (ain, bin) for transmission and reception. these differential signals are coupled via four hybrids and four transformers to the four two-wire u-interfaces. the nominal peak values of 3 correspond to a 3.2 vpp chip output and 2.5 vpp on the u-interface. direct access to the u-interface is not possible. 2b + d user data can be inserted and extracted via the iom ? -2 interface. control of maintenance bits is partly provided via iom ? -2 monitor commands. the remaining maintenance bits are fully controlled by the dfe-q v2.1 itself and allow no external influence (e.g. crc-checksum). 3.7 2b1q frame structure transmission over the u 2b1q -interface is performed at a symbol rate of 80 kbaud. the code used reduces two binary informations to one quaternary symbol (2b1q) resulting in a total bit rate of 160 kbit/s. 144 kbit/s are user data (b1 + b2 + d), 16 kbit/s are used for maintenance and synchronization information. data is grouped together into u-superframes of 12 ms each. the beginning of a new superframe is marked by an inverted synchronization word (isw). each superframe consists of eight basic frames (1.5 ms) which begin with a standard synchronization word (sw) and contain 222 bits of information. the structure of one u-superframe is illustrated in figure 16 and figure 17 . figure 16 u-superframe structure isw 1. basic frame sw 2. basic frame . . . sw 8. basic frame <--- 12 ms ---> pef 24911 functional description data sheet 35 2001-07-16 figure 17 u-basic frame structure out of the 222 information bits 216 contain 2b + d data from 12 iom ? -frames, the remaining 6 bits are used to transmit maintenance information. thus 48 maintenance bits are available per u-superframe. they are used to transmit two eoc-messages (24 bit), 12 maintenance (overhead) bits and one checksum (12 bit). (i) sw (inverted) synch word 18 bit (9 quat) 12 2b + d user data 216 bits (108 quat) m1 ? m6 maintenance data 6 bits (3 quat) <--- 1,5 ms ---> table 6 2b1q u-frame structure framing 2b + d overhead bits (m1 ? m6) quat positions 1 ? 9 10 ? 117 118 s 118 m 119 s 119 m 120 s 120 m bit positions 1 ? 18 19 ? 234 235 236 237 238 239 240 super frame # basic frame # sync word2b + dm1m2m3m4m5m6 1 1 isw 2b + d eoca1 eoca2 eoca3 act/ act 11 2sw2b + deocd m eoci1 eoci2 dea / ps1 1febe 3 sw 2b + d eoci3 eoci4 eoci5 1/ ps2 crc1 crc2 4 sw 2b + d eoci6 eoci7 eoci8 1/ ntm crc3 crc4 5 sw 2b + d eoca1 eoca2 eoca3 1/ cso crc5 crc6 6sw2b + deocd m eoci1 eoci2 1 crc7 crc8 7 sw 2b + d eoci3 eoci4 eoci5 uoa / sai crc9 crc 10 8 sw 2b + d eoci6 eoci7 eoci8 aib / nib crc11 crc12 2,3 ? lt- to nt dir. > / < nt- to lt dir. pef 24911 functional description data sheet 36 2001-07-16 ? isw inverted synchronization word (quad): ? 3 ? 3 + 3 + 3 + 3 ? 3 + 3 ? 3 ? 3 ? sw synchronization word (quad): + 3 + 3 ? 3 ? 3 ? 3 + 3 ? 3 + 3 + 3 ? crc cyclic redundancy check ? eoc embedded operation channel a = address bit d/m = data / message bit i = information (data / message) ? act activation bit act = (1) ? > layer 2 ready for communication ? dea deactivation bit dea = (0) ? > lt informs nt that it will turn off ? cso colt start only cso = (1) ? > nt-activation with cold start only ? uoa u-only activation uoa = (0) ? > u-only activated ? sai s-activity indicator sai = (0) ? > s-interface is deactivated ? febe far-end block error febe = (0) ? > far-end block error occurred ? ps1 power status primary source ps1 = (1) ? > primary power supply ok ? ? ps2 power status secondary source ps2 = (1) ? > secondary power supply ok ? ? ntm nt-test mode ntm = (0) ? > nt busy in test mode ? aib alarm indication bit aib = (0) ? > interruption (according to ansi) ? nib network indication bit nib = (1) ? > no function (reserved) 3.8 maintenance channel the last three symbols (6 bits) form the 4 kbit/s m(maintenance)-channel used for exchange of operations and maintenance data between the network and the nt. approved m-bit data is first processed and then reported to the system by monitor channel messages (mon-0, mon-2). mon-0/ mon-2 - m bit mapping the m1-3 bits over four basic frames constitute one complete eoc word. eoc words are exchanged across the iom ? -2 interface via mon-0 messages. the overhead bits (m4,m5,m6) of one u-superframe are collected and transported in a mon-2 message. figure 18 shows in detail how the maintenance bits of one received u-superframe are mapped to mon-0 and mon-2 messages. m1-6 filtering options to reduce processor load the dfe-q v2.1 provides several programmable filters for the issue of mon-0 and mon-2 messages. in the following paragraphs the various verification algorithms and the provided control mechanism for the overhead bits (m4,m5,m6) are presented. the verification method of received m-channel data can be programmed in the mfilt register using the mon-12 protocol. the following options are provided: pef 24911 functional description data sheet 37 2001-07-16 figure 18 mon-0/2 - m-bit correspondence 1 super frame 1 basic frame a1 m1 a2 m2 eoc 1 m3 d1 1 m4 d10 m5 d9 m6 2 d/ m i1 i2 d8 d7 d6 3 i3 i4 i5 d5 crc1 crc2 4 i6 i7 i8 d4 crc3 crc4 5 a1 a2 a3 d3 crc5 crc6 6 d/ m i1 i2 d2 crc7 crc8 7 i3 i4 i5 d1 crc9 crc10 8 i6 i7 i8 d0 crc11 crc12 2,3 ... mon-0 mon-2 1 super frame 1 basic frame m1 m2 m3 act m4 1 m5 1 m6 2 dea / ps1 1 febe 3 sco/ps2 crc1 crc2 4 1/ntm crc3 crc4 5 1/cso crc5 crc6 6 1 crc7 crc8 7 uoa / sa i crc9 crc10 8 aib/nib crc11 crc12 2,3 ... eoc 2 / < nt to lt lt to nt > a3 u-frame structure mon-0/2 correspondence d11 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1. byte 2. byte mon-2 single bits (m 4, m5, m 6 e xcept crc) mon-2 format a1 a2 a3 d/ m i1 i2 i3 i4 i5 i6 i7 i8 0 0 0 0 1. byte 2. byte mon-0 eoc code mon-0 format address d/m mon02corrsp.emf pef 24911 functional description data sheet 38 2001-07-16 eoc (m1-m3) filtering the first three m-bits (m1-m3) in each basic u-frame constitute an eoc command/ message. for the different eoc commands and their meaning see the next paragraph. via register mfilt the following operating modes can be set: automode (mfilt.eoc= ? 100 ? ) in automode received eoc messages are checked by ? triple-last-look ? (tll) before they are signalled to the system by a mon-0 message. the return message reception function is activated (see ? eoc auto mode ? on page 47 ). transparent mode (mfilt.eoc= ? 001 ? ) in transparent mode received eoc messages are forwarded via mon-0 to the system interface. this means that every 6 ms a mon-0 message is issued. transparent mode with on change function active (mfilt.eoc= ? 010 ? ) only if a change in the eoc message has been detected the received eoc message is reported via a mon-0 message. transparent mode with tll active (mfilt.eoc= ? 011 ? ) a change is only reported via mon-0 if the new eoc command has been detected in at least three consecutive eoc messages. for more details on eoc commands and messages and its processing please refer to chapter 3.9 on page 46. overhead bit (m4, m5, m6) filtering m4 bits are used to communicate status and maintenance functions between the transceivers. the meaning of a bit position depends on the direction of transmission (upstream/downstream) and the operation mode (nt/lt). see table 6 for the different meaning of the m4 bits. to reflect a change of the system status a new value for m4 bits shall be repeated in at least three consecutively transmitted superframes. all overhead bits are set to binary ? 1 ? when leaving a power-down state. four different validation modes can be selected and take effect on a per bit base . only if the received m4 bit change has been approved by the programmed filter algorithm the corresponding mon-2 message is issued. the following filter algorithms are provided: on change (mfilt.m4= ? x00 ? ) triple-last-look (tll) coverage (mfilt.m4= ? x01 ? ) crc coverage (mfilt.m4= ? x10 ? ) crc and tll coverage (mfilt.m4= ? x11 ? ) some m4 bits, act, dea and uoa, have two destinations, the state machine and the system interface. via bit no. 5 of the mfilt register the user can decide whether the m4 bits which are input to the state machine shall be approved by tll (mfilt.m4= ? 0xx ? ) or pef 24911 functional description data sheet 39 2001-07-16 by the same verification mode (mfilt.m4= ? 1xx ? ) as selected for the issue of a mon- 2 message. the user has the choice to program one of the following two options for filtering the m5 and m6 bits changes except febe or crc bits: same validation algorithm as programmed for m4 bits (mfilt.m56= ? x0 ? = default setting ) note that unlike the m4 bits the m56 bits are not included in the crc! on change (mfilt.m56= ? x1 ? ) note: the issue of the corresponding monitor messages is delayed for 12 ms (= u- superframe) if received m-bits are crc covered. this way the m-bit data is checked with the actual crc sum which is received one u-superframe later. filter setting via pin auto and pin crcon once after a pin reset, the settings of both auto and crcon pins are evaluated and the mfilt register is preset as follows. the setting of pin auto determines the operational mode of the embedded operations channel: pin auto set to ? 1 ? selects automode for all line ports and corresponds to the following register setting of mfilt = xxxx x100. pin auto set to ? 0 ? selects transparent mode for all line ports and corresponds to the following register setting of mfilt = xxxx x001. via pin crcon the crc filter mode for the overhead bits can be activated or deactivated (see table 7 ): pin crcon set to ? 1 ? enables the crc mode for all line ports and corresponds to the following register setting of mfilt = 0011 0xxx. pin crcon set to ? 0 ? disables the crc mode for all line ports and corresponds to the following register setting of mfilt = 0000 0xxx. note that the pin setting is only evaluated once after pin reset. this fact allows to reprogram the verification modes later on by a mon-12 command. the mfilt register setting is evaluated each time the u-transceiver enters the deactivated state. figure 19 summarizes the various filtering options that are provided for the several bits of the maintenance channel . pef 24911 functional description data sheet 40 2001-07-16 figure 19 maintenance channel filtering options table 7 overhead bits filter setting by crcon pin pin towards fsm ( ? single ? m4 bits) towards system (m4, m5, m6 bits) crcon = 1 crc crc & on change crcon = 0 tll on change m4 tll & on change mon-2 m u x m1-3 (eoc) m u x tll on change mon-0 m u x state machine mfilt.eoc(bit3,2,1) mfilt.m4(bit5) m456_f i l t er . emf m u x mfilt.m4(bit4,3) crc m5, m6 tll & on change m u x crc mfilt.m56(bit6) mon-2 pef 24911 functional description data sheet 41 2001-07-16 3.8.1 m4 bit reporting to state machine figure 20 illustrates the point of time when a detected m4 bit change is reported to the system interface and when it is reported to the state machine: towards the system interface mon-2 messages might be sent after one complete u-superframe was received, whereas towards the state machine m4-bit changes (act, sai) are instantly passed on as soon as they were approved by tll (default setting in register mfilt, see ? mfilt - m-bit filter options ? on page 122 ). in context to figure 20 this means that a verified act bit change is already reported at the end of basic frame #1 instead at the end of basic frame #8. figure 20 m4 bit report timing bf1 sf1 sf2 sf3 change crc nearend (sf1) crc farend (sf1) sm & mon2 1) crcon = 1: crc sm / crc & on-change mon2 bf1 sf1 sf2 sf3 change 2) crcon = 0: tll sm / on-change mon2 no change bf1 no change sm mon2 bf1 sf1 sf2 sf3 change 3) mon12: mfilt = 14 h : tll sm / crcr on-change mon2 no change bf1 no change sm mon2 bf1 m4tim2sm_a.emf pef 24911 functional description data sheet 42 2001-07-16 however, if the same filter is selected towards the state machine as programmed towards the system interface (by bit5= ? 1 ? in register mfilt) the user has to be aware that if crc mode is active the state machine is informed at the end of the next u- superframe. pef 24911 functional description data sheet 43 2001-07-16 3.8.2 m4, m5, m6 bit control mechanisms figure 21 to figure 22 show the control mechanisms that are provided for m4, m5 and m6 bit data: via the m4wmask register the user can selectively program which m4 bits are externally controlled and which are set by the internal state machine. if one m4wmask bit is set to ? 0 ? then the m4 bit value in the u-transmit frame is determined by the bit value at the corresponding bit position of the mon-2 command. note that the mon-8 command pace/paca corresponds to bit 6 in the m4wmask register. by bit 6 it can be selected whether sai is set by the state machine or by mon- 2 commands. note: during local loop test mode (c/i-input = ?arl?), the user must neither send mon- 8 pace/paca, nor program register m4wmask. otherwise, switching back and forth between pace/paca will easily cause a failure where the sai/uoa bits toggle permanently. via the m4rmask register the user can selectively program which m4 bit changes shall cause a mon-2 message. with respect to the sai bit the corresponding bit (no. 6) in the m4rmask bit decides in addition whether the value of the received sai bit is reported to the state machine or sai= ? 1 ? is signalled. access to m4wmask and m4rmask is provided by the mon-12 protocol. by mon-2 commands the m4 bits can be set that are sent with the next available u-superframe. by mon-2 messages the status of the last validated m4 bit data is reported. also the default values of the spare bits, m51, m52 and m61 can be overwritten at any time by a mon-2 command. a mon-2 messages reports the last received and verified m5, m6 bit data. pef 24911 functional description data sheet 44 2001-07-16 figure 21 m4, m5, m6 bit control in transmit direction figure 22 m4, m5, m6 bit control in receive direction m456_dfeq_tx.emf u transmit superframe m56w register 1 1 1 1 m61 m52 m51 febe mux nebe counter opmode.febe state machine m4w register aib uoa m46 m45 m44 sco dea act mux c/i codes act dea uoa mux m4wmask mux mux mux mux mux mux '1' '1' '1' '1' '1' mon-2 m4wmask.bit6= mon-8(pace, paca) '1'= m4w reg. '0'= sm/ pin mon-2 m4r register nib sai m46 cso ntm ps2 ps1 act m56r register 0 ms2 ms1 m61 m52 m51 u receive superframe m4 filtering (per bit) m56 filtering (per bit) mfilt.m4 mfilt.m56 m4rmask en/ dis en/ dis en/ dis en/ dis en/ dis en/ dis en/ dis en/ dis monitor channel controller mon-2 '0'= enabled '1'= disabled m456_dfeq_rx.emf nebe febe sai act state machine mux m4wmask.bit6 = mon-8(pace/ paca) sai act '1' pef 24911 functional description data sheet 45 2001-07-16 3.8.3 start of maintenance bit evaluation mon-0/2 messages will be issued only if the receiver is synchronized. this is done to avoid meaningless mon-0/2 messages if data transmission is not synchronized. in other words, mon-0/2 messages will be issued only in the following states: states line active pending transparent s/t deactivated pending deactivation transparent pef 24911 functional description data sheet 46 2001-07-16 3.9 embedded operations channel (eoc) the embedded operations channel (eoc) is used to transfer data from the exchange to the terminal side and vice versa without occupying b- or d-channels. it is used to transmit diagnostic functions and signaling information. eoc-data is inserted into the u-frame at the positions m1, m2 and m3 thereby permitting the transmission of two complete eoc-messages (2 x 12 bits) within one u-superframe. with a mon-0-command a complete eoc-message (address field, data/message indicator and information field) can be passed to the u-transceiver. the eoc contains an address field, a data/message indicator and an eight-bit information field. with the address field the destination of the transmitted message/data is defined. addresses are defined for the nt, 6 repeater stations and broadcasting. the data/message indicator needs to be set to (1) to indicate that the information field contains a message. if set to (0), numerical data is transferred to the nt. currently no numerical data transfer to or from the nt is required. from the 256 codes possible in the information field 64 are reserved for non-standard applications, 64 are reserved for internal network use and eight are defined by ansi for diagnostic and loopback functions. all remaining 120 free codes are available for future standardization. table 8 supported eoc-commands eoc address field data/ message indicator information o (rigin) d (estination) message a1 a2 a3 d/m i1 i2 i3 i4 i5 i6 i7 i8 lt nt 000 x nt 1 1 1 x broadcast 0 0 1 1 1 0 x repeater stations no. 1 ? no. 6 0data 1message 1 01010000 o d lbbd 1 01010001 o d lb1 1 01010010 o d lb2 1 01010011 o d rcc 1 01010100 o d ncc pef 24911 functional description data sheet 47 2001-07-16 the eoc protocol operates in a repetitive command/response mode. three identical properly-addressed consecutive messages shall be received by the nt before an action is initiated. in order to cause the desired action the line card controller continues to send the message until it receives three identical consecutive eoc frames from the nt that agree with the transmitted eoc frame. the response of the nt is the echo of the received eoc frame. any reply or echoed eoc frame is sent upstream in the next available returning eoc frame. all actions to be initiated at the nt shall be latching, permitting multiple eoc-initiated actions to be in effect simultaneously. latched functions are resolved by the rtn (return-to-normal) command. access to the eoc is only possible when a superframe is transmitted. this is the case in the following states: ? line active ? pend. transparent ? s/t deactivated ? pend. deactivation ? transparent in other states than the listed above all eoc-bits on the u-interface are clamped to high. 3.10 eoc processor the on-chip eoc-processor is responsible for the correct insertion and extraction of eoc-data on the u-interface. mon-0-messages provide the access to the device internal eoc-registers. the eoc processor performs code repetition. this means that a mon-0 message transporting the eoc command needs to be transferred only once the eoc-processor can be programmed to automode or transparent mode: eoc auto mode ? acknowledgment: there is no acknowledgment in lt mode, i.e received eoc messages are not echoed. ? latching: no latching is performed. ? transfer to iom ? : ? return message reception function ? is enabled as soon as the lt has transmitted an eoc command. it causes the u-transceiver in lt mode to compare the received and verified (by tll) eoc messages with the last downstream 1 11111111 o d rtn 1 00000000 d/o o/d h 1 101 01010 d o utc table 8 supported eoc-commands eoc pef 24911 functional description data sheet 48 2001-07-16 transmitted eoc command. a mon-0 message is issued if they prove to be equal. for this particular received eoc message the ? different from previous ? rule is not applied. this means that a mon-0 message is even issued if the received eoc message is not different to the one previously accepted. all other incoming eoc messages besides the echo of the one transmitted downstream will be evaluated by tll and the ? different from previous ? verification. new received eoc messages will be passed independently of the address used, i.e. not only messages addressed with (000) or (111) but all received eoc-messages will be transmitted with mon-0-messages. ? execution: no execution in lt mode, i.e. verified eoc messages cause no action or execution other than being forwarded to the system. eoc transparent mode every 6 ms a mon-0-message is issued on iom ? . it contains the last received eoc- message. this occurs even if no change occurred in the eoc-channel. no ? triple-last- look ? is performed before a mon-0-message is sent. figure 23 summarizes the different processing of eoc/mon-0 commands/messages in lt and nt mode. pef 24911 functional description data sheet 49 2001-07-16 figure 23 eoc-procedure in auto- and transparent mode lt nt m1,m2,m3, eoc u mon-0 eoc transmi t request will enable return message a t a t 3x iom -2 iom -2 iom -2 iom -2 t a 3x execute echo transmission possible arm (c/i) indication reception possible uai (c/i) indication m1,m2,m3, eoc mon-0 eoc mon-0 eoc mon-0 eoc itd04233.vsd a: auto-mode t: transparent-mode t pef 24911 functional description data sheet 50 2001-07-16 3.11 cyclic redundancy check an error monitoring function is implemented covering the 2b + d and m4 data transmission of a u-superframe by a cyclic redundancy check (crc). the computed polynomial is: g (u) = u 12 + u 11 + u 3 + u 2 + u + 1 (+ modulo 2 addition) the check digits (crc bits crc1, crc2, ? , crc12) generated are transmitted in the u-superframe. the receiver will compute the crc of the received 2b + d and m4 data and compare it with the received crc-bits generated by the transmitter. a crc-error will be indicated to both sides of the u-interface, as a nebe (near-end block error) on the side where the error is detected, as a febe (far-end block error) on the remote side. the febe-bit will be placed in the next available u-superframe transmitted to the originator. far-end or near-end error indications increment the corresponding block error counters of exchange and terminal side. figure 24 illustrates the crc-process. pef 24911 functional description data sheet 51 2001-07-16 figure 24 crc-process g(u) =? nebe error counter febe error counter nebe error counter =? febe error counter g(u) crc 1... crc 12 crc 1. .. crc 12 crc1. .. crc1 2 crc1... crc12 (2b + d), m4 du g(u) g(u) (mon-8) (mon-8) (mon-1) febe du (mon-8) (mon-1) nebe dd iom ? -2 nt u lt dd (mon-8) febe = "0" sfr(n + 2) febe = "1" sfr(n + 2) sfr(n + 1.0625) sfr(n + 0.0625) sfr(n + 1.0625) febe = "0" sfr(n + 1.0625) febe = "1" sfr(n + 1) sfr(n) (2b + d), m4 no yes no yes crc.emf iom ? -2 pef 24911 functional description data sheet 52 2001-07-16 3.12 scrambling/ descrambling the scrambling algorithm ensures that no sequences of permanent binary 0s or 1s are transmitted. it is defined in etsi ts 102 080 and ansi t1.601. the algorithms used for scrambling and descrambling in lt- and nt-mode are given in figure 25 . note that one wrong bit decision in the receiver automatically leads to at least three bit errors. whether all of these are recorded by a bit error counter depends on the fact whether all faulty bits are part of the monitored channels or not. figure 25 scrambler/ descrambler algorithms pef 24911 functional description data sheet 53 2001-07-16 3.13 encoding/ decoding (2b1q) the 2b1q line code is a 4-level pulse amplitude modulation (pam) code without redundancy. 2b1q stands for 2 binary, 1 quaternary. in transmit direction two-bit binary pairs are converted into quaternary symbols that are called quats. in each pair of bits the first bit is called the sign bit and the second is called the magnitude bit. table 9 shows the relationship of the bits to quats. the four values listed under ? quaternary symbol ? in the table above should be understood as symbol names, not numerical values. at the receiver, each quaternary symbol is converted to a pair of bits by reversing the table, descrambled and finally formed into the original bit stream. table 9 2b1q coding table first bit (sign) second bit (magnitude) quaternary symbol (quat) 10+3 11+1 01-1 00-3 pef 24911 functional description data sheet 54 2001-07-16 3.14 c/i codes (2b1q) the operational status of the dfe-q v2.1 is controlled by the control/indicate channel (c/i-channel). the four c/i channels operate completely independently. table 10 presents the existing c/i codes. a new command or indication will be recognized as valid after it has been detected in two to five successive iom ? -frames (unconditional commands must be applied up to 2 ms before they are recognized). indications are strictly state oriented. refer to the state diagrams in the following sections for commands and indications applicable in various states. commands have to be applied continuously on din until the command is validated by the dfe-q v2.1 and the desired action has been initiated. afterwards the command may be changed. an indication is issued permanently by the dfe-q v2.1 on dout until a new indication needs to be forwarded. because a number of states issue identical indications it is not possible to identify every state individually. table 10 command / indicate codes (2b1q) code lt-mode din dout 0000 dr ? 0001 res deac 0010 ? fj 0011 ltd ? 0100 res1 rsy 0101 ssp ei2 0110 dt ? 0111 uar uai 1000 ar ar 1001 arx arm 1010 arl ? 1011 ? ei3 1100 ? ai 1101 ar0 lsl 1110 ?? 1111 dc di pef 24911 functional description data sheet 55 2001-07-16 ai activation indication ei2 error indication 2 (error on s/t) ar activation request lsl loss of signal level on u ar0 activation request with act bit = 0 dc deactivation confirmation arl activation request local loop res reset arm activation request maintenance bits res1 reset receiver arx activation request without 15 sec limit rsy loss of synchronization dr deactivation request ssp send-single-pulses test mode deac deactivation accepted uai u-activation indication di deactivation indication uar u-activation request dt data-through test mode fj frame jump ei3 error indication 3 (time-out t1 [15 s], ltd lt disable error on u) 3.15 state machine notation the state machines control the sequence of signals at the u-interface that are generated during the start-up procedure. the informations contained in the following state diagrams are: ? state name ? u-signal transmitted ? overhead bits transmitted ? c/i-code transmitted ? transition criteria ? timers figure 26 shows how to interpret the state diagrams. figure 26 explanation of the state diagram pef 24911 functional description data sheet 56 2001-07-16 the following example explains the use of a state diagram by an extract of the lt-state diagram. the state explained is the ? deactivated ? state in lt-mode. the state may be entered by either of three methods: ? from state ? receive reset ? after time t7 has expired (t7 e xpired ) ? from state ? tear down ? after the internal transition criterion ? lsu ? is fulfilled ? from state ? reset ? or ? test ? after the c/i-command ? dr ? has been sent on din the following information is transmitted: ? sl0 is sent on the u-interface ? no overhead bits are sent ? c/i-message ? di ? is issued on dout the state may be left by either of the following methods: ? leave for state ? awake ? after nt wake up tone (tn) was detected and the c/i-code dc is present on din ? leave for state ? alerting ? after c/i-commands ? ar ? , ? arx ? , ? ar0 ? or ? uar ? were received ? leave for state ? reset for loop ? after c/i-command ? arl ? was received combinations of transition criteria are possible. logical ? and ? is indicated by ? & ? (tn & dc), logical ? or ? is written ? or ? and for a negation ? / ? is used. the start of a timer is indicated with ? txs ? ( ? x ? being equivalent to the timer number). timers are always started when entering the new state. the action resulting after a timer has expired is indicated by the path labelled ? txe ? . the sections following the state diagram contain detailed information on all states and signals used. these details are mode dependent and may differ for identically named signals/states. they are therefore listed for each mode. pef 24911 functional description data sheet 57 2001-07-16 3.16 lt mode state diagram figure 27 state transition diagram in lt-mode lt_sm_2b1q_cust.emf sl0 deactivated di sl0 reset for loop di sl1 ec-training ar sl2 sl2 ec-converged eq-training arm a=0,d=1 a=0,d=1 . . . tl alerting di . di sl0 wait for tn . sl0 awake ar . a=0,d=1 sl3t loss of synchr. rsy sl0 reset deac . ar awake error sl0 . dr t1s, t2s t1s, t5s t1s t4s, a=0,d=1 a=0,d=1 line active s/t deactivated uai/fj sl3t** ) ar/fj uai/fj sl3t a=1,d=1 pend.transparent uai, fj sl3t a=1,d=1 ai/fj ei2/fj transparent any state pin-dt or dt arl t2s t9s, t4s fw_ok or t6e or arl lsec or t5e t2e t3s res1 t4s, t1s t1e (t9e & lsec) or t4e dr or lof or lsue dr or lof or lsue t8s ar0 act=0 sai=1 act =1 & /ar0 tn lsec or t4e t1s, t2s t5s dr or lof or lsue t8e sai=0 & act=0 lof dr t10s lsue res1 res1 t7s t7s t7e t10e lsu sp/sl0 test deac . pin-res or c/i= 'res' pin-ssp or c/i= 'ssp' or c/i='ltd' ( ar or ar0 or arx or uar ) & /tn res1 dr t3e t6s act=1 sai=0 uar ar0 tn lsu sl3t sl0 tear down error rsy . a=0,d=1 sl0 sl3t loss of signal receive reset lsl lsl . a=0,d=0 sl0 sl3t tear down pend. deactivation deac deac . sl0 alerting_error . ei3 res1 t2e t2s when state line active is entered the first time at startup the 2b+d data must be clamped to '0', until act= '1' has been received from the nt **) tn & ( ar or ar0 or arx or uar or dc) dr or lof or lsue (/t1e or arx) & sfd & (bbd0 or bbd1 or crcok) arm ei 3 t1e t2s res1 pef 24911 functional description data sheet 58 2001-07-16 3.16.1 inputs to the u-transceiver in lt-mode the transition criteria are described in the following sections. they are grouped into: ? c/i-commands ? pin settings ? events related to the u-interface ? timers c/i-commands ar activation request the u-transceiver is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal tl. in case the u-transceiver is in state "deactivated" it is recommended always to apply dc before ar to resolve the situation if a tn tone has been detected before. ar0 activation request with ? act ? bit = (0) the u-transceiver is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal tl. after ? eq training ? the state ? line active ? will be entered independent of the ? act ? bit. evaluation of the ? act ? bit is disabled when ar0 is received and enabled when ar is received. in case the u-transceiver is in state "deactivated" it is recommended always to apply dc before ar0 to resolve the situation if a tn tone has been detected before. arl activation request local loop-back the u-transceiver is requested to operate an analog loop-back (close to the u-interface) and to start the start-up sequence by sending the wake-up tone tl. this command may be issued only after the u-transceiver has been set to the ? deactivated ? state (c/i-channel code di issued on dout) and has to be issued continuously as long as loop-back is requested. arx activation request extended the dfe-q is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal tl. the difference to the command ar is that the activation duration may exceed 15 sec. in case the u-transceiver is in state "deactivated" it is recommended always to apply dc before arx to resolve the situation if a tn tone has been detected before. dc deactivation confirmation if ? dc ? is applied in state ? deactivated ? the dfe-q transitions to state "awake" as soon as it receives a wake-up tone from the nt. if ? dr ? is applied in state ? deactivated ? the wake up request of the nt is not acknowledged. this way the linecard is able to reject an activation attempt by the nt e.g. during a service procedure. by means of the ? dc ? command the lt is also during an u-only activation capable to control the point of time when the complete transmission line is set transparent in case a terminal initiated activation request has occurred. in state ? s/t deactivated ? with applied c/ i code ? uar ? the dfe-q issues ? uoa= 0 ? and receives ? sai= 0 ? from the deactivated s interface. if the terminal requests an activation with ? ar ? issued in the nt the sai bit is set pef 24911 functional description data sheet 59 2001-07-16 to ? 1 ? and the lt indication ? uai ? switches to ? ar ? . as soon as ? dc ? is applied instead of ? uar ? on the lt side the line is set transparent, since the uoa bit reflects the polarity of sai and is thus set to ? 1 ? . dr deactivation request this command requests the u-transceiver to start a deactivation procedure by setting the dea bit to ? 0 ? and to cease transmission afterwards. the dr-code is a conditional command causing the u-transceiver only to react in the states ? reset ? , ? test ? , ? s/t deactivated ? , ? line active ? , ? pending transparent ? and ? transparent ? , i.e. when the c/i- channel codes deac, uai, ar, ai, fj or ei2 are issued on dout. dt data through this unconditional command is used for test purposes only and forces the u-transceiver into the transparent state independent of the wake-up protocol. a far-end transceiver needs not to be connected; in case a far-end transceiver is present it is assumed to be in the same condition. ltd lt disable this unconditional command forces the u-transceiver to state test, where it transmits signal sl0. no further action is initiated. res reset unconditional command which resets the whole chip; note that on contrary to the pin reset a clock signal must be provided for the c/i code processing. res1 reset 1 the reset 1 command resets all receiver functions; especially the ec- and eq-coefficients and the agc are set to zero. the res1-code does not reset any other than receiver functions (e.g. iom ? -functions or relay driver settings). the res1-code should be used when the u-transceiver has entered a failure condition (expiry of timer t1, loss of framing or loss of signal level) indicated by the c/i-channel ei3, rsy or lsl on dout. besides resetting the receiver, this command stops transmission on the u-interface. the dea bit is not set to ? 0 ? by res1. ssp send single pulses unconditional command which requests the transmission of single pulses on the u-interface. the pulses are issued at 1.5 ms intervals and have a duration of 12.5 s. the chip is transferred to the ? test ? state; the receiver will not be reset. uar partial activation request (u only) the u-transceiver is requested to enter power-up state and to start an activation procedure of the u-interface only. pins pin-res pin-reset a hw-reset was applied and released. c/i-message deac will be issued in all channels. pin-ssp send single pulses the function of this pin is the same as for the c/i-code ssp in all channels. the c/i- pef 24911 functional description data sheet 60 2001-07-16 message deac will be issued. the high level needs to be applied continuously for the transmission of single pulses. pin-dt data through the function is identical with the c/i-code dt in all channels. u-interface events act = 0/1 ? act ? bit received from the nt-side. ? act = 1 signals that the nt has detected info3 on the s/t-interface and indicates that the complete basic access system is synchronized in both directions of transmission. the lt-side is requested to provide transparency of transmission in both directions and to respond with setting the act-bit to ? 1 ? . in the case of loop- backs (loop-back 2 or single-channel loop-back in the nt), however, transparency is required even when the nt is not sending act = 1. transparency is achieved in the following manner: ? the u-transceiver performs transparency in both directions of transmission after the receiver has achieved synchronization (state eq-training is left) independent of the status of the received act-bit. ? the status ? ready for sending ? is reached when the state transparent is entered i.e. when the c/i-channel indication ai is issued. this is valid in the case of a normal activation procedure for call control. in the case of loop-backs (loop-back 2 or single-channel loop-back in the nt and analog loop-back in the lt) however, the status ? ready for sending ? is reached when the state line active is entered i.e. when the c/i-channel indication uai is issued. until the status ? ready for sending ? is reached, binary ? 0s ? have to be passed in the b- and d-channels on din. ? act = 0 indicates the loss of transparency on the nt-side (loss of framing or loss of signal level on the s/t-interface). the u-transceiver informs the lt-side by issuing the c/i-channel indication ei2, but performs no state change or other actions. crcok cyclic redundancy check ok this input is used as a criterion that the receiver has acquired frame synchronization and both its ec and eq coefficients have converged. lof loss of framing on the u-interface this condition is fulfilled if framing is lost for 576 ms. 576 ms are the upper limit. if the correlation between synchronization word and input signal is not optimal, lof can be issued earlier. lsec loss of signal level behind the echo canceler in the ? awake ? state, this input is used as indication that the nt has ceased the transmission of signal sn1. in the ec-training state, this input is used as an internal signal indicating that the ec in the lt has converged. lsu loss of signal level on the u-interface this signal indicates that a loss of signal level for the duration of 3 ms has been detected on the u-interface. this short response time is relevant in all cases where pef 24911 functional description data sheet 61 2001-07-16 the lt waits for a response (no signal level) from the nt-side, i.e. after a deactivation procedure has been started or after loss of framing in the lt occurred. lsue loss of signal level on the u-interface (error condition) after a loss of signal level has been noticed, a 492 ms timer is started. after this timer has elapsed, the lsue-criterion is fulfilled. this long response time (see also lsu) is valid in all cases where the lt is not prepared to lose signal level. note that 492 ms represent a minimum value; the actual loss of signal might have occurred earlier, e.g. when a long loop is cut at the lt-side, the echo coefficients need to be readjusted to new parameters. only after the adjusted coefficient cancel the echo completely, the loss of signal is detected and the timer can be started (if the long loop is cut at the remote end, the coefficients are still correct and a loss of signal will be detected immediately). sec signal level behind the echo canceler this signal indicates that a signal level corresponding to sn2 from the nt has been detected on the u-interface. sfd superframe detected tn tone (wake-up signal) received from the nt. when in the ? deactivated ? state, the u-transceiver is requested to start an activation procedure and to inform the lt-side making use of the c/i-channel code ar. when in the ? wait for tn ? state, the signal tn sent by the nt acknowledges the receipt of a wake-up signal tl from the lt. when an analog loop-back is operated, the wake-up signal tl sent by the lt-transmitter is detected by the lt-receiver. the tn-criteria is fulfilled when 12 consecutive periods of the 10 khz wake-up tone were detected. bbd0/1 binary ? 0 ? or ? 1s ? detected in the b- and d-channels this internal signal indicates that for a period of time of 6 ? 12 ms a continuous stream of binary ? 0s ? or ? 1s ? has been detected. it is used as a criterion that the receiver has acquired frame synchronization and both its ec- and eq-coefficients have converged. bbd1 corresponds to the signals sn2 or sn3 in the case of a normal activation and bbd0 corresponds to the internally received signal sl2 in the case of an analog loop-back or possibly a loop-back 2 in the nt. timers the start of timers is indicated by txs, the expiry by txe. the following table 11 shows which timers are used in lt-modes: table 11 timers used in lt-modes timer duration (ms) function state t1 15000 supervisor for start-up t2 3 tl-transmission receiver reset alerting reset for loop pef 24911 functional description data sheet 62 2001-07-16 3.16.2 outputs of the u-transceiver in lt-mode signals and indications are issued on the iom ? -2-interface (c/i-codes) and u-interface (predefined u-signals). c/i-indications ai activation indication this indication signals that ? act ? = 1 has been received and that timer t8 has elapsed. this indication is not issued in case ar0 is applied to dout or an analog loop-back is operated. ar activation request the ar-code signals that a wake-up signal has been received and that a start-up procedure has commenced. receiver synchronization has not yet been achieved. when already partially active (u only activation), ar indicates that the ? sai ? bit was set to (1), i.e. the s/t-interface has become active. deac deactivation this indication is issued in response to a dr-code (pend. deactivation, tear down) and in the ? reset ? and ? test ? states. di deactivation indication idle code on the iom ? -interface. normally the u-transceiver stays in the ? deactivated ? state unless an activation procedure is started by the nt-side. ei2 error indication 2 ei2 is issued if the received act-bit is (0). the nt receiver indicates a loss of signal or framing on the s/t-interface by setting the upstream act-bit to (0). the u- transceiver remains in the ? transparent ? state. after a signal level or framing is detected again, the c/i-indication ai will be issued anew. ei3 error indication 3 this indication is issued when the u-transceiver has not been able to activate successfully (expiry of timer t1). lsl loss of signal level the u-transceiver has entered a failure condition after loss of signal level (lsue). t3 40 re-transmission of tl wait for tn t4 6000 supervisor sn0 detect awake t5 1000 supervisor ec converge ec training t6 6000 supervisor sn2 detect ec converge t7 40 hold time receiver reset t8 24 delay time for ai detection pend. transparent t9 40 hold time awake error t10 40 ? dea ? = (0) transmission pend. deactivation timer duration (ms) function state pef 24911 functional description data sheet 63 2001-07-16 rsy re-synchronization indication after a loss of framing (lof) for ei3, lsl and rsy indication the lt-side should react by applying the c/i-channel code res1 to allow the u-transceiver to enter the ? receive reset ? state and to reset the receiver functions. fj frame jump this indication signals that either a data buffer overflow/underflow has been detected or a phase jump of one of the iom ? -timing signals dcl or fsc has occurred. the fj-code is issued for a period of 1.5 ms. uai u-activation indication the uai-code signals that the line system is synchronized in both directions of transmission (see also the input act = 1). maintenance bits are transmitted normally. arm activation request maintenance transmission of maintenance bits is possible. signals on u-interface the signals slx, tl and sp transmitted on the u-interface are defined in table 12 "u- interface signals" on page 71 . the polarity of the overhead bits act and dea is indicated as follows: a = 0/1 corresponds to act bit set to binary ? 0/1 ? . d = 0/1 corresponds to dea bit set to binary ? 0/1 ? . the polarity of the transmitted uoa-bit depends on the received c/i-channel code: ? uar sets uoa-bit to binary 0. ? ar, ar0, and arx sets uoa-bit to binary 1. ? any other c/i-codes sets the uoa to the same value as the received sai bit. after deactivation the uoa-bit is set to binary 0 until a valid sai-bit is received. pef 24911 functional description data sheet 64 2001-07-16 3.16.3 lt-states this section describes the functions of all states defined in lt-mode. alerting the wake-up signal tl is transmitted for 3 ms (t2) in response to an activation request from the lt side (ar or arl). in the case of an analog loop-back, the signal tl is forwarded internally to the wake-up signal detector and stored. alerting error when timer t1 (15 s) is expired in state "alerting" before tn has been detected then the dfe-q transits from state "alerting" to state "alerting error". once "alerting error" has been entered the receiver must be reset by c/i res1. awake the ? awake ? state is entered upon the receipt of a wake-up or an acknowledge signal tn from the nt. in the case of an activation started by the lt-side, timer t1 is restarted when the ? awake ? state is entered. awake error the ? awake error ? state is equivalent to the ? awake ? state, but is entered only when a wake-up signal is received while being in the ? receive reset ? state. as the ? receive reset ? state was entered upon the application of the c/i-channel code res1, the ? awake error ? state assures that a minimum amount of time elapses between the application of the res1-code and the u-transceiver entering a state (eq training) in which it again reacts on the res1-code. the lt-side is requested to stop issuing the command res1 within t9 after the receipt of the c/i-channel code ar on dout and to replace it by another command such as the idle code dc for instance. deactivated (full reset) in the ? deactivated ? state the device may enter the low power consumption condition. the power-down mode is entered if no monitor messages are to be expected. in power- down the receiver and parts of the interface are deactivated while functions related to the iom ? -2-interface and the wake-up detector are still active. no signal is sent on the u-interface, the differential outputs aout and bout are set to 0 v. the u-transceiver waits for a wake-up signal tn from the nt-side or an activation request (ar, ar0, uar or arl) from the lt-side to start an activation procedure. note that in state "deactivated" no activation can be initiated by ar, arx, ar0 or uar if a tn tone has been recognized before. this situation can be only resolved by applying dc. therefore it is recommended to apply always dc before ar, arx, ar0 or uar. for the recognition of the wake-up signal tn the following procedure applies: pef 24911 functional description data sheet 65 2001-07-16 ? tn detected for 8 periods ? > transfer within the ? deactivated ? state into power-up ? in power-up both differential outputs, aoutx and boutx, are set to the common mode dc level of vddmin/2 ? tn detected for a total of 12 consecutive periods ? > transition criterion tn fulfilled, change to next state, if in addition the c/i-command dc is given on din. ? tn detected for more than 8 but less than 12 periods ? > return to power-down the input sensitivity is stated in the afe v1.1 data sheet. there the minimum level required is specified to meet the tn transition criterion. the power-up condition may thus already be entered at a lower level. ec converged upon the ec-coefficients having converged, the u-transceiver starts the transmission of signal sl2 and waits for the receipt of signal sn2 from the nt (sec). if no signal is detected within t6, nevertheless the start-up procedure will be continued. in the case of an analog loop-back, this state is left immediately because the ec compensates for the looped back transmit signal. ec-training the signal sl1 is transmitted on the u-interface to allow the lt-receiver to update its ec-coefficients. the ? ec-training ? state is left when the ec has converged (lsec) or when timer t5 has elapsed. timer t5 allows the start-up procedure to proceed even if lsec due to a high noise level on the u-interface for instance, could not be detected. eq-training in state ? eq-training ? the equalizer coefficients are trained for a minimum period of 3 ms. upon expiry of timer t2 state ? eq-training 1 ? is entered. line active in the ? line active ? state, the u-transceiver transmits transparently in both directions. the u-interface is synchronized and the maintenance channel is operational. the u- transceiver stays in the line-active state ? during a normal activation procedure while the ? act ? bit = (0) is received ? when an analog loop-back is established ? while c/i-command ar0 is applied to din in the case of normal activation with call control, binary ? 0s ? have to be applied to the b and d channels on the iom ? -interface. after the c/i-channel indication uai has been issued, the layer-2 receiver should be fully operational to prevent the first layer-2 message issued by the nt-side upon the receipt of the ai-code in the te, to be lost. pef 24911 functional description data sheet 66 2001-07-16 loss of signal the ? loss of signal ? state is entered upon the detection of a failure condition i.e. loss of receive signal (lsue). the act bit is set to ? 0 ? and the c/i-channel indication lsl is issued. the u-transceiver waits for the c/i-channel command res1 to enter the ? receive reset ? state. loss of synchronization the ? loss of synchronization ? state is entered upon the detection of a failure condition i.e. loss of framing by the lt-receiver (lof). the act-bit is set to ? 0 ? and the c/i-channel indication rsy is issued. the u-transceiver waits for the c/i-channel command res1 to enter the ? tear down error ? state and subsequently the ? receive reset ? state. pending deactivation ? pending deactivation ? is a transient state entered after the receipt of a dr-code. the dea-bit is set to ? 0 ? . timer t10 assures that the dea-bit is set to ? 0 ? in at least three consecutive superframes before the transmit level is turned off. pending transparent ? pending transparent ? is a transient state entered upon the detection of act = 1 and left by t8. the act-bit is set to ? 1 ? . the purpose of this state is to issue the c/i-channel indication ai (corresponding to ? ready for sending ? ) 24 ms after the act-bit has been set to ? 1 ? by the lt-transceiver. this assures that under normal operating conditions the ai- indication is issued first on the te-side and only afterwards on the lt-side. thus the layer-2 receiver in the te is already operational when the first layer-2 message is issued by the lt-side. reset the ? reset ? state is entered with the unconditional command res, respectively pin- res. it is left when pin resq is inactive and the c/i-channel code dr is received. sl0 and deac are output in ? reset ? state. the u-transceiver does not react to the receipt of a wake-up signal tn. reset for loop ? reset for loop ? resets the receiver in order to guarantee a correct adaption of the echo- and equalizer coefficients. receive reset the ? receive reset ? state assures that for a period of t7 no signal, especially no wake- up signal tl, is sent on the u-interface, i.e. no activation procedure is started from the lt-side. a wake-up signal tn, however, from the nt-side is acknowledged. pef 24911 functional description data sheet 67 2001-07-16 s/t deactivated the state ? s/t deactivated ? will be entered if the received act- and sai-bits are set to (0). in this state the signal sl3t, act = (0), dea = (1) and uoa = (0) are transmitted downstream. on the iom ? -2-bus the c/i-code uai is issued while the received sai = (0). in order to initiate a complete activation from the s/t deactivation state, the lt needs to set the uoa-bit to (1). this will occur if either of the following three conditions are met: ? c/i = ar(lt-activation) ? sai = (1) & ar(te-activation with exchange control [din = c/i uar]) ? sai = (1)(te-activation without exchange control [din = c/i dc]) ? s/t deactivated ? will be left if the received act bit is (1), or the c/i code ar0 is applied. tear down in ? tear down ? state, transmission ceases in order to deactivate the basic access, and the u-transceiver waits for a response (no signal level, lsu) from the nt-side. tear down error ? tear down error ? state is entered after loss of framing has been detected. transmission ceases in order to deactivate the basic access and the u-transceiver waits for a response (no signal level, lsu) from the nt-side. ei3-indication is transmitted after a transition forced by res1 from the wait-for-tn or eq-training states. in the case of transition from the ? loss of synchronization ? state rsy is sent. test this ? test ? mode is entered when the unconditional commands ltd, ssp or pin-ssp is applied. it is left when pin ssp is set inactive again and the c/i-channel code dr or res1 is received. single pulses (sp) and deac are output in ? test ? state. the u- transceiver does not react to the receipt of a wake-up signal tn. transparent this ? transparent ? state corresponds to the fully active state in the case of a normal activation for call control. it may also be entered in the case of a loop-back #2 if the nt issues act = 1 or in case of a single-channel loop-back in the nt. the lt-side is informed that the status ? ready for sending ? is reached (indication ai). if the nt-side loses transparency (receipt of act = 0), the lt-side is informed by making use of the c/ i-channel indication ei2, but no state change is performed. upon reception of act= (1) the c/i indication ai is issued again. if the s/t-interface is deactivated (sai = (0) & act = (0)), the device is transferred to the s/t deactivated state. pef 24911 functional description data sheet 68 2001-07-16 wait for tn in ? wait for tn ? the u-transceiver waits for a response (tone tn from the nt or tone tl in case of an analog loop-back) to the transmission of the wake-up signal tl. if no response is received within t3, the state is left for re-transmission of a wake-up tone tl. this procedure is repeated until the detection of tone tn or until expiry of timer t1. in this case the c/i-channel indication ei3 is issued, but no state change is performed. pef 24911 operational description data sheet 69 2001-07-16 4 operational description the scope of this section is to describe how the dfe-q v2.1 works and behaves in the system environment. activation/ deactivation control procedures are exemplary given for sw programmers reference. 4.1 reset there are two different ways to apply a reset, either as a hardware reset by setting pin res to low or as a software reset by applying ? c/i= res ? hardware reset a hardware reset affects all design components and takes effect immediately (asynchronous reset style). no clock signal other than the 15.36 mhz master clock is required for reset execution. software reset c/i ? res ? resets the receiver and the activation/deactivation state machine. transmission on u is stopped. it is an unconditional command and is therefore applicable in any state. unlike a hardware reset, a software reset triggered by ? c/i= res ? or ? c/i= res1 ? has only effect on the addressed line port. ? c/i= res resets the receiver and the activation/deactivation state machines. it is an unconditional command. ? c/i= res1 resets all receiver functions. transmission on u is stopped. ec-, and eq- coefficients and agc are set to zero. it is a conditional command. the remaining line ports, the system interface, the relay driver/ status pins and other global functions are not affected. note that fsc and dcl clock signals must be provided for the c/i code processing. 4.2 power down each building block of the dfe-q v2.1 is optimized with respect to power consumption and support a power down mode. see chapter 7.6.2 on page 139 for the specified max. power consumption. the dfe-q v2.1 goes in power down mode if the u-transceiver is in state deactivated. the dfe-q v2.1 leaves power down mode when a wake up tone (tn) has been detected on the u-interface for at least 800 s. as the internal control logic of the activation/deactivation procedures are event driven power is saved as soon as one of the four lines transits in the ? deactivated ? state pef 24911 operational description data sheet 70 2001-07-16 regarding the dfe-q v2.1 power down mode means that the dsp clock is turned off all digital circuits (excluding the iom ? -2 interface) go in power down mode no timing signals are delivered (cls0, ... , cls3) as the internal control logic of the activation/deactivation procedures are event driven power is saved as soon as one of the four lines transits in the deactivated state regarding a connected afe power down mode means that no signal is sent on the u-interface only functions that are necessary to detect the wake up conditions are kept active transmit path, receive path and auxiliary functions of the analog line port are switched to a low power consuming mode when the power down function is activated. this implies the following: the adc, the relevant output is tied to gnd. the dac and the output buffer; the outputs aoutx/ boutx are tied to gnd. the internal dc voltage reference is switched off. the range and the loop functions are deactivated. pef 24911 operational description data sheet 71 2001-07-16 4.3 layer 1 activation/ deactivation procedures this chapter illustrates the interactions during activation and deactivation between the lt and nt station. an activation can be initiated by either of the two stations involved. a deactivation procedure can be initiated only by the exchange. this chapter shows the user how to activate and deactivate the device under various circumstances. two types of start-up procedures are supported by the u-transceiver: cold starts and warm starts. cold starts are performed after a reset and require all echo and equalizer coefficients to be recalculated. this procedure typically is completed after 1-7 seconds depending on the line characteristic and the connected nt. cold starts are recommended for activations where the line characteristic has changed considerably since the last deactivation. a warm start procedure uses the coefficient set saved during the last deactivation. it is therefore completed much faster (maximum 300 ms). warm starts are however restricted to activations where the line characteristic has not changed significantly since the last deactivation. both start-up procedures differ only in the fact that the device has been transferred into the reset state (= cold start) prior to activation. activation initialization and procedure is in both cases identical. the following sections thus apply to both warm and cold start- ups. the table below summarizes the existing u-interface signals as specified by etsi/ ansi. table 12 u-interface signals signal synch. word (sw) superframe (isw) 2b + d m-bits nt-modes (nt ? > lt) tn 1) ? 3 3 3 3 sn0 no signal no signal no signal no signal sn1 present absent 1 1 sn2 present absent 1 1 sn3 present present 1 normal sn3t present present normal normal lt-modes (lt ? > nt) tl 1) 3 3 3 3 sl0 no signal no signal no signal no signal sl1 present absent 1 1 pef 24911 operational description data sheet 72 2001-07-16 note: 1) alternating 3 symbols at 10 khz note: 2) must be generated by the exchange note: 3) if state ? line active ? is entered from state ? eq-training 1 ? the 2b+d data must be clamped to ? 0 ? by the exchange until act= ? 1 ? has been received from the nt- side note: 4) alternating 3 single pulses of 12.5 s duration spaced by 1.5 ms sl2 present present 0 normal sl3 2) present present 0 normal sl3t 3) present present normal normal test mode sp 4) no signal no signal 3 no signal signal synch. word (sw) superframe (isw) 2b + d m-bits pef 24911 operational description data sheet 73 2001-07-16 4.3.1 complete activation initiated by lt figure 28 depicts the procedure if the activation has been initiated by the exchange side. figure 28 complete activation initiated by lt dc u - reference point info 0 r iom - 2 di sn0 dc di r iom - 2 sl0 tl tn sn1 sn0 sl1 sl2 act = 0 dea = 1 uoa = 1 sn2 sn3 act = 1 sai = 1 sl3t act = 1 dea = 1 uoa = 1 sn3t sl3t lt actbylt_2b1q.emf nt s/t ar ar arm uai ai ai ai ar ar dc pu info 0 info 3 info 4 info 2 sl3t act = 0 dea = 1 uoa = 1 sn3 act = 0 sai = 1 sn3 act = 0 (sai = 0) dfe-q v2.1 s-transceiver layer-1 controller u-transceiver pef 24911 operational description data sheet 74 2001-07-16 the activation protocol and the user interactions are summarized below: 4.3.2 activation with act-bit status ignored by the exchange side the lt ignores the act-bit transmitted upstream from the nt if the lt-activation has been initiated with ? ar0 ? instead of ? ar ? . activation with c/i-command ? ar0 ? forces the state machine into the state ? line active ? independently of the act-bit status transmitted upstream from the network. because the activation with ar0 is performed with the uoa-bit set to ? 0 ? , initially only a partial activation is started. by setting uoa = 1 via a mon-2 message the s-interface is activated as well. activation may be completed after the act-bit evaluation has been enabled with c/i-command ? ar ? . nt iom ? -2 lt iom ? -2 < ????? c/i dc (1111 b ) ci/dc (1111 b )< ????? ; initial state is ? deactivated ? ????? > c/i di (1111 b ) c/idi (1111 b ) ????? >; < ????? c/i pu (0111 b ) c/i ar (1000 b )< ????? ; start activation < ????? c/i dc (1111 b ) c/i ar (1000 b ) ????? > ; activation proceeds c/i arm (1001 b ) ????? >; : < ????? c/i ar (1000 b ) c/i uai (0111 b ) ????? >; : ????? > c/i ai (1100 b ) ; ; confirm that terminal is active < ????? c/i ai (1100 b ) c/i ai (1100 b ) ????? > ; activation complete pef 24911 operational description data sheet 75 2001-07-16 figure 29 activation with act-bit status ignored by the exchange dc u - reference point info 0 r iom - 2 di sn0 dc di r iom - 2 sl0 tl sn3 act = 0 sai = 1 sn3 act = 1 sai = 1 sn3t sl3t dfe-q v2.1 lt actbylt_ignact_2b1q.emf nt s/t ar0 ai ai ai info 0 info 3 info 4 info 2 sl3t act = 1 dea = 1 uoa = 1 sl3t act = 0 dea = 1 uoa = 0 sl3t act = 0 dea = 1 uoa = 1 ar sn3 act = 0 (sai = 0) sn2 sl2 act = 0 dea = 1 uoa = 0 sl1 sn0 sn1 tn ar ar mon 2: uoa = 1 uai arm ar dc pu u-transceiver layer-1 controller s-transceiver pef 24911 operational description data sheet 76 2001-07-16 the activation protocol and the user interaction is summarized below: nt iom ? -2 lt iom ? -2 < ????? c/i dc (1111 b ) c/i dc (1111 b )< ????? ; initial state is ? deactivated ? ????? > c/i di (1111 b ) c/i di (1111 b ) ????? >; c/i ar0 (1101 b )< ????? ; start activation < ????? c/i pu (0111 b ) c/i ar (1000 b ) ????? >; < ????? c/i dc (1111 b ) c/i arm (1001 b ) ????? >; c/i uai (0111 b ) ????? >; mon8 pace (80 be h )< ???? ? ; enable control of uoa-bit mon2 uoa (2f ff h )< ????? ; and set uoa = 1 < ????? c/i ar (1000 b ) ????? > c/i ai (1100 b ) : ; confirm that terminal is active < ????? c/i ar (1000 b ) c/i uai (1100 b ) ????? > ; act-bit status ignored c/i ar (1000 b )< ????? ; enable act-bit evaluation < ????? c/i ai (1100 b ) c/i ai (1100 b ) ????? > ; activation complete c/i ar0 (1101 b )< ????? : disable act-bit evaluation < ????? c/i ar (1000 b ) c/i uai (0111 b ) ????? > : act-bit status ignored pef 24911 operational description data sheet 77 2001-07-16 4.3.3 complete activation initiated by te figure 30 depicts the procedure if the activation has been initiated by the terminal side. figure 30 complete activation initiated by te when initiating an activation from the terminal side, the lt must be in the deactivated state. for a te initiated activation to be successful the downstream lt c/i-code must be dc. this is not the case if the deactivated state has been entered from the reset or test state (the last code is dr in this case). dc u - reference point info 0 r iom - 2 sn0 dc di r iom - 2 sl0 actbynt_2b1q.emf s/t info 0 sl3t uoa = 1 sn3 sai = 1 sn2 sl2 act = 0 dea = 1 uoa = 0 sl1 sn0 sn1 tn uai arm ar dc pu info 1 di tim ar ar pef 24911 operational description data sheet 78 2001-07-16 nt iom ? -2 lt iom ? -2 < ????? c/i dc (1111 b ) c/i dc (1111 b )< ????? ; initial state is ? deactivated ? ????? > c/i di (1111 b ) c/i di (1111 b ) ????? > ????? > c/i tim (0000 b ) ; start iom ? -clocks < ????? c/i pu (0111 b ) ; u-transceiver is in power- up ????? > c/i ar (1000 b ) ????? > tim release 2) ; start activation < ????? c/i dc (1111 b ) c/i ar (1000 b ) ????? > ; activation proceeds c/i arm (1001 b ) ????? >; : < ????? c/i ar (1000 b ) c/i uai (0111 b ) ????? >; : ????? > c/i ai (1100 b ) ; ; confirm that terminal is active < ????? c/i ai (1100 b ) c/i ai (1100 b ) ????? > ; activation complete pef 24911 operational description data sheet 79 2001-07-16 4.3.4 complete deactivation figure 31 complete deactivation deactivating the u-interface can be initiated only by the exchange. a deactivation can be started when the device is in the states line active, pend. transparent or transparent. . nt iom ? -2 lt iom ? -2 c/i dr (0000 b )< ????? ; start deactivation < ????? c/i dr (0000 b ) c/i deac (0001 b ) ????? > ; deactivation proceeds c/i di (1111 b ) ????? >; ; deactivation complete on lt ai u - reference point info 4 r iom - 2 ai ar ai r iom - 2 s/t info 3 info 0 sl3t act = 0 dea = 1 dc sl3t act = 1 dea = 1 uoa = 1 sn3t act = 1 sai = 1 sn0 sl0 dr dr deac di di dc info 0 3 ms 40 ms lt deac_2b1q.emf nt 3 ms 40 ms tim u-transceiver dfe-q v2.1 layer-1 controller s-transceiver pef 24911 operational description data sheet 80 2001-07-16 4.3.5 partial activation (u only) if the u-transceiver is only partially activated the s-interface remains deactivated. when the partial activation is initiated by the lt-side, the exchange has two options: first, in case the c/i-command dc is not issued after the partial activation is complete, the exchange has to issue ar before a terminal initiated complete activation request is accepted. this allows the exchange to retain full control, even in case of terminal initiated activation requests. secondly the exchange can issue dc after uai has been received. this allows the terminal to activate the s-interface independently of the exchange. in this case the exchange has no control of the s-interface activation procedure. the nt u-transceiver is in the ? synchronized 1 ? state after a successful partial activation. on dout the c/i-message ? dc ? as well as the lt-user data is sent. while the c/i-messages ? di ? (1111 b ) or ? tim ? (0000 b ) are received on din, the u- transceiver will transmit ? sai ? = (0) upstream. any other code results in ? sai ? = (1) to be sent. on the u-interface the signal sn3 (i.e. 2b + d = (1)) will be transmitted continuously regardless of the data on din. the lt will transmit all user data transparently downstream (signal sl3t). in case the last c/i-command applied to din was ? uar ? , the lt retains activation control when an activation request comes from the terminal (confirmation with c/i = ? ar ? required. with c/i ? dc ? applied on din, te initiated activations will be completed without the necessity of an exchange confirmation. ????? > c/i di (1111 b ) ; power down nt < ????? c/i dc (1111 b ); ; deactivation complete on nt nt iom ? -2 lt iom ? -2 < ????? c/i dc (1111 b ) c/i dc (1111 b )< ????? ; initial state is ? deactivated ? ????? > c/i di (1111 b ) c/i di (1111 b ) ????? > c/i uar (0111 b )< ???? ? ; start partial activation < ????? c/i pu (0111 b ) c/i ar (1000 b ) ????? > ; activation proceeds < ????? c/i dc (1111 b ) c/i arm (1001 b ) ????? >; : c/i uai (0111 b ) ????? > ; partial activation complete [c/i dc (1111 b )] < ????? ; ; exchange retains no control of s-interface activation nt iom ? -2 lt iom ? -2 pef 24911 operational description data sheet 81 2001-07-16 figure 32 u only activation actbylt_uar_2b1q.emf dc u - reference point info 0 r iom - 2 di sn0 dc di r iom - 2 sl0 tl tn sn1 sn0 sl1 sl2 act = 0 dea = 1 uoa = 0 sn2 s/t uar ar arm uai (dc) dc pu info 0 sl3t act = 0 dea = 1 uoa = 0 sn3 act = 0 sai = 0 lt nt dfe-q v2.1 layer-1 controller u-transceiver s-transceiver pef 24911 operational description data sheet 82 2001-07-16 4.3.6 activation initiated by lt with u active when u is already active, the s-interface can be activated either by the exchange or by the terminal. the first case is described here, the second in the next section. figure 33 lt initiated activation with u-interface active the s-interface is activated from the exchange with the command ? ar ? . bit ? uoa ? changes to (1) requesting s-interface activation. actbylt_uactiv_2b1q.emf u - reference point info 0 r iom - 2 dc / uar uai r iom - 2 s/t info 0 dc sl3t act = 0 dea = 1 uoa = 0 sn3 act = 0 sai = 0 sn3 act = 0 sai = 1 uai di lt u-transceiver nt ai ai info 2 info 3 sl3t act = 0 dea = 1 uoa = 1 sn3t sn3 act = 1 sai = 1 sl3t act = 1 dea = 1 uoa = 1 ar ar info 4 ai sl3t ar ar dfe-q v2.1 layer-1 controller s-transceiver pef 24911 operational description data sheet 83 2001-07-16 nt iom ? -2 lt iom ? -2 < ????? c/i dc (1111 b ) c/i uar [dc] < ????? ; u only is activated ????? > c/i di (1111 b ) c/i uai (0111 b ) ????? >; ; [exchange retains no control] c/i ar (1000 b )< ???? ? ; start complete activation < ????? c/i ar (1000 b ) ????? > c/i ar (1100 b ) c/i ar (1000 b ) ????? > ; activation proceeds ????? > c/i ai (1100 b ) ; ; confirm that terminal is active c/i uai (0111 b ) ????? > < ????? c/i ai (1100 b ) c/i ai (1100 b ) ????? > ; activation complete pef 24911 operational description data sheet 84 2001-07-16 4.3.7 activation initiated by te with u active when the terminal requests to activate the s-interface (u-interface already active) two cases can occur: in the first case the exchange has retained control over the s-interface activation. then s-activation can proceed only after the explicit permission by the exchange with ar. this situation is discussed in this section under ? case 1 ? . in the second case the exchange is not requested to send ar in order to continue activation. this situation is described in ? case 2 ? of this section. the te initiates complete activation with info 1 leading to ? sai ? = (1). case 1 requires the exchange side to acknowledge the te-activation by sending c/i = ? ar ? , case 2 activates completely without any lt-confirmation. the te recognizes no difference between the two types, the procedure on nt-side consequently is identical in both cases. figure 34 te-activation with u active and exchange control (case 1) actbynt_uactiv1_2b1q.emf u - reference point info 0 r iom - 2 uar uai r iom - 2 s/t dc sl3t act = 0 dea = 1 uoa = 0 sn3 act = 0 sai = 0 uai di lt u-transceiver nt ai ai info 2 info 3 sn3t sn3 act = 1 sai = 1 ar info 4 ai sl3t ar ar info 0 info 1 ar sn3 act = 0 sai = 1 sl3t act = 0 dea = 1 uoa = 1 sl3t act = 1 dea = 1 uoa = 1 dfe-q v2.1 layer-1 controller s-transceiver pef 24911 operational description data sheet 85 2001-07-16 case 1 (controlled by exchange) nt iom ? -2 lt iom ? -2 < ????? c/i dc (1111 b ) c/i uar (0111 b )< ????? ; u only is activated ????? > c/i di (1111 b ) c/i uai (0111 b ) ????? > ????? > c/i ar (1000 b ) ; ; terminal requests activation c/i ar (1000 b ) ????? >; ; exchange is notified of request c/i ar (1000 b )< ????? ; ; exchange permits s-activation < ????? c/i ar (1000 b ) ????? > c/i ai (1100 b ) ; ; confirm that terminal is active c/i uai (0111 b ) ????? > < ????? c/i ai (1100 b ) c/i ai (1100 b ) ????? > ; activation complete pef 24911 operational description data sheet 86 2001-07-16 figure 35 te-activation with u active and no exchange control (case 2) case 2 (no control by exchange) nt iom ? -2 lt iom ? -2 < ????? c/i dc (1111 b ) c/i dc < ????? ; u only is activated ????? > c/i di (0011 b ) c/i uai (0111 b ) ????? > ????? > c/i ar (1000 b ) ; ; terminal requests activation c/i ar (1000 b ) ????? > ; exchange is notified of < ????? c/i ar (1000 b ) ; proceeding s-activation ????? > c/i ai (1100 b ) ; ; confirm that terminal is active c/i uai (0111 b ) ????? > < ????? c/i ai (1100 b ) c/i ai (1100 b ) ????? > ; activation complete actbynt_uactiv2_2b1q.emf u - reference point info 0 r iom - 2 dc uai r iom - 2 s/t dc sl3t act = 0 dea = 1 uoa = 0 sn3 act = 0 sai = 0 uai di lt u-transceiver nt ai ai info 2 info 3 sn3t sn3 act = 1 sai = 1 ar info 4 ai sl3t ar info 0 info 1 ar sn3 act = 0 sai = 1 sl3t act = 0 dea = 1 uoa = 1 sl3t act = 1 dea = 1 uoa = 1 dfe-q v2.1 layer-1 controller s-transceiver pef 24911 operational description data sheet 87 2001-07-16 4.3.8 deactivating s/t-interface only the following shows the procedure for deactivating the s-interface only while leaving the u-interface active. deactivation of the s-interface only is initiated from the exchange by setting the ? uoa ? bit = (0). figure 36 deactivation of s/t only nt iom ? -2 lt iom ? -2 < ????? c/i ai (1100 b ) c/i ai (1100 b ) ????? > ; initial state: layer 1 activated ????? > c/i ai (1100 b ) c/i ar (1000 b )< ????? < ????? c/i dr (0000 b ) c/i uar (0111 b )< ????? ; deactivate s-interface only deacst_2b1q.emf u - reference point info 4 r iom - 2 ar ai r iom - 2 s/t ai sl3t act = 1 dea = 1 uoa = 1 sn3t act = 1 sai = 1 ai dc di info 0 info 0 sn3 act = 0 sai = 0 dr info 3 sl3t act = 1 dea = 1 uoa = 0 sl3t act = 0 dea = 1 uoa = 0 uar uai (dc) lt u-transceiver nt dfe-q v2.1 layer-1 controller s-transceiver pef 24911 operational description data sheet 88 2001-07-16 4.4 maintenance and test functions this chapter summarizes all features provided by the dfe-q v2.1 to support maintenance functions and system measurements. three main groups may be distinguished: ? maintenance functions to close and open test loopbacks ? features facilitating the recognition of transmission errors ? test modes required for system measurements the next sections describe how these test and maintenance functions are implemented and used in applications. 4.4.1 test loopbacks test loopbacks are specified by the national ptts in order to facilitate the location of defect systems. four different loopbacks are defined. the position of each loopback is illustrated in figure 37 . figure 37 test loopbacks ????? > c/i di (1111 b ) c/i uai (0111 b ) ????? > ; s-interface is deactivated < ????? c/i dc (1111 b ) [c/i dc (1111 b )] < ????? ; exchange retains no control nt iom ? -2 lt iom ? -2 iom ? -2 pbx or te u-transceiver iom ? -2 iom ? -2 iom ? -2 u-transceiver u-transceiver u-transceiver u-transceiver u-transceiver loop 2 loop 3 loop 2 loop 1 a loop 2 loop 1 s-bus nt u u loop 2 repeater (optional) s- tr ansc eiv er layer-1 controller layer-1 controller iom-2 exchange l oop_2b1q.emf pef 24911 operational description data sheet 89 2001-07-16 loopbacks #1, #1a and #2 are controlled by the exchange. loopbacks #1 is closed by the dfe-q v2.1 itself whereas loopbacks #1a and #2 are remote controlled and closed in the repeater and nt. loopback #3 is closed and controlled by the terminal. all four loopback types are transparent. this means all bits that are looped back will also be passed onwards in the normal manner. the propagation delay of b- and d-channel data is identical in all loopbacks. beside the remote loopback stimulation via the eoc- and mon-channel the dfe-q v2.1 features also direct loopback control via its register set. the next sections describe how these loopbacks are closed and opened using c/i- and mon-commands. 4.4.1.1 analog loopback (no.1) loopback #1 is closed by the dfe-q v2.1 as near to the u-interface as possible. for this reason it is called analog loopback. the 6 db range attenuation in the receive path is active. transparent all analog signals will still be passed on to the u-interface. as a result the nt-station will be activated as well. only the internal loopback signal is processed. signals on the receive pins are ignored. for this reason the device stays in the ? line active ? state (upstream act-bit cannot be received). loopback activation before an analog loopback is closed the device should have been reset and put into state ? deactivated ? first before loop-back #1 is closed. then the c/i-command arl (activation request loopback) must be applied continuously as long as the loopback is requested. loopback deactivation in order to open an analog loopback again the device should be reset by applying the c/ i-command res (or by pin reset). this ensures that the echo coefficients and equalizer coefficients will converge correctly when activating the next time. the example below demonstrates the control of loopbacks #1. nt iom ? -2 lt iom ? -2 < ????? c/i dc (1111b) c/i di (1111b) ????? > c/i arl (1010b) < ????? ; close loopback #1 pef 24911 operational description data sheet 90 2001-07-16 4.4.1.2 loopback no.2 - overview for loopback #2 several alternatives exist. both the type of loopback and the location may vary. three loopback types belong to the loopback #2 category: complete loopback, in the nt u-transceiver or in a downstream device b1-channel loopback, always performed in the nt u-transceiver b2-channel loopback, always performed in the nt u-transceiver all loop variations are closed as near to the iom ? -interface as possible. complete loopback the complete loopback comprises both b-channels and the d-channel. it may be closed either in the u-transceiver itself or in a downstream device. the propagation delay of b and d-channel data is identical. single channel loopback single channel loopbacks are always performed within the u-transceiver. in this case the digital data of dout will be directly fed back into din. this also applies if the complete loopback is closed in the u-transceiver. normally loopback #2 is controlled from the exchange by the mon-0 commands lbbd, lb1 and lb2. the loop requests are recognized and executed automatically by the nt u-transceiver if automode is selected. all loopback functions are latched in the nt. this allows channel b1 and channel b2 to be looped back simultaneously. all loopbacks are opened again upon reception of the eoc command rtn. transparency data sent downstream will be passed on transparent independently of closed loopbacks. < ????? c/i ar (1000b) c/i ar (1000b) ????? > ; activation proceeds in nt c/i arm (1001b) ????? > ; and lt c/i uai (0111b) ????? >; ; activation complete, #1 closed c/i res (0001b) < ????? ; ; open loopback #1, reset the u-transceiver nt iom ? -2 lt iom ? -2 pef 24911 operational description data sheet 91 2001-07-16 4.4.1.3 loopback no.2 - complete loopback upon receiving the eoc-command lbbd in eoc automode, the nt u-transceiver does not close the loopback immediately. because the intention of this loopback is to test the complete nt, the u-transceiver passes the complete loopback request on to the next downstream device (e.g. s-transceiver). this is achieved by issuing the c/i-code ail in the ? transparent ? state or c/i = arl in states different than ? transparent ? . if the downstream device is not able to close the complete loopback, a mon-8-message lbbd may be returned to the nt u-transceiver. this in turn will close the complete loopback within the nt u-transceiver itself (b1 + b2 + d-channels). all remaining iom ? -information (monitor, c/i-channel as well as the bits mr and mx) are still read from the iom ? -2-interface. for this reason it is still possible for a layer-2 device to deactivate the nt despite the fact that the loopbacks are controlled by the exchange. figure 38 illustrates these two options. figure 38 complete loopback options in the nt the complete loopback is opened again by the nt u-transceiver (e.g. iec-q, peb 2091) when the eoc command rtn or the mon-8-command norm is received. no reset is required for loopback #2. the line stays active and is ready for data transmission. the typical procedure for closing and opening a complete loopback is demonstrated in the examples below. there the lt is always operated in eoc automode. complete loopback in eoc automode (nt-side): nt iom ? -2 lt iom ? -2 c/i ar (1000 b )< ???? ; u-interface is activated < ???? c/i ar (1000 b ) c/i uai (0111 b ) ???? >; ; without terminal confirmation ( ??? > c/i ai (1100 b ) ; or with 2b+d 28 b+d auto- mode mon-8 "lbbd" c/i = ail/arl u eoc= "lbbd" l p2bymon8.emf nt u- tr ans c eiv er layer-1 controller s-transceiver pef 24911 operational description data sheet 92 2001-07-16 < ???? c/i ai (1100 b ) c/i ai (1100 b ) ???? > ; terminal confirmation) mon-0 lbbd (50 h )< ???? ; close complete loop (eoc) < ???? c/i ail (1110 b ) ; request for downstream < ???? mon-0 lbbd (50 h ); ; device to close complete loopback mon-0 lbbd (50 h ) ???? > ; receive acknowledgment ???? >mon-8 lbbd (f1 h ) ; ; if downstream device can ? t close, loop is closed in the nt u-transceiver mon-0 rtn (ff h )< ???? ; open all loopbacks < ???? mon-0 rtn (ff h ) ; all loopbacks opened mon-0 rtn (ff h ) ???? > ; receive acknowledgment nt iom ? -2 lt iom ? -2 pef 24911 operational description data sheet 93 2001-07-16 complete loopback in eoc transparent mode (nt side): 4.4.1.4 loopback no.2 - single channel loopbacks single channel loopbacks are always performed directly in the nt u-transceiver. no difference between the b1-channel and the b2-channel loopback control procedure exists. they are therefore discussed together. in eoc automode the b1-channel is closed by the eoc-command lb1. lb2 causes the channel b2 to loopback. because these functions are latched, both channels may be looped back simultaneously by sending first the command to close one channel followed by the command for the remaining channel. in eoc transparent mode single channels are closed by the corresponding mon-8- commands. single channel loopbacks are resolved in the same manner as described for the complete loopback, either by the eoc command rtn or by the mon-8 command norm. the nt may be deactivated while single loopbacks are closed. typical procedures for closing and opening single channel loopbacks are given in the examples below. there the lt is always operated in eoc automode. nt iom ? -2 lt iom ? -2 ??? > c/i ai (1100 b ) c/i ar (1000 b )< ???? ; u-interface is activated < ??? c/i ai (1100 b ) c/i ai (1100 b ) ???? > mon-0 lbbd (50 h ) < ???? ; close complete loop (eoc) < ???? mon-0 lbbd (50 h ); ; request passes transparently the nt u-transceiver ??? >mon-0 lbbd (50 h ) mon-0 lbbd (50 h ) ???? > ; transmit acknowledgment ??? >mon-8 lbbd (f1 h ) ; close complete loop in iec < ???? mon-0 rtn (ffh) mon-0 rtn (ff h ) < ???? ; request to open all loops ??? > mon-0 rtn (ff h ) mon-0 rtn (ff h ) ???? > ; receive acknowledgment ??? >mon-8 norm (ff h ) ; open all loopbacks pef 24911 operational description data sheet 94 2001-07-16 single-channel loopback in eoc automode (nt-side): single-channel loopback in eoc transparent mode (nt-side): nt iom ? -2 lt iom ? -2 ??? > c/i ai (1100 b ) c/i ar (1000 b )< ???? ; u-interface is activated < ??? c/i ai (1100 b ) c/i ai (1100 b ) ???? > mon-0 lb1 (51 h ) < ???? ; close b1 loop (eoc) < ??? mon-0 lb1 (51 h ) ; loop b1 closed mon-0 lb1 (51h) ???? > ; receive acknowledgment mon-0 lb2 (52 h ) < ???? ; close b2 loopback (eoc) < ??? mon-0 lb2 (52 h ); ; loop-back b1 and b2 closed mon-0 lb2 (52 h ) ???? > ; receive acknowledgment mon-0 rtn (ff h ) < ???? ; open all loopbacks < ??? mon-0 rtn (ff h ) ; all loopbacks opened mon-0 rtn (ff h ) ???? > ; receive acknowledgment nt iom ? -2 lt iom ? -2 ??? > c/i ai (1100 b ) c/i ar (1000 b )< ???? ; u-interface is activated < ??? c/i ai (1100 b ) c/i ai (1100 b ) ???? > mon-0 lb1 (51 h ) < ???? ; close b1 loop (eoc) < ??? mon-0 lb1 (51 h ); ; request passes iec transparent ??? >mon-0 lb1(51 h ) mon-0 lb1 (51 h ) ???? > ; transmit acknowledgment ??? > mon-8 lb1 (f4 h ) ; close b1 loop in iec mon-0 lb2 (52 h ) < ???? ; close b2 loop (eoc) < ??? mon-0 lb2 (52 h ); ; request passes iec transparent ??? >mon-0 lb2(52 h ) mon-0 lb2 (52 h ) ???? > ; transmit acknowledgment ??? > mon-8 lb2 (f2 h ) ; ; close b2 loop in iec b1 and b2 closed mon-0 rtn (ff h ) < ????? ; request to open all loops ??? >mon-0 rtn(ff h ) mon-0 rtn (ff h ) ????? > ; receive acknowledgment ??? >mon-8 norm (ff h ) ; open all loopbacks pef 24911 operational description data sheet 95 2001-07-16 4.4.1.5 local loopbacks featured by register loop besides the standardized remote loopbacks the dfe-q v2.1 features additional local loopbacks for enhanced test and debugging facilities. the local loopbacks that are featured by the internal register loop are shown in figure 39 . they are closed in the dfe-q v2.1 itself. by register loop it can be configured whether the digital local looback is closed only for the b1 and/or b2 or for all isdn-ba channels and whether the loopback is closed towards the iom ? -2 interface or towards the u-interface. the bit trans in the loop register allows for selection of transparent or non- transparent loopback mode. in transparent mode the data is both passed on and looped back. in non-transparent mode the data is not forwarded but substituted by 1s (idle code). note: the digital framer/deframer loopback (dlb) is always transparent. besides the loopbacks in the system interface a further digital loopback, the framer/ deframer loopback, is provided. it allows to test all digital functions of the 2b1q u- transceiver besides the signal processing blocks. however, an activation procedure is not possible by closing the framer/deframer loopback. therefore, before loop dlb may be closed, the dfe-q v2.1 must be in a transparent state, e.g. by applying c/i-command ? data through dt ? . if dlb is set to ? 1 ? in state ? deactivated ? , then a subsequent activation fails. pef 24911 operational description data sheet 96 2001-07-16 figure 39 loopbacks featured by register loop iom ? -2 dfe-q v2.1 loop.lb1=1 or loop.lb2=1 or loop.lbbd= 1 & loop.u/iom= 1 loop.lb1=1 or loop.lb2=1 or loop.lbbd= 1 & loop.u/iom= 0 iom ? -2 dfe-q v2.1 loopreg .emf loop.dlb= 1 dsp a g c equalizer pdm filt er + activation/deactivation controller u protocol processing unit siu de - scr am ble r u de - fr am in g 2b1q de cod e r system interface un it ec h o canceller tim ing recove ry scr am ble r u fr am in g 2b1q encoder dsp a g c eq u a li z e r pdm filter + activation/deactivation controller u protocol processing unit siu de - scram bler u de - fr am ing 2b1q de cod e r system interface un it tim ing re cove r y scram bler u fr am in g 2b1q encoder ec h o canceller pef 24911 operational description data sheet 97 2001-07-16 4.4.2 bit error rate counter for bit error rate monitoring the dfe-q v2.1 features a 16-bit bit error rate counter (berc) per line. the function is channel selective. the user can direct that the measurement is performed only for the b1 or for the b2 or for the b1-, b2- and the d- channel. prerequisite is that the corresponding loop #2 of the addressed channel(s) has been closed on the nt side before by an eoc command. operation: the respective loopback command has to be transmitted to the nt (eoc message lbbd, lb1, or lb2). the system sets the respective channel to ? all zeros ? . the respective lineport is adressed by setting the lp_sel register. the berc counter is reset to ? 0000 ? by reading register berc. the berc counter can be started after some time (full round trip delay) by selecting the channel (s) to be checked in bits test.ber. the berc is stopped by setting test.ber to ? 00 ? . the number of bit errors (received ? 1 ? s) can be read in register berc. the system can enable the tested channel again. 4.4.3 block error counters the dfe-q v2.1 provides internal counters for far-end and near-end block errors. this allows a comfortable surveillance of the transmission quality on the u-interface. in addition mon-messages indicate the occurrence of near-end errors, far-end errors and the simultaneous occurrence of both error types. a block error is detected each time when the calculated checksum of the received data does not correspond to the control checksum transmitted in the successive superframe. one block error thus indicates that one u-superframe has not been transmitted correctly. no conclusion with respect to the number of bit errors is therefore possible. the following two sections describe the operation of near and far-end block error counters as well as the commands available to test them. 4.4.3.1 near-end and far-end block error counter a near-end block error (nebe) indicates that the error has been detected in the receive direction (i.e. nebe = nt => lt error). each detected nebe-error increments the 8-bit nebe-counter. the nebe counter stops at its maximum value ff h and does not overflow. the current value of the nebe counter can be read by the mon-8-command rben. the response comprises two bytes: the first byte always indicates that a mon-8-message is replied (80 h ), the second represents the counter value (00 h ) ? (ff h ). each read operation resets the counter to (00 h ). pef 24911 operational description data sheet 98 2001-07-16 a far-end block error identifies errors in transmission direction (i.e. febe = lt => nt error). febe errors are processed in the same manner as nebe-errors. the febe counter is read and reset by the mon-8-command rbef. pef 24911 operational description data sheet 99 2001-07-16 near-end errors - summary: - definition a near-end block error (nebe) indicates errors that occurred in the receive direction, i.e. an detected error during transmission from nt to lt. a near-end block error is considered detected when the calculated check-sum of the received u-superframe does not correspond to the check-sum sent in the following u-superframe. - indications each detected nebe causes the nebe counter to be incremented (maximum count is ff h , no overflow). the u-maintenance bit ? febe ? is set to zero in the next u-superframe (for a duration of one superframe). - read out and reset the counter value may be read out by the mon-8-command rben c0 ? c7: 8-bit counter value each read operation resets the nebe-counter to 00 h . the counter is also reset in all states except the following ones: - line active - pend. transparent - transparent - s/t deactivated mon-8 rben read block errors near-end 10000000 11111011 mon-8 aben answer block errors near-end 1 0 0 0 0 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0 pef 24911 operational description data sheet 100 2001-07-16 far end errors - summary: - definition a far-end block error (febe) indicates errors that occurred in the transmit direction, i.e. an detected error during transmission from lt to nt. a far-end block error is detected when the u-maintenance bit ? febe ? is set to zero. - indications each detected febe will cause the febe-counter to be incremented (maximum count is ff h , no overflow) - read out and reset the counter value may be read out by the mon-8-command rbef c0 ? c7:8-bit counter value each read operation resets the febe-counter to 00 h . the counter is also reset in all states except the following ones: - line active - pend. transparent - transparent - s/t deactivated the following section illustrates how block error counters are tested. 4.4.3.2 testing block error counters figure 40 illustrates how near- and far-end block error counters can be tested. transmission errors are simulated with artificially corrupted crcs. with two commands the cyclic redundancy checksum can be inverted. a third command offers the possibility to invert single febe-bits. mon-8 ccrc causes the dfe-q v2.1 to permanently transmit inverted crcs. with ccrc issued on lt-side, near-end block errors will be observed at the nt and far-end errors are noticed at the lt. mon-8 rbef read block errors far-end 10000000 11111010 mon-8 aben answer block errors far-end 1 0 0 0 0 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0 pef 24911 operational description data sheet 101 2001-07-16 mon-0 rcc requests the nt to send corrupt crcs. again the crc will be permanently inverted. after issuing rcc (nt in eoc automode) near-end block errors will be registered on the lt-side. mon-0 ncc requests the nt to disable the nebe-detection. however, the ncc command shows only effect if the nt u-transceiver operates in eoc automode. the different behavior of the nt u-transceiver is summarized below auto-modenebe-detection stopped, no mon-1 nebe messages and nebe-counter disabled transparent modenebe-detection enabled, mon-1-message nebe issued and nebe-counter enabled mon-8 sfb causes the dfe-q v2.1 to invert single febe-bits. because this command does not provoke permanent febe-bit inversion but sets only one febe- bit to (0) per sfb command it is possible to predict exactly the febe-counter value. mon-0 rtn and mon-8 norm disable again activated test functions pef 24911 operational description data sheet 102 2001-07-16 figure 40 block error counter test pef 24911 operational description data sheet 103 2001-07-16 4.4.4 system measurements the dfe-q v2.1 features dedicated test modes to enable and ease system measurements on u-interface. how these test modes can be used to conduct the most frequently needed system measurements is described in the following sections. 4.4.4.1 single-pulses test mode (ssp) in the send single pulses test mode the u-transceiver transmits on the u-interface alternating 3 pulses spaced by 1.5 ms. two options exist for selecting the ? send- single-pulses ? (ssp) mode: ? hardware selection: pin-ssp= ? 1 ? ? software selection: c/i code= ssp (0101 b ) both methods are fully equivalent besides the fact that the hw selection impacts all line ports while the sw selection impacts only the chosen line. in ssp-mode the c/i-code transmitted by the dfe-q v2.1 is deac. the ssp-test mode is required for pulse mask measurements. 4.4.4.2 data through test mode (dt) when selecting the data-through test mode the dfe-q v2.1 is forced directly into the ? transparent ? state. this is possible from any state in the state diagram. note: data through is a pure test mode. it is not suited to replace the activation/ deactivation procedures for normal operation, which are described in chapter 4.3 . the data-through option (dt) provides the possibility to transmit a standard scrambled u-signal even if no u-interface wake-up protocol is possible. this feature is of interest when no counter station can be connected to supply the wake-up protocol signals. as with the ssp-mode, two options are available. ? hardware selection: pin-dt= ? 1 ? ? software selection: c/i code= dt (0110 b ) both methods are fully equivalent besides the fact that the hw selection impacts all line ports while the sw selection is channel selective. note: in contrast to former versions, c/i-command ? arl ? is not executed while data through test mode is activated with pin dt = ? 1 ? . the dt test mode is required for power spectral density and total power measurements. 4.4.4.3 reset mode in the reset mode the dfe-q v2.1 does not transmit any signals. the chip is in reset state. all echo canceller and equalizer coefficients are reset. pef 24911 operational description data sheet 104 2001-07-16 there are two methods in order to transfer the u-transceiver into the reset mode (see chapter 7.4.1 for reset timing): ? hardware selection: pin res = ? 0 ? -> ? 1 ? ? software selection: c/i-code= res (0001 b ) both alternatives are fully compatible besides the fact that the sw selection is channel selective. the c/i-code deac is output by the dfe-q v2.1 in the reset state. the master reset test mode is used for return-loss measurements. 4.4.4.4 pulse mask measurement ? pulse mask is defined in ansi t1.601 and etsi ts 102 080 ? u-interface has to be terminated with 135 ? ? dfe-q v2.1 is in send single pulses test mode (c/i = ? ssp ? or pin ssp= ? 1 ? ) ? measurements are done using an oscilloscope 4.4.4.5 power spectral-density measurement ? psd is defined in ansi t1.601 and etsi ts 102 080 ? u-interface has to be terminated with 135 ? ? dfe-q v2.1 is in data through test mode (c/i = ? dt ? or pin dt= ? 1 ? ) ? for measurements a spectrum analyzer is employed 4.4.4.6 total power measurement ? total power is defined in ansi t1.601 and etsi ts 102 080 ? total power must be between 13 dbm and 14 dbm ? u-interface has to be terminated with 135 ? ? dfe-q v2.1 is in data through test mode (c/i= ? dt ? or pin dt= ? 1 ? ) ? measurements are done using an 80 khz high-impedance low-pass filter and true rms-voltmeter figure 41 total power measurement set-up dfe-q v2.1 true rms voltmeter 80 khz totpow .emf pef 24911 operational description data sheet 105 2001-07-16 4.4.4.7 return-loss measurement ? return loss is defined in ansi t1.601 and etsi ts 102 080 ? dfe-q v2.1 is in reset state (c/i = ? res ? or pin res = ? 0 ? ) ? measure complex impedance ? z ? from 1 khz ? 200 khz ? calculate return loss with formula: rl(db) = 20log (abs((z + 135) / (z ? 135))) 4.4.4.8 quiet mode measurement ? quite mode is defined in ansi t1.601 and etsi ts 102 080 ? dfe-q v2.1 is in the ? reset ? state (c/i = ? res ? or pin res = ? 0 ? ) ? trigger and exit criteria have to be realized externally 4.4.4.9 insertion loss measurement ? insertion loss is defined in ansi t1.601 and etsi ts 102 080 ? dfe-q v2.1 is in data through test mode (c/i = ? dt ? or pin dt= ? 1 ? ) ? trigger and exit criteria have to be realized externally 4.4.5 boundary scan the dfe-q v2.1 provides a boundary scan support for a cost effective board testing. it consists of: boundary scan according to ieee 1149.1 specification test access port controller (tap) five dedicated pins (tck, tms, tdi, tdo, trst ) pins trst , tdi and tms are provided with an internal pullup resistor one 32-bit idcode register pin trst tied to low resets the boundary scan tap controller (recommended setting for normal operation if the boundary scan logic is not used) instructions clamp and highz were added, instructions ssp and dt were removed in v2.1 pef 24911 operational description data sheet 106 2001-07-16 boundary scan all pins except the power supply pins, the "not connected" pins and the pins tdi, tdo, tck, tms, and trst are included in the boundary scan chain. depending on the pin functionality one, two or three boundary scan cells are provided. table 13 boundary scan cells. when the tap controller is in the appropriate mode data is shifted into or out of the boundary scan via the pins tdi/tdo using the 6.25 mhz clock on pin tck. the pins are included in the following sequence in the boundary scan chain: pin type number of boundary scan cells usage input 1 input output 2 output, enable i/o 3 input, output, enable boundary scan number tdi ?? > pin number pin name type number of scan cells 1. 62 dt i 1 2. 61 cls3 i/o 3 3. 60 res i 1 4. 59 auto i 1 5. 58 pbx i 1 6. 56 ssp i 1 7. 55 slot0 i 1 8. 53 lt i 1 9. 52 cls2 i/o 3 10. 51 d3d i/o 3 11. 50 d2d i/o 3 12. 49 crcon i 1 13. 48 d1d i/o 3 14. 47 d0d i/o 3 15. 46 d3c i/o 3 pef 24911 operational description data sheet 107 2001-07-16 16. 45 slot1 i 1 17. 44 d2c i/o 3 18. 43 d1c i/o 3 19. 42 d0c i/o 3 20. 40 d3b i/o 3 21. 39 d2b i/o 3 22. 37 d1b i/o 3 23. 35 d0b i/o 3 24. 34 d3a i/o 3 25. 33 d2a i/o 3 26. 32 pup i 1 27. 31 d1a i/o 3 28. 30 d0a i/o 3 29. 29 cls0 i/o 3 30. 28 st00 i 1 31. 27 st01 i 1 32. 26 st10 i 1 33. 24 st11 i 1 34. 23 st20 i/o 3 35. 21 st21 i/o 3 36. 20 cls1 i/o 3 37. 19 st30 i/o 3 38. 18 st31 i/o 3 39. 17 sdx i/o 3 40. 16 tpd i 1 41. 15 dout i/o 3 42. 14 din i 1 43. 13 fsc i 1 44. 12 dcl i 1 45. 11 pdm0 i 1 boundary scan number tdi ?? > pin number pin name type number of scan cells pef 24911 operational description data sheet 108 2001-07-16 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee 1149.1. transitions on pin tms cause the tap controller to perform a state change. before operation the tap controller has to be reset by trst . according to the ieee 1149 standard 7 instructions are executable. the instructions ? clamp ? and ? highz ? were added. instructions ? ssp ? and ? dt ? are no more supported since its function is identical to that of the ssp and dt pins. table 14 tap controller instructions: extest is used to examine the board interconnections. when the tap controller is in the state "update dr", all output pins are updated with the falling edge of tck. when it has entered state "capture dr" the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state "update dr", all inputs are updated internally with the falling edge of tck. when it has entered state "capture dr" the levels of all outputs 46. 10 pdm1 i 1 47. 8 pdm2 i 1 48. 7 pdm3 i 1 49. 5 sdr i 1 50. 4 cl15 i 1 code instruction function 0000 extest external testing 0001 intest internal testing 0010 sample/preload snap-shot testing 0011 idcode reading id code 0100 clamp reading outputs 0101 highz z-state of all boundary scan output pins 1111 bypass bypass operation boundary scan number tdi ?? > pin number pin name type number of scan cells pef 24911 operational description data sheet 109 2001-07-16 are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. 0001 (intest) is the default value of the instruction register. sample/preload provides a snap-shot of the pin level during normal operation or is used to preload (tdi) / shift out (tdo) the boundary scan with a test vector. both activities are transparent to the system functionality. idcode register the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to "1". note: in the state "test logic reset" the code "0011" is loaded into the instruction code register. clamp allows the state of the signals included in the boundary scan driven from the pef 24911 to be determined from the boundary scan register while the bypass register is selected as the serial path between tdi and tdo. these output signals driven from the dfe-q v2.1 will not change while clamp is selected. highz sets all output pins included to the boundary scan path into a high impedance state. in this state, an in-circuit test system may drive signals onto the connections normally driven by the dfe-q v2.1 outputs without incurring the risk of damage to the dfe-q v2.1. bypass , a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacturer code output 0001 0000 0000 0111 0010 0000 1000 001 1 --> tdo pef 24911 monitor commands data sheet 110 2001-07-16 5 monitor commands the registers of the dfe-q v2.1 are accessed via the monitor channel of the iom ? -2 interface. this chapter summarizes the available monitor commands and messages. please refer to chapter 3.2.4 for a detailed description of the monitor handshake procedure. monitor commands supported by the dfe-q v2.1 are divided into three categories. each category derives its name from the first nibble (4 bits) of the two byte long message. these are mon-0, mon-2 and mon-8. all monitor messages representing similar functions are grouped together. a special monitor class are mon-12 commands which exist beside the known classes listed above. by mon-12 commands it is possible to address internal registers directly. mon-12 commands are always prioritized and are acknowledged first. see chapter 3.2.5 for the details on mon-12 commands and messages. 5.1 mon-0 - exchanging eoc information mon-0 messages are used to write and read the registers containing the information of the eoc-channel on the u-interface. it is important to note that mon-0 messages provide only access to the device internal eoc-registers. the insertion and extraction of a message on the u-frame is handled automatically by the eoc-processor of the device. the eoc is controlled and monitored via mon-0 commands and messages in the iom ? - 2 monitor channel. mon-0 commands may be passed at any instant and need to be transferred only once (applicable for auto and transparent mode). code repetition is performed within the chip by the eoc-processor. for more information about the eoc processor and a detailed description of eoc auto/ transparent mode please see chapter 3.9 . the structure of a mon-0 message is shown below. the structure is identical in eoc auto and transparent mode. mon-0 structure addr: address ? 0 = nt ? 1 ? 6 = repeater ? 7 = broadcast d/m: data/message ? 0 = data ? 1 = message e: eoc code ? 00 ? ff h = coded eoc command/indication 1. byte 2. byte 0 0 0 0 a a a | 1 i1 i2 i3 i4 i5 i6 i7 i8 mon-0 addr. | d/m eoc code pef 24911 monitor commands data sheet 111 2001-07-16 nine mon-0 commands are defined and can be interpreted. mon-0 commands are applied at din, mon-0 messages are issued at dout for confirmation. mon-0 messages have the highest priority among mon-0,2,8 and are issued first if i.e. a mon- 2 or a mon-8 message is simultaneously outstanding. table 15 mon-0 functions hex- code lt function i1-i8 d u 00 h h hold provokes no change. it may be used as a preliminary message in configurations where the acknowledgment is delayed. e.g. in a repeater configuration the nt-rp could answer with h while the eoc- acknowledgment is passed upstream. thereby it can be avoided that the lt-control unit misinterprets the delayed ack as a malfunction. the device issues hold if no nt or broadcast address is used or if the d/m indicator is set to (0). 50 lbbd close complete loop-back (b1, b2, d) the nt does not close the complete loop-back immediately after receipt of this code. instead it issues the c/i-command ail (in ? transparent ? state and auto mode) or arl in the states ? error s/t ? and ? synchronized ? . this allows the downstream device to close the loop- back if desired (e.g. s-transceiver). if the downstream device does not close the loop a mon-8 command (lbbd) must be returned and the loop-back is closed within the u-transceiver. 51 lb1 closes b1 loop-back in nt all b1-channel data will be looped back within the nt u-transceiver. 52 lb2 closes b2 loop-back in nt all b2-channel data will be looped back within the nt u-transceiver. 53 rcc request corrupt crc upon receipt the nt transmits corrupted (= inverted) crcs upstream. this allows to test the near end block error counter on the lt-side. the far end block error counter at the nt-side is stopped and nt-error indications (mon-1) are retained. 54 ncc notify of corrupt crc upon receipt of ncc the nt-block error counters (near-end only) are disabled and error indications are retained. this prevents wrong error counts while corrupted crcs are sent (mon-8 ccrc). aa utc unable to comply message sent instead of an acknowledgment if an undefined eoc- command was received by the nt. pef 24911 monitor commands data sheet 112 2001-07-16 5.2 mon-2 - exchanging overhead bits mon-2 indications are used to transfer all overhead bits except those representing eoc- and crc-bits. starting with the act-bit, the order is identical to the position of the bits on the u-interface. the first mon-2 message is issued immediately after reaching the ? line active ? state in lt-mode. thereby the control system is informed about the initial u-interface status after a successful activation. later on mon-2 messages will only be sent if the system status has been changed. no mon-2 messages are issued while crc-violations are detected (default setting). this prevents the system of being overloaded by faulty monitor indications. alternative validation modes besides crc are provided by the mfilt register which can be accessed via the mon-12 protocol (see chapter 3.2.5 for the details). mon-2 monitor messages have the second highest priority after mon-0 commands. via the mon-8 command ? pace ? bit d1, sai/uoa, can be controlled by a mon-2 command. by use of register m4wmask the user can also gain control on all other overhead bits via mon-2 commands (see again chapter 3.8.2 for the details). latching mon-2 data that is received from iom ? is latched and transmitted on u. mon-2 data received from u is just forwarded on iom ? and is not latched. mon-2 structure d0 ? 11: overhead bits ff rtn return to normal with this command all previously sent eoc-commands will be released. the eoc-processor is reset to its initial state (ff h ). xx ack acknowledge if a defined and correctly addressed eoc-command was received by the nt, the nt replies by echoing back the received command. 1. byte 2. byte 0 0 1 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mon-2 overhead bits overhead bits table 15 mon-0 functions (cont ? d) hex- code lt function i1-i8 d u pef 24911 monitor commands data sheet 113 2001-07-16 the bit positions in the mon-2 message correspond to the following overhead bits: table 16 mon-2 and overhead bits control via u-transceiver ? act (activation bit).act = (1) ? > layer 2 ready for communication ? dea (deactivation bit).dea = (0) ? > lt informs nt that it will turn off ? uoa (u-only activation).uoa = (0) ? > u-activation only ? febe (far-end block error).febe = (0) ? > far-end block error occurred control via mon-2 is enabled: ? for sco, aib and the undefined bits marked with binary ? 1 ? : by default ? for all other m4 bits: by programming register m4wmask via mon-12 command especially for uoa (u-only activation): also after mon-8 ? pace ? ? for bit febe: by programming register opmode.febe via mon-12 command control via other mon-commands ? febe (far-end block error) mon-8 message ? sfb ? sets a single febe bit to ? 0 ? for more details about the meaning of the overhead bits please refer to etsi ts 102 080 and ansi t1.601. position lt ? > nt mon-2/ u-frame bit control d11/m41 act u-trans/mon-2 d10/m51 1 mon-2 d9/m61 1 mon-2 d8/m42 dea u-trans/mon-2 d7/m52 1 mon-2 d6/m62 febe u-trans/mon-2 d5/m43 sco mon-2 d4/m44 1 mon-2 d3/m45 1 mon-2 d2/m46 1 mon-2 d1/m47 uoa u-trans/mon-2 d0/m48 aib mon-2 pef 24911 monitor commands data sheet 114 2001-07-16 transmission on u-interface ? in transmit direction register m4wmask decides which m4, m5 and m6 bits are controlled automatically by the internal logic or by a mon-2 message. ? the dfe-q v2.1 transmits a given bit polarity as long as it is not changed by a new mon-2 message. ? the spare bits (m51, m52, m61) are set to binary ? 1 ? when leaving a power-down state. no further processing is performed by the u-transceiver. reception on u-interface ? in the receive direction (on dout), the incoming m4, m5 and m6 bits are checked by the selected validation mode. a mon-2 message defining all 12 bits is issued if a change of at least one single bit other than the febe bit has been approved valid. therefore a mon-2 message is sent not more often than once per superframe (12 ms interval). ? in order to notify the controller of the initial system status, one mon-2 message is issued immediately after reaching the ? line active ? state in lt-mode. ? the dfe-q v2.1 will not issue mon-2 messages while the programmed validation criterion (crc, tll, ... ) is not fulfilled. 5.3 mon-8 - local functions local functions are controlled via mon-8-commands. local functions comprise e.g. reading block error counters, stimulating test functions, etc. mon-8-commands have the lowest priority and may be passed at any time and need to be transferred only once. latching latched commands in the nt must be disabled explicitly with the ? norm ? command. internal transfer commands (rben/f, rid) are not latched. test and activation control commands (pace, paca, ccrc, lb1/2, lbbd) will be latched. the following tables give an overview of structure and features of commands belonging to this category. mon-8 structure the following local commands are defined. if a response is expected, it will comprise 2 bytes. in the two-byte response the first byte will indicate that a mon-8 answer is transmitted, the second byte contains the requested information. 1. byte 2. byte 1 0 0 0 0 0 0 0 / 1 d7 d6 d5 d4 d3 d2 d1 d0 mon-8 local command (message/data) pef 24911 monitor commands data sheet 115 2001-07-16 table 17 mon-8-local function commands mon-8-functions 1.byte 2.byte lt function 2nd nibble code (bin) du 0000 1011 1110 pace partial activation control external the pace-command causes the dfe-q v2.1 to ignore the actual status of the sai-bit and to behave as if sai = (1) is received. the sai-bit is then controlled by mon-2 commands. 0000 1011 1111 paca partial activation control automatic paca enables the device to interpret and control the sai- bit automatically. 0000 1111 0000 ccrc corrupt crc this command causes the device to send inverted (i.e. corrupted) crcs. corrupted crcs are used to test block error counters. 0000 1111 1111 norm return to normal the norm-command requests the device to stop the transmission of corrupted crcs. 0000 1111 1011 rben read near-end block error counter the value of the near-end block error counter is returned and the counter is reset to zero. the maximum value is ff h . 0000 1111 1010 rbef read far-end block error counter the value of the far-end block error counter is returned and the counter is reset to zero. the maximum value is ff h . 0000 r r r r r r r r abec answer block error counter the value of the requested block error counter (febe/ nebe) is returned (8 bit). 0000 0000 0000 rid read identification 0000 0000 0110 aid answer identification . the dfe-q v2.1 will reply with its id upon a rid request 0000 1111 1001 sfb set febe-bit to ? 0 ? febe is set to ? 0 ? for one single u-superframe 0001 0111 dcba setd set status of relay driver pins four driver pins (dxa, dxb, dxc, dxd, x= line port no.) can be set to either low or high. pef 24911 monitor commands data sheet 116 2001-07-16 notes: r ? r result from block error counter x ? x don ? t care 0001 0000 0000 rst read status pin the logic state of the status pins stx0, stx1 is requested. 0001 xxxxxxs 1 s 0 ast answer ? rst ? request also issued without explicit request - issued upon signal change at the pins stx0, stx1 mon-8-functions pef 24911 register description data sheet 117 2001-07-16 6 register description in this section the complete register map is described that is provided with the new mon- 12 protocol. for the protocol details please refer to chapter 6.4 . the register address arrangement is given in figure 42 . the u-interface registers are provided per line port. by register lp_sel it can be determined which u register bank and by that which line port number is addressed. lp_sel adds an offset value to the current address. the offset value is latched as long as register lp_sel is overwritten again. some registers, however, are identical to all line ports, writing into one of these registers affects the settings of all ports independent from the value in lp_sel. figure 42 dfe-q v2.1 register map u registers u registers regmap_cust.emf line port 1 line port 2 line port 3 adr 6..0 offset line port 0 0fh + 1ch 00h opm ode adr 6..0 lp_sel u register banks m4wmask test ... ... pef 24911 register description data sheet 118 2001-07-16 6.1 register summary *) read-back function for test use l adr 76543210wr/rd1/4 ch. lp_sel 1c h 000000ln2ln1 wr /rd* 1 u-interface registers opmode 00 h 0 0 febe 0 0 0 1 0 wr /rd* 1 mfilt 01 h m56 filter m4 filter eoc filter wr /rd* 1 m4rmask 07 h m4 read mask bits wr /rd* 1 m4wmask 08 h m4 write mask bits wr /rd* 1 test 0f h 0 1 ber ccrc +-1 tones 0 40khz wr /rd* 4 loop 10 h 0 dlb trans u/ iom ? 1 lbbd lb2 lb1 wr /rd* 4 febe 11 h febe counter value rd 4 nebe 12 h nebe counter value rd 4 berc 13 h berc counter value (bit 15-8) rd 4 14 h berc counter value (bit 7-0) table 18 register map reference table reg name access address reset value comment page no. lp_sel wr 1c h 00 h line port selection reg. line port 0 is selected by default 121 u-interface registers opmode wr 00 h 02 h opmode register 121 mfilt wr 01 h 14 h m-bit filter register ? eoc in automode ? m4 crc checked vs. iom ? ? m4 tll checked vs. sm ? m56 crc checked 122 m4rmask wr 07 h 00 h m4 read mask register any m4-bit change causes a mon-2 message 125 pef 24911 register description data sheet 119 2001-07-16 m4wmask wr 08 h bc h m4 write mask register automatic control of act, dea, uoa bit 127 test wr 0f h 40 h test register 129 loop wr 10 h 08 h loop register all local loops deactivated 130 febe rd 11 h 00 h febe counter register 132 nebe rd 12 h 00 h nebe counter register 132 berc rd 13 h = ? = 14 h 0000 h bit error rate counter reg. 132 table 18 register map reference table reg name access address reset value comment page no. pef 24911 register description data sheet 120 2001-07-16 6.2 reset of u-transceiver functions in state ? deactivated ? the following u-transceiver registers are reset upon the transition to state ? deactivated ? : 6.3 mode register evaluation timing the point of time when mode settings are detected and executed differs with the mode register type. two different behaviors can be classified evaluation and execution after sw-reset (c/i= res, res1) or upon transition out of state ? deactivated ? note: write access to these registers/bits is allowed only, while the state machine is in state reset or deactivated. immediate evaluation and execution below the mode registers are listed and grouped according to the different evaluation times as stated above. register reset to affected bits/ comment u-interface registers test only the bits ber and ccrc are reset loop only the bits lbbd, lb2 and lb1 are reset febe 00 h reset upon deactivation nebe 00 h reset upon deactivation berc 0000 h reset upon deactivation register affected bits comment registers evaluated after sw-reset or upon transition out of state deactivated mfilt complete register immediate evaluation and execution opmode bit febe m4rmask complete register m4wmask complete register test complete register loop complete register pef 24911 register description data sheet 121 2001-07-16 6.4 detailed register description 6.4.1 lp_sel - line port selection register the line port selection register selects the register bank that is associated with the addressed line port. all line port specific register operations - line port specific registers are indicated by a ? 4 ? in the last column of the register summary - are performed on the line port that is addressed by the value of lp_sel. lp_sel read/ write address: 1c h reset value: 00 h u-interface registers 6.4.2 opmode - operation mode register the op eration mode register determines the operating mode of the dfe-q v2.1 in all ports. opmode read* ) / write address: 00 h reset value: 02 h 76543210 000000ln2ln1 ln2,1 line port number 00 = line port no. 0 is addressed by the following command 01 = line port no. 1 is addressed by the following command 10 = line port no. 2 is addressed by the following command 11 = line port no. 3 is addressed by the following command 76543210 00febe00010 pef 24911 register description data sheet 122 2001-07-16 6.4.3 mfilt - m-bit filter options the m-bit filter register defines the validation algorithm received maintenance channel bits (m1-m6) of the u-interface have to undergo before they are approved and passed on to the system interface. the mfilt register is unique for all ports. writing into mfilt from one channel affects the setting of all channels. m-bit changes are reported to the system environment by mon-0 (eoc) or mon-2 (m4- m6) messages via iom ? -2. to lower processor load due to faulty monitor messages three different filter functions are supported, triple-last-look (tll), crc check and on change. triple-last-look (tll) a change of m-bit data has to be received in three consecutive u-frames until it is approved valid and reported to the system interface. crc a change of m-bit data is only reported to the system interface if no crc violation has been detected. the forwarding of m-bit changes is delayed by 12 ms (= 1x u-superframe) if received m-bits are crc covered. this way the m-bit data is checked with the actual crc sum which is received one u-superframe later. on change every time the m-bit status has changed a mon-0 or mon-2 message is issued. some m4 bits, act, dea and uoa, have two destinations, the state machine and the system interface. regarding these bits triple-last-look (tll) is applied by default before the changed status is input to the state machine. via bit no. 5 of the mfilt register the user can decide whether the m4 bits which are input to the state machine shall be approved by tll (bellcore requirement) or by the same verification mode as selected for the issue of a mon-2 message. the mfilt register setting is evaluated each time the dfe-q v2.1 leaves the ? deactivated ? state. for further information on the handling regarding the maintenance channel please refer to chapter 3.8 . febe enable/disable external write access to febe bit in register m56w 0 = external access to febe bit disabled - febe bit is set by internal febe counter logic 1 = external access to febe bit enabled - febe bit is controlled by mon-2 pef 24911 register description data sheet 123 2001-07-16 mfilt read* ) / write address: 01 h reset value: 14 h 76543210 m56 filter m4 filter eoc filter m56 filter controls the validation mode of the spare bits (m51, m52, m61) on a per bit base. approved m5, m6 bit changes are reported to the system interface by a mon-2 message x0 = apply same filter to m5 and m6 bit data as programmed for m4 bit data x1 = on change if a change of the m5, m6 bit status has occurred a mon-2 message will be issued m4 filter 3-bit field which controls the validation mode of the m4 bits on a per bit base. approved m4 bit changes are reported to the system interface by a mon-2 message. ? bit 3 and 4 determine the filter algorithm that is applied for the triggering of a mon-2 message ? bit 5 controls whether the forwarding of m4 bits to the internal state machine shall be approved by default by tll or by the same filtering mode as selected for the forwarding to the system environment note: bellcore tr-nwt-397 (1993) requires to apply tll to the m4 bits before m4 bit changes are processed by the state machine x00 = on change if a change of the m4 bit status has occurred it will be indicated to the system by a mon-2 message x01 = tll coverage of m4 bit data a change of m4 bit data is only passed on if it has been received in three consecutive frames x10 = crc coverage of m4 bit data a change of m4 bit data is passed on if no crc violation has been detected pef 24911 register description data sheet 124 2001-07-16 x11 = crc and tll coverage of m4 bit data a change in m4 bit data is reported to the system interface if no crc violation has been detected and if it has been received in three consecutive frames, the change is reported as soon as 3 complete u-superframes were successfully analysed 0xx = m4 bits towards state machine are covered by tll 1xx = m4 bits towards state machine are checked by the same validation algorithm as programmed for the reporting to the system interface eoc filter 3-bit field which controls the processing of eoc messages and its verification algorithm 100= eoc automatic mode - ? return message reception function ? is enabled as soon as the lt has transmitted an eoc command. it causes the dfe-q v2.1 in lt mode to compare the received and verified (by tll) eoc messages with the last downstream transmitted eoc command. a mon-0 message is issued if they prove to be equal. for this particular received eoc message the ? different from previous ? rule is not applied. this means that a mon-0 message is even issued if the received eoc message is not different to the one previously accepted. all other incoming eoc messages besides the echo of the one transmitted downstream will be evaluated by tll and the ? different from previous ? verification. - if no eoc command has been transmitted downstream a mon-0 message is issued only after the tll criterion has been met and the message is different from the one previously accepted pef 24911 register description data sheet 125 2001-07-16 6.4.4 m4rmask - m4 read mask register via the m4 read mask register the user can selectively control which m4 bit changes are to be reported via mon-2 messages. the m4rmask register is unique for all ports. m4rmask read* ) / write address: 07 h reset value: 00 h below the cross reference of the mask bits to the m4 bits as they are sent from the nt to the lt is given: 001= eoc transparent mode without any filtering - every 6 ms an eoc message is passed on by a mon-0 message - suitable mode for digital loop carrier applications - no eoc filtering: every 6ms an eoc messages is forwarded to the system interface via a mon-0 message - no acknowledgment - no execution - no latching is performed 010= eoc transparent mode with ? on change ? filtering only if a change of the received eoc message has been detected it is passed on 011 = eoc transparent mode with triple-last-look (tll) filtering tll coverage of eoc messages is enabled 76543210 m4 read mask bits bit 7..0 0 = m4 bit change indication by mon-2 message active 1 = m4 bit change indication by mon-2 message masked 76543210 nib sai m46 cso ntm ps2 ps1 act nib network indication bit pef 24911 register description data sheet 126 2001-07-16 0 = no function (reserved for network use) 1 = no function (reserved for network use) sai s-activity indicator 0 = s-interface is deactivated 1 = s-interface is activated cso cold start only 0 = nt is capable to perform warm starts 1 = nt activation with cold start only ntm nt test mode 0 = nt busy in test mode 1 = inactive ps2 power status secondary source 0 = secondary power supply failed 1 = secondary power supply ok ps1 power status primary source 0 = primary power supply failed 1 = primary power supply ok act activation bit 0 = layer-2 not established 1 = signals layer-2 ready for communication pef 24911 register description data sheet 127 2001-07-16 6.4.5 m4wmask - m4 write mask register by means of the m4wmask register the user can direct on a per bit base which m4 bits are controlled by mon-2 and which are controlled by the state machine. the m4wmask register is unique for all ports. m4wmask read* ) / write address: 08 h reset value: bc h below the cross reference of the mask bits to the m4 bits as transmitted from the lt to the nt is given: 76543210 m4 write mask bits bit 7..0 0 = m4 bit is controlled by state machine 1 = m4 bit is controlled by mon-2 command bit 6 partial activation control external/automatic , function corresponds to the mon-8 commands pace and paca 0 = uoa bit is controlled and sai bit is evaluated by state machine 1 = uoa bit is controlled by mon-2 command, sai= ? 1 ? is reported to statemachine 76543210 aib uoa m46 m45 m44 sco dea act aib interruption (according to ansi) 0 = indicates interruption 1 = inactive uoa u activation only 0 = indicates that only u is activated 1 = inactive pef 24911 register description data sheet 128 2001-07-16 sco start-on-command only bit indicates whether the dlc network will deactivate the loop between calls (defined in bellcore tr-nwt000397) 0 = ? start-on-command-only ? mode active, in lult mode the u-transceiver shall initiate the start-up procedure only upon command from the network ( ? ar ? primitive) 1 = normal mode, if the u-transceiver is operated within a dcl configuration as lult it shall start operation as soon as power is applied dea deactivation bit 0 = lt informs nt that it will turn off 1 = inactive act activation bit 0 = layer 2 not established 1 = signals layer-2 ready for communication pef 24911 register description data sheet 129 2001-07-16 6.4.6 test - test register the test register sets the dfe-q v2.1 in the desired test mode. test read* ) / write address: 0f h reset value: 40 h 76543210 01 ber ccrc+-1 tones 040khz ber bit error rate measurement function ? prerequisite : closed loopback #2 on the nt-side ? allows to measure the ber of either the b1-, the b2-, or the b1- and b2- and d-channel in transparent state ? the user data stream is overwritten by a continuous series of zeros 00 = bit error rate (berc) counter disabled 01 = starts b1-channel ber measurement bit error rate counter (berc) is enabled and a continuous series of zeros is sent in channel b1 10 = starts b2-channel ber measurement bit error rate counter (berc) is enabled and a continuous series of zeros is sent in channel b2 11 = starts b1-, b2- and d-channel ber measurement bit error rate counter (berc) is enabled and a continuous series of zeros is sent in channel b1, b2 and d ccrc send corrupt crc 0 = inactive 1 = send corrupt (inverted) crcs +-1 tones send +/-1 pulses instead of +/-3 pulses 0 = no action 1 = issues +/-1 pulses instead of +/-3 during 40 khz tone generation or in ssp test mode 40khz 40 khz test signal pef 24911 register description data sheet 130 2001-07-16 6.4.7 loop - loop back register the loop register controls local loopbacks within the dfe-q v2.1. for the loopback configurations that are available by the loop register see chapter 4.4.1.5 . loop read* ) / write address: 10 h reset value: 08 h 0 = no action 1 = issues a 40 khz test signal - suitable for testing of test equipment 76543210 0 dlb trans u/iom ? 1 lbbd lb2 lb1 dlb close framer/deframer loopback ? the loopback is closed at the analog/digital interface ? prerequisite is that lb1, lb2, lbbd and u/iom ? are set to ? 0 ? ? prerequisite is that the dfe-q v2.1 is in a transparent state, e.g. by applying c/i-command ? data through dt ? . ? only user data is looped and no maintenance data is not looped back ? the dlb loop operates always in transparent mode 0 = framer/deframer loopback open 1 = framer/deframer loopback closed trans transparent/ non-transparent loopback ? in transparent mode user data is both passed on and looped back, whereas in non-transparent mode data is not forwarded but substituted by ? 1 ? s (idle code) and just looped back ? if lbbd, lb2, lb1 is closed towards the iom ? interface and bit trans is set to ? 0 ? then the state machine has to be put into state ? transparent ? first (e.g. by c/i = dt) before data is output on the u-interface ? bit trans has no effect on dlb (always transparent) and the analog loopback (arl operates always in transparent mode) 0 = sets transparent loop mode for lbbd, lb2, lb1 1 = sets non-transparent mode for lbbd, lb2, lb1 ? 1 ? s are sent on the iom ? -2 interface in the corresponding time-slot pef 24911 register description data sheet 131 2001-07-16 u/iom ? switch that selects whether looback lb1, lb2 or lbbd is closed towards u or iom ? -2 0 = lb1, lb2, lbbd loops are closed towards iom ? -2 1 = lb1, lb2, lbbd loops are closed towards u lbbd close complete loop (b1, b2, d) near the system interface the direction towards the loop is closed is determined by bit u/iom ? 0 = complete loopback open 1 = complete loopback closed lb2 close loop b2 near the system interface the direction towards the loop is closed is determined by bit u/iom ? 0 = loopback b2 open 1 = loopback b2 closed lb1 close loop b1 near the system interface the direction towards the loop is closed is determined by bit u/iom ? 0 = loopback b1 open 1 = loopback b1 closed pef 24911 register description data sheet 132 2001-07-16 6.4.8 febe - far end block error counter register the f ar e nd b lock e rror counter register contains the febe value. if the register is read out it is automatically reset to ? 0 ? . febe read address: 11 h reset value: 00 h 6.4.9 nebe - near end block error counter register the n ear e nd b lock e rror counter register contains the nebe value. if the register is read out it is automatically reset to ? 0 ? . nebe read address: 12 h reset value: 00 h 6.4.10 berc - bit error rate counter register the b it e rror r ate c ounter register contains the number of bit errors that occurred during the period the bit test.ber was set active. if the 2nd byte (addr. 14h) of the 16-bit berc counter is read out the 16-bit value is automatically reset to ? 0 ? . berc read address: 13/14 h reset value: 0000 h 76543210 febe counter value 76543210 nebe counter value 15 14 13 12 11 10 9 8 bit error rate counter value 76543210 bit error rate counter value pef 24911 electrical characteristics data sheet 133 2001-07-16 7 electrical characteristics 7.1 absolute maximum ratings note: absolute maximum ratings are stress ratings only, and functional operation and reliability under conditions beyond those defined in the operating range is not guaranteed. stresses above those absolute maximum ratings are likely to cause permanent damage to the device. 7.2 operating range note: in the operating range, the functions given in the circuit description are fulfilled. parameter symbol limit values unit ambient temperature under bias t a ? 40 to 85 c storage temperature t stg ? 65 to 125 c ic supply voltage v dd ? 0.3 to 4.6 v input voltage on input pins and on high ohmic output pin with respect to ground v s ? 0.3 to 5.5 v maximum current supplied to any pin for more than 5 msec i s 10 ma esd robustness 1) hbm: 1.5 k ? , 100 pf 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. v esd,hbm 2000 v parameter symbol limit values unit test condition min. max. ambient temperature t a ? 40 85 c supply voltage v dd 3.0 3.6 v ground v ss 00 v voltage applied to input pin v s - 0.3 v dd +3.3 (max 5.25) v voltage applied to output pin in high ohmic state (open drain) v s - 0.3 v dd +3.3 (max 5.25) v pef 24911 electrical characteristics data sheet 134 2001-07-16 7.3 dc characteristics 7.4 ac characteristics inputs are driven to 2.4 v for a logical ? 1 ? and to 0.45 v for a logical ? 0 ? . timing measurements are made at 2.0 v for a logical ? 1 ? and 0.8 v for a logical ? 0 ? . the ac testing input/output waveforms are shown in figure 43 . parameter symbol limit values unit notes min. max. input low voltage v il ? 0.3 0.8 v input high voltage 1) 1) apply to all inputs and to dout in high ohmic state v ih 2.0 5,25 v 3.0v < v dd <3.3 v output low voltage v ol 0.45 v i ol =7ma 2) i ol =2ma 3) 2) apply to: dout 3) apply to all other output pins except dout output high voltage v oh 2.4 v i oh = ? 7ma 2) i oh = ? 2ma 3) input leakage current i il -1 1 a v dd =3.3v, v ss = 0 v; all other pins are floating; 0v< v in < v dd 4) 4) apply to inputs having no pull up or pull down resistors note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. output leakage current i oz -1 1 a v dd =3.3v, v ss =0v; 0v< v out < v dd input pull down current i pd 50 200 a v in = v dd input pull up current i pu -170 -50 a v in = v ss pef 24911 electrical characteristics data sheet 135 2001-07-16 figure 43 input/output waveform for ac tests 7.4.1 reset timing figure 44 reset timing parameter symbol limit values unit remark min. max. active low period t res 200 ns the end of reset execution is delayed internally for 900s with respect to the low active phase 15.36 mhz master clock has to be applied 0.4 v 2.4 v test points 2.0 v 0.8 v 2.0 v 0.8 v ac_char .vsd t res res 900s reset intern pef 24911 electrical characteristics data sheet 136 2001-07-16 7.4.2 iom ? -2 interface timing the dynamic characteristics of the iom ? -2-interface are given in figure 45 . in case the period of signals is stated the time reference will be at 1.4 v. in all other cases 0.8 v (low) and 2.0 v (high) thresholds are used as reference. figure 45 iom ? -2 interface timing table 19 iom ? -2 dynamic input characteristics parameter symbol limit values unit min. typ. max. dcl rise/fall time t r , t f 60 ns dcl period t dcl 122 ns dcl pulse width, high low t wh t wl 53 53 (t dcl )/2 (t dcl )/2 ns ns fsc rise/fall t r , t f 60 ns fsc setup time t sf 10 ns fsc hold time t hf 10 ns fsc pulse width, high low t wfh t wfl 2 t dcl 2 t dcl ns data valid data valid din dout fsc dcl t dcl t wl t f t r t wh t sf t wfh t hd t sd t ddc itd05637.vsd t hf t hf t ddf pef 24911 electrical characteristics data sheet 137 2001-07-16 table 20 iom ? -2 dynamic output characteristics notes: 1) the point of time at which the output data will be valid is referred to the rising edges of either fsc ( t ddf ) or dcl ( t ddc ). the rising edge of the signal appearing last (normally dcl) shall be the reference. 7.4.3 interface to the analog front end the ac characteristics of the afe-interface pins are optimized to fit to afe version 2.1 if the following loads are not exceeded. superframe fsc pulse width, high t wfh 100 1 t dcl ns din setup time t sd 10 ns din hold time t hd 10 ns parameter symbol limit values unit test condition min. typ. max. dcl data delay clock 1) pin pup = ? 0 ? pin pup = ? 1 ? t ddc t ddc 100 40 ns ns c l = 150 pf, charged with 5v c l = 100 pf, charged with 3.3v fsc data delay frame 1) t ddf 20 ns c l = 150 pf table 21 interface signals of afe and dfe-q pin signal driving device max. capacitive load max. connection resistance cl15 afe 50pf; 2 ohms sdr afe 20pf; 2 ohms pdm0 3 afe 20pf; 2 ohms sdx dfe-q 20pf; 2 ohms parameter symbol limit values unit min. typ. max. pef 24911 electrical characteristics data sheet 138 2001-07-16 7.4.4 boundary scan timing figure 46 boundary scan timing table 22 boundary scan dynamic timing requirements parameter symbol limit values unit min. max. test clock period ttcp 160 - ns test clock period low t tcpl 70 - ns test clock period high t tcph 70 - ns tms set-up time to tck t mss 30 - ns tms hold time from tck t msh 30 - ns tdi set-up time to tck t dis 30 - ns tdi hold time from tck t dih 30 - ns tdo valid delay from tck t dod -60ns pef 24911 electrical characteristics data sheet 139 2001-07-16 7.5 capacitances 7.6 power supply 7.6.1 supply voltage v dd to gnd = +3.3 v 0.3 v 7.6.2 power consumption all measurements with random 2b+d data in active states, 3.3 v (0 c - 70 c) parameter symbol limit values unit notes min. max. input capacitance c in 7pf output capacitance c out 10 pf table 23 power consumption mode typ. values max. values unit test conditions power-up all channels 85 100 ma 3.3 v, open outputs, inputs at v dd / v ss power-down 35 t.b.d. ma 3.3 v, open outputs, inputs at v dd / v ss pef 24911 package outlines data sheet 140 2001-07-16 8 package outlines p-mqfp-64 (plastic metric quad flat package) gpm05247 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm pef 24911 appendix a: standards and specifications data sheet 141 2001-07-16 9 appendix a: standards and specifications the table below lists the relevant standards concerning transmission performance the dfe-q v2.1 claims to comply with. organization valid for document itu international telecommunication union world- wide itu-t g.961 digital transmission system on metallic line for isdn basic rate access etsi european telecommunications standards institute eu technical specification 102 080 v1.3.1 (1988-11), abbrev. ts 102 080 (formerly known as etr 080) transmission and multiplexing (tm); isdn basic rate access; digital transmission systems on metallic local lines ansi american national standards institute, inc. usa t1e1 4/92-004 - t1.601-1998 basic access interface for use on metallic loops for application on the network side of the nt (layer 1 specification) telcordia technologies inc. (formerly known as bellcore) usa tr-nwt-000393, issue 2, december 1992 generic requirements for isdn basic access digital subscriber lines tr-nwt-000397, issue 3, december 1993 isdn basic access transport system requirements tr-nwt-000829, issue 1, november 1989 otgr: generic operations interface, embedded operations channel sr-nwt-002397, issue 1, june 1993 layer 1 test plan for isdn basic access digital subscriber line transceivers bt british telecommunications plc. gb specification rc7355e, issue e, 03/97 2b1q generic physical layer specification pef 24911 glossary data sheet 142 2001-07-16 10 glossary a/d analog to digital adc analog to digital converter agc automatic gain control ain differential u-interface input ansi american national standardization institute aout differential u-interface output b1, b2 64-kbit/s voice and data transmission channel bin differential u-interface input bout differential u-interface output ccrc corrupted crc c/i command/indicate (channel) crc cyclic redundancy check d 16-kbit/s data and control transmission channel d/a digital-to-analog dac digital-to-analog converter dcl data clock dd data downstream dt data through test mode du data upstream ec echo canceller eoc embedded operations channel eom end of message etsi european telephone standards institute febe far-end block error fifo first-in first-out (memory) fsc frame synchronizing clock gnd ground hdlc high-level data link control iec-q isdn-echo cancellation circuit conforming to 2b1q-transmission code iom ? -2 isdn-oriented modular 2nd generation pef 24911 glossary data sheet 143 2001-07-16 info u- and s-interface signal elements as specified by ansi/ etsi isdn integrated services digital network lbbd loop-back of b- and d-channels lt line termination mon monitor channel command mr monitor read bit mx monitor transmit bit nebe near-end block error nt network termination pll phase locked loop ps power supply status bit psd power spectral density ptt post, telephone, and telegraph administration pu power-up rms root mean square s/t two-wire pair interface ssp send single pulses (test mode) te terminal equipment tl wake-up tone sent from the lt side tn wake-up tone sent from the nt side u single wire pair interface 2b1q transmission code requiring 80-khz bandwidth pef 24911 data sheet 144 2001-07-16 a absolute maximum ratings 133 ac characteristics 134 activation 71 ansi 141 b bellcore 141 boundary scan 105 timing 138 bt 141 c capacitances 139 command/ indicate channel 24 controller 3 d dc characteristics 134 deactivation 71 e electrical characteristics 133 etsi 141 f functional description 20 g general purpose i/os 33 i idcode 109 interface to the analog front end sdx/sdr frame structure 31 timing 137 iom ? -2 interface 21 c/i channel 24 channel assignment 9 data rates 9 frame structure 22 monitor channel 24 timing 136 itu 141 l logic symbol 4 m monitor channel 24 monitor commands 110 o operating range 133 p package outlines 140 pin descriptions 11 pin diagram 11 pinning changes 19 power consumption 139 power down 69 power supply 139 protocol 3 r register summary 118 registers u-interface 121 relay driver pins 33 pin description 16 reset 69 timing 135 s status pins 33 pin description 16 supply voltage 139 system integration 5 t tap controller 108 u u-transceiver 34 http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ? business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction. ? dr. ulrich schumacher |
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