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pd-60325 i p2005apbf high frequency synchronous buck optimized lga power stage integrated power semiconduct ors, driver ic, & passives features ? 40a multiphase buil di ng block ? n o de-rati n g up to t pcb = 95oc ? o ptimized for low power loss ? o ptimized for low emi ? b ias supply range of 4.5v to 7.0v ? o peration up to 1.5mhz ? b i-directi o nal current flow ? u nder voltage lockout ? l ga interfa c e ? 7 .65 mm x 7.65 mm o u t line descr i p t i o n t he ip2005a is a fu lly op timiz e d so lu tion for h i gh cu rr ent s y n c h r ono us buck mu ltipha se applica t ions . boa r d spa c e and des ign time a r e g r eatly r e duced because mos t o f the co mpone n t s required fo r each pha se of a typ i ca l d i sc re te -base d mu ltiphase c i r c u i t a r e in tegra t ed into a sin g l e 7. 6 5 m m x 7. 6 5 mm x 1. 6 6 mm p o wer bl ock. t h e add itional co mponents r equ ired fo r a co mp lete mu ltiphase con v e r te r a r e a pw m con t ro lle r , the output induc to rs , an d the input an d output capa c i to r s . ipo w ir techno logy o f fe r s des igner s an inno vative board space sa ving so lu tion fo r applica t ions requir i ng h i gh powe r dens itie s. ipow ir techno lo g y eases desig n fo r applica t ions whe r e co mponent integra t ion offe rs benefits in pe rfo r mance and functiona lity. ipow ir technolog y so lu tions a r e a l so optimiz ed in te rnally fo r la you t , heat trans fer , and co mponent se lec t ion . applications ? high frequency, lo w profile dc-dc ? multi-phase architectures ? low d u ty cycle, hi gh current solutions ? microprocessor pow e r suppl ies ? general d c / dc converters packa ge d esc r i p t i o n i n te r f ace conn e c tion sta n dard qu a n tit y t & r or i e nt atio n ip 2005 apb f l ga 10 n / a ip 2005 at r p b f lga 2000 f i g u r e 15 2/8/2008 www.irf.com ty pical application 1 ip2005a pr od u c t ef f i c i e n c y v in = 12v , f sw = 1mhz, & t blk = 125 oc 70 72 74 76 78 80 82 84 86 88 90 92 94 4 6 8 1 0 1 21 41 6 1 82 02 2 2 42 62 8 3 03 23 4 3 63 84 0 e f f i ci ency ( % ) ou tp u t c u r r e n t (a) vo ? = ? 3.3v vo ? = ? 2.5v vo ? = ? 1.8v vo ? = ? 1.3v
pd-60325 i p2005apbf v in to p gnd ??????????..?..-0.5v to 16.5v v dd to p gn d ???????.??.??.-0.5v to 7.5v cv cc to p gnd ??..?.??..????...-0.5v to 7.5v pwm to p gnd ????????.???-0.5 v to vdd + 0.5v (note 1) enable to p gnd ?????..????-0.5 v to vdd + 0.5v (note 1) storag e tempe r ature ???????..-60oc to 15 0oc block temperatu r e ????.????. -40o c to 15 0oc (note 2) esd ratin g ???? ???????....jedec, jesd22-a1 14 (h bm[4kv], class 3a) ????????????..jedec, jesd22-a11 5 (mm[400v], cla ss c) msl rati n g ?????????..??..3 reflo w tempe r atur e ?..??????..26 0 oc peak absolute maxi mum ratings (volta ges r e fer enc e d to p gnd ) caution: s tresses above th o se listed i n ?absol u t e m a ximum ratings ? m ay cause permanent damage to t h e device. this is a stre s s only rating and o peration of t h e device at these or any other con d iti o ns ab ove those listed in the ?recommended operating conditi ons? s e c tion of th is specific a tion i s not impli e d. recommended operating conditions paramet e r min t yp max units condit i o n s supp ly vo ltag e (v dd ) 4 .5 - 7 .0 v input vo ltage ( v in ) 6 .5 - 13.2 v ou tput vo ltag e (v out )- - 5 . 5 v ou tput cur r en t ( i out )- - 4 0 a sw itch ing f r equency 250 - 1500 k h z on time dut y cyc l e - - 8 5 % minimum v sw on t i me 60 - - ns v dd = 5.0v, v in = 1 2 v block te mper a t u r e ( t blk ) - 40 - 125 o c ( n o t e 2 ) www.irf.com 2/8/2008 2
pd-60325 i p2005apbf electrical specifications t hese spec ifica t ions apply fo r t blk = 0o c to 125oc and v dd = 5.0v un les s o t her w i se spec ified . paramet e r min t yp max units condit i o n s p loss po we r blo c k losses - 9 . 3 11.1 w v in = 12v, v dd = 5 . 0v , v out = 1.3v, i out = 40a, f sw = 1mh z , l out = 0. 3 u h, t bl k = 2 5 oc (not e 3) v dd supp ly cu r r en t ( s tand by) (i q-vdd ) -2 . 2 3 m a v dd = 5.0 , enable = 0v supp ly cu r r en t ( o pera t ing ) - 5 0 6 5 m a v in = 12v, en able = v dd = 5v , f sw = 1mhz , 1 0 % dc cv cc (ld o output) ou tput vo l t age 5 .5 6 . 0 6 .75 v ou tput cur r en t 8 0 - - m a ou tput capacito r 1 . 0 - - f c e r a m ic , x5r , 16v po w e r-o n reset ( p o r ) v dd risi n g 3. 7 4 . 1 4. 5 v h y s t e r es is 140 185 230 mv v dd risi ng & falling cvcc ri sin g 4. 2 4 . 6 5. 0 v h y s t e r es is 165 220 275 mv c v cc ri sing & f a lling enabl e in p u t log ic leve l lo w th resho l d ( v il )- - 0 . 8 v log ic leve l high th resho l d (v ih ) 2. 0 - - v t h resho l d h y s t e r es is - 100 - m v w eak pu ll- dow n impedance - 100 - k ? r i s i ng propa gation de la y (t pd h ) -4 0 - n s f a lling propa gation de la y (t pd l ) -7 5 - n s sch m itt t r igg e r input v dd = po r to 7.0v www.irf.com 2/8/2008 3
pd-60325 i p2005apbf 2/8/2008 www.irf.com 4 paramet e r min t yp max units condit i o n s pwm input log ic leve l lo w th resho l d ( v il )- - 0 . 8 v log ic leve l high th resho l d (v ih ) 2. 0 - - v t h resho l d h y s t e r es is - 100 - m v w eak pu ll- dow n impedance - 100 - k ? r i s i ng propa gation de la y (t pd h ) -6 0 - n s f a lling propa gation de la y (t pd l ) -3 0 - n s schmitt trigg e r i nput v dd = po r to 7.0v (not e 4) electrical specifi cat i ons (cont i n ued) t hese spec ifica t ions apply fo r t blk = 0o c to 125oc and v dd = 5.0v un les s o t her w i se spec ified . notes: 1. m u st not ex ceed 7.5 v 2. b l o ck te m p e r atur e ( t bl k ) is def ined a s any d i e te m p e r a t u r e w i th in the pa ckage 3. m e a s u r e m ent made w i th six 10 f ( t d k c3225 x5 r1 c106 kt o r equ iva l ent ) ce ra m i c capa cit o r s p l a c ed a c r o ss vi n to p g nd pins (s e e figur e 8) 4. n o t a sso ciated w i t h r i se and fa ll t i m e s. d o e s no t af fe ct pow e r lo ss
pd-60325 i p2005apbf power loss curve figur e 1 po w e r lo s s curv e power loss (w ) soa cur v e figur e 2 s a fe op e r ating ar e a curv e o u tput cur r ent (a ) www.irf.com 2/8/2008 5
pd-60325 i p2005apbf t y pical performance curves 2/8/2008 www.irf.com 6 fig u re 3 norma lize d po w e r los s v s . input volta g e p o we r l o s s (n or m a liz ed ) f igure 4 norma lize d po w e r los s v s . output volta g e 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 0. 8 1.3 1 .8 2.3 2 .8 3.3 ou tp ut v o l t ag e (v ) -0 .9 -0 .5 0.0 0.5 0.9 1.4 1.9 2.3 2.8 3.3 3.7 4.2 v in = 12.0 v v dd = 5.0v i out = 4 0 a f sw = 1 m h z l out = 300 nh t bl k = 125 oc 0. 90 0. 92 0. 94 0. 96 0. 98 1. 00 1. 02 1. 04 1. 06 1. 08 1. 10 6 7 8 9 10 1 1 12 13 1 4 in pu t v o lta g e (v ) -2 . 4 -1 . 9 -1 . 4 -1 . 0 -0 . 5 0. 0 0. 5 1. 0 1. 4 1. 9 2. 4 s o a te mp a d jus t men t (oc) v dd = 5. 0 v v out = 1. 3v i ou t = 4 0 a f sw = 1m hz l out = 30 0n h t bl k = 12 5o c f i g u r e 5 no rmalized po w e r l o ss v s . in d u ctan ce figure 6 norma lize d po w e r los s v s . s w it c h ing fre que nc y 0. 6 0. 7 0. 8 0. 9 1. 0 1. 1 1. 2 1. 3 25 0 5 00 75 0 1 00 0 1 25 0 1 50 0 swi t chi n g f r e que ncy ( k h z ) -10 . 0 -7 . 5 -5 . 0 -2 . 5 0. 0 2. 5 5. 0 7. 5 v in = 1 2 . 0 v v dd = 5. 0v v ou t = 1 . 3v i ou t = 40 a l ou t = 30 0n h t bl k = 12 5o c 0. 96 0. 97 0. 98 0. 99 1. 00 1. 01 1. 02 1. 03 1. 04 1. 05 1. 06 1. 07 0. 1 0. 2 0 . 3 0. 4 0 . 5 0. 6 0 . 7 0. 8 out put ind u ct ance (h ) -1. 0 -0. 7 -0. 5 -0. 2 0. 0 0. 2 0. 5 0. 7 1. 0 1. 2 1. 4 1. 7 v in = 12. 0v v dd = 5. 0v v out = 1. 3 v i ou t = 40a f sw = 1mhz t blk = 125o c figure 7 v dd supply curre nt v s . s w itc h i n g fre que nc y a v er a g e i dd (m a )
pd-60325 i p2005apbf figur e 8 p o w e r lo s s t e st cir c uit figur e 9 t i ming di agr a m www.irf.com 2/8/2008 7
pd-60325 i p2005apbf appl y i ng the safe operating area (soa) curve the soa graph i n corporates po w e r loss and thermal resistance information i n a way that all o ws one to solve for maximum current cap abi lity in a simpl i fie d g r ap hic a l m a n n e r . it incorporates the ability to so lve thermal probl e ms where heat is drawn out through the pri n ted circuit board a nd the top of the case. please re fer to international rectifier application note an1047 for further details on using thi s soa cu rv e in your thermal envi r onment. p r ocedur e 1.calculate (based on estimate d power loss) or measure t he c a se temperature on the device and the board temp erature near the device (1mm from the edge). 2.draw a li ne from case temperature axis to the pcb temperature axis. 3.draw a vertical li ne from the t x ax is interce p t to the soa curve. 4.draw a hori zontal li ne from th e intersecti on of the vertical li ne with the soa curve to the y- axis (output current). the poi nt at which th e horizontal l i ne meets the y-axis i s the soa conti n uous current. v in = 12 .0v v dd = 5.0v v ou t = 1.3v f sw = 1mhz l ou t = 300nh figur e 1 0 s o a e x a m pl e, continuous cu rr ent 31a f o r t pcb = 100oc & t ca se = 110oc www.irf.com 2/8/2008 8
pd-60325 i p2005apbf calculating power loss and soa fo r differen t o p eratin g co ndition s to calcul ate power loss for a given set of operat i on conditi ons, the foll owi ng procedure shoul d be foll owed: powe r loss p r oce dure 1.determi ne the maximum curre nt for each ip 2005a and obt ain the maximum pow er l o ss from figure 1 2.use the normal i zed curv es to obtain power l o ss val ues th at match t he operati ng conditions in the appli c ation 3.the maximum pow e r l o ss under the applicati on c ondit ion s is t h en t he pr oduc t of t he po wer loss from f i gure 1 and the normal ized val ues. to calcul ate the safe operating area (soa) for a given set of op erati n g conditions, the foll owi ng procedure should be foll ow ed: so a p r oc edure 1.determi ne the maximum pcb and case temper ature at the maximu m operating current for each ip 2005a 2.use the normal i zed curves to o b tain soa tempe r atur e adjustments that match the operating conditi ons i n the appl ication 3.then, add the sum of the soa te mperature adjustments to the t x axis intercept in figure 2 design e x a m ple operating conditi ons: output c u rrent = 30a input volt age = 10v output voltage = 1.3v switching freq = 750khz inducto r = 0.2h d rive voltage (v dd ) = 5v calc ulati n g max i mum power los s: (figure 1) maximum pow er l o ss = 9.0w (figure 3) normal ized pow er l o ss for input voltage 0.95 (figure 4) normal ized pow er l o ss for output voltage 1. 0 (figure 5) normal ized pow er l o ss for output i n ductor 1.026 (figure 6) normal ized pow er l o ss for switch freq u ency 0.87 calculated maximum power loss 9.0w x 0.95 x 1. 0 x 1.026 x 0.87 7.63w www.irf.com 2/8/2008 9
pd-60325 i p2005apbf calculating so a temperature: (figure 3) soa temperature adjustment for input voltage -1.2 oc (figure 4) soa temperature adjustment for output voltage 0.0oc (figure 5) soa temperature adj ustme n t for outp u t in d u ctor 0.6 oc (figure 6) soa temperature adj ustme n t for switch fre q ue ncy -3.5 oc t x axis intercept adjustment -1.2 oc + 0.0 oc + 0.6 oc ? 3 .5 oc - 4 .1 oc assumin g t pcb = 100oc & t case = 110oc the followi ng exampl e shows how t he soa current is adjusted for t x decrease of 4.1oc v in = 12 .0v v dd = 5 . 0v v out = 1.3v f sw = 1 m hz l out = 300 nh 1. draw a li ne from case temperature axis to the pcb temperature axis. 2. draw a vertical li ne from the t x ax is interce p t to the soa curve. 3. draw a hori zontal li ne from the intersecti on of the vertical li ne with the soa curve to the y-axis (output current). the poi nt at which the horizontal li ne meets the y-axis is the soa continuous current. 4. draw a new vertic al li ne from the t x axis by addi ng or subtra cting the soa adjustment temperature from the ori g i nal t x intercept point. 5. draw a hori zontal li ne from the intersecti on of the new vertical li ne with the s o a curve to the y-axis (output c u rrent). the poi nt at whi c h the hori z ont al li ne meets the y-axis is the new soa continuous current. the soa adjustment indicates the part is stil l all o wed to run at a continuous current of 36a. www.irf.com 2/8/2008 10
2/8/2008 www.irf.com 11 pd-60325 i p2005apbf optimized emi feature 5v/d iv 20ns/d iv 5v/d iv 20ns/d iv vs w of ip2 005 a vs w of ip2 003 a the ip2005a is designed for lo w electromagnetic interference (emi) whic h mini miz e s pow e r loss and space, and si mplifi e s sy stem design by el imi n ating t he need for external snubber circuits. these benefits are ac hi eved by opti m izing the i n ternal component l a yout, integrating bypass filters and impl ementi ng ac tive clamp circuitry as a means of reducing switchi ng node voltage ringing; which is one of mai n sources of emi. t he figures above show waveform comparisons of switching node voltages of the previ ous generati o n ip2003a product and ip2005a under equivalent oper at ion c ondit ions .
pd-60325 i p2005apbf in tern a l block diagram figur e 1 1 inte rn al blo c k di agr a m pin description pi n numb er pi n name descriptio n 1, 8 v in input vo ltage p i n . connect input capac ito r s c l ose to th is p i n . 2 v s w vo ltage sw itch ing node ? p in connection to the outpu t inducto r . 3p gnd po we r g r oun d 4v dd supp ly vo ltage to in te rna l cir c u i tr y. 5p w m t t l le ve l inpu t to mo sfet d r ive r s . w hen pw m is h i g h , the con t ro l f e t is on and the sync fet is o f f. when pw m is lo w , the sync f e t is on and the c o ntro l f e t is o f f. 6 e n able w hen set to log i c le ve l h i gh , inte rna l c i r c u i tr y o f the de vice is enabled. w hen set to log i c le ve l lo w, the contro l and syn c h r on ous fets a r e tu rned off. 7c v cc ou tput of in ter n a l regu lato r . at tached a min i mu m of 1.0f capacitance fr o m th is p i n to pg n d . reco mmended to use 16v, x5 r, ce ra mic type capac ito r . www.irf.com 2/8/2008 12
pd-60325 i p2005apbf recommended pcb lay o ut figur e 1 2 top copp e r an d sold er-m a s k l a y e r of p cb l a y out www.irf.com 2/8/2008 13
pd-60325 i p2005apbf figur e 1 3 top & bottom component and vi a pl a c em e n t (tops ide , tr an s p a r ent v i e w do w n ) pcb lay o u t guid elin es the followi ng gui d eli n es are recommended to reduce the parasiti c v alues and optimize overal l performance. ? all pads on t he ip2005a f oot pr int des ign need t o be sold er- m as k def i ned ( s ee f i gur e 12) . also refe r to inter nati o nal r e ctifi e r ap p lication notes an1028 an d an10 2 9 for furth e r footprint design guidance. ? place as many vi as ar ound the powe r p ads (v in , v sw , and p gnd ) for both el ectrical and optimal therma l performance. ? a minimum of six 10f, x5r, 16v ceramic capa citors per ip 2005a ar e needed for greater than 30a operati on. this wil l result in the lowest loss due to i n put capacitor esr. ? placement of the ceramic input ca p a cito rs is critical to o p timi ze swi t ching performance. in cases w h ere there is a heatsi nk on the case of ip2005a , place all si x ceramic capacitors right underneath the i p 2005a footpri n t (s ee f i gur e 13 bot t o m com p onent lay e r) . i n cases w h ere there is not heatsink, c1 and c 6 on the bottom layer may be moved to the c1x and c 6 x locations (respectively) on th e top component layer (see figure 13 top component layer). in both cases, c2 ? c 5 need to be placed ri ght underneath the ip2005a pcb footpri n t. ? ded i cate at least two l a yer to for p gnd only ? duplicate the power nodes on mult i p l e lay e rs (r efe r to an10 2 9 ). www.irf.com 2/8/2008 14
pd-60325 i p2005apbf mech an ical o u tline drawing el ect r ic al i / o bottom v i ew 0.1 0 c 2x top view 5 4 s i de view b o ttom view corn er id 0.1 0 c 2x 5 no t e s: 1 . d i m ensio ns & to le r a nces per a s m e y14 . 5m ? 1 9 9 4 2 . d i m ensio ns are show n in m i llime t ers 3. t o l e r a nc es a r e : .xx = +/ - 0 .1 . x xx = +/ - 0 .0 2 5 .xx x x = + / - 0 .01 p r im ary datu m c is seating pla n e b i late r a l to le r a nce zone is ap pli ed to ea ch side of pa ckag e bo dy l a yout n o tes: 1 . l and patte r n s on user?s pcb shou ld be an id entical mir r o r im age of th e pa ttern sho w n in b o ttom vie w 2 . l ands shou ld be solder m a sk defined 3 . a l l i/o p ads on this product a r e me tal finish w i th fla s h gold en able 6 cv cc 7 v in 8 v in 1 v sw 2 p gnd 3 v dd 4 pw m 5 4 5 figur e 1 4 me ch an i c al outlin e dr a w i n g www.irf.com 2/8/2008 15
pd-60325 i p2005apbf tap e and reel in formation feed dir e ct ion 1 2 . 00 (. 47 3) 200 5a p xx xx yy mm 16 .0 0 (.6 3 0 ) 20 05a p xx xx yy mm xx xx figur e 1 5 t a pe a nd re e l i n formation www.irf.com 2/8/2008 16
pd-60325 i p2005apbf recommend e d sold er paste sten cil desig n no tes: 1.t h is view is stencil squeegee vie w 2.dimens ions ar e sho w n i n mill i m eters 3.t h is opening is based on us in g 150 micro n thick stencil. if usi ng a d i ffere nt thickness stencil, this op en ing ne eds to b e adjuste d accor d ing l y . 4.dashe d lin es sho w stenci l op enin g s. solid li nes sho w pcb pad ope nin g s. 5.t he recommended reflo w pea k temperatur e i s 260oc. t he total furnace ti me is appro x im atel y 5 minutes w i th appro x imatel y 10 secon d s at peak temper ature. corner id figur e 1 6 s o lde r p a s t e sten cil de si gn part marking figur e 1 7 p a rt ma r k ing www.irf.com 2/8/2008 17
pd-60325 i p2005apbf ir world h e ad quart ers: 1 0 1 n. sepu lveda b l vd ., e l segundo , ca li fo r n ia 90245 , u s a te l: ( 310 ) 252 - 7105 t a c fax: (310 ) 252 -7903 this p r odu ct ha s b e en d e sign e d for th e indu stri a l ma r k et. vis i t us a t w w w . ir f.co m fo r sa le s contac t in fo r m a t ion d a ta and spe c ifica t ions sub j ec t to chan ge w i thout no tice . 12/24/2007 www.irf.com 2/8/2008 18

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