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24-bit, 96khz sampling cmos delta-sigma stereo audio digital-to-analog converter 49% fpo international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 ? twx: 910-952-1111 internet: http://www.burr-brown.com/ ? faxline: (800) 548-6133 (us/canada only) ? cable: bbrcorp ? telex: 066-6491 ? fa x: (520) 889-1510 ? immediate product info: (800) 548-6132 pcm1728 tm description the pcm1728 is designed for mid- to high-grade digital audio applications which achieve 96khz sam- pling rates with 24-bit audio data. pcm1728 uses a newly developed, enhanced multi-level delta-sigma modulator architecture that improves audio dynamic performance and reduces jitter sensitivity in actual applications. the internal digital filter operates at 8x oversampling at a 96khz sampling rate. the pcm1728 has superior audio dynamic perfor- mance, 24-bit resolution, and 96khz sampling, mak- ing it ideal for mid- to high-grade audio applications such as cd, dvd, and musical instruments. features l enhanced multi-level delta-sigma dac l sampling frequency (f s ): 16khz - 96khz l input audio data word: 16-, 20-, 24-bit l high performance: thd+n: C96db dynamic range: 106db snr: 106db analog output range: 0.62 x v cc (vp-p) l 8x oversampling digital filter: stop band attenuation: C82db passband ripple: 0.002db l multi functions: digital de-emphasis soft mute zero flag l +5v single supply operation l small 28-lead ssop package ? 1998 burr-brown corporation pds-1453a printed in u.s.a. april, 1998 serial input i/f mode control i/f 8x oversampling digital filter with function controller crystal/osc xti sck xto clko v cc1 agnd1 v dd dgnd enhanced multi-level delta-sigma modulator v out l v cc2 l v cc2 r agnd2l agnd2l extl open drain dac low-pass filter low-pass filter v out r extr zero dac dm1 i 2 s lrcin din bckin iw0 dm0 iw1 mute rst power supply pcm1728 sbas096
2 pcm1728 specifications all specifications at +25 c, +v cc = +v dd = +5v, f s = 44.1khz, and 24-bit input data, sysclk = 384f s , unless otherwise noted. pcm1728 parameter conditions min typ max units resolution 24 bits data format audio data interface format standard/i 2 s data bit length 16/20/24 selectable audio data format msb-first, twos binary comp sampling frequency (f s ) 16 96 khz system clock frequency (1) 256/384/512/768f s digital input/output logic level input logic level v ih 2.0 v v il 0.8 v output logic level (clko) v oh i oh = 2ma 4.5 v v ol i ol = 4ma 0.5 v clko performance (2) output rise time 20 ~ 80% v dd , 10pf 5.5 ns output fall time 80 ~ 20% v dd , 10pf 4 ns output duty cycle 10pf load 37 % dynamic performance (3) (24-bit data) thd+n v o = 0db f s = 44.1khz C97 C90 db f s = 96khz C94 db v o = C60db f s = 44.1khz C42 db dynamic range f s =44.1khz eiaj a-weighted 98 106 db f s = 96khz a-weighted 103 db signal-to-noise ratio f s =44.1khz eiaj a-weighted 98 106 db f s = 96khz a-weighted 103 db channel separation f s = 44.1khz 96 102 db f s = 96khz 101 db dynamic performance (3) (16-bit data) thd+n v o = 0db f s = 44.1khz C94 db f s = 96khz C92 db dynamic range f s = 44.1khz eiaj a-weighted 98 db f s = 96khz a-weighted 97 db dc accuracy gain error 1.0 3.0 % of fsr gain mismatch: channel-to-channel 1.0 3.0 % of fsr bipolar zero error v o = 0.5v cc at bipolar zero 30 60 mv analog output output voltage full scale (0db) 0.62 v cc vp-p center voltage 0.5 v cc v load impedance ac load 5 k w digital filter performance filter characteristics passband 0.002db 0.454f s C3db 0.490f s stopband 0.546f s passband ripple 0.002 db stopband attenuation stop band = 0.546f s C75 db stop band = 0.567f s C82 db delay time 30/f s sec de-emphasis error 0.1 db internal analog filter C3db bandwidth 100 khz passband response f = 20khz C0.16 db power supply requirements voltage range v dd, v cc 4.5 5 5.5 vdc supply current: i cc +i dd f s = 44.1khz 32 45 ma f s = 96khz 45 ma power dissipation f s = 44.1khz 160 225 mw f s = 96khz 225 mw temperature range operation C25 +85 c storage C55 +100 c notes: (1) refer section of system clock. (2) external buffer is recommended. (3) dynamic performance specs are tested with 20k hz low pass filter and thd+n specs are tested with 30khz lpf, 400hz hpf, average mode.
3 pcm1728 pin name i/o description 1 lrcin in left and right clock input. this clock is equal to the sampling rate - f s . (1) 2 din in serial audio data input (1) 3 bckin in bit clock input for serial audio data. (1) 4 clko out buffered output of oscillator. equivalent to system clock. 5 xti in oscillator input (external clock input) 6 xto out oscillator output 7 dgnd digital ground 8v dd digital power +5v 9v cc 2r analog power +5v 10 agnd2r analog ground 11 extr out rch, common pin of analog output amp 12 nc no connection 13 v out r out rch, analog voltage output of audio signal 14 agnd1 analog ground 15 v cc 1 analog power +5v 16 v out l out lch, analog voltage output of audio signal 17 nc no connection 18 extl out lch, common pin of analog output amp 19 agnd2l analog ground 20 v cc 2l analog power +5v 21 zero out zero data flag 22 rst in reset. when this pin is low, the df and modulators are held in reset. (2) 23 iw0 in input format selection (3) 24 iw1 in input format selection (3) 25 mute in mute control 26 dm0 in de-emphasis selection 1 (2) 27 dm1 in de-emphasis selection 2 (2) 28 i 2 s in input format selection (2) notes: (1) pins 1, 2, 3; schmitt trigger input. (2) pins 22, 25, 26, 27, 28; schmitt trigger input with pull-up resister. (3) pins 23, 24; schmitt trigger input with pull-down resister. pin assignments pin configuration package drawing product package number (1) PCM1728E 28-pin ssop 324 note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix c of burr-brown ic data book. package information electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. power supply voltage ...................................................................... +6.5v +v cc to +v dd difference ................................................................... 0.1v input logic voltage .................................................. C0.3v to (v dd + 0.3v) input current (except power supply) ............................................... 10ma power dissipation .......................................................................... 400mw operating temperature range ......................................... C25 c to +85 c storage temperature ...................................................... C55 c to +125 c lead temperature (soldering, 5s) ................................................. +260 c absolute maximum ratings lrcin din bckin clko xti xto dgnd v dd v cc 2r agnd2r extr nc v out r agnd1 i 2 s dm1 dm0 mute iw1 iw0 rst zero v cc 2l agnd2l extl nc v out l v cc 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PCM1728E
4 pcm1728 ?0db output spectrum (f = 1khz, f s = 44.1khz, 24-bit data) frequency (hz) amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 ?50 202468101214161820 ?0db output spectrum (f = 1khz, f s = 44.1khz, 16-bit data) frequency (hz) amplitude (db) ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 ?50 202468101214161820 typical performance curves all specifications at +25 c, +v cc = +v dd = +5v, f s = 44.1khz, and 24-bit input data, sysclk = 384f s , unless otherwise noted. thd+n vs sampling frequency (v cc = v dd = 5v, 24-bit) sampling frequency f s (khz) thd+n at f/s (db) 88 91 94 97 100 103 32 44.1 48 96 256fs 384fs thd+n vs level (f s = 44.1khz) amplitude (db) thd+n (%) 10 1 0.1 0.010 0.001 thd+n (db) ?0 ?0 ?0 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 16-bit 24-bit dynamic range vs sampling frequency (v cc = v dd = 5v, 24-bit) sampling frequency f s (khz) dynamic range (a-weighted) (db) 110 108 106 104 102 100 32 44.1 48 96 256/384f s snr vs sampling frequency (v cc = v dd = 5v, 24-bit) sampling frequency f s (khz) snr (a-weighted) (db) 110 108 106 104 102 100 32 44.1 48 96 256/384f s
5 pcm1728 typical performance curves (cont) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 amplitude (db) overall frequency characteristic frequency (x f s ) 0 0.1 0.2 0.3 0.4 0.5 0.003 0.002 0.001 0 ?.001 ?.002 ?.003 amplitude (db) passband ripple characteristic frequency (x f s ) de-emphasis frequency response (f s = 32khz) 02468101214 frequency (khz) 0 ? ? ? ? ?0 level (db) de-emphasis frequency response (f s = 48khz) 0246810121416182022 frequency (khz) 0 ? ? ? ? ?0 level (db) de-emphasis frequency response (f s = 44.1khz) 02468101214161820 frequency (khz) 0 ? ? ? ? ?0 level (db) de-emphasis error (f s = 32khz) 02468101214 frequency (khz) 0.5 0.3 0.1 ?.1 ?.3 ?.5 0.5 0.3 0.1 ?.1 ?.3 ?.5 0.5 0.3 0.1 ?.1 ?.3 ?.5 level (db) de-emphasis err0r (f s = 48khz) 0246810121416182022 frequency (khz) level (db) de-emphasis error (f s = 44.1khz) 02468101214161820 frequency (khz) level (db)
6 pcm1728 system clock the system clock for pcm1728 must be either 256f s , 384f s , 512f s or 768f s , where f s is the audio sampling frequency (typically 32khz, 44.1khz, 48khz, or 96khz). but 768f s at 96khz is not accepted. the system clock can be either a crystal oscillator placed between xti (pin 5) and xto (pin 6), or an external clock input to xti. if an external system clock is used, xto is open (floating). figure 1 illustrates the typical system clock connections. pcm1728 has a system clock detection circuit which auto- matically senses if the system clock is operating at 256f s ~ 768f s . the system clock should be synchronized with lrcin (pin 1) clock. lrcin (left-right clock) operates at the sam- pling frequency f s . in the event these clocks are not synchro- nized, pcm1728 can compensate for the phase difference internally. if the phase difference between left-right and system clocks is greater than 6-bit clocks (bckin), the synchronization is performed internally. while the synchro- nization is processing, the analog output is forced to a dc level at bipolar zero. the synchronization typically occurs in less than 1 cycle of lrcin. system clock frequency - mhz sampling rate frequency (f s ) - lrcin 256f s 384f s 512f s 768f s 32khz 8.1920 12.2880 16.3840 24.5760 44.1khz 11.2896 16.9340 22.5792 33.8688 (1) 48khz 12.2880 18.4320 24.5760 36.8640 (1) 96khz 24.5760 36.8640 (1) 49.1520 (1) note: (1) the internal crystal oscillator frequency cannot be larger than 24.576mhz. table i. typical system clock frequency. typical input system clock frequencies to the pcm1728 are shown in table i, also, external input clock timing require- ments are shown in figure 2. figure 1. system clock connection. figure 2. xti clock timing. system clock (256/384/ 512/768f s ) externl clock input clko xti xto 4 5 6 pcm1728 system clock buffer out crystal resonator oscillation clko xti xto 4 5 6 pcm1728 xtal c 1 c 2 c 1 c 2 : 10pf ~ 30pf buffer t sckh system clock pulse width high t sckih : 7ns min system clock pulse width low t sckil : 7ns min t sckl 2.0v 0.8v ? ? xti data interface formats digital audio data is interfaced to pcm1728 on pins 1, 2, and 3, lrcin (left-right clock), din (data input) and bckin (bit clock). pcm1728 can accept both standard, i 2 s, and left justified data formats. figure 3 illustrates acceptable input data formats. figure 4 shows required timing specification for digital audio data. reset pcm1728 has both internal power-on reset circuit and the rst pin (pin 22), which accepts an external forced reset by rst = low. for internal power on reset, initialization is done automatically at power on v dd >2.2v (typ). during internal reset = low, the output of the dac is invalid and the analog outputs are forced to v cc /2. figure 5 illustrates the timing of the internal power on reset. pcm1728 accepts an external forced reset when rst = low. when rst = low, the output of the dac is invalid and the analog outputs are forced to v cc /2 after internal initialization (1024 system clocks count after rst = high.) figure 6 illustrates the timing of the rst pin. zero out (pin 21) if the input data is continuously zero for 65536 cycles of bck, an internal fet is switched to on. the drain of the internal fet is the zero-pin, it will enable wired-or with external circuit.
7 pcm1728 figure 3. audio data input formats. 14 15 16 1 2 3 14 15 1/f s l_ch r_ch msb lsb 16 lrcin (pin 1) bckin (pin 3) (1) 16-bit right justified din (pin 2) 1 2 3 14 15 msb lsb 16 18 19 20 1 2 3 18 19 msb lsb 20 (2) 20-bit right justified din (pin 2) 1 2 3 18 19 msb lsb 20 23 24 1 2 3 22 23 msb lsb 24 (3) 24-bit right justified din (pin 2) (4) 24-bit left justified din (pin 2) 1 2 3 22 23 msb lsb 24 1 2 3 22 23 msb lsb 24 1 2 3 22 23 msb lsb 24 1 2 3 14 15 1/f s l_ch r_ch msb lsb 16 lrcin (pin 1) bckin (pin 3) (5) 16-bit i 2 s din (pin 2) 1 2 3 14 15 msb lsb 16 2 1 2 1 1 2 3 22 23 msb lsb 24 (6) 24-bit i 2 s din (pin 2) 1 2 3 22 23 msb lsb 24 lrckin bckin din 1.4v 1.4v 1.4v t bch t bcl t lb t bl t ds bckin pulse cycle time bckin pulse width high bckin pulse width low bckin rising edge to lrcin edge lrcin edge to bckin rising edge din set-up time din hold time : t bcy : t bch : t bcl : t bl : t lb : t ds : t dh : 100ns (min) : 50ns (min) : 50ns (min) : 30ns (min) : 30ns (min) : 30ns (min) : 30ns (min) t dh t bcy figure 4. audio data input timing specification.
8 pcm1728 figure 5. internal power-on reset timing. functional description pcm1728 has several built-in functions including digital input data format selection, soft mute, and digital de-empha- sis. these functions are hardware controlled where static control signals are used on pin 28 (i 2 s), pin 27 (dm1), pin 26 (dm0), pin 25 (mute), pin 24 (iw1), and pin23 (iw0). data formal selection pcm audio data format can be selected by pin 28 (i 2 s), pin 24 (iw1), and pin 23 (iw0), as shown in table ii. figure 6. external forced reset timing. 1024 system (= xti) clocks reset reset removal v cc = v dd internal reset xti clock 1024 system (xti) clocks reset reset removal xti clock internal reset rst t rst (1) note: (1) t rst = 20ns min. iw1 iw0 i 2 s audio interface 0 0 0 16-bit standard, right-justified 0 1 0 20-bit standard, right-justified 1 0 0 24-bit standard, right-justified 1 1 0 24-bit left-justified, msb-first 0 0 1 16-bit i 2 s 0 1 1 24-bit i 2 s 1 0 1 reserved 1 1 1 reserved table ii. data format control. soft mute soft mute function can be controlled by mute (pin 25). mute (pin 25) soft mute l mute on h mute off (normal operation) table iii. soft mute control. de-emphasis control de-emphasis control can be selected by dm1 (pin 27) and dm0 (pin 26). dm1 (pin 27) dm0 (pin 26) de-emphasis l l off l h 48khz h l 44.1khz h h 32khz table iv. de-emphasis control.
9 pcm1728 the advantage of stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. the combined oversampling rate of the delta-sigma modu- lator and the internal 8-times interpolation filter is 64f s for all system clock ratios (256/384/512/768f s ). the theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in figure 8. this enhanced multi-level delta-sigma architecture also has ad- vantages for input clock jitter sensitivity due to the multi- level quantizer, simulated jitter sensitivity is shown in figure 9. + z ? 8-level quantizer + z ? + z ? + z ? + + figure 7. 8-level delta-sigma modulator. 012345678 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 ?60 ?80 amplitude (db) frequency (f s ) figure 8. quantization noise spectrum. 0 100 200 300 400 500 600 125 120 115 110 105 100 95 90 85 80 dynamic range (db) jitter (ps) clock jitter figure 9. jitter sensitivity. theory of operation the delta-sigma section of pcm1728 is based on an 8-level amplitude quantizer and a 4th-order noise shaper. this section converts the oversampled input data to 8-level delta- sigma format. this newly developed, enhanced multi-level delta-sigma architecture achieves high-grade audio dynamic performance and sound quality. a block diagram of the 8-level delta-sigma modulator is shown in figure 7. this 8-level delta-sigma modulator has
10 pcm1728 application considerations delay time there is a finite delay time in delta-sigma converters. in a/d converters, this is commonly referred to as latency. for a delta-sigma d/a converter, delay time is determined by the order number of the fir filter stage, and the chosen sampling rate. the following equation expresses the delay time of pcm1728: t d = 30 x 1/f s for f s = 44.1khz, t d = 30/44.1khz = 680 m s applications using data from a disc or tape source, such as cd audio, dvd audio, video cd, dat, minidisc, etc., generally are not affected by delay time. for some profes- sional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. output filtering for testing purposes all dynamic tests are done on the pcm1728 using a 20khz low pass filter. this filter limits the measured bandwidth for thd+n, etc. to 20khz. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the specifications. the low pass filter removes out of band noise. although it is not audible, it may affect dynamic specification numbers. the performance of the internal low pass filter from dc to 40khz is shown in figure 10. the higher frequency roll-off of the filter is shown in figure 11. if the users application has the pcm1728 driving a wideband amplifier, it is recom- mended to use an external low pass filter. bypassing power supplies the power supplies should be bypassed as close as possible to the unit. refer to figure 12 for optimal values of bypass capacitors. 1 10 100 1k 10k 100k 1 0.5 0 ?.5 ? level (db) log frequency (hz) figure 10. low pass filter response. figure 11. low pass filter response. power supply connections pcm1728 has four power supply pin for digital (v dd ), and analog (v cc ). each connection also has a separate ground. if the power supplies turn on at different times, there is a possibility of a latch-up condition. to avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. if separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.1v. 1 10 100 1k 10k 100k 10m 1m 20 0 ?0 ?0 ?0 ?0 ?00 level (db) log frequency (hz)
11 pcm1728 figure 12. typical circuit connection diagram. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lrcin din bckin clko xti xto dgnd v dd v cc 2r agnd2r extr nc v out r agnd1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 iis dm1 dm0 mute iw1 iw0 rst zero v cc 2l agnd2l extl nc v out l v cc 1 c 2 post low-pass filter analog mute rch audio out mode control PCM1728E external reset pcm audio data input system clock (256/384/512/768f s ) xti buffer out to dgnd of digital source post low-pass filter analog mute external mute control lch audio out c 4 c 6 10? c 1 , c 2 : 10? + 0.1? ceramic c 3 , c 4 : 1? ~ 10? c 3 c 5 10? + + c 1 +5v v cc 10k w
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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