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W78E354 monitor microcontroller publication release date: april 1997 - 1 - revision a1 general description the W78E354 is a stand-alone high-performance microcontroller asic specially designed for use in monitor control applications. using the winbond 0.8 m dpdm process, the W78E354 integrates an embedded 8031 microcontroller core, 16k bytes of flash cell, 512 bytes of ram and a number of dedicated hardware functions. these hardware functions include a 6-bit a/d converter, two/fourteen 12/8-bit pwm static dacs, one/three 12/8-bit pwm dynamic dacs, a sync processor, one ddc port, a watchdog timer and other custom glue logic. additional special function registers are incorporated to control the on-chip peripheral hardware. the chip is used to control the interface signals of other devices in the monitor and to process the video sync signals. because of high integration and the incorporation of flash cell for program memory, the device offers the user the competitive advantages of low cost and reduced development time. features 80c31 mcu core included 16k bytes flash otp memory for program storage total 512 bytes of on-chip data ram: 256 bytes accessed as in the 80c32, 256 bytes accessed as external data memory via "movx @ri". one spi/rs232 port (a serial port of 8051 standard) one external interrupt input two timers/counters pwm d acs: - two 12-bit pwm/brm static dacs - fourteen 8-bit pwm static dacs - one 12-bit pwm/brm dynamic dac - three 8-bit pwm dynamic dacs one 6-bit adc with 4 multiplexed analog inputs sync processor: - horizontal & vertical polarity detector - sync separator for composite sync - horizontal & vertical frequency counter - programmable dummy frequency generator - programmable h-clamp pulse output - soa output (hardware h frequency change detection) one ddc port (master/slave mode i 2 c with two slave address reg., support dc1/ddc2b/ddc2b+) one 8-bit auto-reload timer for software time base
W78E354 - 2 - watchdog timer two 15 ma output pins for driving leds power down reset clock: dc to 20 mhz packaged in 68-pin plcc, 48-pin dip and 40-pin dip pin configurations 6 7 6 8 6 6 6 5 6 4 6 3 6 2 6 1 3 2 1 4 9 8 7 6 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 p 2 . 4 / s d a c 1 0 p 4 . 5 p 2 . 5 / s d a c 1 1 s d a c 6 s d a c 5 p 4 . 6 s d a c 7 s d a c 8 s d a c 9 p 3 . 7 v d d s d a c 4 s d a c 3 s d a c 2 p 4 . 4 p 3 . 3 s d a c 1 sdac0 p4.3 ddac0 vpp p4.1 p4.0 p1.0 vdd p1.4/hclamp p1.3/dsda p1.1 p1.2/dscl p1.5/soa p4.2 bddac ddac2 ddac1 p2.2 p3.4/t0 p2.3/stp p3.5/t1 p2.7/sdac13 p2.6/sdac12 sdac11 sdac10 oscin oscout p2.0 vss p2.1 sdac12 sdac13 vin hin a d c 0 v o u t h o u t v s s v a a p 3 . 1 / t x d p 3 . 2 / i n t 0 v s s a p 3 . 0 / r x d b s d a c 0 p 3 . 6 r e s e t b s d a c 1 a d c 1 a d c 2 / p 1 . 6 a d c 3 / p 1 . 7 t e s t c l k W78E354p (plcc-68)
W78E354 publication release date: april 1997 - 3 - revision a1 pin cinfigurations, continued 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 p1.4/hclamp p1.3/dsda vssa v testclk p1.5/soa v adc0 vaa p1.2/dscl p1.0 p1.1 bddac sdac4 sdac3 sdac2 sdac1 sdac0 ddac2 ddac1 ddac0 p3.3 p3.6 p3.2/int0 p2.4/sdac10 p2.5/sdac11 sdac6 sdac5 p3.4/t0 p2.6/sdac12 p3.0/rxd p2.7/sdac13 sdac7 p3.1/txd p3.5/t1 oscout oscin vss p2.0 p2.2 p2.1 p2.3/stp hin vin hout vout bsdac0 reset W78E354e (dip-48) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 bddac v sdac4 sdac3 sdac2 sdac1 sdac0 p1.4/hclamp p1.3/dsda p1.5/soa v p1.2/dscl p1.0 p1.1 ddac0 p3.1/txd testclk adc0 p3.2/int0 reset W78E354 (dip-40) dd pp p2.4/sdac10 p2.5/sdac11 sdac6 sdac5 sdac7 p2.6/sdac12 p2.7/sdac13 oscout oscin v p2.0 p2.2 p2.1 p2.3/stp hin vin hout vout bsdac0 p3.0/rxd ss pp dd pin description pin no. 68p 64p 48p 40p pin name i/o type test name functional description 60 62 63 65 66 3 4 5 6 7 10 11 19 20 57 59 60 61 62 1 2 3 4 5 8 9 17 18 42 44 45 46 47 1 2 3 - - - - - - 35 36 37 38 39 1 2 3 - - - - - - sdac0 sdac1 sdac2 sdac3 sdac4 sdac5 sdac6 sdac7 sdac8 sdac9 sdac10 sdac11 sdac12 sdac13 i/o o/p a0 a1 a2 a3 a4 a5 a6 a7 - - - - - - 8-bit pwm static dac output. sink/source current 4 ma/-4 ma. with slew rate control and output delay : 1. delay about 5 ns: sdac2, 5, 8, 11. 2. delay about 10 ns: sdac0, 3, 6, 9, 12. 3. without delay: the others. --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): sdac0 - 7: a0 - a7 inputs. * in the functional test mode (cpu executes out of ext. program memory): sdac0 - 7: a0 - a7 outputs.
W78E354 - 4 - pin description, continued pin no. 68p 64p 48p 40p pin name i/o type test name functional description 29 30 27 28 21 - 19 - bsdac0 bsdac1 i/o o/p a8 - 12-bit pwm/brm static dac output. sink/source current 8 ma/-8 ma. with slew rate control and output delay : 1. delay about 5ns: bsdac1 2. without delay: bsdac0. --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): bsdac0: a8 input. * in the functional test mode (cpu executes out of ext. program memory): bsdac0: a8 output. 56 57 58 53 54 55 38 39 40 33 - - ddac0 ddac1 ddac2 i/o o/p a9 - - 8-bit pwm dynamic dac output. sink/source current 8 ma/-8 ma. with slew rate control and output delay : 1. delay about 5 ns: ddac1. 2. delay about 10 ns: ddac2. 3. without delay: ddac0. --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): ddac0: a9 input. * in the functional test mode (cpu executes out of ext. program memory): ddac0: a9 output. 59 56 41 34 bddac i/o a10 12-bit pwm/brm dynamic dac output. sink/source current 8ma/-8ma. with slew rate control . --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): bddac: a10 input. * in the functional test mode (cpu executes out of ext. program memory): bddac: a10 output.
W78E354 publication release date: april 1997 - 5 - revision a1 pin description, continued pin no. 68p 64p 48p 40p pin name i/o type test name functional description 36 37 39 40 34 35 37 38 26 - - - 23 - - - adc0 adc1 adc2 (p1.6) adc3 (p1.7) i/p - - - - analog signal input channel to adc. alternate function: adc2: p1.6 input (input only). adc3: p1.7 input (input only). 46 47 44 45 31 32 26 27 p1.0 p1.1 i/o a13 a14 general purpose i/o. open-drain, sink current 2ma. schmitt trigger i/p. no pmos esd cell. v ih = 3.0v (min), v il = 1.5v (max) --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): p1.0 and p1.1: a13 and a14 inputs. * in the functional test mode (cpu executes out of ext. program memory): p1.0 and p1.1: do not output a13 and a14, but function in their normal operational state. 48 49 46 47 33 34 28 29 p1.2 (dscl) p1.3 (dsda) i/o a13ctrl a14ctrl general purpose i/o. open-drain, sink current 6ma. schmitt trigger i/p. no pmos esd cell. v ih = 3.0v (min), v il = 1.5v (max) alternate function: p1.2: ddc port serial clock dscl. p1.3: ddc port serial data dsda. --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): p1.2: a13ctrl input. p1.3: a14ctrl input.
W78E354 - 6 - pin description, continued pin no. 68p 64p 48p 40p pin name i/o type test name functional description 50 48 35 30 p1.4 (hclamp) i/o a9ctrl general purpose i/o. sink/source current 4 ma/-100 m a. alternate function: p1.4: hclamp (h-clamp pulse) output. while outputing special function, p1.4's sink/source current is 4 ma/-4 ma . --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): p1.4: a9ctrl input. 51 49 36 31 p1.5 (soa) i/o a11 general purpose o/p. sink/source current 4 ma/-4 ma. alternate function: p1.5: soa (safe operation area) outpout. --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): p1.5: a11 input. * in the functional test mode (cpu executes out of ext. program memory): p1.5: doesn't output a11, but functions as its normal operation. 17 18 15 16 11 12 11 12 p2.0 p2.1 i/o d0 d1 general purpose i/o. sink/source current 15ma/-100 m a. with slew rate control . --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): p2.0 - p2.1: d0 - d1 data inputs/outputs. * in the functional test mode (cpu executes out of ext. program memory): p2.0 - p2.1: d0 - d1 program inputs.
W78E354 publication release date: april 1997 - 7 - revision a1 pin description, continued pin no. 68p 64p 48p 40p pin name i/o type test name functional description 21 22 8 9 12 13 19 20 6 7 10 11 13 14 4 5 6 7 13 14 4 5 6 7 p2.2 p2.3 (stp) p2.4 (sdac10) p2.5 (sdac11) p2.6 (sdac12) p2.7 (sdac13) i/o d2 d3 d4 d5 d6 d7 general purpose i/o. sink/source current 4 ma/-100 m a. alternate function: p2.3: stp (self-test pattern) output. p2.4 - p2.7: sdac10 - 13 outputs. while outputing special function, p2.3 - p2.7's sink/source current is 4ma/-4ma . --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): p2.2 - p2.7: d2 - d7 data inputs/outputs. * in the functional test mode (cpu executes out of ext. program memory): p2.2 - p2.7: d2 - d7 program inputs. 31 32 42 61 23 24 43 67 29 30 40 58 21 22 41 63 22 23 29 43 15 16 30 - 20 21 25 - - - - - p3.0 (rxd) p3.1 (txd) p3.2 (int0) p3.3 p3.4 (t0) p3.5 (t1) p3.6 p3.7 i/o - - a12 (psen) - - - - - general purpose i/o. sink/source current 2 ma/-100 m a. alternate function: p3.0: 8051 serial input port. p3.1: 8051 serial output port. p3.2: external interrupt input. p3.4 and p3.5: timer/counter 0 and 1 external inputs. --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): p3.2: a12 input. * in the functional test mode (cpu executes out of ext. program memory): p3.2: psen output (the read strobe to external program memory) instead of a12.
W78E354 - 8 - pin description, continued pin no. 68p 64p 48p 40p pin name i/o type test name functional description 44 45 53 55 64 1 2 42 43 51 - - - - - - - - - - - - - - - - - - p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 o/p - - - - - - - output port (latch output). sink/source current 2 ma/-2 ma. 25 26 23 24 17 18 15 16 h in v in i/p oe ce h in : hsync/composite sync input. v in : vsync input. schmitt trigger i/p. with internal high value pull-down (about 200 k w ). no pmos esd diode. --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): h in : oe input. v in : ce input. 27 28 25 26 19 20 17 18 h out v out i/o oectrl prog h out : hsync output. v out : vsync output with internal weak pull-up (above 200 k w ). sink/source current 4 ma/-4 ma. --------------------------------------------------------- * in the flash/ram-test mode (when the chip is in reset state): h out : oectrl input. v out : prog input. 33 31 24 22 reset i/p - reset the controller (active low). schmitt trigger i/p. with internal pull-up (about 30 k w ). 41 39 28 24 testclk i/p ea clock input while in internal (glue logic's) function test. with internal pull-up (about 30 k w ). --------------------------------------------------------- * if the ea (testclk) pin is pulled low when the chip is being reset, and remains low for at least 24 clock periods after the reset, the cpu will execute from the external program memory regardless of the pc value. i.e., the cpu is forced to enter the functional test mode .
W78E354 publication release date: april 1997 - 9 - revision a1 pin description, continued pin no. 68p 64p 48p 40p pin name i/o type test name functional description 14 15 12 13 8 9 8 9 osc out osc in o/p i/p - - output from the inverting oscillator amplifier. input to the inverting oscillator amplifier. freq.: 16 mhz to 24 mhz. 54 52 37 32 v pp - v pp in the test/flash mode, this pin is the power supply input for the flash cell. 68 64 48 40 v dd - - positive digital power supply, +5v. 16 14 10 10 v ss - - digital ground. 52 50 - - v dd - - positive digital power supply, +5v. internally connected to the other power source. 34 32 - - v ss - - digital ground. internally connected to the other power source. 38 36 27 - vaa - - positive analog power supply, +5v. 35 33 25 - vssa - - analog ground.
W78E354 - 10 - block diagram W78E354 v a a, v ssa 8031 mcu core with 256b scratchpad ram power source supervisor reset circuit wdt osc/timing generator reset t1 (p3.5) t0 (p3.4) txd (p3.1) rxd (p3.0) sync processor vpp 16kb flash rom 256b data memory interrupt processor sdac ddac int0 (p3.2) sdac0~13 bsdac0~1 ddac0~2 bddac adc adc0~3 v v ss dd srial port timer 0 timer1 ddc i/o port autoload timer dscl (p1.2) dsda (p1.3) port 1, 2, 3 (except p1.5) p1.5, port 4 oscin oscout hin, vin hout, vout soa (p1.5) hclamp (p1.4)
W78E354 publication release date: april 1997 - 11 - revision a1 functional description a. 80c31 core the W78E354's 80c31 (cmos mcu) core architecture consists of a cpu surrounded by various special function registers or sfrs. some of these sfrs are standard 80c31 registers while others are new additions, cf. table 1. the device includes three general purpose i/o ports (p1, p2 and p3), one output-only port (p4), 256 bytes of scratchpad ram, two timer/counters (timer0 and timer1) and one 8051 standard serial port. the processor supports 109 different instructions (without "movx a,@dptr" and "movx @dptr,a") all of which are compatible with those of the mcs-51 family. one distinguishing feature of the device architecture is the sfr address space into which all the registers, peripherals and scratchpad ram are mapped. many of the instructions operate on an sfr address rather than a specific register, greatly increasing the power of the instruction set. the core controller has been designed around a state machine rather than utilizing a microcode approach, a design methodology which offers several advantages. the first of these is that faster circuits can be produced due to the fact that flip-flops are inherently faster than roms. secondly, a rom-free approach allows the design to be directly utilized in asic gate array implementations, an important factor for cost reductions. finally, an entire digital logic approach provides better supply noise immunity in most applications. table 1. W78E354's special function registers (sfrs) f8 ff f0 + b f7 e8 ef e0 + acc e7 d8 + s1con s1sta s1dat s1adr df d0 + psw d7 c8 + contreg4 cf c0 c7 b8 + ip sbrm0 sbrm1 port4 soareg soaclr bf b0 + p3 adc intvect status hfcountl hfcounth vfcountl vfcounth b7 a8 + ie sdac7 sdac8 sdac9 sdac10 sdac11 sdac12 sdac13 af a0 + p2 sdac0 sdac1 sdac2 sdac3 sdac4 sdac5 sdac6 a7 98 + scon sbuf bsdac0 bsdac1 wdtclr ddac0 ddac1 ddac2 9f 90 + p1 autoload dhreg dvreg ddc1 intmsk bddac dbrm 97 88 + tcon tmod tl0 tl1 th0 th1 paral parah 8f 80 + contreg1 sp dpl dph contreg5 contreg2 contreg3 pcon 87 notes: 1. the sfrs with a "+" are both byte- and bit-addressable. 2. the registers in the shaded region are new additions to the 80c31 sfrs. a.1 address space (cf. figure 1) the W78E354 cpu operates out of three separate address spaces:
W78E354 - 12 - 1. the first of these is the internal program space (internal flash memory) with 16k byte size (0000h - 3fffh). the program space can be accessed by both opcode fetches and the "movc" instructions. 2. the second is referred to as the data memory space and has a size of 256 bytes (0000h - 00ffh). the data memory is integrated within the chip rather than being outside as in the case of the standard 8031. the "inside" data memory space is accessed by the "movx @ri" instruction. 3. the third address space has 256 locations while it is used by 384 bytes (256 bytes of ram and 128 bytes of sfrs). the lower 128 locations of this address space (00h - 7fh) are for the lower 128 bytes of scratchpad ram. any of these 128 bytes may be used by a programmer but some of them have special uses. the lowest 32 bytes are organized to four 8-byte register banks. the bank select bits (rs0 and rs1 in the psw register) selects one of these four banks which is to be used currently as an operand in the instruction set. registers 0 to 7 in the bank are referenced by the register direct opcodes. registers 0 and 1 may also contain an address that is referenced by the register indirect opcodes. the higher 128 locations of this address space (80h - ffh) are shared by the higher 128 bytes of scratchpad ram and the special function registers (sfrs). the sfrs are accessed only by "direct" addressing while the higher 128 bytes of scrachpad ram are accessed only by "indirect" addressing. the higher 128 bytes of scratchpad data ram are also available for stack space. address spaces 20h to 2fh are bit-addressable and can be used by the boolean variable manipulation instructions. for example, bit 0 of address 20h has a boolean address 00h, and bit 7 of address 2fh has a boolean address 7fh. the higher boolean addresses (80h - ffh) are mapped into the sfr address space. to determine a boolean address in some bit-addressable sfr, the higher 5 bits of the sfr's address can be combined with the 3 lower bits that specify the desired bit in the sfr. 0000h 3fffh 00h ffh 00h on-chip program memory on-chip data memory ffh 7fh 80h (direct addressing) (direct/indirect addressing) sfr scratchpad ram (indirect addressing) scratchpad ram (movx @ri) figure1. addres space
W78E354 publication release date: april 1997 - 13 - revision a1 a.2 the modified 80c31 sfrs 1. timer/counter control register: tcon bit name function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when the processor vectors to the interrupt routine. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn the timer/counter on or off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when the processor vectors to the interrupt routine. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn the timer/counter on or off. tcon.3 - (reserved, not used by users.) tcon.2 - (reserved) tcon.1 ie0 interrupt 0 edge flag. set by hardware when an external interrupt edge is detected. cleared when the interrupt is processed. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupt. 2. power control register: pcon bit name function 7 smod double baud rate bit. 6 - (reserved) 5 - (reserved, not used by users.) 4 - (reserved for testing, not used by users. normally 0. if set, p2.4 - p2.7 will output sdac8-11 after reset (not power- on reset).) 3 gf1 general-purpose flag bit. 2 gf0 general-purpose flag bit. 1 pd power-down mode bit. 0 idl idle mode bit.
W78E354 - 14 - 3. interrupt enable register: ie bit name function ie.7 ea if ea = 0, no interrupt will be acknowledged (disable all interrupts). if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ie.6 - (reserved) ie.5 *1 set/clear to enable/disable the ddc port's i 2 c interrupt. ie.4 es set/clear to enable/disable the serial port 0 interrupt. ie.3 et1 set/clear to enable/disable the timer 1 overflow interrupt. ie.2 *1 set/clear to enable/disable the *2 interrupt. ie.1 et0 set/clear to enable/disable the timer 0 overflow interrupt. ie.0 ex0 set/clear to enable/disable the external interrupt 0. notes: *1: no name for assembler, must be used via "ie.x". *2 = (dsclint + adcint + timeout + soaint + vevent + paraint + ddc1int). 4. interrupt priority register: ip bit name function ip.7 - (reserved) ip.6 - (reserved) ip.5 *1 define the ddc port's i 2 c interrupt priority level. if ip.5 = 1, the priority level is higher. ip.4 ps define the serial port interrupt priority level. if ps = 1, the priority level is higher. ip.3 pt1 define the timer 1 interrupt priority level. if pt1 = 1, the priority level is higher. ip.2 *1 define the *2 priority level. if ip.2 = 1, the priority level is higher. ip.1 pt0 define the timer 0 interrupt priority level. if pt0 = 1, the priority level is higher. ip.0 px0 define the external interrupt 0 priority level. if px0 = 1, the priority level is higher. notes: *1: no name for assembler, must be used via "ip.x". *2 = (dsclint + adcint + timeout + soaint + vevent + paraint + ddc1int).
W78E354 publication release date: april 1997 - 15 - revision a1 a.3 new register description in addition to the 80c31 standard sfrs, the W78E354 has some newly added special function registers in the sfr address space as listed in table 2. table 2. newly added special function registers (sfrs) register address length r/w type reset content register address length r/w type reset content 1 contreg1 80h 8 r/w 00h 31 vfcountl b6h 8 r 00h 2 contreg2 85h 8 w 00h 32 vfcounth b7h 8 r 00h 3 contreg3 86h 8 w 00h 33 dhreg 92h 4 w 00h 4 contreg4 c8h 8 r/w 00h 34 dvreg 93h 8 w 00h 5 contreg5 84h 8 r/w 00h 35 paral 8eh 8 w 00h 6 sdac0 a1h 8 w 00h 36 parah 8fh 8 w 00h 7 sdac1 a2h 8 w 00h 37 autoload 91h 8 w 00h 8 sdac2 a3h 8 w 00h 38 wdtclr 9ch - w - 9 sdac3 a4h 8 w 00h 39 soareg bch 8 w 00h 10 sdac4 a5h 8 w 00h 40 soaclr bdh - w - 11 sdac5 a6h 8 w 00h 41 intmsk 95h 8 w 00h 12 sdac6 a7h 8 w 00h 42 intvect b2h 8 r/w 00h 13 sdac7 a9h 8 w 00h 43 status b3h 4 r 00h 14 sdac8 aah 8 w 00h 44 adc b1h 8 r 80h 15 sdac9 abh 8 w 00h 45 port4 bbh 7 w 00h 16 sdac10 ach 8 w 00h 46 ddc1 94h 8 w 00h 17 sdac11 adh 8 w 00h 47 s1con d8h 8 r/w 00h 18 sdac12 aeh 8 w 00h 48 s1sta d9h 8 r f8h 19 sdac13 afh 8 w 00h 49 s1dat dah 8 r/w 00h 20 bsdac0 9ah 8 w 00h 50 s1adr dbh 8 r/w 00h 21 sbrm0 b9h 4 w 00h 22 bsdac1 9bh 8 w 00h 23 sbrm1 bah 4 w 00h 24 ddac0 9dh 8 w 00h 25 ddac1 9eh 8 w 00h 26 ddac2 9fh 8 w 00h 27 bddac 96h 8 w 00h 28 dbrm 97h 4 w 00h 29 hfcountl b4h 8 r 00h 30 hfcounth b5h 8 r 00h note: '-' means the sfr has no real hardware but an address.
W78E354 - 16 - * contreg1 : control register1, bit-addressable. bit name function note 0 adcs0 adc channel select bit 0 see section e.10. 1 adcs1 adc channel select bit 1 see section e.10. 2 enddc1 enable ddc1 see below. 3 hces h-clamp edge select see section e.12.f. 4 hcws0 h-clamp width select bit 0 see section e.12.f. 5 hcws1 h-clamp width select bit 1 see section e.12.f. 6 dummyen dummy signal enable see section e.12. 'sync processor block diagram' & e.12.e. 7 adcstrt start adc conversion 0: stop, 1: start see section e.10. ddc1 enddc1 ddc port p1.2/dscl p1.3/dsda i c 2 support ddc2b/2b+ support ddc1 in in out out out scl sda sda scl 0 1 from vsync
W78E354 publication release date: april 1997 - 17 - revision a1 * contreg2 : control register2. bit name function note 0 envs enable vsync separator see section e.12. 'sync processor block diagram' & e.12.e. 1 hsps hsync polarity select 0: positive, 1: negative see section e.12. 'sync processor block diagram'. 2 vsps vsync polarity select 0: positive, 1: negative see section e.12. 'sync processor block diagram'. 3 oscsel osc or osc/2 select see below. 4 eintes external int edge select 0: high-level/rising-edge triggered 1: low-level/falling-edge triggered see below. 5 enm0 enable sdac0 moire cancel function 0: disable, 1:enable 6 enm1 enable sdac1 moire cancel function 0: disable, 1:enable 7 vdishc vsync disable h-clamp pulse 0: enable, 1:disable see section e.12. 'sync processor block diagram'. oscout oscin 0 1 oscsel divided by 2 to sync processor to cpu core 0 1 eintes ie0 it0 0 1 int0 (p3.2)
W78E354 - 18 - * contreg3 : control register3. bit name function note 0 p4sf port 4 special function 1 tstmod1 function test mode1 2 tstmod2 function test mode2 3 tstmod3 function test mode3 4 tvsep test vsep signal 5 - (reserved for internal use.) 6 - (reserved for internal use.) 7 - (reserved for internal use.) *contreg4 : control register4, bit-addressable. bit name function note 0 p24sf port 2.4 special function* (sdac10) see below. 1 p25sf port 2.5 special function* (sdac11) see below. 2 p26sf port 2.6 special function* (sdac12) see below. 3 p27sf port 2.7 special function* (sdac13) see below. 4 p14sf port 1.4 special function* see below. 5 p15sf port 1.5 special function* see below. 6 p23sf port 2.3 special function* see below. 7 invstp invert self-test pattern *note:in addition to setting pxysf, the port latch pxy must have been cleared previously to enable the pxy output special functions. 0 1 p14sf p1.4/hclamp p1.4 latch h-clamp pulse 0 1 p15sf p1.5/soa p1.5 latch soa output
W78E354 publication release date: april 1997 - 19 - revision a1 0 1 p2msf p2.m/sdacn p2.m latch sdacn 4 10 5 11 6 12 7 13 0 1 p23sf p2.3/stp p2.3 latch stp output m n *contreg5 : control register5. bit name function note 0 1 2 3 4 5 hdsel hclamp source select 6 dparaint enable parabola with dummy sync. 7 * status : status register. bit name function 0 hp hsync polarity. 0: positive, 1: negative. 1 vp vsync polarity. 0: positive, 1: negative. 2 noh set by hardware if no hsync. 3 nov set by hardware if no vsync.
W78E354 - 20 - * intmsk : interrupt mask register. bit name function 0 dsclintmsk set/clear to enable/disable dsclint interrupt. 1 adcintmsk set/clear to enable/disable adcint interrupt. 2 timeoutmsk set/clear to enable/disable timeout interrupt. 3 soaintmsk set/clear to enable/disable soaint interrupt. 4 veventmsk set/clear to enable/disable vevent interrupt. 5 paraintmsk set/clear to enable/disable paraint interrupt. 6 ddc1intmsk set/clear to enable/disable ddc1int interrupt. 7 note: a '1' in any bit of the intmsk register enables the corresponding interrupt flag in intvect to be set by hardware when the interru pt source generates an interrupt. * intvect : interrupt vector register. bit name function note 0 dsclint set by hardware when dscl is toggled from high to low and kept low for at least 12/fosc sec. see section e.6 . 1 adcint set by hardware when adc conversion is completed. see section e.10 . 2 timeout set by hardware when autoload timer timeout. see section e.8 . 3 soaint set by hardware when soa is high. see section e.12.g . 4 vevent set by hardware when vsync or vertical frequency counter timeout. vsep vevent nov 5 paraint for parabola interrupt generator (set by hardware). see section e.9 . 6 ddc1int for ddc1 of ddc port (set by hardware). see section e.6 . 7 note: to clear the interrupt flag, write a '1' (not '0') to the corresponding bit in intvect register. * paral : parabola interrupt generator register, low byte. * parah : parabola interrupt generator register, high byte. * autoload : 8-bit auto-reload timer register. (see section h .) * dhreg : dummy hsync frequency generator register. (see section l.e .) * dvreg : dummy vsync frequency generator register. (see section l.e .) * ddc1 : ddc port's ddc1 data buffer. * ddac0 - ddac2 : 8-bit pwm dynamic dac register. (see section k .) * bddac (8 bits)+ dbrm (4 bits): 12-bit pwm/brm dynamic dac register. (see section k .) * sdac0 - sdac13 : 8 bits, 8-bit pwm static dac register. (see section k .) * bsdac0 (8 bits)+ sbrm0 (4 bits): 12-bit pwm/brm static dac register. (see section k .)
W78E354 publication release date: april 1997 - 21 - revision a1 * bsdac1 (8 bits)+ sbrm1 (4 bits): 12-bit pwm/brm static dac register. (see section k .) * wdtclr : watchdog-timer-clear register, no specific hardware but an address. writing any value to wdtclr will clear the watchdog timer. * adc : result of the a-to-d conversion. * hfcountl : horizontal frequency counter register, low byte. (see section l.d .) * hfcounth : horizontal frequency counter register, high byte. (see section l.d .) * vfcountl : vertical frequency counter register, low byte. (see section l.d .) * vfcounth : vertical frequency counter register, high byte. (see section l.d .) * port4 : latch outputs (output only). * soareg : safe-operation-area register. (see section l.g .) * soaclr : safe-operation-area clear register, no specific hardware but an address. writing anyvalue to soaclr will clear the soa output (p1.5). * s1con : serial port 1 control register. * s1sta : serial port 1 status register. * s1dat : serial port 1 data register. * s1adr : serial port 1 address register. b. 16k bytes flash memory programming the flash memory will be described in section f. c. 256 bytes of on-chip data memory this data memory is mapped to external locations 00h to ffh and can only be accessed by the "movx @ri" instruction. since no external data can be accessed by this chip, there is no need for the external memory read/write control signals ( rd , wr ) as the "movx @ri" instruction can only be executed internally. d. spi (synchronous peripheral interface) and rs232 port: serial port 0 p3.0(rxd) and p3.1(txd) can be used as a spi port (serial port mode 0 of standard 80c51) or a rs232 port (mode 1, 2 or 3). the spi port can be used to communicate to osd chip, dac ... an rs232 port can be used to talk to auto-alignment system, by using an 18.432 mhz crystal, aximun baud rate is 19200 bps. e. ddc port (support ddc1/2b/2b+, with two slave address registers) one ddc1 port to support ddc1 one i2c port support ddc2b/2b+: serial port 1 an interrupt is generated when dscl has a transition from high to low and then remains low for 12 clock periods.
W78E354 - 22 - 16 mhz 18.432 mhz 20 mhz 24 mhz dscl low 750 ns 651 ns 600 ns 499 ns f. i 2 c port: serial port 2 (s/w emulation). g. interrupts the W78E354 has 6 interrupt sources. five of them, with the exception of int1 (at vector address 0013h) are identical to those of the 8051 series. the remaining one (at vector address 002bh) is a new addition. all the interrupt sources and the corresponding interrupt vector addresses for the W78E354 are given in the following table: source vector ddress description priority within a level 1 ie0 0003h same as the 8051. highest 2 tf0 000bh same as the 8051. 3 *1 0013h replaces int1 of the 8051. 4 tf1 001bh same as the 8051. 5 ri+ti 0023h same as the 8051. 6 *2 002bh new addition. (like tf2 + exf2 in the 8052) lowest notes: *1 = dsclint + adcint + timeout + soaint + vevent + paraint + ddc1int. *2 is the interrupt generated by the i 2 c in the ddc port. the interrupt at vector address 0013h is driven by another seven different sources. these are 1) a high-to-low transition of the dscl-pin, 2) the a/d converter, 3) the auto-reload timer, 4) the soa output, 5) vsync, 6) the parabola interrupt generator, and 7) ddc1 in the ddc port. the programmer must read the intvect register to identify the interrupt request source. these seven sources can be masked individually by setting the corresponding bit within the intmsk register (bit0..6). the newly added interrupt at vector address 002bh is driven by the i2c circuit in the ddc port. the interrupt enable control bits for the two interrupts at 0013h and 002bh are the bits ie.2 and ie.5 in the ie register, respectively. they can be disabled by clearing ie.7 (disable all interrupts). the interrupt priority control bits are ip.2 and ip.5 in the ip register, respectively. the following diagram illustrates the above description.
W78E354 publication release date: april 1997 - 23 - revision a1 i c in ddc port 2 or timeout source dsclint source adcint source paraint source vevent source ddc1int source ie0 tf0 tf1 ri+ti intmsk ie 0013h 001bh 0023h 002bh 000bh 0003h ie.3 ie.4 ie.5 ie.2 ie.1 ie.0 ie.7 ip ip.0 ip.1 ip.2 ip.3 ip.4 ip.5 vector address high priority low priority interrupt polling sequence soaint source timeout dsclint adcint paraint vevent ddc1int soaint intvect bit 0 bit 1 bit 2 bit 4 bit 3 bit 6 bit 5 h. 8-bit auto-reload timer for software time base this is an 8-bit auto-reload timer, which generates a periodic interrupt to the cpu. the time interval is programmable: the minimun interval (unit) = 1/ (f clock ? 1024), the programmable interval = the minimun interval (autoload reg. value +1), the maximum interval = the minimun interval 255. 16 mh z 18.432 mh z 20 mh z 24 mh z minimum interval 64 m s 55 m s 51.2 m s 42.6 m s maximum interval 16.3 ms 14.2 ms 13.1 ms 10.9 ms i. parabola interrupt generator this is an 16-bit auto-reload timer, which generates a periodic interrupt to the cpu. the interrupt period is programmable: the time base = 1/fclock, the programmable interrupt period = the time base ([parah, paral] 16-bit reg. value+1), the maximum period = the time base 65535. j. 6-bit adc one 6-bit analog-to-digital converter. spec.: 1 lsb
W78E354 - 24 - conversion time: <150 12/fosc sec. 4 channels selected by an analog multiplexer (adcs1, adcs0) (0, 0) (0, 1) (1, 0) (1, 1) selected channel adc0 adc1 adc2 adc3 set bits adcs1 and adcs2 in contreg1 to select one of the four analog input channels. the adc conversion is started by setting bit adcstrt in contreg1 using software. when the conversion is comple, the adcstrt bit is cleared by hardware to stop the adc operation. the adcint bit in intvect is set by hardware at the same time. k. pwm dacs there are two/fourteen 12/8-bit pwm sdacs and one/three 12/8-bit pwm ddacs in this chip. all the dac output buffers have slew rate control to prevent the slew rate from being too large. additionally, their outputs are delay-controlled and divided into three groups with different delay times as follows: 1. delay about 5ns: bsdac1, sdac2, 5, 8, 11, ddac1. 2. delay about 10ns: sdac0, 3, 6, 9, 12, ddac2. 3. no delay: for the others. functional descriptions: a. 14 channels of 8-bit static dac the static dacs are used to generate dc voltages (0 - 5v). there are 14 registers each corresponding to one 8-bit pwm 14 channel outputs. unused pwm channels can be used as a standard output pin, as these pins can supply 0v or 5v. the duty cycle of the pwm output = register value ? 255 the dc voltage after the low pass filter = v cc duty cycle reg. value duty cycle dc voltage 0 0/255 0v 1 1/255 1/255 5v n n/255 n/255 5v 255 255/255 +5v the pwm frequency fpwm = fclock ? 255 16 mhz 18.432 mhz 20 mhz 24 mhz f pwm 62.745 khz 72.282 khz 78.431 khz 94.117 khz t pwm 15.94 m s 13.83 m s 12.75 m s 10.62 m s
W78E354 publication release date: april 1997 - 25 - revision a1 sdac application circuit: 8/12bit resolution sdac low pass filter output r c d1616 t = rc voutput = v cc n/255, if t >> t pwm b. 2 channels of 12-bit static dac the two channel, 12-bit pwm outputs are composed of an 8-bit pwm and a 4-bit brm (bit rate multiplier). the 4-bit brm reg. value decides which one is to be added one clock preiod in every 16 pwm outputs. brm reg. 4-bit data one clock period is incremented in the n-th output in every 16 pwm outputs. 0000 none 0001 n = 8 0010 n = 4, 12 0100 n = 2, 6, 10, 14 1000 n = 1, 3, 5, 7, 9, 11, 13, 15 note: see the positions marked with an "*" in the following figure. brm brm cycle reg. value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0001 - - - - - - - - * - - - - - - - 0010 - - - - * - - - - - - - * - - - 0100 - - * - - - * - - - * - - - * - 1000 - * - * - * - * - * - * - * - * example: 0000 - - - - - - - - - - - - - - - - 0011 - - - - * - - - * - - - * - - - 1111 - * * * * * * * * * * * * * * * the 12-bit pwm frequency is the same as that of the 8-bit pwm output.
W78E354 - 26 - c. 1 channel of 12-bit & 3 channels of 8-bit dynamic dac the dynamic dacs are used to generate a parabola waveform for geometric compensation. ddac application circuit: d 1 6 1 6 2.5v balanced/unbalanced parabola 8/12 bit resolution ddac geometry compensation parabola waveform: ddac0 can be used to compensate h size distortion: 1. pincushion correction (amplitude) (pcc amplitude) 2. trapezoid (keystone) 3. cbow (s-comp) 25% 25% 4. pincushion correction (corner) (pcc corner) the pcc amplitude can be compensated against v size adjustment automatically. the trapezoid can be compensated against v center adjustment automatically. ddac1 is used to compensate h center distortion: 1. pin balance (bow) 2. key balance (tilt) note: the unused dynamic dacs can be used as static dacs.
W78E354 publication release date: april 1997 - 27 - revision a1 l. sync processor sync processor block diagram h v digital filter envs ad[7:0 ] h-clamp generator soa generator vsps hsps dummyen 1 0 0 0 0 0 1 1 1 1 vdishc h/v dummy sync generator hdummy vdummy vsep vrest hrest h soa h-clamp v h/v frequency counter vsync separator polarity detect & restoration in in out out a. h/v sync digital filter both hsync and vsync inputs have an internal digital filter to improve noise immunity. any pulse that is shorter than an internal clock period will be regarded as a glitch and will be ignored. ex: tclock = 62 ns @16 mhz, any sync with pulse width less than 62 ns will be regarded as a glitch. b. polarity detector the h/v polarity is detected automatically and can be read from the status register, the h/v input signals are then polarity restored (become hrest/vrest) for internal processing and output to h out /v out to drive the deflection circuit. the maximun sync width to h in pin is: (1/fclock ) 16384 the maximun sync width to v in pin is: (1/fclock ) 16384 f clock 16 mh z 18.432 mh z 20 mh z 24 mh z max. sync width for h in 1024 m s 888 m s 819 m s 681 m s max. sync width for v in 1024 m s 888 m s 819 m s 681 m s
W78E354 - 28 - c. sync separator h v v h to deflection circuit vsync hsync/ composite sync out out in in h v h (h+v) v v v tdelay wvmin vsync separator output (vout = vsep when dummyen = 0, envs = 1): in in out in in out the vsync is separated from the composite sync automatically, without any software effort. the limitation for the vsync signal is: the v in pulse width must be larger than wvmin = (1/fclock) 128.5, +/- 1/fclock ? 2 v out is also delayed from the v in signal by tdelay = (1/fclock) 128.5, +/- 1/fclock ? 2 (if envs bit is set to 1) f clock 16 mh z 18.432 mh z 20 mh z 24 mh z 1/f clock 62.5 ns 54 ns 50 ns 41 ns min. vsync width (wvmin) 8031 +/- 31 ns 6939 +/- 27 ns 6425 +/- 25 ns 5268 +/- 20 ns v out delay from v in (tdelay) 8031 +/- 31 ns 6939 +/- 27 ns 6425 +/- 25 ns 5268 +/- 20 ns d. horizontal & vertical frequency counter there are two 16-bit counters which can count h and v frequency automatically. when a vevent (v frequency counter timeout) interrupt occurs, the mcu may read the count value (hcount and vcount) from the counter registers (hfcounth, hfcountl, vfcounth and vfcountl) to calculate the h and v frequency by the formulas listed below.
W78E354 publication release date: april 1997 - 29 - revision a1 v frequency: the resolution of v frequency counter: vresol = (1/fclock ) 16. the v frequency: vfreq = 1/(vcount vresol ). the lowest v frequency can be detected: fclock ? 1048576. h frequency: the resolution of h frequency counter: hresol = (1/fclock ) ? 8. the h frequency: hfreq = 1/(hcount hresol ). the lowest h frequency can be detected: fclock ? 8192. 16 mhz 18.432 mhz 20 mhz 24 mhz vresol 1 m s 868 ns 800 ns 666 ns the lowest vfreq 15 hz 17.6 hz 19 hz 23 hz hresol 7.8 ns 6.8 ns 6.3 ns 5.2 ns the lowest hfreq 1.9 khz 2.3 khz 2.4 khz 2.9 khz e. dummy frequency generator the dummy h and v frequencies are generated for 1) factory burn-in and 2) displaying warning messages if there is no input frequency. there are two registers in the dummy sync generator: dhreg: 4-bit register, determines the dummy hsync output frequency dvreg: 8-bit register, determines the dummy vsync output frequency dummy hsync frequency f dh = fclock ? 32 ? (dhreg+1) dummy vsync frequency f dv = f dh ? 8 ? (dvreg+1) dummyen h out v out 0 hrest vrest (if envs = 0), vsep (if envs = 1) 1 hdummy vdummy ex. if system clock = 16 mhz dhreg f dh dvreg f dv 15 31.25k 48 79.7 hz 12 38.5k 59 80.2 hz 10 45.5k 70 80.1 hz 9 50k 77 80.1 hz 7 62.5k 96 80.5 hz 6 71k 109 80.7 hz 5 82k 127 80.1 hz 4 100k 155 80.1 hz
W78E354 - 30 - f. h-clamp pulse generator if p14sf = 0, p1.4 is a general purpose i/o port. if p14sf = 1, p1.4 is the h-clamp pulse output. 1. leading edge / trailing edge selectable hces = 0: select leading edge hces = 1: select trailing edge hrest leading edge trailing edge hsync 2. pulse width selectable h s y n c h - c l a m p o u p u t the pulse width is programmable: (1/fclock) option, +/- 1/fclock ? 2 (hcws1, hcws0) option 16 mhz 18.432 mhz 20 mhz 24 mhz (0, 0) 4.5 281 +/- 31 ns 244 +/- 27 ns 225 +/- 25 ns 187 +/- 20 ns (0, 1) 8.5 531 +/- 31 ns 461 +/- 27 ns 425 +/- 25 ns 353 +/- 20 ns (1, 0) 16.5 1031 +/- 31 ns 896 +/- 27 ns 825 +/- 25 ns 686 +/- 20 ns (1, 1) 32.5 2031 +/- 31 ns 1764 +/- 27 ns 1625 +/- 25 ns 1352 +/- 20 ns g. soa output if p15sf = 0, p1.5 is a general purpose i/o port. if p15sf = 1, p1.5 is the soa output.
W78E354 publication release date: april 1997 - 31 - revision a1 purpose: to protect the hot (horizontal oscillating transistor) and other critical circuitry by making a quick response when the hsync frequency drops below the preset boundary frequency. operation: when the hsync frequency is lower than the boundary frequency for three consecutive cycles or stopped for a certain period, the soa pin (p1.5) will change to a "high" state (for the extenal protection circuit to function). writing any value to the soaclr register will release the soa pin. to set the boundary frequency, one can write some formula:value to the soareg register according to the soareg value = 2m ? boundary frequency ex: if 50 khz is considered the boundary frequency, then soareg = 2m ? 50k = 40. no hsync response time = 2048 (1/f clock ). 16 mhz 18.432 mhz 20 mhz 24 mhz no h response time 128 m s 110 m s 102 m s 85 m s m. power supervisor, watchdog timer and reset circuitry the reset signals come from the following three sources: 1. external reset input (active low) 2. power low detect 3. hardware watchdog timer the power-low detection circuit generates a reset signal once the v cc voltage falls below 3.8v. this reset signal is released a short time after v cc has increased above 4.3v. this function can be enabled or disabled by a code option. the purpose of a watchdog timer is to reset the cpu if it enters erroneous processor states (possibly caused by electrical noise or rfi) within a reasonable period of time. the watchdog timer clock source comes from the internal system clock and can be enabled or disabled by a code option. when enabled, the watchdog circuitry will generate a system reset if the user program fails to reload the watchdog timer (by writing any value to the wdtclr register) within a specified length of time known as the "watchdog interval". the watchdog interval has four code options: 219/fosc, 221/fosc, 223/fosc and 224/fosc sec. the block diagram of the reset circuitry is shown as follows: watchdog timer power-low detect circuit enwdt_bit ensvs_bit en en external reset cpu por reset the other function blocks xreset reset all dacs
W78E354 - 32 - flash cell description a. flash rom interface the following diagram shows the flash cell block control interface. a<0:14> are the address bus inputs and dout<0:7> are the data bus outputs of the flash rom. flash rom (16kb) vpp vdd vss 0 1 s 0 1 s 0 1 s 0 1 s 0 1 s 0 1 s 0 1 s oscen (normally "0") /ce (pad) /ce /oe (pad) /oe a13ctrl (pad) a9ctrl (pad) a9hv a13hv a14ctrl (pad) a14hv a<0:14> (pad) select signal will be decided by /reset, /prog, a9ctrl, a13ctrl, a14ctrl and oectrl. din<0:7> a<0:14> dout<0:7> 8 mux d<0:7> (pad) 8 8 15 pc 15 15 * a14 = 0 at normal operation all the time. 8 8 option<0:7> rom-map<0:7> 8 8 oectrl (pad) oectrl 0 1 s flash rom block diagram
W78E354 publication release date: april 1997 - 33 - revision a1 v pp is the high voltage input while in flash mode. a<0:14> is the address bus of the flash cell while in flash mode. dout<0:7> is the data bus output of the flash cell and din<0:7> is the data bus input while the chip is in flash mode. the a9ctrl, a13ctrl, a14ctrl and oectrl signals are used to select the flash mode. the oe and ce signals are the control strobe signals for flash mode operation. these signals are operational only in flash mode and appear as inputs/outputs via the external pins with a "test name" as listed in the pin description in sec. d. during normal operation, the critical timing parameter is the flash data access time. when operating at 24 mhz, the flash cell requires 150 ns after an address out until the data is valid, as shown below. timing for flash rom data access 0000 0001 0002 rom address a<0:14> rom data dout<0:7> #aah sample clock max. 150 ns for 24 mhz b. option setting bits the option setting bits are used to set user-selectable options. these bits are programmed in the same way as the 16k byte flash rom except for the address a<14:0> which is 7fffh. msb lsb b4 b3 b2 b1 note: default value is 1 for each bit. b1: enwdt_bit. (1: disable, 0:enable) this bit is used to enable/disable the watchdog timer operation. (b3, b2): watchdog timer period set. these two bits are used to set the time period of the watchdog timer. (0, 0): 219/fosc sec. (0, 1): 221/fosc sec. (1, 0): 223/fosc sec. (1, 1): 224/fosc sec. where fosc is the crystal frequ ency. b4: ensvs_bit. (1: disable, 0:enable) this bit is used to enable/disable the power-low-detection function.
W78E354 - 34 - c. rom-map bits in order to increase the functionality of the 16k byte flash rom, the flash rom is divided into 4 blocks. if some blocks contain bad flash cells but the other blocks are good, the 16kb flash can be treated as either 8kb or 4kb, and the W78E354 downgraded to either the w78e352 or the w78e351. four rom-map bits are used to indicate the availability of the 16k bytes of flash rom after testing. msb lsb rom-map b3 b2 b1 b0 16k bytes flash rom set b0 = 1 if block 0 is available. block 0, 4k bytes set b1 = 1 if block 1 is available. block 1, 4k bytes set b2 = 1 if block 2 is available. block 2, 4k bytes set b3 = 1 if block 3 is available. block 3, 4k bytes note: only one/two/four of the four bits can be set to indicate whether 4k/8k/16k are usable. flash/test mode a. flash modes 1. read this mode is supported for customer code verification. the data will be invalid if the lock bit is set low. 2. output disable when the oe is set high, no data outputs appear on d7..d0. 3. standby this condition disables the dc path from the flash cell to reduce power consumption. 4. program this mode is used to program the flash cell and option bits. it is the only way to change data from "1" to "0". 5. program verify all the programming data must be checked after program or mass program operations. this operation should be performed after each byte is programmed to ensure a substantial program margin. 6. erase an erase operation is the only way to change data from "0" to "1". 7. erase verify after an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to 1 or not. the erase verify operation automatically ensures a substantial erase margin. this operation will be implemented after the erase operation if v pp = v ep (14.5v), ce is high and oe is low.
W78E354 publication release date: april 1997 - 35 - revision a1 8. proram/erase inhibit this operation allows parallel erasing or programming of multiple chips with different data. 9. mass program in order to increase the throughput of testing, this operation programs 256 bytes with the same data simultaneously. note that 256 program verify operations must follow each mass program operation. all the timings for this operation are the same as those of the byte program operation except that the /ce program pulse width is 125 m s. in addition, this operation is also used for cell reliability analysis by stressing the source line. 10. read company id and device id these two modes are especially useful in eprom writers, which can read the silicon identification to set the appropriate erase or program algorithm to match the device being erased or programmed. 11. vt this operation is used for cell performance analysis. by connecting 2v to the d7..d0 pins, the cell currents can be measured for each location within the chip by specifying its appropriate address. 12. read rom-map bits this operation is used to verify the rom-map bits which were programmed previously. its action is the same as an eeprom read operation. 13. fuse rom-map bits the rom-map bits can be fused by this operation only. its action is the same as an eeprom program operation. 14. erase rom-map bits the rom-map bits can be erased by this operation only. its action is the same as an eeprom erase operation. 15. ckbd & /ckbd mass program these two operations are used to mass program the flash cells in such a way that the state of any bit is different from those of its neighboring bits. 16. read disturb b. test mode *ram-test mode this mode is used to verify the function of the internal 512 bytes of ram by a write-in and then read- out operation. *functional test mode if the ea (testclk) pin is pulled low when the chip is being reset and remains low for at least 24 clock periods after the reset, the cpu will execute from the external program memory (maximum program size is 2k bytes). this feature may be used to test the chip's functions via an external program. it should be noted that this mode is like the normal operation except that the cpu executes from external program memory and that some different pins are used in place of a10 - a0, d7 - d0 and psen instead of their original functions.
W78E354 - 36 - flash/ram-test mode configuration table. configuration flash modes a9ctrl a13ctrl a14ctrl oectrl /ce /oe v pp a14..a0 d7..d0 read 0 0 0 0 0 0 1 address data out output disable 0 0 0 0 0 1 1 x high-z standby 0 0 0 0 1 x 1 x high-z program 0 0 0 0 0 1 v cp address data in program verify 0 0 0 0 1 0 v cp address data out erase [*3] 1 0 0 0 0 1 v ep a0 = 0, others: x data in (ffh) erase verify 1 0 0 0 1 0 v ep address data out program/erase inhibit 0 0 0 0 1 1 v cp /v ep x x mass program 0 0 1 0 0 1 v cp x data in read company id read device id 1 0 0 0 0 0 1 a0 = 0, others: x a0 = 1, others: x data out (dah) data out (64h) vt 0 0 0 1 0 1 1 address cell current read rom-map 0 1 0 0 0 0 1 7fffh data out fuse rom-map 0 1 0 0 0 1 v cp 7fffh data in erase rom-map 1 1 0 0 0 1 v ep x data in (ffh) ckbd & /ckbd mass program 1 0 1 0 0 1 v cp a6, a0 [*4] data in (00h) read disturb 1 1 1 0 0 0 1 address data out configuration ram-test modes a9ctrl a13ctrl a14ctrl oectrl /ce /oe v pp a14..a9 a8 a7..a0 d7..d0 8032's 256 bytes of ram-write 0 1 1 x 0 1 x x 0 address data in 8032's 256 bytes of ram-read 0 1 1 x 1 0 x x 0 address data out data memory by movx-write 0 1 1 x 0 1 x x 1 address data in data memory by movx-read 0 1 1 x 1 0 x x 1 address data out notes: 1: reset and prog must be kept low for all the above modes. 2: "x" means "don't care" but not floating. v cp = 12.5v, v ep = 14.5v, "1" stands for v dd and "0" for v ss . *3: the erase operation erases all the 16k bytes of flash cell but not the rom-map cell. *4: a0/a6 decides whether the bit-line/word-line is even or odd.
W78E354 publication release date: april 1997 - 37 - revision a1 for ckbd, (a6, a0) = (0, 0) and then (1, 1); for /ckbd, (a6, a0) = (1, 0) and then (0, 1). g.3 flash mode timing waveforms *read operation (including eeprom, company id, device id, option bits and rom-map bits read) parameter symbol min. typ. max. unit address access time t acc - - 150 ns chip enable access time t ce - - 150 ns output enable access time t oe - - 150 ns output data hold time t odh 0 - - ns output data float time t odf - - 100 ns read waveform (a14..a0) valid address v ih v il ce v ih v il v ih v il oe d7..d0 v ih v il data t ce t acc t odh/odf t oe note: please pay attention to the relation between /ce's and /oe's waveforms.
W78E354 - 38 - *erase operation (including eeprom&option bits and rom-map bits erase) parameter symbol min. typ. max. unit vpp setup time t vps 2.0 - - m s address setup time t as 2.0 - - m s address hold time t ah1 2.0 - - m s erase pulse width t epw - 1 5 ms output data valid after oe low t odv - - 150 ns address hold time t ah2 0 - - m s output data hold time t odh 0 - - ns output data float time t odf - - 100 ns erase waveform a14..a0 a0 = 0 v ih v il ce v ih v il v ih v il oe d7..d0 v ih v il vpp d out vep v ih erase erase verify address stable t as t vps t ah1 t odv t epw t ah2 t odh/odf t as
W78E354 publication release date: april 1997 - 39 - revision a1 *program & mass program operation (including eeprom, option bits and rom-map bits program, and mass program) parameter symbol min. typ. max. unit vpp setup time t vps 2.0 - - m s address setup time t as 2.0 - - m s input data setup time t ids 2.0 - - m s input data hold time t idh 2.0 - - m s program pulse width t ppw - 100 200 m s mass program pulse width t mppw - 500 1000 ms output data valid after oe low t odv - - 150 ns address hold time t ah 0 - - m s output data hold time t odh 0 - - ns output data float time t odf - - 100 ns program waveform a14..a0 v ih v il ce v ih v il v ih v il oe d7..d0 v ih v il vpp vcp v ih program program verify address stable t as t vps t idh t odv t ppw t odh/odf data in data out t ids t ah
W78E354 - 40 - d.1 smart erase algorithm start vpp = 14.5v enter erase mode n = 0 erase one 1 ms pulse increment n n = 10 ? erase verify (verify all bytes, must be ffh) vpp = 5.0v enter read mode read verify (blank check) no yes pass fail erase fail ! fail pass erase pass !
W78E354 publication release date: april 1997 - 41 - revision a1 d.2 smart program algorithm start vpp = 12.5v enter program mode n = 0 program one 100 us pulse increment n n = 10 ? program verify (verify one byte) last address ? vpp = 5.0v enter rdad mode read verify (verify all bytes) increment address address = first location no yes pass fail program fail ! fail pass yes no program pass !
W78E354 - 42 - absolute maximum ratings parameter symbol min. max. unit dc power supply v dd -0.3 +7.0 v input voltage v in v ss -0.3 v dd +0.3 v input current i i -100 +100 ma operating temperature t a 0 70 c storage temperature t st -55 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. electrical characteristics normal operation d.c. characteristics (v dd & v aa ) - v ss = 5v 10%, t a = 25 c, fosc = 20 mhz, unless otherwise specified. parameter sym. specification unit test conditions min. typ. max. operating voltage v dd 4.5 5 5.5 v operating current i dd - - 65 ma no load, v dd = 5.5v idle current i idle - - 30 ma no load, v dd = 5.5v power-down current i pd - - 10 m a no load, v dd = 5.5v inputs logic 0 input current p1, p2, p3 (except p1.0 - p1.3, p1.5) i in1 -75 - -10 m a v dd = 5.5v v in = 0v input current reset , testclk (*1) i in2 -250 - - m a v dd = 5.5v v in = 0v input current h in , v in (*2) i in3 - - +30 m a v dd = 5.5v v in = v dd input leakage current p1.0 - p1.3, adc0 - adc3 i lk -10 - +10 m a v dd = 5.5v 0v < v in < v dd logical 1-to-0 transition current p1, p2, p3 (*3) (except p1.0 - p1.3, p1.5) i tl -650 - - m a v dd = 5.5v v in = 2.0v
W78E354 publication release date: april 1997 - 43 - revision a1 normal operation d.c. characteristics, continued parameter sym. specification unit test conditions min. typ. max. input low voltage (*4) p1, p2, p3 (except p1.0 - p1.3, p1.5) reset v il1 0 - 0.8 v v dd = 4.5v input low voltage (*4) h in , v in v il2 0 - 0.8 v v dd = 4.5v input low voltage (*4) p1.0 - p1.3 v il3 0 - 1.5 v v dd = 4.5v input high voltage p1, p2, p3 (except p1.0 - p1.3, p1.5) v ih1 2.4 - v dd +0.2 v v dd = 5.5v input high voltage (*4) reset , oscin v ih2 3.5 - v dd +0.2 v v dd = 5.5v input high voltage (*4) h in , v in v ih3 2.4 - v dd +0.2 v v dd = 5.5v input high voltage (*4) p1.0 - p1.3 v ih4 3.0 - v dd +0.2 v v dd = 5.5v outputs output low voltage p1.0, p1.1 v ol1 - - 0.4 v v dd = 4.5v i ol = +2 ma output low voltage p1.2, p1.3 v ol2 - - 0.4 v v dd = 4.5v i ol = +6 ma output low voltage p1.4, p1.5, p2.2 - p2.7 sdac0 - 13, h out , v out v ol3 - - 0.45 v v dd = 4.5v i ol = +4 ma output low voltage p2.0, p2.1 v ol4 - - 0.5 v v dd = 4.5v i ol = +15 ma output low voltage p3, p4 v ol5 - - 0.45 v v dd = 4.5v i ol = +2 ma output low voltage bsdac0 - 1, ddac0 - 2, bddac v ol6 - - 0.45 v v dd = 4.5v i ol = +8 ma
W78E354 - 44 - normal operation d.c. characteristics, continued parameter sym. specification unit test conditions min. typ. max. output high voltage p1.4, p2, p3 v oh1 2.4 - - v v dd = 4.5v i ol = -100 m a output high voltage p4 v oh2 2.4 - - v v dd = 4.5v i oh = -2 ma output high voltage p1.5, sdac0 - 13, h out , v out s.f. of p1.4 and p2.3 - p2.7 (*5) v oh3 2.4 - - v v dd =4.5v i oh = -4 ma output high voltage bsdac0 - 1, ddac0 - 2, bddac v oh4 2.4 - - v v dd = 4.5v i oh = -8 ma notes: *1. reset and testclk have an internal pull-up resistor of about 30 k w . *2. h in and v in have an internal pull-down resistor of about 200 k w . *3. p1, p2 and p3 (except p1.0 - p1.3 and p1.5) can source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. *4. p1.0 - p1.3, reset , h in and v in are schmitt trigger inputs, and oscin is a cmos input. *5. while outputing a special function, the source current of p1.4 and p2.3 - p2.7 is -4 ma. flash operation d.c. characteristics (v dd & v aa ) - v ss = 5v 10%, t a = 25 c, fosc = 20 mhz, unless otherwise specified. parameter sym. specification unit test conditions min. typ. max. input current a0 - a14, d0 - d7, a9ctrl, a13ctrl, a14ctrl, oectrl, oe , ce i in -75 - +10 m a v dd = 5.5v v in = 0v or v dd v pp erase current (v pp = v ep ) i ep - - +200 m a v dd = 5.5v ce = v il , ce = v ih v pp program current (v pp = v cp ) i cp - - +200 m a v dd = 5.5v ce = v il , ce = v ih input low voltage a0 - a14, d0 - d7, a9ctrl, a13ctrl, a14ctrl, oectrl, oe , ce v il 0 - 0.8 v v dd = 4.5v
W78E354 publication release date: april 1997 - 45 - revision a1 flash operation d.c. characteristics, continued parameter sym. specification unit test conditions min. typ. max. input high voltage a0 - a14, d0 - d7, a9ctrl, a13ctrl, a14ctrl, oectrl, oe , ce v ih 2.4 - v dd +0.2 v v dd = 5.5v output low voltage d0 - d7 v ol - - 0.45 v v dd = 4.5v i ol = +2 ma output high voltage d0 - d7 v oh 2.4 - - v v dd = 4.5v i oh = -100 m a v pp erase voltage v ep 14.25 14.5 14.75 v v pp program voltage v cp 12.25 12.5 12.75 v typical application please note: while the chip is being powered on and the reset pin is low, if p1.5 and p3.2 are kept low at the same time, then the por (power-on reset) will last until p1.5 or p3.2 is pulled high, whichever occurs first. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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