View R5H30211_2116866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rej03b0259-0110 rev.1.10 jun. 05, 2009 page 1 of 17 R5H30211 renesas microcomputer rej03b0259-0110 rev.1.10 jun. 05, 2009 overview this lsi is a single-chip microcontroller unit (mcu) bu ilt around the h8/300h cpu. four i/o ports, rom, ram, eeprom, a random number generator (rng), a watchdog timer (wdt), a firewall management unit (fmu), interval timers (tmr1/tmr2), i 2 c bus interface (iic2), synchronous serial comm unication unit (ssu), and a coprocessor are included. operating at a maximum 10-mhz internal clock rate, the h8/300h cpu rapidly executes bit manipulation instructions, arithmetic and logic instructions, and data transfer instructions. the on-chip coprocessor executes modular multiplications (such as abr -1 modn + kn), which are used to calculate modular exponentiation x y modn, and des calculation pr ocessing at a high speed. table 1 lists the features of this lsi. table 1 features item specification cpu h8/300h cpu upper compatible with the h8/300 cpu in the object level sixteen 16-bit registers (sixteen 8-bit registers + eight 16-bit registers or eight 32-bit registers) ? high-speed operation ? maximum clock rate: internal clock 10 mhz ? add/subtract: 0.20 s (10 mhz) ? multiply/divide: 1.40 s (10 mhz) ? streamlined, concise instruction set ? 16-bit variable instruction length: 2 to 10 bytes ? arithmetic and logic operations between registers ? mov instruction for data transfer between registers and memory ? maximum 16-mbyte address space ? instruction set features ? 8-, 16-, or 32-bit transfer or arithmetic instructions ? unsigned or signed multiply instruction (8 bits 8 bits and 16 bits 16 bits) ? unsigned or signed divide instruction (16 bits 8 bits and 32 bits 16 bits) ? bit-accumulator instructions ? register-indirect specific ation of bit positions ? eeprom write instruction (eepmov.b instruction) ? high-speed block transfer instru ction (eepmov.w instruction) i/o ports ? four general-purpose input/output ports (also used for interrupts) note: when writing to the ddr7 to ddr4 bits, use the mov instructi on instead of the bit manipulation instruction.
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 2 of 17 item specification on-chip memory ? eeprom: 16 kbytes + 2 kbytes (64 bytes (256 + 32) pages) ? writing function by dedicated transfer instruction from cpu ? page write (1 byte to 64 bytes) and erase ? protected against accidental writing and erasing ? generates an ewe interrupt before an eepmov.b instruction is executed ? on-chip high voltage generation circuit for writing and erasing ? built-in oscillator and timer ? write/erase time (maximum value): 3 ms (rewrite), 1.5 ms (erase) ? rewrite endurance: 1 10 5 times (-20 c to +75 c) ? data retention time: 10 years ? rom: 112 kbytes ? ram: 4 kbytes random number generator (rng) ? generates 16-bit random numbers. ? interrupts can be generated on comple tion of random number generation. ? one of four random number g eneration times can be selected. watchdog timer (wdt) ? generates a udf interrupt co nstantly at any interval. ? stops the on-chip functions when the halt flag is set. ? one of four counter clo ck sources can be selected. firewall management unit (fmu) ? monitors memory access address of the user application. ? monitoring function of access between memory (monitors program execution on ram and eeprom) interval timer (tmr1/tmr2) ? generates an interval interrupt constantly at any interval. ? one of four counter clo ck sources can be selected. ? countable at a maximum of 4.5 seconds. modular multiplication coprocessor ? modular multiplication (abr -1 mod n + kn, etc.) ? modular exponentiation (x y mod n) with cpu control ? programmable data length: 160, 192, 256, 320, 384, 448, 512, 576, 640, 768, 896, or 1024 bits ? four operations: ? three types of modular multiplications: abr -1 mod n + kn, a 2 r -1 mod n + kn, and ar -1 mod n + kn ? one type of multiplication: a n (a is fixed to 32 bits, and the maximu m data length of operation results is 1024 bits) ? 512-byte special-purpose registers ? four 128-byte (1024-bit) registers (registers a, b, n, and w) ? can be used as ram for the cpu when coprocessor calculations are not being performed ? interrupt request to the cpu when the coprocessor completes calculation ? built-in multiplier allows up to 4 speed operation. interrupt ? four external interrupt pins: p1/ irq to p4/ irq ? used for interrupt input in sleep modes 1 and 2 ? same exception handling vector is assigned to the four pins ? internal interrupts (exc luding trapa instruction) ? ten interrupt sources: ewe, udf, rng, tmr1, tmr2, ii c2, ssu, modular multiplication coprocessor, voltage monitor circuit, and clock multiplier notes: 1. when using i/o ports and sleep mode 1 is entered, clear ddr to 0 to use the pins as i/o input port pins before execut ing the sleep instruction. 2. execute mov instruction instead of bit manipulation when writing to bits ddr7 to ddr4. 3. set the corresponding bit of ioirqs to 1 when using the external interrupt on returning from sleep modes 1 and 2.
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 3 of 17 item specification security ? high frequency detector ? high voltage detector ? high temperature detector ? low frequency detector ? low voltage detector ? low temperature detector ? illegal access detector ? illegal instruction detector ? ewe interrupt ? rng failure detector power-down states sleep modes 1 and 2 (sleep mode is entered by the sleep instruction) power-on reset circuit ? on-chip on-chip oscillator ? internal clock ? cpu: 6 mhz ( 20 %) ? modular multiplication coprocessor: 12 mhz ( 20 %) power ? single-voltage power supply 1.8 v to 3.6 v operating frequency range ? when the internal clock for the cpu is generated by dividing the external clock by 2 (cpucs1, cpucs0 = 00): f clk = 1 mhz to 8 mhz ? when the external clock is directly supplied as the internal clock for the cpu (cpucs1, cpucs0 = 01): f clk = 1 mhz to 8 mhz ? when the internal clock for the cpu is generated by multiplying the external clock by 1 by on-chip pll (cpucs1, cpucs0 = 10): f clk = 1 mhz to 8 mhz ? when the internal clock for the cpu is generated by multiplying the external clock by 2 by on-chip pll (cpucs1, cpucs0 = 11): f clk = 1 mhz to 5 mhz operating frequency of the modular multiplication coprocessor is as follows: ? when 4 speed calculation (ps1, ps0 = 10): f copro = 20 mhz at maximum ? when 2 speed calculation (ps1, ps0 = 01): f copro = 16 mhz at maximum ? when 1 speed calculation (ps1, ps0 = 00): f copro = 8 mhz at maximum (f clk : externally input clock frequency; f copro : operating frequency of the modular multiplication coprocessor) operating temperature ? ?20 to +75c other function ? cold/warm reset judgment function ? system clock multiplying function by pll circuit
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 4 of 17 block diagram figure 1 is a block diagram of this lsi. p2/sso/scl/ ir q p1/ssi/sda/ irq internal address bus res internal data bus vcc vss power-on reset circuit p4/ scs / irq p3/ssck/ irq interval timer 2 rom (112 kbytes) ram (4 kbytes) eeprom (16 kbytes + 2 kbytes) interval timer 1 h8/300h cpu i/o port rng wdt fmu voltagle monitoring circuit security logic system control register (512 bytes) modular multiplication coprocessor on-chip oscillator iic2 ssu clock divider/ multiplier clk figure 1 block diagram
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 5 of 17 pin assignment figure 2 shows the pin arrangement of this lsi. nc 20 19 18 (top view) 17 16 6 5 4 3 2 1 11 12 13 14 15 78910 p3/ssck/ irq p1/ssi/sda/ irq p2/sso/scl/ ir q v ss nc p4/ scs / irq clk res v cc nc nc nc nc nc nc nc nc nc nc figure 2 pin assignment
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 6 of 17 pin functions table 2 lists the pin functions of this lsi. table 2 pin functions type symbol i/o na me and description power supply v cc i power supply pin: 3.0 v to 3.6 v v ss i ground pin: 0 v clock clk i external clock input pin reset res * 1 i reset pin: low-level input resets the chip. scl i/o iic2 clock input/output pin i 2 c bus interface 2 (iic2) sda i/o iic2 data input/output pin ssi i/o ssu data input/output pin sso i/o ssu data input/output pin ssck i/o ssu clock input/output pin synchronous serial communication unit(ssu) scs i/o ssu chip select input/output pin external interrupt irq * 2 i interrupt pin: in sleep modes 1 and 2, this pin can be used as an interrupt input pin. p1 i/o i/o port pin: input or outpu t can be selected by software. p2 i/o i/o port pin: input or outpu t can be selected by software. p3 i/o i/o port pin: input or outpu t can be selected by software. port p4 i/o i/o port pin: input or outpu t can be selected by software. notes: 1. an input pull-up mos is connected to the res pin as shown in figure 3. input pull-up mos input buffer internal res signal v cc res pin figure 3 block diagram of the res pin 2. the p1/ irq to p4/ irq pins can be used as data i/o and interrupt input pins. input pull-up moss are c onnected to these pins.
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 7 of 17 electrical characteristics absolute maximum ratings table 3 absolute maximum ratings item symbol rating unit power supply voltage v cc ?0.3 to +7.0 v input voltage v in ?0.3 to v cc + 0.3 v operating temperature t opr ?20 to +75 c storage temperature t stg ?55 to +75 c note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the recommended operating conditions. exceeding these c onditions could affect the reliability of the chip.
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 8 of 17 dc characteristics table 4 dc characteristics conditions: v cc = 1.8 to 3.6 v, v ss = 0 v, t a = ?20 to +75c, unless otherwise specified. item symbol test conditions min. typ. max. unit v cc = 3.0 to 3.6 v v cc 0.7 ? v cc + 0.3 v input high voltage res , clk p1, p2, p3, p4 sda, scl, scs , ssck, ssi, sso v ih v cc = 1.8 to 3.0 v v cc 0.85 ? v cc + 0.3 v v cc = 3.0 to 3.6 v ?0.3 ? v cc 0.2 v input low voltage res , clk p1, p2, p3, p4 sda, scl, scs , ssck, ssi, sso v il v cc = 1.8 to 3.0 v ?0.3 ? 0.2 v output high voltage p1, p2, p3, p4 scs , ssck, ssi, sso v oh i oh = ?200 a v cc 0.7 ? v cc v output low voltage p1, p2, p3, p4 sda, scl, scs , ssck, ssi, sso v ol i ol = 1 ma 0 ? 0.4 v input leakage current p1, p2, p3, p4, clk |i in | v in = 0.5 to v cc ? 0.5 v ? ? 10 a res ? ? 150 input pull-up mos current * 1 p1, p2, p3, p4 ?i p v in = 0 v ? ? 150 a cpu half of the external clock/ external clock coprocessor stops * 3 ? ? 7.5 cpu multiplied by one with pll exclusive mode * 3 ? ? 7.5 supply current * 2 cpu multiplied by two with pll normal speed of coprocessor in maximum mode * 3 ? ? 10 ma i cc v in (i/o ports and res ) = v cc -0.5 v to v cc or i/o ports open * 1 t a 50c ? ? 100 supply current * 2 sleep mode 1 v in (i/o ports and res ) = v cc -0.5 v to v cc or i/o ports open * 1 t a > 50c ? ? 200 a pin capacitance cp v in = 0 v, f clk = 1 mhz, t a = 25c ? ? 15 pf notes: 1. the input pull-up mos's in the res is always turned on, even in sleep mode 1 and sleep mode 2. to avoid the input pull-up mos current, the res must be kept high during sleep mode 1 and sleep mode 2. 2. v ihmin = v cc ? 0.5 v, v ilmax = 0.5 v, and values are when all output pins are unloaded. 3. these are operating modes other than sleep mode 1. in this case, clk must be input according to the dc and ac characteristics.
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 9 of 17 ac characteristics table 5 ac characteristics conditions: v cc = 1.8 to 3.6 v, v ss = 0 v, t a = ?20 to +75c, unless otherwise specified. item symbol test conditions min. typ. max. unit clock cycle time (external clock) t cyc figure 4.1 see table 7 system clock ( * t cyc clock rise time t cr figure 4.1 ? ? 0.09 * t cyc i/o port input fall time t f figure 5 ? ? 1.0 s i/o port input rise time t r figure 5 ? ? 1.0 s cold reset t rwl1 figure 6 500 ? ? s res pulse width warm reset t rwl2 figure 6 400 ? ? t scyc power supply on time t on figure 6 0 ? ? ms power supply off time t off figure 6 0 ? ? ms rewrite ? ? 3 ms eeprom write time t epw erase ? ? 1.5 ms clock hold time t clkh figure 7 400 ? ? t cyc clock setup time t clks figure 7 20 ? ? t cyc sleep mode 2 4 ? ? t scyc interrupt pulse width ( irq ) other modes t irqw figure 7 400 ? ? ns notes: * set clk so as no noise is generated by the clock in put and the frequency of the clock signal increases or decreases monotonically.
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 10 of 17 table 6 clock cycle times conditions: v cc = 1.8 to 3.6 v, unless otherwise specified. item coprocessor operation min. typ. max. unit stopped or normal speed operation (vcc = 1.8 to 3.0v) 0.2 ? 1.0 s stopped or normal speed operation (vcc = 3.0 to 3.6v) 0.125 ? 1.0 s double speed operation (vcc = 1.8 to 3.0v) 0.2 ? 1.0 s double speed operation (vcc = 3.0 to 3.6v) 0.125 ? 1.0 s cpu is driven by an external clock divided by 2 quad speed operation 0.2 ? 1.0 s stopped or normal speed operation (vcc = 1.8 to 3.0v) 0.2 ? 1.0 s stopped or normal speed operation (vcc = 3.0 to 3.6v) 0.125 ? 1.0 s double speed operation (vcc = 1.8 to 3.0v) 0.2 ? 1.0 s double speed operation (vcc = 3.0 to 3.6v) 0.125 ? 1.0 s cpu is driven at the same clock rate as the external clock quad speed operation 0.2 ? 1.0 s stopped or normal speed operation (vcc = 1.8 to 3.0v) 0.2 ? 1.0 s stopped or normal speed operation (vcc = 3.0 to 3.6v) 0.125 ? 1.0 s double speed operation (vcc = 1.8 to 3.0v) 0.2 ? 1.0 s double speed operation (vcc = 3.0 to 3.6v) 0.125 ? 1.0 s cpu is driven by an external clock doubled by pll quad speed operation 0.2 ? 1.0 s stopped or normal speed operation 0.2 ? 1.0 s double speed operation 0.2 ? 1.0 s cpu is driven at the same clock rate as the external clock (doubled by pll and then divided by 2) quad speed operation 0.2 ? 1.0 s clk t ch t cr t cyc t cf t cl v ih v ih v il v il v il figure 4.1 clk input waveform rc t scyc t scyc same as on-chip oscillator clock half of on-chip oscillator clock figure 4.2 system clock timing (internal clock)
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 11 of 17 clk double of oscillator clock same as on-chip oscillator clock half of on-chip oscillator clock t scyc t scyc t scyc figure 4.3 system clo ck timing (external clock) i/o port (input) t f t r v ih v il v il v ih figure 5 i/o port input waveform v il v il t rwl2 t rwl1 v il t on 1.8 v t off 0.8v v il v ih v il t rwl2 v cc clk res note: at power-on and after power-off, vcc, clk, and res pins should be driven low (gnd level). figure 6 power on/off and res input timing t clkh v il t clks v il clk (in sleep mode 1) clk (in sleep mode 2) irq v ih program execution state sleep instruction irq t irqw power-down state exception handling state sleep mode 1 sleep mode 2 figure 7 interrupt timing in sleep mode 1 and sleep mode 2
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 12 of 17 reset circuit characteristics table 7 reset circuit characteristics conditions: v cc = 1.8 to 3.6 v, v ss = 0 v, t a = ?20 to +75c, unless otherwise specified. item symbol test conditions min. typ. max. unit power-on reset effective voltage v por1 figure 8 ? ? 0.1 v power-on reset release voltage rise time t pwon1 figure 8 t por1 1s * ? ? 0.5 ms power-on reset release voltage rise time t pwon1 figure 8 t por1 10s * ? ? 1 ms power-on reset release time t prst figure 8 ? ? 500 s note: * t por1 is the time needed to enable the power-on reset by keeping the external power supply vcc to lower than the effective voltage (v por1 ). v cc internal reset signal (active-low) v cc - min v por1 t pwon1 t por1 t prst figure 8 power-on reset timing voltage monitoring circuit table 8 voltage monitoring circuit characteristics conditions: v cc = 1.8 to 3.6 v, v ss = 0 v, t a = ?20 to +75c, unless otherwise specified. item symbol test conditions min. typ. max. unit voltage detect level v det0 figure 9 1.9 2.3 2.6 v v cc voltage monitoring circuit output v det0 - max. v det0 - min. v cc - min v ss figure 9 voltage monitoring circuit timing
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 13 of 17 communication interface timing timing of synchronous communication unit (ssu) table 9 timing of synchronous communication unit (ssu) conditions: v cc = 3.0 to 3.6 v, v ss = 0 v, t a = ?20 to +75c, c l = 30 pf * , unless otherwise specified. item symbol applicable pin min. typ. max. unit test conditions clock period t sucyc ssck 4 ? ? t scyc clock high-level pulse width t hi ssck 0.4 ? 0.6 t sucyc clock low-level pulse width t lo ssck 0.4 ? 0.6 t sucyc clock rise time master t rise ssck ? ? 1 t scyc slave ? ? 0.1 s clock fall time master t fall ssck ? ? 1 t scyc slave ? ? 0.1 s data input setup time t su sso, ssi 1 ? ? t scyc data input hold time t h sso, ssi 1 ? ? t scyc cs setup time slave t lead scs 4 ? ? t scyc cs hold time slave t lag scs 2 ? ? t scyc data output delay time t od sso, ssi ? ? 1 t scyc slave access time t sa ssi ? ? 2 t scyc slave out release time t or ssi ? ? 2 t scyc figures 10 to figure 14 note: * load capacitance of the measured pins. ssck sso (output) ssi (input) t su t h t od t sucyc t hi t lo v ih or v oh v ih or v oh figure 10 ssu i/o timing (clock synchronous mode)
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 14 of 17 ssck (output) cpos = 0 scs (output) ssck (output) cpos = 1 sso (output) ssi (input) t su t h t od t fall t rise t sucyc t lo t hi t hi t lo v ih or v oh v ih or v oh figure 11 ssu i/o timing (4-line bus communication mode, master, cphs = 1) ssck (output) cpos = 0 scs (output) ssck (output) cpos = 1 sso (output) ssi (input) t su t h t od t fall t rise t sucyc t lo t hi t hi t lo v ih or v oh v ih or v oh figure 12 ssu i/o timing (4-line bus communication mode, master, cphs = 0)
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 15 of 17 ssck (input) cpos = 0 scs (input) ssck (input) cpos = 1 sso (input) ssi (output) t lead t fall t rise t sucyc t lag t od t su t sa t lo t hi t hi t lo t or t h v ih or v oh v ih or v oh figure 13 ssu i/o timing (4-line bus communication mode, slave, cphs = 1) ssck (input) cpos = 0 scs (input) ssck (input) cpos = 1 sso (input) ssi (output) t lead t fall t rise t sucyc t lag t od t su t sa t lo t hi t hi t lo t od t h v ih or v oh v ih or v oh figure 14 ssu i/o timing (4-line bus communication mode, slave, cphs = 0)
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 16 of 17 timing of i 2 c bus interface 2 (iic2) table 10 timing of i 2 c bus interface 2 (iic2) conditions: v cc = 3.0 to 3.6 v, v ss = 0 v, t a = ?20 to +75c, unless otherwise specified. item symbol applicable pin min. typ. max. unit test conditions scl input cycle time t scl scl 12 t scyc + 600 ? ? ns scl input high-level pulse width t sclh scl 3 t scyc + 300 ? ? ns scl input low-level pulse width t scll scl 5 t scyc + 300 ? ? ns scl/sda input fall time t sf scl, sda ? ? 300 ns scl/sda input spike pulse removal time t sp scl, sda ? ? 1 t scyc sda input bus free time t buf sda 5 ? ? t scyc start condition input hold time t stah scl, sda 3 ? ? t scyc repeated start condition input setup time t stas scl, sda 3 ? ? t scyc stop condition input setup time t stos scl, sda 3 ? ? t scyc data input setup time t sdas sda 1 t scyc + 20 ? ? ns data input hold time t sdah sda 0 ? ? ns figures 15 scl note: * s, p, and sr denote the following. s: start condition p: stop condition sr: repeated start condition v ih v il t stah t buf p * s * t sf t scl t sdah t sclh t scll sda sr * t stas t sp t stos t sdas p * figure 15 i/o timing of i 2 c bus interface 2
R5H30211 rej03b0259-0110 rev.1.10 jun. 05, 2009 page 17 of 17 package dimensions * dimension including the plating thickness base material dimension package code jeita code jedec code mass pvqn0020kd-a unit:mm ? ? 0.04 g
revision history R5H30211 data sheet description rev. date page summary 1.00 2008.jul.29 ? first edition issued 1 a logo mark is added to the cover page. 5 figure 2 the pin number (pin 13) in the pin assignment figure was changed. 9 table 5 the minimum values of the items " res pulse width" and "interrupt pulse width ( irq )" were changed. "a system clock (f) cycle time (external clock)" ware added. part of the symbols and units were changed from t cyc to t scyc . reference figures were changed because figures 4.2 and 4.3 were added. 10 table 6 the item of "the cpu operates on the clock pulse obtained by multiplying the external clock frequency by two using the internal pll" was changed. 10 to 11 the figure number of figure 4 was changed to figure 4.1. figures 4.2 and 4.3 were added. 13 table 9 the item of "min, typ, and max" was changed. the unit of t cyc was changed to t scyc . 1.10 2009.jun.05 16 table 10 the item of "min, typ, and max" were changed. the unit of t cyc was changed to t scyc . all trademarks and registered trademarks ar e the property of their respective owners.
notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas product s for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of t he use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application ci rcuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attentio n to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the t otal system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding th e suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this do cument or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi gned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of h uman injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion co ntrol, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a r enesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to us e renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renes as semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 2009. renesas technology corp., all rights reserved. printed in japan. colophon .7.2

▲Up To Search▲

Price & Availability of R5H30211

	To Download R5H30211 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .