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pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use pm5350 155-ultra s/ uni- r s/uni-155-ultra saturn user network interface 155.52 & 51.84 mbit/s data sheet issue 5: june 1998
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use public revision history issue no date of issue details of change 5 june 1998 data sheet reformatted no change in technical content. generated r5 data sheet from pmc-969489, r7 4 november 1997 eng doc (7) revised. 3 dec 20, 1996 third revision 2 oct 15, 1996 second revision 1 sept 12, 1996 creation of document
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use i contents 1 features ...............................................................................................1 2 applications ........................................................................................ 4 3 references ......................................................................................... 5 4 application examples ...................................................................... 6 5 block diagram.................................................................................... 7 6 pin diagram ........................................................................................ 10 7 pin description ................................................................................ 11 7.1 utp-5 and pecl receiver .................................................... 27 7.2 clock recovery.................................................................... 27 7.3 serial to parallel converter......................................... 28 7.4 receive section overhead processor........................ 28 7.4.1 framer ........................................................................... 28 7.4.2 descramble ................................................................. 29 7.4.3 error monitor............................................................ 29 7.4.4 loss of signal ............................................................ 29 7.4.5 loss of frame ............................................................. 30 7.5 receive line overhead processor ...............................30 7.5.1 line remote defect indication detect .............. 30 7.5.2 line ais detect ............................................................ 30 7.5.3 error monitor............................................................ 30 7.6 receive path overhead processor ...............................31 7.6.1 pointer interpreter ................................................ 31
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use ii 7.6.2 error monitor............................................................ 32 7.7 receive atm cell processor ........................................... 32 7.7.1 cell delineation......................................................... 32 7.7.2 descrambler...............................................................33 7.7.3 cell filter and hcs verification.......................... 34 7.7.4 performance monitor............................................. 35 7.7.5 gfc extraction port................................................ 36 7.7.6 receive fifo ................................................................. 36 7.8 utp-5 and pecl transmitter ............................................. 37 7.9 clock synthesis ................................................................... 37 7.10 parallel to serial converter......................................... 37 7.11 transmit section overhead processor ..................... 37 7.11.1 line ais insert ............................................................. 37 7.11.2 bip-8 insert ................................................................... 37 7.11.3 framing and identity insert.................................. 38 7.11.4 scrambler.................................................................... 38 7.12 transmit line overhead processor ............................. 38 7.12.1 bip calculate...............................................................38 7.12.2 line remote defect indication insert................ 38 7.12.3 line febe insert.......................................................... 39 7.13 transmit path overhead processor ............................ 40 7.13.1 pointer generator ................................................... 40 7.13.2 bip-8 calculate ........................................................... 41
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use iii 7.13.3 febe calculate ........................................................... 41 7.13.4 spe multiplexer.......................................................... 41 7.14 transmit atm cell processor......................................... 42 7.14.1 idle/unassigned cell generator......................... 43 7.14.2 scrambler.................................................................... 43 7.14.3 hcs generator............................................................ 43 7.14.4 gfc insertion port ................................................... 43 7.14.5 transmit fifo...............................................................43 7.15 drop side interface ............................................................ 44 7.15.1 receive interface...................................................... 44 7.15.2 transmit interface ................................................... 45 7.16 parallel output port and led display controller45 7.17 microprocessor interface ............................................. 45 8 register memory map.................................................................... 46 8.1 test mode register memory map ................................. 131 8.2 test mode 0 details............................................................ 134 9 operation ......................................................................................... 136 9.1 overhead byte usage ....................................................... 136 9.2 cell data structure.......................................................... 139 9.3 parallel output port and led display controller operation .............................................................................. 141 9.3.1 direct control parallel output port ........... 141 9.3.2 alarm monitor .......................................................... 141 9.3.3 traffic monitor ....................................................... 141
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use iv 9.4 loopback operation.......................................................... 142 9.5 board design recommendations .................................. 146 9.6 power supplies sequencing .......................................... 147 9.7 selecting betwn twisted-pair and pecl interfaces ................................................................................................... 148 9.8 interfacing transmit and receive data lines with pecl devices......................................................................... 148 9.9 interfacing transmit and receive data lines with utp-5 cable............................................................................ 151 9.10 clocking options ...............................................................152 9.11 drop side receive interface.......................................... 154 9.12 drop side transmit interface ....................................... 156 10 absolute maximum ratings........................................................ 158 11 d.c. characteristics .................................................................... 159 12 external components ................................................................164 13 microprocessor interface timing characteristics ...... 167 14 s/uni-ultra timing characteristics........................................ 171 15 ordering and thermal information ...................................... 180 16 mechanical information............................................................. 181
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use v list of registers register 0x00: s/uni-ultra master reset and identity / load meters................................................................................................. 50 register 0x01: s/uni-ultra master configuration ........................ 52 register 0x02: s/uni-ultra master interrupt status.................... 54 register 0x03: s/uni-ultra master mode control......................... 56 register 0x04: s/uni-ultra master clock monitor ........................ 57 register 0x05: s/uni-ultra master control..................................... 59 register 0x06: s/uni-ultra clock synthesis control and status ................................................................................................................ 61 register 0x08: s/uni-ultra clock recovery control and status ................................................................................................................ 62 register 0x09: s/uni-ultra clock recovery configuration ...... 64 register 0x0a: s/uni-ultra line transmitter configuration 1.. 65 register 0x0b: s/uni-ultra line transmitter configuration 2.. 66 register 0x0c: s/uni-ultra line receiver configuration............ 67 register 0x10: rsop control/interrupt enable............................ 68 register 0x11: rsop status/interrupt status ................................. 70 register 0x12: rsop section bip-8 lsb ................................................ 72 register 0x13: rsop section bip-8 msb ............................................... 73 register 0x14: tsop control................................................................. 74 register 0x15: tsop diagnostic ............................................................ 75 register 0x18: rlop control/status................................................... 76 register 0x19: rlop interrupt enable/interrupt status ........... 77
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use vi register 0x1a: rlop line bip-8/24 lsb ................................................... 79 register 0x1b: rlop line bip-8/24........................................................... 80 register 0x1c: rlop line bip-8/24 msb.................................................. 81 register 0x1d: rlop line febe lsb ....................................................... 82 register 0x1e: rlop line febe ...............................................................83 register 0x1f: rlop line febe msb....................................................... 84 register 0x20: tlop control ................................................................. 85 register 0x21: tlop diagnostic ............................................................ 86 register 0x30: rpop status/control .................................................. 87 register 0x31: rpop interrupt status ............................................... 88 register 0x33: rpop interrupt enable .............................................. 89 register 0x37: rpop path signal label............................................... 91 register 0x38: rpop path bip-8 lsb ....................................................... 92 register 0x39: rpop path bip-8 msb ...................................................... 93 register 0x3a: rpop path febe lsb....................................................... 94 register 0x3b: rpop path febe msb...................................................... 95 register 0x3d: rpop path bip-8 configuration ................................ 96 register 0x40: tpop control/diagnostic.......................................... 97 register 0x41: tpop pointer control ................................................ 98 register 0x45: tpop arbitrary pointer lsb ................................... 100 register 0x46: tpop arbitrary pointer msb .................................. 101 register 0x48: tpop path signal label ............................................. 102 register 0x49: tpop path status.......................................................... 103
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use vii register 0x50: racp control/status ................................................ 104 register 0x51: racp interrupt enable/status .............................. 106 register 0x52: racp match header pattern ................................... 108 register 0x53: racp match header mask......................................... 109 register 0x54: racp correctable hcs error count.................. 110 register 0x55: racp uncorrectable hcs error count ............ 111 register 0x56: racp receive cell counter (lsb) ......................... 112 register 0x57: racp receive cell counter.................................... 113 register 0x58: racp receive cell counter (msb)......................... 114 register 0x59: racp configuration .................................................. 115 register 0x60: tacp control/status.................................................. 117 register 0x61: tacp idle/unassigned cell header pattern ...... 119 register 0x62: tacp idle/unassigned cell payload octet pattern.............................................................................................. 120 register 0x63: tacp fifo control....................................................... 121 register 0x64: tacp transmit cell counter (lsb) ........................ 123 register 0x65: tacp transmit cell counter .................................. 124 register 0x66: tacp transmit cell counter (msb) ....................... 125 register 0x67: tacp configuration.................................................... 126 register 0x68: s/uni-ultra popc control ....................................... 128 register 0x69: s/uni-ultra popc strobe rate 0 ............................. 130 register 0x6a: s/uni-ultra popc strobe rate 1............................. 131 register 0x80: master test .................................................................. 133
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use viii list of figures figure 1 - typical atm adapter utp-5 interface .............................. 6 figure 2 - sts-3c/stm-1jitter tolerance .......................................... 28 figure 3 - cell delineation state diagram....................................... 33 figure 4 - hcs verification state diagram ....................................... 35 figure 5 - sts-3c/stm-1 default transport overhead values .. 39 figure 6 - sts-1 default transport overhead values ................ 40 figure 7 - default path overhead values......................................... 42 figure 8 - sts-3c (stm-1) overhead.................................................... 136 figure 9 - sts-1 overhead .................................................................... 137 figure 10- data structure .................................................................... 140 figure 11- twisted-pair loopback operation ................................143 figure 12- line loopback operation ................................................. 144 figure 13- serial diagnostic loopback operation ..................... 145 figure 14- parallel diagnostic loopback operation ................ 146 figure 15- interfacing txd+/- to pecl ............................................... 149 figure 16- interfacing with rxd+/- using pecl (2 examples) .... 150 figure 17- interfacing txd+/- and rxd+/- with utp-5..................... 152 figure 18- conceptual clocking structure ................................ 153 figure 19- receive fifo empty option (rcalevel0=1) .................. 154 figure 20- receive fifo near empty option (rcalevel0=0) ....... 154 figure 21- receive gfc serial link .................................................... 155 figure 22- transmit fifo ........................................................................ 156
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use ix figure 23- transmit gfc serial link .................................................. 157 figure 24- microprocessor interface read timing.................... 168 figure 25- microprocessor interface write timing .................. 170 figure 26- receive frame pulse output timing ............................ 171 figure 27- line side transmit interface timing............................. 172 figure 28- drop side receive synchronous interface timing (tsen = 0) ..................................................................................................... 173 figure 29- drop side receive synchronous interface timing (tsen = 1) ..................................................................................................... 175 figure 30- gfc extract port timing .................................................. 176 figure 31- drop side transmit synchronous interface........... 177 figure 32- gfc insert port timing...................................................... 178 figure 33- theta ja vs. air flow........................................................... 180
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use x list of tables table 1 - microprocessor interface read access (figure 24) . ..................................................................................................... 167 table 2 - microprocessor interface write access (figure 25) ..................................................................................................... 169 table 3 - line side reference clock.............................................. 171 table 4 - line side receive interface (figure 26)....................... 171 table 5 - line side transmit interface (figure 27) .................... 172 table 6 - drop side receive synchronous interface (tsen = 0) (figure 28) ................................................................................................... 172 table 7 - drop side receive synchronous interface (tsen = 1) (figure 29) ................................................................................................... 174 table 8 - gfc extract port (figure 30).......................................... 176 table 9 - drop side transmit synchronous interface (figure 31) ..................................................................................................... 176 table 10 - gfc insert port (figure 32) ............................................. 178 table 11 - s/uni-ultra ordering information................................ 180 table 12 - s/uni-ultra thermal information .................................. 180
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 1 1 features single chip atm user-network interface operating at 155.52 and 51.84 mbit/s. provides an analog edge interface that can be selected to interface directly with category-5 unshielded twisted pair (utp-5) or shielded twisted pair cables, or to interface with pseudo-ecl (pecl) optical data links (odls), using a minimum of passive components. implements the atm forum user network interface specification and the atm physical layer for broadband isdn according to ccitt recommendation i.432. processes duplex 155.52 mbit/s sts-3c/stm-1 (direct interface to a twisted pair cable or pecl interface to a pmd device) or 51.84 mbit/s sts-1 (pecl interface to a pmd device only) data streams with on-chip clock and data recovery and clock synthesis. performs clock recovery and clock synthesis using on-chip loop filters. provides saturn compliant interface - physical layer (sci-phy?) fifo buffers in both transmit and receive paths with parity support. compatible with atm forum utopia level 1 specification. inserts and extracts the generic flow control (gfc) bits via a simple serial interface and provides a transmit xoff function to allow for local flow control. provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. low power, +5 volt, cmos technology. 128 pin high performance plastic quad flat pack (pqfp) 14 mm x 20 mm package. the receiver section: provides a serial interface at 155.52 or 51.84 mbit/s. adaptively equalizes the received differential signal.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 2 recovers the clock and data; frames to the recovered data stream; descrambles the received data; interprets the received payload pointer (h1, h2); and extracts the sts-3c or sts-1 synchronous payload envelope (vc4) and path overhead. extracts atm cells from the synchronous payload envelope using atm cell delineation and provides optional atm cell payload descrambling, header check sequence (hcs) error detection and error correction, and idle/unassigned cell filtering. provides a synchronous 8-bit wide, four cell fifo buffer. detects loss of signal (los), out of frame (oof), loss of frame (lof), line alarm indication signal (lais), line remote defect indication (rdi), loss of pointer (lop), path alarm indication signal (pais), loss of cell delineation and path remote defect indication (prdi). counts received section bip-8 (b1) errors, received line bip-8/24 (b2) errors, line far end block errors (line febe), received path bip-8 (b3) errors and path far end block errors (path febe). counts received hcs errored cells that are discarded, received hcs errored cells that are corrected and passed on, and the total received cells passed on. the transmitter section: provides a serial interface at 155.52 or 51.84 mbit/s. provides a serial interface at 155.52 or 51.84 mbit/s. generates data of the correct amplitude and shape to directly interface with a signal transformer and transmit over a utp-5 cable. provides a synchronous 8-bit wide, four cell fifo buffer. provides idle/unassigned cell insertion, hcs generation/insertion, and atm cell payload scrambling; inserts atm cells into the transmitted sts-3c (stm- 1) or sts-1 synchronous payload envelope using h4 framing generates the transmit payload pointer (h1, h2) and inserts the path overhead; scrambles the transmitted sts-3c (stm-1) or sts-1 stream and inserts framing bytes (a1, a2) and the identity byte (c1).
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 3 synthesizes the 155.52 mhz, 51.84 mhz transmit clock from a one-eighth frequency reference. inserts path alarm indication signal (pais), path remote defect indication (rdi), line alarm indication signal (lais) and line rdi. inserts path bip-8 codes (b3), path far end block error (path febe) indications, line bip-8/24 codes (b2), line far end block error (line febe) indications, section bip-8 codes (b1) to allow performance monitoring at the far end. allows forced insertion of all zeros data (after scrambling) or corruption of framing byte or section, line, or path bip-8 codes for diagnostic purposes.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 4 2 applications atm lans over twisted pair cables (utp-5) at155.52 mbit/s atm lans over optical fibers (using pecl odls) at either 155 mbit/s or 51.84 mbit/s workstations and personal computer nic cards lan switches and hubs sonet or sdh compliant atm user-network interfaces
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 5 3 references 1. ccitt recommendation g.709 - "synchronous multiplexing structure", 1990. 2. ccitt recommendation i.432, "b-isdn user network interface - physical interface specification", june 1990. 3. bell communications research - sonet transport systems: common generic criteria, gr-253-core, issue 1, december 1994. 4. atm forum - atm user-network interface specification,v3.1, september 1994 5. atm forum - atm physical medium dependent interface specification for 155 mbit/s over twister pair cable, v1.0, september 1994 6. t1.105, american national standard for telecommunications - digital hierarchy - optical interface rates and formats specifications (sonet), 1991. 7. telecommunications industry association (tia), commercial building telecommunications wiring standard, eia/tia-568.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 6 4 application examples the pm5350 s/uni-ultra is typically used to implement the core of an atm user network interface by which an atm terminal is linked to an atm switching system using sonet/sdh compatible transport. the s/uni-ultra finds application at either end of terminal to switch links or switch to switch links, typically in private network (lan) applications. in this application, the s/uni-ultra typically interfaces on its line side with line coupling transformers and baluns. the s/uni-ultra may be loop timed internally (the recovered clock is used in the transmit direction) or source timed (separate transmit and receive clocks). the drop side interfaces directly with atm adaptation layer or atm layer processors. the initial configuration and ongoing control and monitoring of the s/uni-ultra is provided via a generic microprocessor interface. the s/uni- ultra also supports a "hardware-only" operating mode where an external microprocessor is not required. this application is shown in figure 1. figure 1 - typical atm adapter utp-5 interface pm5350 s/uni-155-ultra sci-phy interface receive transmit 19.44 mhz oscillator rxd+ rxdC txd+ txdC refclk utp-5 facilit y rj-45 atm terminal rdat[7:0] rsoc rfclk rca rrdenb receive aal processor rxprty tfclk tdat[7:0] tsoc tca twrenb transmit aal processor txprty magnetics
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 7 5 block diagram tx atm cell fifo rx atm cell fifo txd+ rxd+ out[1:0] tdat[7:0] tca tsoc rdat[7:0] rsoc d[7:0] a[7:0] ale csb rdb wrb rstb intb microprocessor i/f tx framer & overhead processor rx framer & overhead processor twrenb tfclk tx atm cell processor rx atm cell processor rca rclk rfp rfclk rrdenb parallel to serial serial to parallel clk gen. sd clk/data rec. rxd- tclk tsen tgfc rcp tfp txd- tcp rgfc atp2 atp1 txprty rxprty xoff tvref rcap2 rcap1 twisted pair rx twisted pair tx refclk analo g ed g e trref peclsel led control tm description the pm5350 s/uni-ultra saturn user network interface is a monolithic integrated circuit that implements the sonet/sdh processing and atm mapping functions of a 155 mbit/s or 51mbit/s atm user network interface. it is fully compliant with both sonet and sdh requirements and atm forum uni specifications. the s/uni-ultra is capable of directly interfacing with utp-5 cable. at the receiver end, it performs adaptive equalization. it is fully compliant with the atm forum pmd interface specifications for 155 mb/s over twisted pair cable. the s/uni-ultra receives sonet/sdh frames via a bit serial interface, recovers clock and data, and processes section, line, and path overhead. it
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 8 performs framing (a1, a2), descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (b1, b2, b3), accumulating error counts at each level for performance monitoring purposes. line and path far end block error indications (m0 or m1, g1) are also accumulated. the s/uni-ultra interprets the received payload pointers (h1, h2) and extracts the synchronous payload envelope which carries the received atm cell payload. the s/uni-ultra frames to the atm payload using cell delineation. hcs error correction is provided. idle/unassigned cells may be dropped according to a programmable filter. cells are also dropped upon detection of an uncorrectable header check sequence error. the atm cell payloads are descrambled. generic flow control (gfc) bits from error free cells are extracted and presented on a serial link for external processing. legitimate atm cells are written to a four cell fifo buffer. these cells are read from the fifo using a synchronous 8 bit wide datapath interface with cell-based handshake. counts of received atm cell headers that are errored and uncorrectable, those that are errored and correctable and all passed cells are accumulated independently for performance monitoring purposes. the s/uni-ultra transmits sonet/sdh frames via a bit serial interface and formats section, line, and path overhead appropriately. it performs framing pattern insertion (a1, a2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (b1, b2, b3) as required to allow performance monitoring at the far end. line and path far end block error indications (m0 or m1, g1) are also inserted. the s/uni-ultra generates the payload pointer (h1, h2) and inserts the synchronous payload envelope which carries the atm cell payload. it supports the insertion of a variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics. atm cells are written to an internal programmable-length 4-cell fifo using a synchronous 8 bit wide datapath interface. idle/unassigned cells are automatically inserted when the internal fifo contains less than one cell or the xoff input is asserted. generic flow control (gfc) bits may be inserted downstream of the fifo via a serial link so that all fifo latency may be bypassed. a transmission off (xoff) input is provided to allow the suspension of active atm cell transmission independent of the fifo fill state. the s/uni-ultra generates the header check sequence and scrambles the payload of the atm cells. payload scrambling can be disabled.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 9 no line rate clocks are required directly by the s/uni-ultra as it synthesizes the transmit clock and recovers the receive clock using a 19.44 mhz reference clock. the s/uni-ultra provides output control signals that can be used to command an led display, making it easy to visually monitor either alarms, or the transmit and receive activity. the s/uni-ultra is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. it is implemented in low power, +5 volt cmos technology. it has ttl and pseudo-ecl (pecl) compatible inputs and outputs and is packaged in a 128 pin pqfp package.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 10 6 pin diagram the s/uni-ultra is packaged in an 128 pin pqfp package having a body size of 14 mm by 20 mm and a pin pitch of 0.50 mm. . pin 1 pin 128 pm5350 s/uni-ultra top view pin 38 pin 39 pin 64 pin 65 pin 102 pin 103 vss vss vss vss vss vss index pin qavd tavd1 tavs1 tavs2 refclk tavs3 tavd3 txd+ txd- tavd4 trref tavs4 ravd3 ravs3 rxd- rxd+ sd ravs3 rcap1 rcap2 ravs3 tavd3 tavs3 tavs4 tvref tavd2 ravd3 ravd1 ravs1 ravs2 ravd2 qavd qavs xoff tcp tgfc tfp tclk vddo2 vsso2 rclk rfp rgfc rcp vddi2 vssi2 vss vss rstb csb tsoc txprty tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] tca twrenb tfclk rsoc rxprty vddo5 vsso5 rdat[7] rdat[6] rdat[5] rdat[4] rdat[3] rdat[2] vddo4 vsso4 rdat[1] rdat[0] rca rrdenb rfclk tsen wrb rdb vssi4 vddi4 intb d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] ale vddo6 vsso6 atp2 atp1 qavs peclsel vddo3 vssi1 vddi1 vsso3 out[1] out[0] vddi3 vssi3 vssi5 vddi5 vddo1 vsso1 vssi6
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 11 7 pin description pin name type pin no. function peclsel ttl input 40 the pecl mode select (peclsel) is used to configure the analog edge pmd interface for either pecl or twisted-pair. a ttl low configures the interface for while a ttl high configures the interface for pecl, enabling direct interfacing with optical transceivers. refer to the operation section for a detailed description of twisted-pair mode and pecl mode configurations. different termination at txd+/- and rxd+/- are required depending on the selected mode. rxd+ rxd- diff. analog input 24 23 the differential receiver inputs (rxd+/-) nrz data, from the balun/transformer module interface to these pins when operating in twisted-pair mode (as configured via the peclsel pin tied low), or from an optical data link (odl) when in pecl mode (as configured via the peclsel pin tied high). rxd+/- are truly differential inputs offering superior common-mode noise rejection. refer to the applications section of this document for a description of the required termination network. refclk ttl input 2 the reference clock input (refclk) must provide a jitter-free 19.44 mhz reference clock. it is used as the reference clock by both clock recovery and clock synthesis circuits.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 12 pin name type pin no. function sd single- ended pecl input 29 the signal detect pin (sd) indicates the presence of valid receive signal power from the optical physical medium dependent device when operating in pecl mode (as configured via the peclsel pin tied high). a pecl high indicates the presence of valid data and a pecl low indicates a loss of signal. it is mandatory that sd be terminated into the equivalent network that rxd+/- is terminated into. when operated in twisted-pair mode (as configured via the peclsel pin tied low), sd has no function and should be connected to the analog ground common to ravs3. rclk output 55 the receive clock (rclk) output provides a timing reference for the s/uni-ultra receive outputs. rclk is a divide by eight of the recovered line rate clock. rgfc, rcp, rfp and out[1] (when configured for alarm monitoring) are updated on the rising edge of rclk.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 13 pin name type pin no. function out[1] out[0] output 41 42 the alarm/output port pins has three functions as selected by popc control register bits. when configured to output alarms, the out[1] output indicates a receive alarm (ralm function) based on the state of the receive framer. out[1] is low if no receive alarms are active. out[1] is high if an alarm condition is detected. out[1] is updated on the rising edge of rclk. in this operation mode out[0] is used as a single bit parallel output port, as described below. when configured as a parallel output port, out[1] and out[0] can be used to control the operation of external devices. the signal levels on the output port are determined by register bits. when configured as a traffic indicator port, out[1] indicates the receive traffic activity and out[0] indicates the transmit traffic activity. in this operation mode out[1] and out[0] pulses high fom 100ms on cell receive and transmit events and can be used to control an led display. rfp output 56 the receive frame pulse (rfp) output, when the framing alignment has been found (the oof register bit is logic 0), is an 8 khz signal derived from the receive line clock. rfp pulses high for one rclk cycle every 2430 rclk cycles for sts-3c (stm-1) rate or every 810 rclk cycles for sts-1 rate. rfp is updated on the rising edge of rclk.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 14 pin name type pin no. function txd+ txd- diff. analog output 12 13 the transmit differential data/positive pulse outputs (txd+, txd-) contain nrz encoded data. these outputs are open drain current sinks which interface directly with the twisted- pair network or with an optical interface module requiring pecl levels. refer to the applications section of this document for a description of the required termination network. tfp i/o 58 the active high framing position (tfp) signal is an 8 khz timing marker for the transmitter. tfp defaults to being an input and is used to align the sonet/sdh transport frame generated by the s/uni-ultra device to a system reference. tfp should be brought high for a single tclk period every 810 (sts-1) or 2430 (sts-3/stm-1) tclk cycles, or a multiple thereof. tfp may be tied low if such synchronization is not required. tfp is sampled on the rising edge of tclk. tfp must not be used as an input when loop-timed. when selected as an output through the interface configuration register, tfp pulses high for one tclk cycle every 2430 tclk cycles for sts-3c (stm-1) rate or every 810 tclk cycles for sts-1 rate. tfp is updated on the rising edge of tclk.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 15 pin name type pin no. function tsen input 59 the tristate enable (tsen) input selects the configuration of the receive datapath (rdat[7:0], rxprty and rsoc). when tsen is tied high, rdat[7:0] operates as a tristate bus controlled by rrdenb. when rrdenb is high upon rfclk rising, rdat[7:0], rxprty and rsoc are tristated. when rrdenb is low upon rfclk rising, rdat[7:0], rxprty and rsoc are enabled. when tsen is tied low, rdat[7:0], rxprty and rsoc are always enabled, regardless of the state of rrdenb. rfclk input 66 the receive read clock (rfclk) is used to read atm cells from the receive fifo. rfclk must cycle at a high enough rate to avoid fifo overflow. rrdenb is sampled using the rising edge of rfclk. rsoc, rdat[7:0], rxprty and rca are updated on the rising edge of rfclk rrdenb input 67 the active low receive read enable input (rrdenb) is used to initiate reads from the receive fifo. when sampled low using the rising edge of rfclk, a byte is read from the internal synchronous fifo and output on bus rdat[7:0] if one is available. when sampled high using the rising edge of rfclk, no read is performed and rdat[7:0] and rsoc are tristated if the tsen input is high. rrdenb must operate in conjunction with rfclk to access the fifo at a high enough instantaneous rate as to avoid fifo overflows. the atm layer device may deassert rrdenb at anytime it is unable to accept another byte. when the rca signal is configured to be deasserted with zero octets (as opposed to four) in the fifo, the rca signal identifies the valid octets.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 16 pin name type pin no. function rdat[0] rdat[1] rdat[2] rdat[3] rdat[4] rdat[5] rdat[6] rdat[7] tristate output 69 70 73 74 75 76 77 78 the receive cell data (rdat[7:0]) bus carries the atm cell octets that are read from the receive fifo. rdat[7:0] is updated on the rising edge of rfclk and is tristated when not valid if the tsen input is high. the rdat[7:0] bus is always driven when tsen is low, regardless of the level of rrdenb. rxprty tristate output 81 the receive parity (rxprty) signal indicates the parity of the rdat[7:0] bus. odd or even parity selection can be made using a register. rxprty is updated on the rising edge of rfclk and is tristated when not valid if the tsen input is high. rxprty is always driven when tsen is low, regardless of the level of rrdenb. rsoc tristate output 82 the receive start of cell (rsoc) signal marks the start of cell on the rdat[7:0] bus. when rsoc is high, the first octet of the cell is present on the rdat[7:0] stream. rsoc is updated on the rising edge of rfclk and is tristated when not valid if the tsen input is high. rsoc is always driven when tsen is low, regardless of the level of rrdenb. rca output 68 the receive cell available (rca) signal indicates when a cell is available in the receive fifo. rca can be configured to be deasserted when either zero or four bytes remain in the fifo. rca is updated on the rising edge of rfclk. the active polarity of this signal is programmable and defaults to active high.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 17 pin name type pin no. function rgfc output 57 the receive generic flow control (rgfc) output presents the extracted gfc bits in a serial stream. the four gfc bits are presented for each received cell, with the rcp output indicating the position of the most significant bit. the updating of rgfc by particular gfc bits may be disabled through the racp configuration register. the serial link is forced low if cell delineation is lost. rgfc is updated on the rising edge of rclk. rcp output 49 the receive cell pulse (rcp) indicates the location of the four gfc bits in the rgfc serial stream. rcp is coincident with the most significant gfc bit. rcp is updated on the rising edge of rclk. tclk output 52 the transmit byte clock (tclk) output provides a timing reference for s/uni-ultra transmit outputs. tclk is a divide by eight of the synthesized line rate clock. tgfc, tcp and tfp are sampled on the rising edge of tclk. tfclk input 86 the transmit write clock (tfclk) is used to write atm cells to the four cell transmit fifo. a complete 53 octet cell must be written to the fifo before being inserted in the synchronous payload envelope (spe). idle/unassigned cells are inserted when a complete cell is not available. tdat[7:0], txprty, twrenb and tsoc are sampled on the rising edge of tfclk. tca is updated on the rising edge of tfclk.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 18 pin name type pin no. function tdat[0] tdat[1] tdat[2] tdat[3] tdat[4] tdat[5] tdat[6] tdat[7] input 88 89 90 91 92 93 94 95 the transmit cell data (tdat[7:0]) bus carries the atm cell octets that are written to the transmit fifo. tdat[7:0] is sampled on the rising edge of tfclk and is considered valid only when twrenb is simultaneously asserted. txprty input 96 the transmit parity (txprty) signal indicates the parity of the tdat[7:0] bus. odd or even parity selection can be made using a register bit. txprty is sampled on the rising edge of tfclk and is considered valid only when twrenb is simultaneously asserted. a parity error is indicated by a status bit and a maskable interrupt. cells with parity errors are not filtered, so the txprty input may be unused. twrenb input 87 the active low transmit write enable input (twrenb) is used to initiate writes to the transmit fifo. when sampled low using the rising edge of tfclk, the byte on tdat[7:0] is written into the transmit fifo. when sampled high using the rising edge of tfclk, no write is performed. a complete 53 octet cell must be written to the transmit fifo before it is inserted into the spe. idle/unassigned cells are inserted when a complete cell is not available.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 19 pin name type pin no. function tsoc input 97 the transmit start of cell (tsoc) signal marks the start of cell on the tdat[7:0] bus. when tsoc is high, the first octet of the cell is present on the tdat[7:0] stream. it is not necessary for tsoc to be present at each cell. an interrupt may be generated if tsoc is high during any byte other than the first byte. tsoc is sampled on the rising edge of tfclk tca output 83 the transmit cell available (tca) signal indicates when a cell is available in the transmit fifo. when high, tca indicates that the transmit fifo is not full and a complete cell may be written in. when tca goes low, it indicates either that the transmit fifo is near full and can accept no more than four writes or that the transmit fifo is full. selection is made using a register bit in the tacp fifo control register. to reduce fifo latency, the fifo depth at which tca indicates "full" can be set to one, two, three or four cells by the tacp fifo control register. if the programmed depth is less than four, additional cells may be written after tca is deasserted. tca is updated on the rising edge of tfclk. the active polarity of this signal is programmable and defaults to active high. xoff input 45 the transmit off (xoff) input prevents the insertion of cells from the transmit fifo. if xoff is asserted high, the next cell transmitted is an idle/unassigned cell regardless of the number of cells in the fifo. idle/unassigned cells are transmitted until xoff is deasserted. xoff may be treated as an asynchronous signal. when the device in set in production test mode (master test register pmctst bit set to logic 1) xoff is used as the test vector clock (vclk) signal.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 20 pin name type pin no. function tgfc input 51 the transmit generic flow control (tgfc) input provides the ability to insert the gfc value. the four tclk periods following the tcp output pulse contain the gfc value to be inserted into the current cell. the gfc enable bits of the tacp configuration register enable the insertion of each serial bit. by default, the gfc values are the contents of the tacp idle/unassigned cell header control register for idle/unassigned cells and the value received from tdat[7:0] for assigned cells. tgfc is sampled on the rising edge of tclk. tcp output 50 the transmit cell pulse (tcp) indicates where the valid tgfc serial bits are expected. if tcp is asserted high, the most significant gfc bit is expected in the subsequent tclk period. tcp pulses high for one tclk for every transmitted cell six payload octets before the first octet of the cell read from the transmit fifo, or the idle cell if the fifo is empty. tcp is updated on the rising edge of tclk. trref analog 19 the reference resistor (trref) input is connected to an off-chip precision resistor r ref to produce calibrated currents for the txd+/- outputs. the resistor should be connected between trref and tavs4. please refer to the applications and the external components sections of this document for a detailed r ref specification.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 21 pin name type pin no. function tvref analog 18 the reference voltage (tvref) is optionally used to produce calibrated currents for the txd +/- outputs. in order to meet tight amplitude tolerances over process, temperature and supply, a precise reference voltage generator v ref is required. the other terminal of the reference generator should be connected to tavs4. if this pin is unused, this input should be connected to analog tavs4. please refer to the applications and the external components sections of this document for a detailed v ref specification. rcap1 rcap2 analog 27 28 the rcap1 and rcap2 pins should be connected to the ravs3 analog ground. at p 1 at p 2 analog 7 33 two analog test points (atp1, atp2) are provided for production test purposes. these pins must be connected to analog ground during normal operation. csb input 100 the active low chip select (csb) signal is low during s/uni-ultra register accesses. if csb is used, it must be held high while rstb is low to properly initialize the device. if csb is not required (i.e. register accesses are controlled using the rdb and wrb signals only), csb must be connected to an inverted version of the rstb input to ensure proper device initialization. csb is a schmitt triggered input with an integral pull up resistor. rdb input 99 the active low read enable (rdb) signal is low during s/uni-ultra register read accesses. the s/uni-ultra drives the d[7:0] bus with the contents of the addressed register while rdb and csb are low.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 22 pin name type pin no. function wrb input 98 the active low write strobe (wrb) signal is low during a s/uni-ultra register write accesses. the d[7:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] i/o 108 109 110 111 114 115 116 117 the bidirectional data bus d[7:0] is used during s/uni-ultra register read and write accesses. a[0] a[1] a[2] a[3] a[4] a[5] a[6] input 120 121 122 123 124 125 126 the address bus a[7:0] selects specific registers during s/uni-ultra register accesses. a[7]/trs 127 the test register select (trs) signal selects between normal and test mode register accesses. trs is high during test mode register accesses, and is low during normal mode register accesses. rstb input 101 the active low reset (rstb) signal provides an asynchronous s/uni-ultra reset. rstb is a schmitt triggered input with an integral pull up resistor.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 23 pin name type pin no. function ale input 104 the address latch enable (ale) is active high and latches the address bus a[7:0] when low. when ale is high, the internal address latches are transparent. it allows the s/uni-ultra to interface to a multiplexed address/data bus. intb open- drain output 107 the active low interrupt (intb) signal goes low when a s/uni-ultra interrupt source is active, and that source is unmasked. the s/uni-ultra may be enabled to report many alarms or events via interrupts. intb returns high when the interrupt is acknowledged via an appropriate register access. intb is an open drain output and must have an external pull-up resistor. vddi1 vddi2 vddi3 vddi4 vddi5 power 44 60 85 106 119 the core power (vddi1 - vddi5) pins should be connected to a well decoupled +5 v dc in common with vddo. vssi1 vssi2 vssi3 vssi4 vssi5 vssi6 ground 43 61 84 105 118 46 the core ground (vssi1 - vssi6) pins should be connected to gnd in common with vsso. vddo1 vddo2 vddo3 vddo4 vddo5 vddo6 power 47 53 62 72 80 113 the pad ring power (vddo1 - vddo6) pins should be connected to a well decoupled +5 v dc in common with vddi.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 24 pin name type pin no. function vsso1 vsso2 vsso3 vsso4 vsso5 vsso6 ground 48 54 63 71 79 112 the pad ring ground (vsso1 - vsso6) pins should be connected to gnd in common with vssi. vss thermal ground 1 38 39 64 65 102 103 128 the thermal grounds (vss) provide a low thermal resistance for the dissipated heat. these pins are shorted internally and must be connected to vssi ground for correct operation. tavd1 analog power 6 the power (tavd1) pin for the transmit clock synthesizer reference circuitry. tavd1 should be connected to analog +5v. tavd2 analog power 4 the power (tavd2) pin for the transmit clock synthesizer oscillator. tavd2 should be connected to analog +5v. tavd3 analog power 11 14 the power (tavd3) pins for the twisted pair and pecl transmitter output driver. tavd3 should be connected to analog +5v. tavd4 analog power 16 the power (tavd4) pin for the twisted pair and pecl transmitter block reference circuitry. tavd4 should be connected to analog +5v. tavs1 analog ground 5 the ground (tavs1) pin for the transmit clock synthesizer reference circuitry. tavs1 should be connected to analog gnd.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 25 pin name type pin no. function tavs2 analog ground 3 the ground (tavs2) pin for the transmit clock synthesizer oscillator. tavs2 should be connected to analog gnd. tavs3 analog ground 10 15 the ground (tavs3) pins for the twisted pair and pecl transmitter output driver. tavs3 should be connected to analog gnd. tavs4 analog ground 17 20 the ground (tavs4) pins for the twisted pair and pecl transmitter block reference circuitry. tavs4 should be connected to analog gnd. ravd1 analog power 34 the power (ravd1) pin for receive clock and data recovery block reference circuitry. ravd1 should be connected to analog +5v. ravd2 analog power 36 the power (ravd2) pin for receive clock and data recovery block active loop filter and oscillator. ravd2 should be connected to analog +5v. ravd3 analog power 21 30 the power (ravd3) pins for the twisted pair and pecl receiver block. ravd3 should be connected to analog +5v. ravs1 analog ground 35 the ground (ravs1) pin for receive clock and data recovery block reference circuitry. ravs1 should be connected to analog gnd. ravs2 analog ground 37 the ground (ravs2) pin for receive clock and data recovery block active loop filter and oscillator. ravs2 should be connected to analog gnd. ravs3 analog ground 22 25 26 the ground (ravs3) pins for the twisted pair and pecl receiver block. ravs3 should be connected to analog gnd. qavd analog power 9 31 the power (qavd) pins for the analog core. qavd should be connected to analog +5v. qavs analog ground 8 32 the ground (qavs) pins for the analog core. qavs should be connected to analog gnd.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 26 notes on pin description: 1. all s/uni-ultra inputs and bidirectionals present minimum capacitive loading and operate at ttl logic levels except: the sd input operates at pseudo-ecl (pecl) logic levels; the rxd+ and rxd- inputs can be configured to operate at either pecl levels or utpC5 cable interface levels, respectively. 2. the rdat[7:0], rxprty, rcp, rgfc, rsoc, rca, tca, tcp, tclk and rclk outputs have a 4 ma drive capability. all other s/uni-ultra digital outputs and bidirectionals have 2 ma drive capability. all 4 ma and 2 ma outputs are slew rate limited. the txd+ and txd- outputs have either a 16ma or 20ma capability, depending if they are configure to operate at pecl or utpC5 levels. 3. the vsso and vssi ground pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the device. 4. the vddo and vddi power pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the device. 5. all analog power and ground pins are sensitive to noise. they must be isolated from the digital power and ground. the tavd2 and ravd2 pins power oscillators; therefore, they generate significant switching noise. care must be taken to decouple these pins from each other and all other analog power and ground pins. 6. the out[1] and out[0] outputs can control an led display but must be buffered to provide a sufficient drive. 7. due to esd protection structures in the pads it is necessary to exercise caution when powering a device up or down. esd protection devices behave as diodes between power supply pins and from i/o pins to power supply pins. under extreme conditions it is possible to blow these esd protection devices or trigger latch up. please adhere to the recommended power supply sequencing as described in the operation section of this document .
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 27 functional description 7.1 utp-5 and pecl receiver the line receiver (rutp-5) can be configured to interface with a utp-5 twisted pair cable, or to interface with an optical interface module. in the former case it performs adaptive equalization on the received signal. it is fully compliant to the atm forum pmd interface specification for 155 mbit/s over twisted pair cable. in the latter case, it provides a pecl line interface. 7.2 clock recovery the clock recovery unit recovers the clock from the incoming bit serial data stream. the clock recovery unit is fully compliant with sonet and sdh jitter tolerance requirements. the clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery pll. under loss of signal conditions, the clock recovery unit will continue to output a line rate clock that is locked to this reference for "keep alive" purposes. the clock recovery unit utilizes a 19.44 mhz reference clock. the clock recovery unit provides status bits that indicate whether it is locked to data or the reference. the clock recovery unit also supports diagnostic loopback and a loss of signal input that squelches normal input data. initially, the pll locks to the reference clock, refclk. when the frequency of the recovered clock is within 488 ppm of the reference clock, the pll attempts to lock to the data. once in data lock, the pll reverts to the reference clock if no data transitions occur in 80 bit periods or if the recovered clock drifts beyond 488 ppm of the reference clock. the internal loop filter transfer function is optimized to enable the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. the total loop dynamics of the clock recovery pll yield a jitter tolerance which exceeds the minimum tolerance required for sonet equipment by gr-253-core (figure 2).
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 28 figure 2 - sts-3c/stm-1jitter tolerance jitter freq. (hz) 0.1 1 10 100 100 1000 10000 100000 1000000 10000000 gr-253-core note that for frequencies below 300 hz the jitter tolerance is greater than 15 uipp; 15 uipp is the maximum jitter tolerance of the test equipment. if the recovered clock drifts beyond 488 ppm of the reference, the pll locks to the reference clock. 7.3 serial to parallel converter the serial to parallel converter (sipo) converts the received bit serial sonet stream to a byte serial stream. the sipo searches for the sonet/sdh framing pattern (a1, a2 ) in the incoming stream, and performs serial to parallel conversion on octet boundaries. 7.4 receive section overhead processor the receive section overhead processor (rsop) provides frame synchronization, descrambling, section level alarm and performance monitoring. 7.4.1 framer the framer block determines the in-frame/out-of-frame status of the sts-3c or stsC1 data stream. the loss of frame condition asserts the out[1] output with timing aligned to rclk (provided popc receive alarm monitor mode is selected).
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 29 while in-frame, the framing bytes (a1, a2) in each frame are compared against the expected pattern. out-of-frame is declared when four consecutive frames containing one or more framing pattern errors have been received. while out-of-frame, the sipo block monitors the bit serial data stream for an occurrence of the framing pattern. when a framing pattern has been recognized, the framer block verifies that an error free framing pattern is present in the next frame before declaring in-frame. 7.4.2 descramble the descramble block utilizes a frame synchronous descrambler to process the received byte serial stream. the generating polynomial is 1+x 6 +x 7 and the sequence length is 127. details of the descrambling operation are provided in the references. note that the framing bytes (a1 and a2) and the section trace/section growth bytes (j0/z0) are not descrambled. a register bit is provided to disable the descrambling operation. 7.4.3 error monitor the error monitor block calculates the received section bip-8 error detection code (b1) based on the scrambled data of the complete sts-3c or sts-1 frame. the section bip-8 code is based on a bit interleaved parity calculation using even parity. details are provided in the references. the calculated bip-8 code is compared with the bip-8 code extracted from the b1 byte of the following frame. differences indicate that a section level bit error has occurred. up to 64000 (8x8000) bit errors can be detected per second. the error monitor block accumulates these section level bit errors in a 16 bit saturating counter that can be read via the microprocessor interface. circuitry is provided to latch this counter so that its value can be read while simultaneously resetting the internal counter to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. it is intended that this counter be polled at least once per second so as not to miss bit error events. 7.4.4 loss of signal the loss of signal block monitors the scrambled data of the complete stsC3c or sts-1 stream for the absence of 1's. when 203 s of all zeros patterns is detected, a loss of signal (los) is declared. loss of signal is cleared when two valid framing words are detected and during the intervening time, no loss of signal condition is detected. the loss of signal condition asserts the ralm output with timing aligned to rclk.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 30 7.4.5 loss of frame the loss of frame block monitors the in-frame / out-of-frame status of the framer block. a loss of frame (lof) is declared when an out-of-frame (oof) condition persists for 3 ms. to provide for intermittent out-of-frame conditions, the 3 ms timer is not reset to zero until an in-frame condition persists for 3 ms. the loss of frame is cleared when an in frame condition persists for a period of 3 ms. the loss of frame condition asserts the ralm output with timing aligned to rclk. 7.5 receive line overhead processor the receive line overhead processor (rlop) provides line level alarm and performance monitoring. 7.5.1 line remote defect indication detect the line rdi detect block detects the presence of line remote defect indication (rdi) in the data stream. line rdi is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the k2 byte, for five consecutive frames. line rdi is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the k2 byte for five consecutive frames. the line rdi status is available through a maskable interrupt and register bits. 7.5.2 line ais detect the line ais block detects the presence of a line alarm indication signal (ais) in the data stream. line ais is declared when a 111 binary pattern is detected in bits 6,7,8 of the k2 byte, for five consecutive frames. lais is removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the k2 byte for five consecutive frames. line ais detection asserts the ralm output with timing aligned to rclk. 7.5.3 error monitor the error monitor block calculates the received line bip-8/24 error detection code (b2) based on the line overhead and synchronous payload envelope of the data stream. the line bip-8/24 code is a bit interleaved parity calculation using even parity. details are provided in the references. the calculated bip code is compared with the bip-8/24 code extracted from the b3 byte(s) of the following frame. any differences indicate that a line layer bit error has occurred. up to 192000 (24 x 8000) bit errors can be detected per second.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 31 the error monitor block accumulates these line layer bit errors in a 20 bit saturating counter that can be read via the microprocessor interface. during a read, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). note, this counter should be polled at least once per second to avoid saturation which in turn may result in missed bit error events. the error monitor block also accumulates line far end block error indications (contained in the m0/m1 byte) in a similar manner. 7.6 receive path overhead processor the receive path overhead processor (rpop) provides pointer interpretation, extraction of path overhead, extraction of the synchronous payload envelope, and path level alarm and performance monitoring. 7.6.1 pointer interpreter the pointer interpreter interprets the incoming pointer (h1, h2) as specified in the references. the pointer value is used to determine the location of the path overhead (the j1 byte) in the incoming stsC3c (au4) or stsC1 (au3) stream. the pointer interpreter block detects loss of pointer (lop) in the incoming stsC 1 or stsC3c. lop is declared as a result of eight consecutive invalid pointers or eight consecutive ndf enabled indications. lop is removed when the same valid pointer with normal ndf is detected for three consecutive frames. the pointer interpreter block detects path ais in the incoming stsC1 or stsC3c stream. pais is declared on entry to the ais_state after three consecutive ais indications. pais is removed when the same valid pointer with normal ndf is detected for three consecutive frames or when a valid with ndf enabled is detected. the pointer value is used to extract the path overhead from the incoming stream. note that due to anomalies in the standard pointer interpretation rules, certain illegal pointers may not cause the device to declare a loss of pointer (lop) state. in this situation, however, the device will declare a loss of cell delineation state and return to normal operation when presented with legal pointer values. such illegal pointers typically can only be generated continuously by test equipment and will not normally occur during live-traffic operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 32 7.6.2 error monitor the error monitor block contains two 16-bit counters that are used to accumulate path bip-8 errors (b3), and far end block errors (febe). the contents of the two counters may be transferred to holding registers, and the counters reset under microprocessor control. path bip-8 errors are detected by comparing the path bip-8 byte (b3) extracted from the current frame, to the path bip-8 computed for the previous frame. febes are detected by extracting the 4-bit febe field from the path status byte (g1). the legal range for the 4-bit field is between 0000 and 1000, representing zero to eight errors. any other value is interpreted as zero errors. path remote defect indication (rdi) is detected by extracting bit 5 of the path status byte. path rdi is declared when bit 5 is set high for five consecutive frames and is cleared when bit 5 is low for five consecutive frames. 7.7 receive atm cell processor the receive atm cell processor (racp) performs atm cell delineation, provides cell filtering based on idle/unassigned cell detection and hcs error detection, and performs atm cell payload descrambling. the racp also provides a four cell deep receive fifo. this fifo passes a 53 byte data structure and is used to separate the line timing from the higher layer atm system timing. 7.7.1 cell delineation cell delineation is the process of framing to atm cell boundaries using the header check sequence (hcs) field found in the cell header. the hcs is a crc-8 calculation over the first 4 octets of the atm cell header. when performing delineation, correct hcs calculations are assumed to indicate cell boundaries. cells must be byte aligned before insertion in the synchronous payload envelope. the cell delineation algorithm searches the 53 possible cell boundary candidates one at a time to determine the valid cell boundary location. while searching for the cell boundary location, the cell delineation circuit is in the hunt state. when a correct hcs is found, the cell delineation state machine locks on the particular cell boundary and enters the presync state. this state validates the cell boundary location. if the cell boundary is invalid then an incorrect hcs will be received within the next delta cells, at which point a transition back to the hunt state is executed. if no hcs errors are detected in this presync period then the sync state is entered. while in the sync state,
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 33 synchronization is maintained until alpha consecutive incorrect hcs patterns are detected. in such an event a transition is made back to the hunt state. the state diagram of the delineation process is shown in figure 3. figure 3 - cell delineation state diagram hunt presync sync correct hcs ( b y te b y b y te ) delta consecutive correct hcs's ( cell b y cell ) incorrect hcs ( cell b y cell ) alpha consecutive incorrect hcs's ( cell b y cell ) the values of alpha and delta determine the robustness of the delineation method. alpha determines the robustness against false misalignments due to bit errors. delta determines the robustness against false delineation in the synchronization process. alpha is chosen to be 7 and delta is chosen to be 6. these values result in a maximum average time to delineate of 31 s for stsC3c and 93 s for stsC1. 7.7.2 descrambler the self synchronous descrambler operates on the 48 byte cell payload only. the circuitry descrambles the information field using the 'x 43 +1' polynomial. the descrambler is disabled for the duration of the header and hcs fields, and may optionally be disabled.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 34 7.7.3 cell filter and hcs verification cells are filtered (or dropped) based on hcs errors and/or a cell header pattern. cell filtering is optional and is enabled through the racp registers. cells are passed to the receive fifo while the cell delineation state machine is in the sync state as described above. when both filtering and hcs checking are enabled, cells are dropped if uncorrectable hcs errors are detected, or if the corrected header contents match the pattern contained in the 'match header pattern' and 'match header mask' registers. idle or unassigned cell filtering is accomplished by writing the appropriate cell header pattern into the 'match header pattern' and 'match header mask' registers. idle/unassigned cells are assumed to contain the all zeros pattern in the vci and vpi fields. the 'match header pattern' and 'match header mask' registers allow filtering control over the contents of the gfc, pti, and clp fields of the header. the hcs is a crc-8 calculation over the first 4 octets of the atm cell header. the racp block verifies the received hcs using the polynomial, x 8 +x 2 +x+1. the coset polynomial, x 6 +x 4 +x 2 +1 is added (modulo 2) to the received hcs octet before comparison with the calculated result. while the cell delineation state machine (described above) is in the sync state, the hcs verification circuit implements the state machine shown in figure 4:
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 35 figure 4 - hcs verification state diagram detection mode atm delineation sync state correction mode no errors detected (pass cell) apparent multi-bit error (drop cell) errors detected (drop cell) no errors detected (pass cell) alpha consecutive incorrect hcs's (to hunt state) delta consecutive correct hcs's (from presync state) single bit error (correct error and pass cell) in normal operation, the hcs verification state machine remains in the 'correction mode' state. incoming cells containing no hcs errors are passed to the receive fifo. incoming single bit errors are corrected, and the resulting cell is passed to the fifo. upon detection of a single bit error or a multi bit error, the state machine transitions to the 'detection mode' state. in this state, the detection of any hcs error causes the corresponding cell to be dropped. cells containing an error-free hcs are passed, and the state machine transitions back to the 'correction mode' state. 7.7.4 performance monitor the performance monitor consists of two 8-bit saturating hcs error event counters and a 19-bit cell counter. one of the counters accumulates correctable hcs errors (i.e. single hcs bit errors detected while the hcs verification state machine is in the 'correction mode' state described above). the second counter accumulates uncorrectable hcs errors (i.e. hcs bit errors detected while the
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 36 hcs verification state machine is in the 'detection mode' state or multiple hcs bit errors detected while the state machine is in the 'correction mode' state as described above). the cell counter accumulates the number of received assigned cells. all counters are enabled only when the racp is in the sync state. each counter may be read through the microprocessor interface. circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. it is intended that the counters be polled at least once per second so hcs error events or cell counts will not be missed. 7.7.5 gfc extraction port the gfc extraction port outputs the received gfc bits in a serial stream. the four gfc bits are presented for each received cell, with the rcp output indicating the position of the most significant bit. the updating of rgfc by particular gfc bits may be disabled through an internal register. the serial link is forced low if cell delineation is lost. 7.7.6 receive fifo the receive fifo provides fifo management and a synchronous interface between the s/uni-ultra device and the external environment. the receive fifo can accommodate four cells. the receive fifo provides for the separation of the sts-1 or sts-3c line or physical layer timing from the atm layer timing. management functions include filling the receive fifo, indicating when cells are available to be read from the receive fifo, maintaining the receive fifo read and write pointers, and detecting fifo overrun and underrun conditions. upon detection of an overrun condition, the fifo will drop all incoming cells until at least one cell has been read from the fifo. at least one cell will be lost during the fifo drop operation. upon detection of an underrun, the offending read is ignored. fifo overruns are indicated through a maskable interrupt and register bit. the interface provided indicates the start of a cell (rsoc) when data is read from the receive fifo (using rfclk) and indicates the cell available status (rca). the cell available status may be configured to change from available to unavailable on read cell boundaries or four reads before the cell boundary. when the rca signal is configured to be deasserted with zero octets (as opposed to four) in the fifo, it is not an error condition to hold the read enable (rrdenb) active. in this situation, the rca signal identifies the valid octets.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 37 7.8 utp-5 and pecl transmitter the line transmitter (tutp-5) provides the accurate logic levels required to interface with a utp-5 twisted pair, or pecl levels to interface with an optical interface module. it is fully compliant to the atm forum pmd interface specification for 155 mb/s over twisted pair. 7.9 clock synthesis the transmit clock is synthesized from a 19.44 mhz reference. the intrinsic jitter is minimized when the reference frequency is 19.44 mhz. with a jitter free 19.44 mhz reference input and a low noise board layout, the intrinsic jitter is typically less than 0.01 ui rms and 0.10 ui peak-to-peak when measured using a band pass filter with 12 khz and 1.3 mhz cutoff frequencies. 7.10 parallel to serial converter the parallel to serial converter (piso) converts the internal byte serial stream to a bit serial stream. 7.11 transmit section overhead processor the transmit section overhead processor (tsop) provides frame pattern insertion (a1, a2), scrambling, section level alarm signal insertion, and section bip-8 (b1) insertion. 7.11.1 line ais insert line ais insertion results in all bits of the sonet/sdh frame being set to 1 before scrambling except for the section overhead. the line ais insert block substitutes all ones as described when enabled through an internal register accessed through the microprocessor interface. activation or deactivation of line ais insertion is synchronized to frame boundaries. 7.11.2 bip-8 insert the bip-8 insert block calculates and inserts the bip-8 error detection code (b1) into the unscrambled data stream. the bipC8 calculation is based on the scrambled data of the complete stsC3c or stsC1 frame. the section bipC8 code is based on a bit interleaved parity calculation using even parity. details are provided in the references. the
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 38 calculated bipC8 code is then inserted into the b1 byte of the following frame before scrambling. bip-8 errors may be continuously inserted under register control for diagnostic purposes. 7.11.3 framing and identity insert the framing and identity insert block inserts the framing bytes (a1, a2) and identity bytes (c1) into the sts-3c or sts-1 frame. framing bit errors may be continuously inserted under register control for diagnostic purposes. 7.11.4 scrambler the scrambler block utilizes a frame synchronous scrambler to process the transmit serial stream when enabled through an internal register accessed via the microprocessor interface. the generating polynomial is 1+x 6 +x 7 . precise details of the scrambling operation are provided in the references. note that the framing bytes and the identity bytes are not scrambled. all zeros may be continuously inserted (after scrambling) under register control for diagnostic purposes. 7.12 transmit line overhead processor the transmit line overhead processor (tlop) provides line level alarm signal insertion and line bip-8/24 insertion (b2). 7.12.1 bip calculate the bip calculate block calculates the line bip error detection code (b2) based on the line overhead and synchronous payload envelope of the sts-3c or sts-1 stream. the line bip code is a bit interleaved parity calculation using even parity. details are provided in the references. the calculated bip code is inserted into the b2 byte positions of the following frame. bip errors may be continuously inserted under register control for diagnostic purposes. 7.12.2 line remote defect indication insert the line rdi insert block multiplexes the line overhead bytes into the output stream and optionally inserts line rdi. line rdi is inserted by this block when enabled via register control. line rdi is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the k2 byte contained in the stsC3c or stsC1 stream.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 39 7.12.3 line febe insert the line febe insert block accumulates line bip errors (b2) detected by the receive line overhead processor and encodes far end block error indications in the transmit m0/m1 byte. figure 5 - sts-3c/stm-1 default transport overhead values j0 ( 0x01 ) z0 ( 0x02 ) z0 ( 0x03 ) a2 ( 0x28 ) a2 ( 0x28 ) a2 ( 0x28 ) a1 ( 0xf6 ) f1 ( 0x00 ) ( 0x00 ) ( 0x00 ) e1 ( 0x00 ) ( 0x00 ) ( 0x00 ) b1 ( * ) ( 0x00 ) ( 0x00 ) d3 ( 0x00 ) ( 0x00 ) ( 0x00 ) d2 ( 0x00 ) ( 0x00 ) ( 0x00 ) d1 ( 0x00 ) ( 0x00 ) ( 0x00 ) h3 ( 0x00 ) h3 ( 0x00 ) h3 ( 0x00 ) h2 ( 0x0a ) h2 ( 0xff ) h2 ( 0xff ) h1 ( 0x62 ) h1 ( 0x93 ) h1 ( 0x93 ) k2 ( 0x00 ) ( 0x00 ) ( 0x00 ) k1 ( 0x00 ) ( 0x00 ) ( 0x00 ) b2 ( * ) b2 ( * ) b2 ( * ) d6 ( 0x00 ) ( 0x00 ) ( 0x00 ) d5 ( 0x00 ) ( 0x00 ) ( 0x00 ) d4 ( 0x00 ) ( 0x00 ) ( 0x00 ) d9 ( 0x00 ) ( 0x00 ) ( 0x00 ) d8 ( 0x00 ) ( 0x00 ) ( 0x00 ) d7 ( 0x00 ) ( 0x00 ) ( 0x00 ) d12 ( 0x00 ) ( 0x00 ) ( 0x00 ) d11 ( 0x00 ) ( 0x00 ) ( 0x00 ) d10 ( 0x00 ) ( 0x00 ) ( 0x00 ) e2 ( 0x00 ) ( 0x00 ) ( 0x00 ) z2 ( 0x00 ) z2 ( 0x00 ) m1 ( * ) z1 ( 0x00 ) z1 ( 0x00 ) z1 ( 0x00 ) * : b1, b2 values de p end on p a y load contents m1 value de p ends on incomin g line bit errors a1 ( 0xf6 ) a1 ( 0xf6 )
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 40 figure 6 - sts-1 default transport overhead values j0 ( 0x01 ) a2 ( 0x28 ) f1 ( 0x00 ) e1 ( 0x00 ) b1 ( * ) d3 ( 0x00 ) d2 ( 0x00 ) d1 ( 0x00 ) h3 ( 0x00 ) h2 ( 0x0a ) h1 ( 0x62 ) k2 ( 0x00 ) k1 ( 0x00 ) b2 ( * ) d6 ( 0x00 ) d5 ( 0x00 ) d4 ( 0x00 ) d9 ( 0x00 ) d8 ( 0x00 ) d7 ( 0x00 ) d12 ( 0x00 ) d11 ( 0x00 ) d10 ( 0x00 ) e2 ( 0x00 ) m0 ( * ) z1 ( 0x00 ) a1 ( 0xf6 ) * : b1, b2 values de p end on p a y load contents m0 value de p ends on incomin g line bit errors 7.13 transmit path overhead processor the transmit path overhead processor (tpop) provides transport frame alignment generation, pointer generation (h1, h2), path overhead insertion, insertion of the synchronous payload envelope, insertion of path level alarm signals and path bip-8 (b3) insertion. 7.13.1 pointer generator the pointer generator block generates the outgoing payload pointer (h1, h2). the block contains a free running time slot counter that locates the start of the
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 41 synchronous payload envelope based on the generated pointer value and the sonet/sdh frame alignment. the pointer generator block generates the outgoing pointer as specified in the references. the concatenation indication (the ndf field set to 1001, i-bits and d-bits set to all ones, and unused bits set to all zeros) is inserted in the second and third pointer bytes. 7.13.2 bip-8 calculate the bip-8 calculate block performs a path bit interleaved parity calculation on the spe of the outgoing stream. the resulting parity byte is inserted in the path bipC8 (b3) byte position of the subsequent frame. bipC8 errors may be continuously inserted under register control for diagnostic purposes. 7.13.3 febe calculate the febe calculate block accumulates far end block errors on a per frame basis, and inserts the accumulated value (up to maximum value of eight) in the febe bit positions of the path status (g1) byte. the febe information is derived from path bip-8 errors detected by the receive path overhead processor, rpop. the asynchronous nature of these signals implies that more than eight febe events may be accumulated between transmit g1 bytes. if more than eight receive path bip-8 errors are accumulated between transmit g1 bytes, the accumulation counter is decremented by eight, and the remaining febes are transmitted at the next opportunity. far end block errors may be inserted under register control for diagnostic purposes. 7.13.4 spe multiplexer the spe multiplexer block multiplexes the payload pointer bytes, the spe stream, and the path overhead bytes into the stsC3c or stsC1 stream.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 42 figure 7 - default path overhead values j1 ( 0x00 ) b3 ( * ) c2 ( 0x13 ) z3 ( 0x00 ) z4 ( 0x00 ) z5 ( 0x00 ) f2 ( 0x00 ) h4 ( * ) * : b3 value de p end on p a y load contents g1 value de p ends on incomin g p ath bit errors h4 value de p ends on cell boundar y offset g1 ( * ) 7.14 transmit atm cell processor the transmit atm cell processor (tacp) inserts h4 framing, provides rate adaptation via idle/unassigned cell insertion, provides hcs generation and insertion, and performs atm cell scrambling. the tacp contains a four cell transmit fifo. an idle or unassigned cell is transmitted if a complete atm cell has not been written into the fifo.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 43 7.14.1 idle/unassigned cell generator the idle/unassigned cell generator inserts idle or unassigned cells into the cell stream when enabled. registers are provided to program the gfc, pti, and clp fields of the idle cell header and the idle cell payload. an all zeros pattern is inserted into the vci/vpi bit locations. the idle cell hcs is automatically calculated and inserted. 7.14.2 scrambler the scrambler scrambles the 48 octet information field. scrambling is performed using a parallel implementation of the self synchronous scrambler described in the references. the cell headers are transmitted unscrambled, and the scrambler may optionally be completely disabled. 7.14.3 hcs generator the hcs generator performs a crc-8 calculation over the first four header octets. a parallel implementation of the polynomial, x 8 +x 2 +x+1 is used. the coset polynomial, x 6 +x 4 +x 2 +1 is added (modulo 2) to the residue. the hcs generator inserts the result into the fifth octet of the header. 7.14.4 gfc insertion port the gfc insertion port provides the ability to insert the gfc value downstream of the fifo. the four gfc bits are received on a serial stream the is synchronized to the transmit cell by a framing pulse. the gfc enable register bits control the insertion of each serial bit. if the enable is cleared, the default gfc value is inserted. for idle/unassigned cells, the default is the contents of the tacp idle/unassigned cell header control register. for assigned cells, the default is the value received from tdat[7:0]. 7.14.5 transmit fifo the transmit fifo provides fifo management and a synchronous interface between the s/uni-ultra device and the external environment. the transmit fifo can accommodate four cells. it provides for the separation of the physical layer timing from the atm layer timing. management functions include filling the transmit fifo, indicating when cells are available to be written to the transmit fifo, maintaining the transmit fifo read and write pointers, and detecting a fifo overrun condition. the synchronous
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 44 interface provided to an external device expects the start of a cell (tsoc) when the first byte of the cell is written to the fifo (using tfclk in conjunction with twrenb) and indicates the cell available status (tca). the fifo status changes from cell unavailable to cell available on read cell boundaries. the fifo status can be configured to change from cell available to cell unavailable on write cell boundaries or four octets before the end of the cell. the latency through the transmit fifo can be controlled by setting the fill level at which the cell available (tca) signal is deasserted. although all four cell buffers are always accessible, tca may be programmed to indicate when the fifo contains one, two, three or four cells. (the current cell being read out of the fifo is included in the count. be aware that setting a depth of one may limit throughput.) if a cell write is started immediately after tca is asserted, the latency through the device for sts-3c/stm-1 is latency = depth*(53 line byte periods) + 16 line byte periods (min.) = depth*(53 line byte periods) + 26 line byte periods (max.). the latency for sts-1 is latency = depth*(53 line byte periods) + 10 line byte periods (min.) = depth*(53 line byte periods) + 14 line byte periods (max.). the presence of the sonet/sdh overhead accounts for the difference between the minimum and maximum latencies. when the fifo contains four cells and the upstream device writes into the fifo, the tacp indicates a fifo overrun condition using a maskable interrupt and register bits. the offending write and all subsequent writes are ignored until there is room in the fifo. 7.15 drop side interface 7.15.1 receive interface the drop side receive interface can be accessed through a generic 8-bit wide interface. external circuitry is notified, using the rca signal, when a cell is available in the receive fifo. external circuitry may then read the cell from the buffer as a byte wide stream (along with a bit marking the first byte of the cell).
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 45 7.15.2 transmit interface the drop side transmit interface can be accessed through a generic 8-bit wide interface. external circuitry is notified, using the tca signal, when a cell may be written to the transmit fifo. the cell is written to the fifo as a byte wide stream (along with a bit marking the first byte of the cell). 7.16 parallel output port and led display controller the parallel output port (out[1:0]) and led display controller (popc) has three modes of operation: parallel output port, alarm monitor and traffic monitor. the output port mode provides direct output control, while register bits set the out[1:0] outputs. the output port is either set to a fixed logic value and used to command an external device, or it toggles at a programmable rate and is used to command an led display. the alarm monitor mode allows external monitoring of alarm conditions through the out[1] output (used as ralm). the out[1] output is either set to a static logic value and used to command an external device, or it toggles at a programmable rate and is used to command an led display. the traffic monitor mode provides traffic activity indication and is only intended to command an external led display. the controller produces a separate fixed length 100 ms pulse on out[1] when a cell transmit event occurs or on out[0] when a cell receive event occurs. 7.17 microprocessor interface the microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. the normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the s/uni-ultra. the microprocessor interface consist of a bidirectional 8 bit data bus and a separate 8 bit address bus, which allows both separate address/data bus and multiplexed address/data bus operations. the interface uses separate read (rdb) and write (wrb) signals, an address latch enable (ale), a chip select (csb), a master chip reset (rstb) and the active low interrupt output (intb). the register set is accessed as follows:
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 46 8 register memory map for all register accesses, csb must be low. address register 0x00 s/uni-ultra master reset and identity / load meters 0x01 s/uni-ultra master configuration 0x02 s/uni-ultra master interrupt status 0x03 s/uni-ultra master mode control 0x04 s/uni-ultra master clock monitor 0x05 s/uni-ultra master control 0x06 s/uni-ultra clock synthesis control and status 0x07 reserved 0x08 s/uni-ultra clock recovery control and status 0x09 s/uni-ultra clock recovery configuration 0x0a s/uni-ultra transmit interface configuration 0x0b reserved 0x0c s/uni-ultra receive interface configuration 0x0d-0x0f reserved 0x10 rsop control/interrupt enable 0x11 rsop status/interrupt status 0x12 rsop section bip-8 lsb 0x13 rsop section bip-8 msb 0x14 tsop control 0x15 tsop diagnostic 0x16-0x17 tsop reserved 0x18 rlop control/status 0x19 rlop interrupt enable/status 0x1a rlop line bip-8/24 lsb
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 47 address register 0x1b rlop line bip-8/24 0x1c rlop line bip-8/24 msb 0x1d rlop line febe lsb 0x1e rlop line febe 0x1f rlop line febe msb 0x20 tlop control 0x21 tlop diagnostic 0x22-0x23 tlop reserved 0x24-0x2f reserved 0x30 rpop status/control 0x31 rpop interrupt status 0x32 rpop reserved 0x33 rpop interrupt enable 0x34 rpop reserved 0x35 rpop reserved 0x36 rpop reserved 0x37 rpop path signal label 0x38 rpop path bip-8 lsb 0x39 rpop path bip-8 msb 0x3a rpop path febe lsb 0x3b rpop path febe msb 0x3c rpop reserved 0x3d rpop path bip-8 configuration 0x3e-0x3f rpop reserved 0x40 tpop control/diagnostic 0x41 tpop pointer control 0x42 tpop reserved 0x43 tpop reserved
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 48 address register 0x44 tpop reserved 0x45 tpop arbitrary pointer lsb 0x46 tpop arbitrary pointer msb 0x47 tpop reserved 0x48 tpop path signal label 0x49 tpop path status 0x4a tpop reserved 0x4b-0x4f tpop reserved 0x50 racp control/status 0x51 racp interrupt enable/status 0x52 racp match header pattern 0x53 racp match header mask 0x54 racp correctable hcs error count 0x55 racp uncorrectable hcs error count 0x56 racp receive cell counter (lsb) 0x57 racp receive cell counter 0x58 racp receive cell counter (msb) 0x59 racp configuration 0x5a-0x5f racp reserved 0x60 tacp control/status 0x61 tacp idle/unassigned cell header pattern 0x62 tacp idle/unassigned cell payload octet pattern 0x63 tacp fifo configuration 0x64 tacp transmit cell counter (lsb) 0x65 tacp transmit cell counter 0x66 tacp transmit cell counter (msb) 0x67 tacp configuration 0x68 popc control
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 49 address register 0x69 popc rate 0 0x6a popc rate 1 0x6b popc reserved 0x6c-0x7f reserved 0x80 s/uni-ultra master test 0x81-0xff reserved for test normal mode register description normal mode registers are used to configure and monitor the operation of the s/uni-ultra. normal mode registers (as opposed to test mode registers) are selected when trs (a[7]) is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the s/uni-ultra to determine the programming state of the block. 3. writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect s/uni-ultra operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the s/uni-ultra operates as intended, reserved register bits must only be written with either logic zero or logic one, as indicated. similarly, writing to reserved registers should be avoided.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 50 register 0x00: s/uni-ultra master reset and identity / load meters bit type function default bit 7 r/w reset 0 bit 6 r type[2] 1 bit 5 r type[1] 1 bit 4 r type[0] 1 bit 3 r tip 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 0 this register allows the revision of the s/uni-ultra to be read by software permitting graceful migration to support for newer, feature enhanced versions of the s/uni-ultra. it also provides software reset capability. writing to this register (without setting the reset bit) loads all the error counters in the rsop, rlop, rpop, racp and tacp blocks. id[2:0]: the id bits can be read to provide a binary s/uni-ultra revision number. tip: the tip bit is set to a logic one when any value with the reset bit set to logic 0 is written to this register. such a write initiates an accumulation interval transfer and loads all the performance meter registers in the rsop, rlop, rpop, racp, and tacp blocks. tip remains high while the transfer is in progress, and is set to a logic zero when the transfer is complete. tip can be polled by a microprocessor to determine when the accumulation interval transfer is complete. type[2:0]: the type bits distinguish the s/uni-ultra from the other members of the s/uni family of devices.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 51 reset: the reset bit allows the s/uni-ultra to be reset under software control. if the reset bit is a logic one, the entire s/uni-ultra is held in reset. this bit is not self-clearing. therefore, a logic zero must be written to bring the s/uni- ultra out of reset. holding the s/uni-ultra in a reset state places it into a low power, stand-by mode. a hardware reset clears the reset bit, thus negating the software reset. otherwise the effect of a software reset is equivalent to that of a hardware reset.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 52 register 0x01: s/uni-ultra master configuration bit type function default bit 7 unused bit 6 r/w autofebe 1 bit 5 r/w autolrdi 1 bit 4 r/w autoprdi 1 bit 3 r/w tcainv 0 bit 2 r/w rcainv 0 bit 1 r/w reserved 0 bit 0 r/w tfp_in 1 tfp_in: the transmit frame pulse interface (tfp_in) bit determines whether the tfp pin is used as input or output. if tfp_in is a logic 0, tfp outputs the transmit overhead frame pulse for external use. if tfp_in is a logic 1, tfp is used to align the sonet/sdh transport frame generated by the s/uni-ultra device to a system reference. rcainv: the rcainv bit selects the active polarity of the rca signal. the default configuration selects rca to be active high, indicating that a received cell is available when high. when rcainv is set to logic one, the rca signal becomes active low. tcainv: the tcainv bit selects the active polarity of the tca signal. the default configuration selects tca to be active high, indicating that a cell is available in the transmit fifo when high. when tcainv is set to logic one, the tca signal becomes active low. autoprdi the autoprdi bit determines whether sts path remote defect indication (rdi) is sent immediately upon detection of an incoming alarm. when autoprdi is set to logic one, sts path rdi is inserted immediately upon declaration of loss of signal (los), loss of frame (lof), line ais, loss of pointer (lop) or sts path ais.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 53 autolrdi the autolrdi bit determines whether line remote defect indication (rdi) is sent immediately upon detection of an incoming alarm. when autolrdi is set to logic one, line rdi is inserted immediately upon declaration of loss of signal (los), loss of frame (lof) or line ais. autofebe the autofebe bit determines whether line and path far end block errors are sent upon detection of an incoming line and path bip error events. when autofebe is set to logic one, one line or path febe is inserted for each line or path bip error event, respectively. when autofebe is set to logic zero, incoming line or path bip error events do not generate febe events. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 54 register 0x02: s/uni-ultra master interrupt status bit type function default bit 7 r csui x bit 6 r lcdi x bit 5 r crui x bit 4 r tacpi x bit 3 r racpi x bit 2 r rpopi x bit 1 r rlopi x bit 0 r rsopi x when the interrupt output intb goes low, this register allows the source of an active interrupt to be identified down to the block level. further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. rsopi: the rsopi bit is high when an interrupt request is active from the rsop block. the rsop interrupt sources are enabled in the rsop control/interrupt enable register. rlopi: the rlopi bit is high when an interrupt request is active from the rlop block. the rlop interrupt sources are enabled in the rlop interrupt enable/status register. rpopi: the rpopi bit is high when an interrupt request is active from the rpop block. the rpop interrupt sources are enabled in the rpop interrupt enable register. racpi: the racpi bit is high when an interrupt request is active from the racp block. the racp interrupt sources are enabled in the racp interrupt enable/status register.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 55 ta c p i : the tacpi bit is high when an interrupt request is active from the tacp block. the tacp interrupt sources are enabled in the tacp interrupt control/status register. csui: the csui bit is high when an interrupt request is active from the clock synthesis unit. the csu interrupt sources are enabled in the clock synthesis interrupt control/status register. lcdi: the lcdi interrupt bit is set high when entering and exiting loss of cell delineation. this bit is reset immediately after a read to this register. the lcd interrupt is enabled in the s/uni-ultra master control register. crui: the crui bit is high when an interrupt request is active from the clock recovery unit. the cru interrupt sources are enabled in the clock recovery interrupt control/status register.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 56 register 0x03: s/uni-ultra master mode control bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w rate[1] 1 bit 0 r/w rate[0] 1 rate[1:0]: the rate[1:0] bits select the operation rate of the s/uni-ultra. the default configuration selects sts-3c rate operation. the s/uni-ultra will not operate correctly if a reserved mode is selected. rate[1:0] mode 00 reserved 01 reserved 10 51.84 mbit/s, sts-1 11 155.52 mbit/s, sts-3c/stm-1
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 57 register 0x04: s/uni-ultra master clock monitor bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r rfclka x bit 3 r tfclka x bit 2 r refclka x bit 1 r rclka x bit 0 r tclka x this register provides activity monitoring on s/uni-ultra clocks. when a monitored clock signal makes a low to high transition, the corresponding register bit is set high. the bit will remain high until this register is read, at which point, all the bits in this register are cleared. a lack of transitions is indicated by the corresponding register bit reading low. this register should be read at periodic intervals to detect clock failures. tclka: the tclk active (tclka) bit monitors for low to high transitions on the tclk output. tclka is set high on a rising edge of tclk, and is set low when this register is read. rclka: the rclk active (rclka) bit monitors for low to high transitions on the rclk output. rclka is set high on a rising edge of rclk, and is set low when this register is read. refclka: the refclk active (refclka) bit monitors for low to high transitions on the refclk reference clock input. refclka is set high on a rising edge of refclk, and is set low when this register is read.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 58 tfclka: the tfclk active (tfclka) bit monitors for low to high transitions on the tfclk transmit fifo clock input. tfclka is set high on a rising edge of tfclk, and is set low when this register is read. rfclka: the rfclk active (rfclka) bit monitors for low to high transitions on the rfclk receive fifo clock input. rfclka is set high on a rising edge of rfclk, and is set low when this register is read.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 59 register 0x05: s/uni-ultra master control bit type function default bit 7 r/w lcde 0 bit 6 r lcdv x bit 5 r/w fixptr 1 bit 4 r/w tple 0 bit 3 r/w pdle 0 bit 2 r/w lle 0 bit 1 r/w sdle 0 bit 0 r/w loopt 0 this register controls the timing and high speed loopback features of the s/uni- ultra. loopt: the loopt bit selects the source of timing for the transmit section of the s/uni-ultra. when loopt is a logic zero, the transmitter timing is derived from input refclk. only one of the loopt, sdle and lle bits can be set to iogic one at any time . when loopt is a logic one, the transmitter timing is derived from the receiver inputs rxd+ and rxd- when the cru is locked on data (rdool is low) and from refclk when the cru is out of data lock (rdool is high). sdle: the sdle bit enables the s/uni-ultra serial diagnostic loopback. when sdle is a logic one, the transmit stream is connected to the receive stream. only one of the loopt, sdle and lle bits can be set to iogic one at any time . lle: the lle bit enables the s/uni-ultra line loopback. when lle is a logic one, the receive serial data stream is looped back into the transmit serial stream. this loopback mode includes the rutp-5, cru, csu and tutp-5 blocks. only one of the loopt, sdle and lle bits can be set to iogic one at any time .
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 60 pdle: the pdle bit enables the s/uni-ultra parallel diagnostic loopback. when pdle is a logic one, the transmit parallel stream is connected to the receive stream. the loopback point is between the tpop and the rpop blocks. blocks upstream of the loopback point continue to operate normally. for example, line ais may still be inserted in the transmit stream using tsop. tple: the tple bit enables the s/uni-ultra twisted pair diagnostic loopback. when tple is a logic one, the receive serial data stream is looped back into the transmit serial stream. this loopback mode includes only the rutp-5 and tutp-5 blocks. fixptr: the fixptr bit disables transmit payload pointer adjustments. if the fixptr bit is a logic 1, the transmit payload pointer is set at 522. if fixptr is a logic zero, the payload pointer is controlled by the contents of the tpop pointer control register. lcdv: the lcdv bit reflects the current loss of cell delineation state. lcdv becomes a logic 1 when an out of cell delineation state has persisted for 4ms without any lower level alarms (los, lop, path ais, line ais) occurring. lcdv becomes logic 0 when the sync state has been maintained for 4ms. lcde: the lcde bit enables the loss of cell delineation (lcd) interrupt. when logic one, the s/uni-ultra intb output is asserted when there is a change in the lcd state. when logic zero, the s/uni-ultra intb output is not affected by the change in lcd state.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 61 register 0x06: s/uni-ultra clock synthesis control and status bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 r trooli x bit 4 unused x bit 3 r troolv x bit 2 unused x bit 1 r/w troole 0 bit 0 r/w reserved 0 this register controls the clock synthesis and reports the state of the transmit phase locked loop. troole: the troole bit is an interrupt enable for the transmit reference out of lock status. when troole is set to logic one, an interrupt is generated when the troolv bit changes state. troolv: the transmit reference out of lock status indicates the clock synthesis phase locked loop is unable to lock to the reference on refclk. troolv is a logic one if the divided down synthesized clock frequency not within 488 ppm of the refclk frequency. trooli: the trooli bit is the transmit reference out of lock interrupt status bit. trooli is set high when the troolv bit of the s/uni-ultra clock synthesis control and status register changes state. troolv indicates the clock synthesis phase locked loop is unable to lock to the reference on refclk and is a logic one if the divided down synthesized clock frequency not within 488 ppm of the refclk frequency. trooli is cleared when this register is read. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 62 register 0x08: s/uni-ultra clock recovery control and status bit type function default bit 7 r/w reserved 0 bit 6 r rrooli x bit 5 r rdooli x bit 4 r rroolv x bit 3 r rdoolv x bit 2 r/w rroole 0 bit 1 r/w rdoole 0 bit 0 r/w reserved 0 this register controls the clock recovery and reports the state of the receive phase locked loop. rdoole: the rdoole bit is an interrupt enable for the receive data out of lock status. when rdoole is set to logic one, an interrupt is generated when the rdoolv bit changes state. rroole: the rroole bit is an interrupt enable for the reference out of lock status. when rroole is set to logic one, an interrupt is generated when the rroolv bit changes state. rdoolv: the receive data out of lock status indicates the clock recovery phase locked loop is unable to lock to the incoming data stream. rdoolv is a logic one if the divided down recovered clock frequency is not within 488 ppm of the refclk frequency or if no transitions have occurred on the rxd+/- inputs for more than 80 bit periods. rroolv: the receive reference out of lock status indicates the clock recovery phase locked loop is unable to lock to the receive reference (refclk). rroolv should be polled after a power up reset to determine when the cru pll is operational. when rroolv is a logic 1, the cru is unable to lock to the
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 63 receive reference. when rroolv is a logic 0, the cru is locked to the receive reference. the rroolv bit may remain set at logic 1 for several hundred milliseconds after the removal of the power on reset as the cru pll locks to the receive reference clock. rdooli: the rdooli bit is the receive data out of lock interrupt status bit. rdooli is set high when the rdoolv bit of the s/uni-ultra clock recovery control and status register changes state. rdooli is cleared when this register is read. rrooli: the rrooli bit is the receive reference out of lock interrupt status bit. rrooli is set high when the rroolv bit of the clock synthesis control and status register changes state. rrooli is cleared when this register is read. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 64 register 0x09: s/uni-ultra clock recovery configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w reserved 1 bit 1 r/w reserved 1 bit 0 r/w reserved 1 reserved: the reserved bits must be programmed to logic one for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 65 register 0x0a: s/uni-ultra line transmitter configuration 1 bit type function default bit 7 r/w vrefsel 0 bit 6 unused x bit 5 r/w oen 1 bit 4 r/w otq 0 bit 3 r/w reserved 1 bit 2 r/w reserved 1 bit 1 r/w reserved 0 bit 0 r/w reserved 0 this register controls the s/uni-ultra pecl/twisted-pair transmitter. otq: the output true quiet (otq) bit, when set to logic 1, puts the txd+/- outputs into a "true quiet" mode, where the output current is split equally between the two outputs. when otq is set to logic 0 the txd+/- outputs operate normally. oen: the output enable (oen) bit enables the txd+ and txd- outputs. when this signal is set to logic 0, txd+ and txd- are high-impedance. when this signal is set to logic 1, txd+ and txd- operate in their normal mode. vrefsel: the voltage reference select (vrefsel) bit selects which reference voltage will be used. when vrefsel is set to logic 0, the internal reference voltage is selected. when vrefsel is set to logic 1, the external reference (vref) is selected. reserved: the reserved bits must be programmed to logic 0 or logic 1 for proper operation, as indicated by their default value.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 66 register 0x0b: s/uni-ultra line transmitter configuration 2 bit type function default bit 7 r/w reserved 1 bit 6 r/w reserved 1 bit 5 r/w reserved 1 bit 4 r/w reserved 1 bit 3 r/w reserved 1 bit 2 r/w reserved 1 bit 1 r/w reserved 1 bit 0 r/w reserved 1 this register controls the s/uni-ultra pecl/twisted-pair transmitter. reserved: the reserved bits must be programmed to logic one for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 67 register 0x0c: s/uni-ultra line receiver configuration bit type function default bit 7 unused x bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 1 this register controls the s/uni-ultra pecl/twisted-pair receiver. reserved: the reserved bits must be programmed to logic 0 or logic 1 for proper operation, as indicated by their default value.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 68 register 0x10: rsop control/interrupt enable bit type function default bit 7 r/w reserved 0 bit 6 r/w dds 0 bit 5 w foof x bit 4 r/w reserved 0 bit 3 r/w bipee 0 bit 2 r/w lose 0 bit 1 r/w lofe 0 bit 0 r/w oofe 0 oofe: the oofe bit is an interrupt enable for the out of frame alarm. when oofe is set to logic one, an interrupt is generated when the out of frame alarm changes state. lofe: the lofe bit is an interrupt enable for the loss of frame alarm. when lofe is set to logic one, an interrupt is generated when the loss of frame alarm changes state. lose: the lose bit is an interrupt enable for the loss of signal alarm. when lose is set to logic one, an interrupt is generated when the loss of signal alarm changes state. bipee: the bipee bit is an interrupt enable for the section bip-8 errors. when bipee is set to logic one, an interrupt is generated when a section bip-8 error (b1) is detected. foof: the foof bit controls the framing of the rsop. when a logic one is written to foof, the rsop is forced out of frame at the next frame boundary. the foof bit is a write only bit, register reads may yield a logic one or a logic zero.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 69 dds: the dds bit is set to logic one to disable the descrambling of the sts-3c (stm-1) or sts-1 stream. when dds is a logic zero, descrambling is enabled. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 70 register 0x11: rsop status/interrupt status bit type function default bit 7 unused x bit 6 r bipei x bit 5 r losi x bit 4 r lofi x bit 3 r oofi x bit 2 r losv x bit 1 r lofv x bit 0 r oofv x oofv: the oofv bit is read to determine the out of frame state of the rsop. when oofv is high, the rsop is out of frame. when oofv is low, the rsop is in-frame. lofv: the lofv bit is read to determine the loss of frame state of the rsop. when lofv is high, the rsop has declared loss of frame. losv: the losv bit is read to determine the loss of signal state of the rsop. when losv is high, the rsop has declared loss of signal. oofi: the oofi bit is the out of frame interrupt status bit. oofi is set high when a change in the out of frame state occurs. this bit is cleared when this register is read. lofi: the lofi bit is the loss of frame interrupt status bit. lofi is set high when a change in the loss of frame state occurs. this bit is cleared when this register is read.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 71 losi: the losi bit is the loss of signal interrupt status bit. losi is set high when a change in the loss of signal state occurs. this bit is cleared when this register is read. bipei: the bipei bit is the section bip-8 interrupt status bit. bipei is set high when a section layer (b1) bit error is detected. this bit is cleared when this register is read.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 72 register 0x12: rsop section bip-8 lsb bit type function default bit 7 r sbe[7] x bit 6 r sbe[6] x bit 5 r sbe[5] x bit 4 r sbe[4] x bit 3 r sbe[3] x bit 2 r sbe[2] x bit 1 r sbe[1] x bit 0 r sbe[0] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 73 register 0x13: rsop section bip-8 msb bit type function default bit 7 r sbe[15] x bit 6 r sbe[14] x bit 5 r sbe[13] x bit 4 r sbe[12] x bit 3 r sbe[11] x bit 2 r sbe[10] x bit 1 r sbe[9] x bit 0 r sbe[8] x sbe[15:0]: bits sbe[15:0] represent the number of section bip-8 errors (b1) that have been detected since the last time the error count was polled. the error count is polled by writing to either of the rsop section bip-8 register addresses. such a write transfers the internally accumulated error count to the section bip-8 registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that ensures that coincident events are not lost. the error count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop and racp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 74 register 0x14: tsop control bit type function default bit 7 unused x bit 6 r/w ds 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w lais 0 lais: the lais bit controls the insertion of line alarm indication signal (ais). when lais is set to logic one, the tsop inserts ais into the transmit sonet stream. activation or deactivation of line ais insertion is synchronized to frame boundaries. line ais insertion results in all bits of the sonet frame being set to 1 prior to scrambling except for the section overhead. the dc1 bit controls the overwriting of the identity byte(s) in the sts-3c stream. when dc1 is set low, the identity bytes of the constituent sts-1s in the sts-3c stream are programmed as specified in the references: sts-1 #1 c1 = 01 hexadecimal, sts-1 #2 c1 = 02 hexadecimal,.., sts-1 #n c1 = n hexadecimal. when dc1 is set high the pin[7:0] identity byte positions in each of the constituent sts-1s are not overwritten. ds: the ds bit is set to logic one to disable the scrambling of the sts-3c (stm-1) or stsC1 stream. when ds is a logic zero, scrambling is enabled. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 75 register 0x15: tsop diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w dlos 0 bit 1 r/w dbip8 0 bit 0 r/w dfp 0 dfp: the dfp bit controls the insertion of a single bit error continuously in the most significant bit (bit 1) of the a1 section overhead framing byte. when dfp is set to logic one, the a1 bytes are set to 0x76 instead of 0xf6. dbip8: the dbip8 bit controls the insertion of bit errors continuously in the section bip-8 byte (b1). when dbip8 is set to logic one, the b1 byte is inverted. dlos: the dlos bit controls the insertion of all zeros in the transmit stream. when dlos is set to logic one, the transmit stream is forced to 0x00.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 76 register 0x18: rlop control/status bit type function default bit 7 r/w bipword 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 unused x bit 1 r laisv 0 bit 0 r rdiv 0 rdiv: the rdiv bit is read to determine the remote defect indication state of the rlop. when rdiv is high, the rlop has declared line rdi. laisv: the laisv bit is read to determine the line ais state of the rlop. when laisv is high, the rlop has declared line ais. bipword: the bipword bit controls the accumulation of b2 errors. when bipword is logic one, the b2 error event counter is incremented only once per frame whenever one or more b2 bit errors occur during that frame. when bipword is logic zero, the b2 error event counter is incremented for each b2 bit error that occurs during that frame (the counter can be incremented up to 8 times per frame for sts-1 and 24 times per frame for sts-3c). reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 77 register 0x19: rlop interrupt enable/interrupt status bit type function default bit 7 r/w febee 0 bit 6 r/w bipee 0 bit 5 r/w laise 0 bit 4 r/w rdie 0 bit 3 r febei x bit 2 r bipei x bit 1 r laisi x bit 0 r rdii x rdii: the rdii bit is the far end receive failure interrupt status bit. rdii is set high when a change in the line rdi state occurs. this bit is cleared when this register is read. laisi: the laisi bit is the line ais interrupt status bit. laisi is set high when a change in the line ais state occurs. this bit is cleared when this register is read. bipei: the bipei bit is the line bip interrupt status bit. bipei is set high when a line layer (b2) bit error is detected. this bit is cleared when this register is read. febei: the febei bit is the line far end block error interrupt status bit. febei is set high when a line layer febe (m0/m1) is detected. this bit is cleared when this register is read. rdie: the rdie bit is an interrupt enable for the far end receive failure alarm. when rdie is set to logic one, an interrupt is generated when rdi changes state.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 78 laise: the laise bit is an interrupt enable for line ais. when laise is set to logic one, an interrupt is generated when line ais changes state. bipee: the bipee bit is an interrupt enable for the line bip-24 errors. when bipee is set to logic one, an interrupt is generated when a line bip-24 error (b2) is detected. febee: the febee bit is an interrupt enable for the line far end block errors. when febe (m0/m1) is detected.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 79 register 0x1a: rlop line bip-8/24 lsb bit type function default bit 7 r lbe[7] x bit 6 r lbe[6] x bit 5 r lbe[5] x bit 4 r lbe[4] x bit 3 r lbe[3] x bit 2 r lbe[2] x bit 1 r lbe[1] x bit 0 r lbe[0] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 80 register 0x1b: rlop line bip-8/24 bit type function default bit 7 r lbe[15] x bit 6 r lbe[14] x bit 5 r lbe[13] x bit 4 r lbe[12] x bit 3 r lbe[11] x bit 2 r lbe[10] x bit 1 r lbe[9] x bit 0 r lbe[8] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 81 register 0x1c: rlop line bip-8/24 msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r lbe[19] x bit 2 r lbe[18] x bit 1 r lbe[17] x bit 0 r lbe[16] x lbe[19:0] bits lbe[19:0] represent the number of line bip-8/24 errors (b2) that have been detected since the last time the error count was polled. the error count is polled by writing to any of the rlop line bip register or line febe register addresses. such a write transfers the internally accumulated error count to the line bip registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. the error count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 82 register 0x1d: rlop line febe lsb bit type function default bit 7 r lfe[7] x bit 6 r lfe[6] x bit 5 r lfe[5] x bit 4 r lfe[4] x bit 3 r lfe[3] x bit 2 r lfe[2] x bit 1 r lfe[1] x bit 0 r lfe[0] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 83 register 0x1e: rlop line febe bit type function default bit 7 r lfe[15] x bit 6 r lfe[14] x bit 5 r lfe[13] x bit 4 r lfe[12] x bit 3 r lfe[11] x bit 2 r lfe[10] x bit 1 r lfe[9] x bit 0 r lfe[8] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 84 register 0x1f: rlop line febe msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r lfe[19] x bit 2 r lfe[18] x bit 1 r lfe[17] x bit 0 r lfe[16] x lfe[19:0] bits lfe[19:0] represent the number of line febe errors (m0/m1) that have been detected since the last time the error count was polled. the error count is polled by writing to any of the rlop line bip register or line febe register addresses. such a write transfers the internally accumulated error count to the line febe registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. the error count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 85 register 0x20: tlop control bit type function default bit 7 unused x bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w rdi 0 rdi: the rdi bit controls the insertion of line far end receive failure (rdi). when rdi is set to logic one, the tlop inserts line rdi into the transmit sonet stream. line rdi is inserted by transmitting the code 110 in bit positions 6, 7, and 8 of the k2 byte of the transmit stream. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 86 register 0x21: tlop diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r/w dbip 0 dbip: the dbip bit controls the insertion of bit errors continuously in the line bip byte(s) (b2). when dbip is set to logic one, the b2 byte(s) are inverted.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 87 register 0x30: rpop status/control bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 r lop x bit 4 unused x bit 3 r pais x bit 2 r prdi x bit 1 unused x bit 0 r/w reserved 0 this register allows the status of path level alarms to be monitored. prdi, pais,lop: the prdi, pais, and lop bits reflect the current state of the corresponding path level alarms. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 88 register 0x31: rpop interrupt status bit type function default bit 7 r psli x bit 6 unused x bit 5 r lopi x bit 4 unused x bit 3 r paisi x bit 2 r prdii x bit 1 r bipei x bit 0 r febei x this register allows identification and acknowledgment of path level alarm and error event interrupts. febei, bipei: the bipei and febei bits are set to logic one when the corresponding event, a path bip-8 error or path febe is detected. prdii, paisi, lopi: the prdii, paisi, and lopi bits are set to logic one when a transition occurs in the corresponding alarm state. psli: the psli bit is set to logic one when a change is detected in the path signal label register. the current path signal label can be read from the rpop path signal label register. these bits (and the interrupt) are cleared when this register is read.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 89 register 0x33: rpop interrupt enable bit type function default bit 7 r/w psle 0 bit 6 r/w reserved 0 bit 5 r/w lope 0 bit 4 r/w reserved 0 bit 3 r/w paise 0 bit 2 r/w prdie 0 bit 1 r/w bipee 0 bit 0 r/w febee 0 this register allows interrupt generation to be enabled for path level alarm and error events. febee: when a 1 is written to the febee interrupt enable bit position, the reception of one or more febes will activate the interrupt output. bipee: when a 1 is written to the bipee interrupt enable bit position, the detection of one or more path bip-8 errors will activate the interrupt output. prdie, paise: when a 1 is written to the prdie interrupt enable bit position, a change in the path remote defect indication state will activate the interrupt output. when a 1 is written to the paise interrupt enable bit position, a change in the path ais state will activate the interrupt output. lope: when a 1 is written to the lope interrupt enable bit position, a change in the loss of pointer state will activate the interrupt output. psle: when a 1 is written to the psle interrupt enable bit position, a change in the path signal label will activate the interrupt output.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 90 reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 91 register 0x37: rpop path signal label bit type function default bit 7 r psl[7] x bit 6 r psl[6] x bit 5 r psl[5] x bit 4 r psl[4] x bit 3 r psl[3] x bit 2 r psl[2] x bit 1 r psl[1] x bit 0 r psl[0] x this register allows the received path signal label byte to be read. psl[7:0]: the psl7 - psl0 bits contain the path signal label byte (c2). the value in this register is updated to a new path signal label value if the same new value is observed for three consecutive frames.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 92 register 0x38: rpop path bip-8 lsb bit type function default bit 7 r pbe[7] x bit 6 r pbe[6] x bit 5 r pbe[5] x bit 4 r pbe[4] x bit 3 r pbe[3] x bit 2 r pbe[2] x bit 1 r pbe[1] x bit 0 r pbe[0] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 93 register 0x39: rpop path bip-8 msb bit type function default bit 7 r pbe[15] x bit 6 r pbe[14] x bit 5 r pbe[13] x bit 4 r pbe[12] x bit 3 r pbe[11] x bit 2 r pbe[10] x bit 1 r pbe[9] x bit 0 r pbe[8] x these registers allow path bip-8 errors to be accumulated. pbe[15:0]: bits pbe[15:0] represent the number of path bip-8 errors (b3) that have been detected since the last time the error count was polled. the error count is polled by writing to either of the rpop path bip-8 register addresses or to either of the rpop path febe register addresses. such a write transfers the internally accumulated error count to the path bip-8 registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that ensures that coincident events are not lost. the error count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 94 register 0x3a: rpop path febe lsb bit type function default bit 7 r pfe7 x bit 6 r pfe6 x bit 5 r pfe5 x bit 4 r pfe4 x bit 3 r pfe3 x bit 2 r pfe2 x bit 1 r pfe1 x bit 0 r pfe0 x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 95 register 0x3b: rpop path febe msb bit type function default bit 7 r pfe15 x bit 6 r pfe14 x bit 5 r pfe13 x bit 4 r pfe12 x bit 3 r pfe11 x bit 2 r pfe10 x bit 1 r pfe9 x bit 0 r pfe8 x these registers allow path febes to be accumulated. pfe[15:0]: bits pfe[15:0] represent the number of path febe errors (g1) that have been detected since the last time the error count was polled. the error count is polled by writing to either of the rpop path bip-8 register addresses or to either of the rpop path febe register addresses. such a write transfers the internally accumulated error count to the path febe registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that ensures that coincident events are not lost. the error count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 96 register 0x3d: rpop path bip-8 configuration bit type function default bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w blkbip 0 bit 4 r/w reserved 0 bit 3 unused x bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 blkbip: when set high, the block bip-8 bit (blkbip) indicates that path bip-8 errors are to be reported and accumulated on a block basis. a single bip error is accumulated and reported to the return transmit path overhead processor if one or more of the bip-8 results indicates a mismatch. when blkbip is set low, bip-8 errors are accumulated and reported on a bit basis. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 97 register 0x40: tpop control/diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w reserved 0 bit 1 r/w db3 0 bit 0 r/w pais 0 this register allows insertion of path level alarms and diagnostic signals. pa i s : the pais bit controls the insertion of sts path alarm indication signal. when a logic one is written to this bit position, the complete spe, and the pointer bytes (h1, h2, and h3) are overwritten with the all ones pattern. when a logic zero is written to this bit position, the pointer bytes and the spe are processed normally. db3: the db3 bit controls the inversion of the b3 byte value. when a logic one is written to this bit position, the b3 byte is inverted, causing the insertion of eight path bip-8 errors per frame. when a logic zero is written to this bit position, the b3 byte is transmitted uncorrupted. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 98 register 0x41: tpop pointer control bit type function default bit 7 unused x bit 6 r/w ftptr 0 bit 5 r/w sos 0 bit 4 r/w pld 0 bit 3 r/w ndf 0 bit 2 r/w nse 0 bit 1 r/w pse 0 bit 0 r/w reserved 0 this register allows control over the transmitted payload pointer for diagnostic purposes. pse: the pse bit controls the insertion of positive pointer movements. a zero to one transition on this bit enables the insertion of a single positive pointer justification in the outgoing stream. this register bit is automatically cleared when the pointer movement is inserted. this bit has no effect if the fixptr bit of the master control register is a logic 1. nse: the nse bit controls the insertion of negative pointer movements. a zero to one transition on this bit enables the insertion of a single negative pointer justification in the outgoing stream. this register bit is automatically cleared when the pointer movement is inserted. this bit has no effect if the fixptr bit of the master control register is a logic 1. ndf: the ndf bit controls the insertion of new data flags in the inserted payload pointer. when a logic one is written to this bit position, the pattern contained in the ndf[3:0] bit positions in the arbitrary pointer msb register is inserted continuously in the payload pointer. when a logic zero is written to this bit position, the normal pattern (0110) is inserted in the payload pointer.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 99 pld: the pld bit controls the loading of the pointer value contained in the arbitrary pointer registers. normally, the arbitrary pointer registers are written to set up the arbitrary new pointer value and a logic one is then written to this bit position to load the new pointer value. if a legal value (i.e. 0 ? pointer value ? 782) is transferred from the arbitrary pointer registers, the transmit payload pointer will immediately change to the corresponding byte position. if a value greater than 782 is transferred, the payload pointer remains unchanged. this bit is automatically cleared after the new payload pointer has been loaded. this bit has no effect if the fixptr bit of the master control register is a logic 1. sos: the sos bit controls the stuff opportunity spacing between consecutive spe positive or negative stuff events. when sos is a logic zero, stuff events may be generated every frame as controlled by the pse and nse register bits described above. when sos is a logic one, stuff events may be generated at a maximum rate of once every four frames. ftptr: the force transmit pointer bit (ftptr) enables the insertion of the pointer value contained in the arbitrary pointer registers into the transmit stream for diagnostic purposes. this allows upstream payload mapping circuitry to continue functioning normally and a valid spe to continue to be generated, although it is unlikely to be extracted by far end circuitry. if ftptr is set to logic 1, the aptr[9:0] bits of the arbitrary pointer registers are inserted into the h1 and h2 bytes of the transmit stream. at least one corrupted pointer is guaranteed to be sent. if ftptr is a logic 0, a valid pointer is inserted. this bit has no effect if the fixptr bit of the master control register is a logic 1. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 100 register 0x45: tpop arbitrary pointer lsb bit type function default bit 7 r/w aptr[7] 0 bit 6 r/w aptr[6] 0 bit 5 r/w aptr[5] 0 bit 4 r/w aptr[4] 0 bit 3 r/w aptr[3] 0 bit 2 r/w aptr[2] 0 bit 1 r/w aptr[1] 0 bit 0 r/w aptr[0] 0 this register allows an arbitrary pointer to be inserted for diagnostic purposes. aptr[7], aptr[6], aptr[5], aptr[4], aptr[3], aptr[2], aptr[1], aptr[0]: the aptr[7:0] bits, along with the aptr[9:8] bits in the arbitrary pointer msb register are used to set an arbitrary payload pointer value. the arbitrary pointer value is transferred by writing a logic one to the pld bit in the pointer control register. a legal value (i.e. 0 ? pointer value ? 782) results in the transmit payload pointer immediately changing to the corresponding byte position. if a value greater than 782 is transferred, the payload pointer remains unchanged. if the ftptr bit in the pointer control register is a logic 1, the current aptr[9:0] value is inserted into the payload pointer bytes (h1 and h2) in the transmit stream.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 101 register 0x46: tpop arbitrary pointer msb bit type function default bit 7 r/w ndf[3] 1 bit 6 r/w ndf[2] 0 bit 5 r/w ndf[1] 0 bit 4 r/w ndf[0] 1 bit 3 r/w s[1] 0 bit 2 r/w s[0] 0 bit 1 r/w aptr[9] 0 bit 0 r/w aptr[8] 0 this register allows an arbitrary pointer to be inserted for diagnostic purposes. aptr[9], aptr[8]: the aptr[9:8] bits, along with the aptr[7:0] bits in the tpop arbitrary pointer lsb register are used to set an arbitrary payload pointer value. the arbitrary pointer value is inserted in the outgoing stream by writing a logic one to the pld bit in the tpop pointer control register. s[1], s[0]: the s[1:0] bits contain the value inserted in the s[1:0] bit positions (also referred to as the unused bits) in the payload pointer. ndf[3], ndf[2], ndf[1], ndf[0]: the ndf[3:0] bits contain the value inserted in the ndf bit positions when an arbitrary new payload pointer value is inserted (using the pld bit in the pointer control register) or when new data flag generation is enabled using the ndf bit in the tpop pointer control register.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 102 register 0x48: tpop path signal label bit type function default bit 7 r/w c2[7] 0 bit 6 r/w c2[6] 0 bit 5 r/w c2[5] 0 bit 4 r/w c2[4] 1 bit 3 r/w c2[3] 0 bit 2 r/w c2[2] 0 bit 1 r/w c2[1] 1 bit 0 r/w c2[0] 1 this register allows control over the path signal label. c2[7], c2[6], c2[5], c2[4], c2[3], c2[2], c2[1], c2[0]: the c2[7:0] bits are inserted in the c2 byte position in the transmit stream.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 103 register 0x49: tpop path status bit type function default bit 7 r/w febe[3] 0 bit 6 r/w febe[2] 0 bit 5 r/w febe[1] 0 bit 4 r/w febe[0] 0 bit 3 r/w prdi 0 bit 2 r/w g1[2] 0 bit 1 r/w g1[1] 0 bit 0 r/w g1[0] 0 this register allows control over the path status byte. febe[3], febe[2], febe[1], febe[0]: the febe[3:0] bits are inserted in the febe bit positions in the path status byte. the value contained in febe[3:0] is cleared after being inserted in the path status byte. any non-zero febe[3:0] value overwrites the value that would normally have been inserted based on the number of febes accumulated during the last frame. when reading this register, a non-zero value in these bit positions indicates that the insertion of this value is still pending. prdi: the prdi bit controls the insertion of the path remote defect indication (rdi). when a logic one is written to this bit position, the prdi bit position in the path status byte (g1) is set high. if the autordi bit is a logic one, an alarm state also sets the prdi bit high. when a logic zero is written to this bit position, the prdi bit position in the path status byte is set low provided autordi is low or no alarms are currently active. g1[2], g1[1], g1[0]: the g1[2:0] bits are inserted in the unused bit positions in the path status byte.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 104 register 0x50: racp control/status bit type function default bit 7 r oocdv x bit 6 r/w rxptyp 0 bit 5 r/w pass 0 bit 4 r/w discor 0 bit 3 r/w hcspass 0 bit 2 r/w hcsadd 1 bit 1 r/w ddscr 0 bit 0 r/w fiforst 0 fiforst: the fiforst bit is used to reset the four cell receive fifo. when fiforst is set to logic zero, the fifo operates normally. when fiforst is set to logic one, the fifo is immediately emptied and ignores writes. the fifo remains empty and continues to ignore writes until a logic zero is written to fiforst. ddscr: the ddscr bit controls the descrambling of the cell payload. when ddscr is a logic one, cell payload descrambling is disabled. when ddscr is a logic zero, payload descrambling is enabled. hcsadd: the hcsadd bit controls the addition of the coset polynomial, x 6 +x 4 +x 2 +1, to the hcs octet prior to comparison. when hcsadd is a logic one, the polynomial is added, and the resulting hcs is compared. when hcsadd is a logic zero, the polynomial is not added, and the unmodified hcs is compared. hcspass: the hcspass bit controls the dropping of cells based on the detection of an uncorrectable hcs error. when hcspass is a logic zero, cells containing an uncorrectable hcs error are dropped. when hcspass is a logic one, cells are passed to the receive fifo regardless of errors detected in the hcs. in addition, the hcs verification finite state machine never exits the correction
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 105 mode. regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'hunt' or 'presync' states. discor: the discor bit disables the hcs error correction algorithm. when discor is a logic zero, the error correction algorithm is enabled, and single bit errors detected in the cell header are corrected. when discor is a logic one, the error correction algorithm is disabled, and any error detected in the cell header is treated as an uncorrectable hcs error. pass: the pass bit controls the function of the cell filter. when pass is written with a logic zero, all cells matching the cell filter are dropped. when pass is a logic one, the match header pattern registers are ignored and filtering of cells with vpi and vci fields set to 0 is not performed. the default state of this bit together with the default states of the bits in the match mask and match pattern registers enable the dropping of cells containing all zero vci and vpi fields. rxptyp: the rxptyp bit selects even or odd parity for outputs rxprty. when it is set to logic one, output rxprty is the even parity bit for outputs rdat[7:0]. when it is set to logic zero, rxprty is the odd parity bits for outputs rdat[7:0]. oocdv: the oocdv bit indicates the cell delineation state. when oocdv is set high, the cell delineation state machine is in the 'hunt' or 'presync' states, and is hunting for the cell boundaries in the synchronous payload envelope. when oocdv is set low, the cell delineation state machine is in the 'sync' state and cells are passed through the receive fifo.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 106 register 0x51: racp interrupt enable/status bit type function default bit 7 r/w oocde 0 bit 6 r/w hcse 0 bit 5 r/w fifoe 0 bit 4 r oocdi x bit 3 r chcsi x bit 2 r uhcsi x bit 1 r fovri x bit 0 unused x fovri: the fovri bit is set high when a fifo overrun occurs. this bit is reset immediately after a read to this register. uhcsi: the uhcsi bit is set high when an uncorrectable hcs error is detected. this bit is reset immediately after a read to this register. chcsi: the chcsi bit is set high when a correctable hcs error is detected. this bit is reset immediately after a read to this register. oocdi: the oocdi bit is set high when a change of cell delineation state has occurred. the oocdi bit is set high when the racp block transitions from the presync state to the sync state and from the sync state to the hunt state. this bit is reset immediately after a read to this register. fifoe: the fifoe bit enables the generation of an interrupt due to a fifo overrun error condition. when fifoe is set to logic one, the interrupt is enabled.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 107 hcse: the hcse bit enables the generation of an interrupt due to the detection of a correctable or an uncorrectable hcs error. when hcse is set to logic one, the interrupt is enabled. oocde: the oocde bit enables the generation of an interrupt due to a change of cell delineation state. when oocde is set to logic one, the interrupt is enabled.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 108 register 0x52: racp match header pattern bit type function default bit 7 r/w gfc[3] 0 bit 6 r/w gfc[2] 0 bit 5 r/w gfc[1] 0 bit 4 r/w gfc[0] 0 bit 3 r/w pti[2] 0 bit 2 r/w pti[1] 0 bit 1 r/w pti[0] 0 bit 0 r/w clp 0 this register extends the cell filtering criteria beyond the all zeros pattern that must be present in the vpi and vci fields of the idle or unassigned cell. the pass bit in the racp control/status register must be set to logic zero to enable dropping of idle/unassigned cells matching the pattern defined by the contents of this register and the racp match header mask register. gfc[3:0]: the gfc[3:0] bits contain the pattern to match in the first, second, third and fourth bits of the first octet of the 53 octet cell, in conjunction with the racp match header mask register. pti[2:0]: the pti[2:0] bits contain the pattern to match in the fifth, sixth and seventh bits of the fourth octet of the 53 octet cell, in conjunction with the racp match header mask register. clp: the clp bit contains the pattern to match in the eighth bit of the fourth octet of the 53 octet cell, in conjunction with the racp match header mask register.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 109 register 0x53: racp match header mask bit type function default bit 7 r/w mgfc[3] 0 bit 6 r/w mgfc[2] 0 bit 5 r/w mgfc[1] 0 bit 4 r/w mgfc[0] 0 bit 3 r/w mpti[2] 0 bit 2 r/w mpti[1] 0 bit 1 r/w mpti[0] 0 bit 0 r/w mclp 0 the mask contained in this register is applied to the racp match header pattern register to select the bits included in the cell filter. a logic one in any bit position enables the corresponding bit in the pattern register to be compared. a logic zero causes the masking of the corresponding bit. mgfc[3:0]: the mgfc[3:0] bits contain the mask pattern for the first, second, third and fourth bits of the first octet of the 53 octet cell. mpti3:0]: the mpti[3:0] bits contain the mask pattern for the fifth, sixth and seventh bits of the fourth octet of the 53 octet cell. mclp: the mclp bit contains the mask pattern for the eighth bit of the fourth octet of the 53 octet cell.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 110 register 0x54: racp correctable hcs error count bit type function default bit 7 r chcs[7] x bit 6 r chcs[6] x bit 5 r chcs[5] x bit 4 r chcs[4] x bit 3 r chcs[3] x bit 2 r chcs[2] x bit 1 r chcs[1] x bit 0 r chcs[0] x chcs[7:0]: the chcs[7:0] bits indicate the number of correctable hcs error events that occurred during the last accumulation interval. the contents of these registers are valid 200 ns after a transfer is triggered by a write to the correctable hcs error count register address, or to the uncorrectable hcs error count register address. the error count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 111 register 0x55: racp uncorrectable hcs error count bit type function default bit 7 r uhcs[7] x bit 6 r uhcs[6] x bit 5 r uhcs[5] x bit 4 r uhcs[4] x bit 3 r uhcs[3] x bit 2 r uhcs[2] x bit 1 r uhcs[1] x bit 0 r uhcs[0] x uhcs[7:0]: the uhcs[7:0] bits indicate the number of uncorrectable hcs error events that occurred during the last accumulation interval. the contents of these registers are valid 200 ns after a transfer is triggered by a write to the correctable hcs error count register address, or to the uncorrectable hcs error count register address. the error count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 112 register 0x56: racp receive cell counter (lsb) bit type function default bit 7 r rcell[7] x bit 6 r rcell[6] x bit 5 r rcell[5] x bit 4 r rcell[4] x bit 3 r rcell[3] x bit 2 r rcell[2] x bit 1 r rcell[1] x bit 0 r rcell[0] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 113 register 0x57: racp receive cell counter bit type function default bit 7 r rcell[15] x bit 6 r rcell[14] x bit 5 r rcell[13] x bit 4 r rcell[12] x bit 3 r rcell[11] x bit 2 r rcell[10] x bit 1 r rcell[9] x bit 0 r rcell[8] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 114 register 0x58: racp receive cell counter (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r rcell[18] x bit 1 r rcell[17] x bit 0 r rcell[16] x rcell[18:0]: the rcell[18:0] bits indicate the number of cells received and written into the receive fifo during the last accumulation interval. cells received and filtered due to hcs errors or idle/unassigned cell matches are not counted. the counter should be polled every second to avoid saturating. the contents of these registers are valid 200 ns after a transfer is triggered by a write to the correctable hcs error count register addresses, the uncorrectable hcs error count register addresses or the receive cell counter register addresses. the cell count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 115 register 0x59: racp configuration bit type function default bit 7 r/w rgfce[3] 1 bit 6 r/w rgfce[2] 1 bit 5 r/w rgfce[1] 1 bit 4 r/w rgfce[0] 1 bit 3 r/w fsen 1 bit 2 r/w rcalevel0 1 bit 1 r/w reserved 0 bit 0 r/w reserved 0 the configuration register is provided at racp read/write address 9. hcsftr[1:0] correction mode reversion cell threshold 00 one atm cell with correct hcs. this error free cell is accepted. 01 two atm cells with correct hcs. error free cells are accepted. 10 four atm cells with correct hcs. error free cells are accepted. 11 eight atm cells with correct hcs. error free cells are accepted. rcalevel0: the rca level 0 bit, rcalevel0, determines what output rca indicates when it transitions low. when rcalevel0 is set to logic one, a high to low transition on output rca indicates that the receive fifo is empty. when rcalevel0 is set to logic zero, a high to low transition on output rca indicates that the receive fifo is near empty and contains four only bytes. fsen: the active high fix stuff control enable bit fsen selects the expected payload mapping of atm cells when sts-1 mapping is selected. when fsen is set to logic one, it is assumed columns 30 and 59 of the synchronous payload
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 116 envelope (spe) contain fixed stuff bytes. when fsen is set to logic zero, it is assumed atm payload fills the entire spe except the path overhead column. rgfce[3:0]: the receive gfc enable bits, rgfce[3:0], determine which generic flow control bits are presented on the rgfc output. rgfce[3] corresponds to the most significant gfc bit (first bit in the cell). if a rgfce bit is a logic 1, the rgfc output presents in the appropriate bit location the state of the associated gfc bit in the current cell; otherwise, rfgc is deasserted low. reserved: the reserved bits must be programmed to logic zero for proper operation.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 117 register 0x60: tacp control/status bit type function default bit 7 r/w fifoe 0 bit 6 r tsoci x bit 5 r fovri x bit 4 r/w dhcs 0 bit 3 r/w hcsb 0 bit 2 r/w hcsadd 1 bit 1 r/w dscr 0 bit 0 r/w fiforst 0 fiforst: the fiforst bit is used to reset the four cell transmit fifo. when fiforst is set to logic zero, the fifo operates normally. when fiforst is set to logic one, the fifo is immediately emptied and ignores writes. the fifo remains empty and continues to ignore writes until a logic zero is written to fiforst. dscr: the dscr bit controls the scrambling of the cell payload. when dscr is a logic one, cell payload scrambling is disabled. when dscr is a logic zero, payload scrambling is enabled. hcsadd: the hcsadd bit controls the addition of the coset polynomial, x 6 +x 4 +x 2 +1, to the hcs octet prior to insertion in the synchronous payload envelope. when hcsadd is a logic one, the polynomial is added, and the resulting hcs is inserted. when hcsadd is a logic zero, the polynomial is not added, and the unmodified hcs is inserted. hcsb: the active low hcs bit enables the internal generation and insertion of the hcs octet into the transmit cell stream. when hcsb is a logic zero, the hcs is generated and inserted internally. when hcsb is a logic one, the hcs octet read from the fifo is inserted transparently into the transmit cell stream.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 118 dhcs: the dhcs bit controls the insertion of hcs errors for diagnostic purposes. when dhcs is set to logic one, the hcs octet is inverted prior to insertion in the synchronous payload envelope. fovri: the fovri bit is set high when a fifo overrun occurs. this bit is reset immediately after a read to this register tsoci: the tsoci bit is set high when the tsoc input is sampled high during any position other than the first byte. the write address counter is reset to the first byte of the cell when tsoc is sampled high. this bit is reset immediately after a read to this register. fifoe: the fifoe bit enables the generation of an interrupt due to a fifo overrun error condition, or when the tsoc input is sampled high during any position other than the first byte. when fifoe is set to logic one, the interrupt is enabled.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 119 register 0x61: tacp idle/unassigned cell header pattern bit type function default bit 7 r/w gfc[3] 0 bit 6 r/w gfc[2] 0 bit 5 r/w gfc[1] 0 bit 4 r/w gfc[0] 0 bit 3 r/w pti[2] 0 bit 2 r/w pti[1] 0 bit 1 r/w pti[0] 0 bit 0 r/w clp 0 gfc[3:0]: the gfc[3:0] bits contain the first, second, third, and fourth bit positions of the first octet of the idle/unassigned cell pattern. cell rate decoupling is accomplished by transmitting idle/unassigned cells when the tacp detects that no outstanding cells exist in the transmit fifo. the all zeros pattern is transmitted in the vci and vpi fields of the idle cell. pti[3:0]: the pti[3:0] bits contain the fifth, sixth, and seventh bit positions of the fourth octet of the idle/unassigned cell pattern. idle cells are transmitted when the tacp detects that no outstanding cells exist in the transmit fifo. clp: the clp bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. idle cells are transmitted when the tacp detects that no outstanding cells exist in the transmit fifo.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 120 register 0x62: tacp idle/unassigned cell payload octet pattern bit type function default bit 7 r/w icp[7] 0 bit 6 r/w icp[6] 1 bit 5 r/w icp[5] 1 bit 4 r/w icp[4] 0 bit 3 r/w icp[3] 1 bit 2 r/w icp[2] 0 bit 1 r/w icp[1] 1 bit 0 r/w icp[0] 0 icp[7:0]: the icp[7:0] bits contain the pattern inserted in the payload octets of the idle or unassigned cell. cell rate decoupling is accomplished by transmitting idle/unassigned cells when the tacp detects that no outstanding cells exist in the transmit fifo. bit icp[7] corresponds to the most significant bit of the octet, the first bit transmitted.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 121 register 0x63: tacp fifo control bit type function default bit 7 r/w txptyp 0 bit 6 r/w txprtye 0 bit 5 reserved x bit 4 r txprtyi x bit 3 r/w fifodp[1] 0 bit 2 r/w fifodp[0] 0 bit 1 r/w tcalevel0 0 bit 0 reserved 0 tcalevel0: the active high tca level 0 bit, tcalevel0 determines what output tca indicates when it transitions low. when tcalevel0 is set to logic one, output tca indicates that the transmit fifo is full and can accept no more writes. when tcalevel0 is set to logic zero, output tca indicates that the transmit fifo is near full and can accept no more than four additional writes. fifodp[1:0]: the fifodp[1:0] bits determine the transmit fifo cell depth. fifo depth control may be important in systems where the cell latency through the tacp must be minimized. when the fifo is filled to the specified depth, the transmit cell available signal, tca is deasserted. tca is asserted only after a complete cell has been read out; therefore, the current cell being read is included in the count. the selectable fifo cell depths are shown below: fifodp[1] fifodp[0] fifo depth 0 0 4 cells 0 1 3 cells 1 0 2 cells 111 cell note that fifodp[1:0] only affects when tca is asserted. all four cells of the fifo may be filled before an over flow is declared.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 122 it is not recommended that the fifo depth be set to 1 cell. if a cell write is initiated only when tca is asserted, half the bandwidth is lost to idle/unassigned cells. for minimum latency and maximum throughput, set the fifo depth to 2 cells. reserved: the reserved bits must be programmed to logic zero for proper operation. txprtyi: the txprtyi bit indicates if a parity error was detected on the tdat[7:0] bus. this bit is cleared when this register is read. odd or even parity is selected using the txptyp bit. txprtye: the txprtye bit enables transmit parity interrupts. when set to logic one, parity errors on inputs tdat[7:0] are indicated by the txprtyi bit and the intb output. when set to logic zero, parity errors are indicated by the txprtyi bit but are not indicated on the intb output. txptyp: the txptyp bit selects even or odd parity for input txprty. when set to logic one input txprty is the even parity bit for inputs tdat[7:0]. when set to logic zero, inputs txprty is the odd parity bit for inputs tdat[7:0].
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 123 register 0x64: tacp transmit cell counter (lsb) bit type function default bit 7 r tcell[7] x bit 6 r tcell[6] x bit 5 r tcell[5] x bit 4 r tcell[4] x bit 3 r tcell[3] x bit 2 r tcell[2] x bit 1 r tcell[1] x bit 0 r tcell[0] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 124 register 0x65: tacp transmit cell counter bit type function default bit 7 r tcell[15] x bit 6 r tcell[14] x bit 5 r tcell[13] x bit 4 r tcell[12] x bit 3 r tcell[11] x bit 2 r tcell[10] x bit 1 r tcell[9] x bit 0 r tcell[8] x
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 125 register 0x66: tacp transmit cell counter (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r tcell[18] x bit 1 r tcell[17] x bit 0 r tcell[16] x tcell[15:0]: the tcell[18:0] bits indicate the number of cells read from the transmit fifo and inserted into the spe during the last accumulation interval. idle/unassigned cells inserted into the spe are not counted. a write to any one of the transmit cell counter registers loads the registers with the current counter value and resets the internal 19 bit counter to 1 or 0. the counter reset value is dependent on if there was a count event during the transfer of the count to the transmit cell counter registers. the counter should be polled every second to avoid saturating. the contents of these registers are valid 200 ns after a transfer is triggered by a write to the transmit cell count register space. the cell count can also be polled by writing to the s/uni-ultra master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 126 register 0x67: tacp configuration bit type function default bit 7 r/w tgfce[3] 0 bit 6 r/w tgfce[2] 0 bit 5 r/w tgfce[1] 0 bit 4 r/w tgfce[0] 0 bit 3 r/w fsen 1 bit 2 r/w h4insb 0 bit 1 r/w fixbyte[1] 0 bit 0 r/w fixbyte[0] 0 fixbyte[1:0]: the fixbyte[1:0] bits identify the byte pattern inserted into fixed byte columns of the synchronous payload envelope. fixbyte[1] fixbyte[0] byte 0 0 00h 0 1 55h 1 0 aah 1 1 ffh h4insb: the active low h4 insert enable, h4insb bit determines the contents of the h4 byte in the outgoing spe. if h4insb is set to logic one, the h4 byte is set to the value of 00 hexadecimal. if h4insb is set to logic zero, the h4 byte is set to the cell indicator offset value. fsen: the active high fix stuff control enable, fsen bit determines the payload mapping of atm cells for sts-1 mapping. when fsen is set to logic one, a fixed pattern is inserted into columns 30 and 59 of the synchronous payload envelope (spe). when fsen is set to logic zero, atm payload fills the entire spe except the path overhead column.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 127 tgfce[3:0]: the gfc enable bits, tgfce[3:0], enable the insertion of the associated gfc bit by the tgfc serial input. if mfc[3] is a logic 1, first bit of the 4 bit serial sequence is inserted into the most significant gfc bit transmitted. likewise, if mfc[0] is a logic 1, last bit of the sequence is inserted into the least significant gfc bit transmitted. if a bit is logic 0, the associated gfc bit value is derived from tdat[7:0] in the case of an assigned cell, or from the idle/unassigned cell header control register in the case of unassigned cells.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 128 register 0x68: s/uni-ultra popc control bit type function default bit 7 r/w pdat[1] 0 bit 6 r/w pdat[0] 0 bit 5 r/w toggle[1] 0 bit 4 r/w toggle[0] 0 bit 3 unused x bit 2 unused x bit 1 r/w traffic 0 bit 0 r/w alarm 1 alarm: the receive alarm interface (alarm) bit determines whether the out[1] output is used as receive alarm (ralm) or as an extension to the parallel output port (out[1:0] output). if alarm is a logic 0, out[1] is an output port bit. if alarm is a logic 1, ralm is used as the receive alarm (ralm). traffic: the traffic monitoring enable (traffic) allows to select between the traffic pulse generation when set high and a programmable rate toggling signal when set low. toggle[1:0]: the output port toggle (toggle[1:0]) bits determine whether the corresponding output port is held at a constant value or toggles at a register defined rate. if toggle is a logic 0, the corresponding pdat value is driven onto its corresponding output, as selected by the alarm bit. if toggle is a logic 1, a logic one in the corresponding pdat enables the toggle rate register for the corresponding output, as selected by the alarm bit. pdat[1:0]: the values written to the pdat[1:0] bits in the s/uni-ultra output port control register either directly correspond to the states set on the out[1:0] output pins or enable the corresponding pin to strobe at a selectable rate. pdat[1] corresponds to output out[1]; pdat[0] corresponds to output
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 129 out[0]. this provides a generic port useful for controlling an external pmd device or supplying external led drivers. refer to the operation section for more details on how to use the parallel output port and led display controller.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 130 register 0x69: s/uni-ultra popc strobe rate 0 bit type function default bit 7 r/w rate0[7] 0 bit 6 r/w rate0[6] 0 bit 5 r/w rate0[5] 1 bit 4 r/w rate0[4] 1 bit 3 r/w rate0[3] 1 bit 2 r/w rate0[2] 1 bit 1 r/w rate0[1] 1 bit 0 r/w rate0[0] 0 rate0[7:0]: the output strobe rate 0 (rate0[7:0]) bits determine the period (in milliseconds increasing in 8 ms increments) of the out[0] output pin. the default setting is for a strobe period of 496 ms, resulting in a 2.0 hz strobe. note that a register value of 0x00 results in a steady logic 0 value.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 131 register 0x6a: s/uni-ultra popc strobe rate 1 bit type function default bit 7 r/w rate1[7] 0 bit 6 r/w rate1[6] 0 bit 5 r/w rate1[5] 0 bit 4 r/w rate1[4] 0 bit 3 r/w rate1[3] 0 bit 2 r/w rate1[2] 1 bit 1 r/w rate1[1] 1 bit 0 r/w rate1[0] 0 rate1[7:0]: the output strobe rate 1 (rate1[7:0]) bits determine the period (in milliseconds increasing in 8 ms increments) of the ralm/out[1] output pin. the default setting is for a strobe period of 48 ms, resulting in a 20.8 hz strobe. note that a register value of 0x00 results in a steady logic 0 value. test features description simultaneously asserting (low) the csb, rdb and wrb inputs causes all digital output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the s/uni-ultra. test mode registers (as opposed to normal mode registers) are selected when trs (a[7]) is high. test mode registers may also be used for board testing. when all of the tsbs within the s/uni-ultra are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "test mode 0" for details). 8.1 test mode register memory map
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 132 address register 0x00-0x7f normal mode registers 0x80 master test 0x81-0xff reserved for test notes on test mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. writable test mode register bits are not initialized upon reset unless otherwise noted.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 133 register 0x80: master test bit type function default bit 7 unused x bit 6 w bypass x bit 5 w pmcatst x bit 4 w pmctst x bit 3 w dbctrl x bit 2 r/w iotst 0 bit 1 w hizdata x bit 0 r/w hizio 0 this register is used to enable s/uni-ultra test features. all bits, except pmctst, pmcatst and bypass are reset to zero by a reset of the s/uni- ultra using either the rstb input or the master reset register. pmctst and bypass are reset when csb is logic 1. pmcatst is reset when both csb is high and rstb is low. pmctst, pmcatst and bypass can also be reset by writing a logic 0 to the corresponding register bit. hizio,hizdata: the hizio and hizdata bits control the tristate modes of the s/uni-ultra . while the hizio bit is a logic one, all output pins of the s/uni-ultra except the data bus are held in a high-impedance state. the microprocessor interface is still active. while the hizdata bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. iotst: the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each tsb block in the s/uni-ultra for board level testing. when iotst is a logic one, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequentially the device outputs (refer to the "test mode 0 details" in the "test features" section).
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 134 dbctrl: the dbctrl bit is used to pass control of the data bus drivers to the csb pin. when the dbctrl bit is set to logic one, the csb pin controls the output enable for the data bus. while the dbctrl bit is set, holding the csb pin high causes the s/uni-ultra to drive the data bus and holding the csb pin low tristates the data bus. the dbctrl bit only has effect if the iotst bit is a logic one. the dbctrl bit overrides the hizdata bit. the dbctrl bit is used to measure the drive capability of the data bus driver pads. pmctst: the pmctst bit is used to configure the s/uni-ultra for pmc's manufacturing tests. when pmctst is set to logic one, the s/uni-ultra microprocessor port becomes the test access port used to run the pmc "canned" manufacturing test vectors. the pmctst bit is logically "ored" with the iotst bit. pmcatst: the pmcatst bit is used to configure the analog portion of the s/uni- ultra for pmc's manufacturing tests. bypass the bypass bit forces the clock recovery and clock synthesis units into a reset, and permits the input data and clock to feed directly into the serial-to- parallel converter. bypass is available for pmc manufacturing test purposes only. 8.2 test mode 0 details in test mode 0, the s/uni-ultra allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface. the iotst bit in the master test register should be set to logic one. to enable test mode 0, the iotst bit in the master test register is set to logic one and the following addresses must be written with 00h: 91h, 95h, 99h, a1h, b1h, d1h and e1h. reading the following address locations returns the values for the indicated inputs :
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 135 addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 82h tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] 83h tfp 3 tgfc xoff tsoc txprty twrenb tfclk 84h rfclk rrdenb tsen the following inputs can not be read using the iotst feature: refclk, rxd+/-, sd, d[7:0], a[7:0], ale, csb, wrb, rdb and rstb. writing the following address locations forces the outputs to the value in the corresponding bit position: addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 90h rfp 2 96h tfp 3 d0h rsoc 4 rca 4 rcp rgfc rxprty 4 int 1 d2h rdat[7] 4 rdat[6] 4 rdat[5] 4 rdat[4] 4 rdat[3] 4 rdat[2] 4 rdat[1] 4 rdat[0] 4 e0h tcp eah out[1] out[0] notes: 1. bit int corresponds to output intb. intb is an open drain output and should be pulled high for proper operation. writing a logic one to the int bit allows the s/uni-ultra to drive intb low. writing a logic zero to the int bit tristates the intb output. 2. rfp must be clocked by vclk at least twice to become valid. 3. tfp is bidirectional and must be configured appropriately using the tfp_in register bit. 4. the corresponding device output is assigned the programmed register value only on a rising edge of rfclk. the following outputs can not be controlled using the iotst feature: txd+/-, tclk, rclk, d[7:0] and tca.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 136 9 operation 9.1 overhead byte usage under normal operating conditions, the s/uni-ultra processes a subset of the complete transport overhead present in an sts-3c/stm-1 stream. the byte positions processed by the s/uni-ultra are indicated in figure figure 8 and figure 9. figure 8 - sts-3c (stm-1) overhead transport overhead soh path overhead poh a1 a1 a1 a2 a2 a2 j0 z0 z0 b1 h1 h1 h1 h2 h2 h2 h3 h3 h3 b2 b2 b2 k2 m1 b3 g1 c2 h4
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 137 figure 9 - sts-1 overhead transport overhead soh path overhead poh a1 a2 j0 b1 h1 h2 h3 b2 k2 b3 g1 c2 h4 m0 a1, a2: the frame alignment bytes (a1, a2) locate the sonet frame in the 155.52 mbit/s data stream. the transmitter inserts these bytes in the outgoing stream. the receiver searches for the a1, a2 bit sequence in the incoming stream. a1 and a2 are not scrambled by the frame synchronous sonet scrambler. j0, z0: the section trace and section growth bytes are disabled for this application. the sequence 0x01, 0x02, 0x03 is inserted in the transmit direction (only 0x01 is transmitted in sts-1 mode). these bytes are ignored in the receive direction. these bytes are not scrambled by the frame synchronous sonet scrambler. b1: the section bit interleaved parity byte provides a section error monitoring function. b1 is calculated over all bits of the previous frame after scrambling. b1 is placed in the current
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 138 frame before scrambling. receive b1 errors are accumulated in an error event counter. h1, h2: the pointer value bytes locate the start of the synchronous payload envelope (spe) in the sonet/sdh frame. in the transmit direction, a fixed pointer value of 522 decimal, with a normal new data flag indication, is inserted in the first h1- h2 pair. the concatenation indication is inserted in the remaining two h1-h2 pairs in sts-3c mode. in the receive direction, the pointer is interpreted to locate the spe. the loss of pointer state is entered when a valid pointer cannot be found. path ais is detected when h1, h2 contain an all ones pattern. h3: the pointer action bytes contain synchronous payload envelope data when a negative stuff event occurs. the all zeros pattern is inserted in the transmit direction. this byte is ignored in the receive direction unless a negative stuff event is detected. b2: the line bit interleaved parity bytes provide a line error monitoring function. b2 is calculated over all bits of the line overhead, and the spe capacity of the previous frame before scrambling. b2 is placed in the current frame before scrambling. receive b2 errors are accumulated in an error event counter. k2: the k2 byte is used to identify line layer maintenance signals. in the transmit direction, line rdi is inserted by setting bits 6, 7, and 8 of the k2 byte to the pattern '110'. line ais is inserted by overwriting the line overhead (including bits 6, 7, and 8 of the k2 byte), and the spe with the all ones pattern before scrambling. in the receive direction, bits 6, 7, and 8 of the k2 byte are examined to determine the presence of the line ais, and the line rdi maintenance signals. m0/m1: the growth byte provides a line far end block error function for remote performance monitoring. in the transmit direction, the number of b2 errors detected in the previous interval is inserted. this number has 25 legal values, namely 0 to 24 errors. in the receive direction, a legal m0/m1 byte value is added to the line febe event counter.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 139 b3: the path bit interleaved parity byte provides a path error monitoring function. b3 is calculated over all bits of the spe capacity of the previous frame before scrambling. b3 is placed in the current frame before scrambling. receive b3 errors are accumulated in an error event counter. c2: the path signal label byte indicates the content of the spe. a hexadecimal value of 13 is transmitted, which indicates "mapping for atm." g1: the path status byte provides a path far end block error function, and provides control over the path remote defect indication maintenance signal. in the transmit direction, path remote alarm indication (rdi) and the number of b3 errors detected in the previous interval are inserted. this number has 9 legal values, namely 0 to 8 errors. in the receive direction, a legal g1 byte value is added to the path febe event counter. in addition, the path remote defect indication is detected. h4: the cell offset indicator byte indicates the offset in bytes between itself, and the first cell boundary following the h4 byte. this byte is inserted correctly in the transmit direction, and is ignored in the receive direction. 9.2 cell data structure atm cells may be passed to/from the s/uni-ultra using a 9 bit data structure, consisting of a start of cell indication and an 8-bit wide word. the data structure is shown in figure 10.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 140 figure 10 - data structure bit 0 h1 h2 h4 bit 7 h5 payload1 word 1 word 2 word 3 word 4 word 5 word 6 payload48 word 53 h3 fifty-three 8-bit words are contained in this data structure. bit 7 of each word is the most significant bit (which corresponds to the first bit transmitted or received). the header check sequence octet (hcs) is passed through this structure. the start of cell indication input and output (tsoc and rsoc) are coincident with word 1 (containing the first cell header octet). word 5 of this structure contains the hcs octet. in the receive direction, cells containing uncorrectable header errors are dropped while the hcspass bit in the racp control/status register is set to logic zero. no header status information is passed within this data structure; error free headers, and "corrected" headers are passed while hcspass is a logic zero. error free headers, "corrected" headers, and headers containing uncorrectable errors are passed while hcspass is a logic one. in the transmit direction, the hcs bit in the tacp control register determines whether the hcs is calculated internally, or is inserted directly from word 5.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 141 9.3 parallel output port and led display controller operation the parallel output port and led display controller is configured by programming the popc block registers, located at addresses 0x68, 0x69 and 0x6a. 9.3.1 direct control parallel output port the popc direct control parallel output port mode allows to directly control the two bit output port out[1:0]. this mode can be used to control external pmd devices. the direct control output port mode is activated by setting both traffic and alarm popc configuration register bits to logic 0. the value of register bits pdat[1:0] is directly assigned to outputs out[1:0]. the toggle[1:0] register bits are affecting the behavior and out[1:0]. when the toggle bit is set to logic 0, the pdat bit is assigned as is. when the toggle bit is set to logic 1, the out output toggles at the programmed rate and pdat act as an enable. 9.3.2 alarm monitor the alarm monitoring mode allows to directly command an external alarm display. the led can be turned on and off, or toggled at a programmable rate. in this mode, the out[1] output is used for alarm monitoring and the out[0] output remains a direct control output port. the alarm monitoring mode is activated by setting the traffic and alarm popc configuration register bits to logic 0 and logic 1, respectively. out[1:0] operates as described above for the direct control parallel output port mode, except that out[1] is enabled by the internal receive alarm indicator instead of the pdat[1] register bit. 9.3.3 traffic monitor the traffic monitoring mode allows to visually monitor atm cells transmit and receive events. it is intended to be used with an external led display and provides a quick and easy monitoring capability to a system operator. the traffic monitoring mode is activated by setting the popc configuration register bits as follows: traffic to logic 1, alarm to logic 0 and toggle[1:0] to logic 0b11. pdat[1:0] is unused. when a successful atm cell transmit or receive event occurs the out[1] or out[0] outputs, respectively, produces a fixed length 100 ms pulse, which is long enough to be visible to the human eye.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 142 9.4 loopback operation the s/uni-ultra supports four loopback functions: twisted-pair loopback, line loopback, parallel diagnostic loopback and serial diagnostic loopback. loopback modes are activated by bits contained in the s/uni-ultra master control register, and are provided to ease system design. the twisted-pair loopback connects the high speed receive data to the high speed transmit data as shown by the block diagram in figure 11, and can be used for line side investigations (does not include clock recovery and clock synthesis). while in this mode, the entire receive path is operating normally and cells can be received through the fifo interface. the line loopback connects the high speed receive data and clock to the high speed transmit data and clock as shown by the block diagram in figure 12, and can be used for line side investigations (including clock recovery and clock synthesis). while in this mode, the entire receive path is operating normally and cells can be received through the fifo interface. the serial diagnostic loopback connects the high speed transmit data and clock to the high speed receive data and clock as shown by the block diagram in figure 13. while in this mode, the entire transmit path is operating normally and data is transmitted on the txd+/- outputs. the parallel diagnostic loopback connects the byte wide transmit data and clock to the byte wide receive data and clock as also shown by the block diagram in figure 14. while in this mode, the entire transmit path is operating normally and data is transmitted on the txd+/- outputs.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 143 figure 11 - twisted-pair loopback operation tx atm cell fifo rx atm cell fifo txd+ rxd+ tdat[7:0] tca tsoc rdat[7:0] rsoc d[7:0] a[7:0] ale csb rdb wrb rstb intb microprocessor i/f tx framer & overhead processor rx framer & overhead processor twrenb tfclk tx atm cell processor rx atm cell processor rca rclk rfp rfclk rrdenb parallel to serial serial to parallel clk gen. sd clk/data rec. rxd- tclk tsen tgfc rcp tfp txd- tcp rgfc atp2 atp1 txprty rxprty xoff tvref rcap2 rcap1 twisted pair rx twisted pair tx refclk analo g ed g e' trref eclsel out[1:0] led control
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 144 figure 12 - line loopback operation tx atm cell fifo rx atm cell fifo txd+ rxd+ tdat[7:0] tca tsoc rdat[7:0] rsoc d[7:0] a[7:0] ale csb rdb wrb rstb intb microprocessor i/f tx framer & overhead processor rx framer & overhead processor twrenb tfclk tx atm cell processor rx atm cell processor rca rclk rfp rfclk rrdenb parallel to serial serial to parallel clk gen. sd clk/data rec. rxd- tclk tsen tgfc rcp tfp txd- tcp rgfc atp2 atp1 txprty rxprty xoff tvref rcap2 rcap1 twisted pair rx twisted pair tx refclk analo g ed g e' trref eclsel out[1:0] led control
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 145 figure 13 - serial diagnostic loopback operation tx atm cell fifo rx atm cell fifo txd+ rxd+ tdat[7:0] tca tsoc rdat[7:0] rsoc d[7:0] a[7:0] ale csb rdb wrb rstb intb microprocessor i/f tx framer & overhead processor rx framer & overhead processor twrenb tfclk tx atm cell processor rx atm cell processor rca rclk rfp rfclk rrdenb parallel to serial serial to parallel clk gen. sd clk/data rec. rxd- tclk tsen tgfc rcp tfp txd- tcp rgfc atp2 atp1 txprty rxprty xoff tvref rcap2 rcap1 twisted pair rx twisted pair tx refclk analo g ed g e' trref eclsel out[1:0] led control
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 146 figure 14 - parallel diagnostic loopback operation tx atm cell fifo rx atm cell fifo txd+ rxd+ tdat[7:0] tca tsoc rdat[7:0] rsoc d[7:0] a[7:0] ale csb rdb wrb rstb intb microprocessor i/f tx framer & overhead processor rx framer & overhead processor twrenb tfclk tx atm cell processor rx atm cell processor rca rclk rfp rfclk rrdenb parallel to serial serial to parallel clk gen. sd clk/data rec. rxd- tclk tsen tgfc rcp tfp txd- tcp rgfc atp2 atp1 txprty rxprty xoff tvref rcap2 rcap1 twisted pair rx twisted pair tx refclk analo g ed g e' trref eclsel out[1:0] led control 9.5 board design recommendations the noise environment and signal integrity are often the limiting factors in system performance. therefore, the following board design guidelines must be followed in order to ensure proper operation: 1. use a single plane for both digital and analog grounds. 2. provide separate +5 volt analog transmit, +5 volt analog receive, and +5 volt digital supplies, but otherwise connect the supply voltages together at one point close to the connector where +5 volts is brought to the card. 3. ferrite beads are not advisable in digital switching circuits because inductive spiking (di/dt noise) is introduced into the power rail. simple rc filtering is probably the best approach provided care is taken to ensure the ir drop in the resistance does not lower the supply voltage below the recommended operating voltage.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 147 4. ferrite beads are recommended for tavd1, tavd2, tavd3, tavd4, ravd1, ravd2, ravd3 and qavd. 5. separate high-frequency decoupling capacitors are recommended for each analog power (tavd1, tavd2, tavd3, tavd4, ravd1, ravd2, ravd3 and qavd) pin as close to the package pin as possible. separate decoupling is required to prevent the transmitter from coupling noise into the receiver and to prevent transients from coupling into some reference circuitry. 6. the high speed serial streams (txd+/- and rxd+/) must be routed with controlled impedance circuit board traces and must be terminated with a matched load. normal ttl-type design rules are not recommended and will reduce the performance of the device. 9.6 power supplies sequencing due to esd protection structures in the pads it is necessary to exercise caution when powering a device up or down. esd protection devices behave as diodes between power supply pins and from i/o pins to power supply pins. under extreme conditions it is possible to blow these esd protection devices or trigger latch up. the recommended power supply sequencing follows: 1. vddi power must be supplied either before vddo or simultaneously with vddo to prevent current flow through the esd protection devices which exist between vddi and vddo power supplies. connection to a common vdd power plane is the recommended standard practice for customer applications. 2. to prevent damage to the esd protection on the device inputs the maximum dc input current specification must be respected. this is accomplished by either ensuring that the vddi power is applied before input pins are driven or by increasing the source impedance of the driver so that the maximum driver short circuit current is less than the maximum dc input current specification. (20 ma) 3. qavd power must be supplied either after vddi or simultaneously with vddi to prevent current flow through the esd protection devices which exist between qavd and vddi power supplies. to prevent forward biasing the esd protection diode between qavd supplies and vddi the differential voltage measured between these power supplies must be less than 0.5 volt. this recommended differential voltage is to include peak to peak noise on the vddi power supply as digital noise will otherwise be coupled into the analog circuitry. current limiting can be accomplished by using an off chip three terminal voltage regulator supplied by a quiet high voltage supply.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 148 4. analog power supplies (avd, includes ravds, tavds but not qavd) must be applied after all qavd, vddi and vddo have been applied or the they must be current limited to the maximum latchup current specification. (100 ma). to prevent forward biasing the esd protection diode between avd supplies and qavd the differential voltage measured between these power supplies must be less than 0.5 volt. this recommended differential voltage is to include peak to peak noise on the qavd and avd power supplies as digital noise will otherwise be coupled into the analog circuitry. current limiting can be accomplished by using an off chip three terminal voltage regulator supplied by a quiet high voltage supply. if the vdd power supply is relatively quiet, vdd can be filtered using a ferrite bead and a high frequency decoupling capacitor to supply avd. the relative power sequencing of the multiple avd power supplies is not important. 5. power down the device in the reverse sequence. use the above current limiting technique for the analog power supplies. small offsets in vdd / avd discharge times will not damage the device. 9.7 selecting between twisted-pair and pecl interfaces although intended to be used with utp-5 cables, the s/uni-ultra can also be configured to interface with pecl devices. when set to logic 0, the peclsel input selects the twisted-pair mode interface. when set to logic 1, the peclsel input selects the pecl mode interface. no special register programming is required. 9.8 interfacing transmit and receive data lines with pecl devices the s/uni-ultra is capable of interfacing with pecl devices. in this type of application some external components are required to ensure proper operation of the device. figure 15 and figure 16 illustrate the recommended circuits.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 149 figure 15 - interfacing txd+/- to pecl s/uni-ultra + zo=50 w txd+ txd- 10 nf zo=50 w 50 w 50 w odl - r x v dd tavs4 rref trref tvref tavs4 tavd4 vref tavs4 see external components section for a com p lete s p ecification
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 150 figure 16 - interfacing with rxd+/- using pecl (2 examples) odl zo=50 w zo=50 w 132 w 82 w 132 w 82 w v dd + zo=50 w zo=50 w 50 w rxd+ rxd- s/uni-ultra 50 w - v tt rxd+ rxd- s/uni-ultra rcap1 rcap2 odl + - see external components section for a com p lete s p ecification 50 w sd rcap1 rcap2 sd 132 w 82 w the txd+/- is a true differential pecl output and thus only requires proper line termination. the termination resistor r x should have a nominal value of r x = ( avd - v poh ) z 0 v poh - v pol @ 63 . 4 w the reference resistor r ref should be 1.30k w when either the internal reference voltage is used or when an external bandgap reference voltage is used. the external bandgap reference voltage v ref , if used, must be 1.23v, and referenced to tavd4 and tavs4. if unused, the tvref pin should be tied to tavs4. refer to the external components section for a more detailed pecl mode specification of r x , r ref and v ref . the internal reference voltage exceeds 3% tolerance over process, temperature and supply, and is more than sufficient to meet the tight amplitude tolerances required. two methods to terminate the rxd+/- pecl differential inputs are illustrated, one using a bias voltage source v tt and the other a z 0 =50 w thevenin equivalent circuit. the choice of the method to be used will primarily depend on the availability of a bias voltage source v tt . if used, v tt must be well decoupled
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 151 to the common ground plane. it is important that the sd termination be identical to the rxd+ and rxd- termination. 9.9 interfacing transmit and receive data lines with utp-5 cable the s/uni-ultra will directly interface to signal transformers for transmission over utp category 5 cable and is designed to meet the atm forum 155 mbit/s physical media dependent (pmd) twisted pair copper specification. a minimal set of external components is required at both transmit and receive ends. however, many issues must be handled carefully in order to insure proper operation. figure 17 shows a typical utp-5 application circuit. an example of common mode termination is provided but other designs may provide improved performance. the reference resistor r ref should 1.0k w when the internal reference voltage is used and 976 w when an external bandgap reference voltage is used, assuming no insertion loss. the external bandgap reference voltage v ref , if used, must be 1.23v, and referenced to tavd4 and tavs4. if unused, the tvref pin should be tied to tavs4. refer to the external components section for a more detailed utp-5 mode specification of r ref and v ref.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 152 figure 17 - interfacing txd+/- and rxd+/- with utp-5 pm5350 s/uni-ultra receive transmit rxd+ rxdC txd+ txdC utp-5 facility rj-45 50 w 100 w 50 w rcap1 rcap2 trref tvref tavs4 r tavs4 tavd4 tavd3 vref tavs4 see external components section for a com p lete s p ecification ref 8 7 5 4 6 3 2 1 sd ravs3 note 1: this is one of the o p tions for common mode note 2: exam p les of a pp ro p riate transformer modules: bel fuse pn# a558-5999-00 pulse engineering pn# 75 w 75 w 50 w 50 w 50 w 50 w 50 w 50 w note 1 utp-5 transformer module note 2 the above is a basic operation description and more details on interfacing the s/uni-ultra with utp-5 cable will be provided in a dedicated pmc-sierra application note. 9.10 clocking options the s/uni-ultra supports several clocking modes. figure 18 is an abstraction of the clocking topology.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 153 figure 18 - conceptual clocking structure clock synthesizer clock recovery internal tx clock source a b rxd+/- refclk internal rx clock source tclk conceptual clockin g structure 8 8 rclk mode b loop timed mode a source timed mode a is provided for all public user network interfaces (unis) and for private unis and private network node interfaces (nnis) that are not synchronized to the recovered clock. the transmit clock in a private uni or a private nni may be locked to an external reference or may free-run. the simplest implementation requires an oscillator free-running at 19.44 mhz. mode a is selected by clearing the loopt bit of the master control register. refclk is multiplied by 8 (sts-3) or 8/3 (sts-1) to become the 155.52 mhz or 51.84 mhz transmit clock. refclk must be jitter free. the source refclk is also internally used as the clock recovery reference. mode b is provided for private unis and private nnis that require synchronization to the recovered clock. mode b is selected by setting the loopt bit of the master control register. normally, the transmit clock is locked to the receive data. in the event of a loss of signal condition, the transmit clock is synthesized from refclk.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 154 functional timing 9.11 drop side receive interface figure 19 - receive fifo empty option (rcalevel0=1) rfclk ???? rdat[7:0] w2 w1 ???? rca ???? rsoc ???? rxprty ???? w(1) w(n-1) w(n) w(n-2) xx xx xx rrdenb ???? invalid read, no data available xx xx figure 20 - receive fifo near empty option (rcalevel0=0) rdat[7:0] ???? w(n) w(n-2) rca ???? rxprty ???? w(n-3) w(n-4) w(n-5) w(1) w(n-1) rfclk ???? rrdenb ???? w2 w1 xx xx the s/uni-ultra indicates that a cell is available by asserting the receive cell available signal, rca. rca remains high until the internal fifo is near empty or
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 155 empty. near empty implies that the atm layer device can initiate at most four additional reads. the atm layer device indicates, by asserting the rrdenb signal, that the data on the rdat[7:0] bus during the next rfclk cycle will be read from the s/uni-ultra. figure 19 illustrates the receive fifo empty option. rca transitions low when the last word of the last cell is available on the rdat[7:0] bus. the rdat[7:0] bus, rxprty and rsoc are valid in cycles for which rca is high and rrdenb was low is the previous cycle. if the atm layer device requests a read while rca is deasserted, the phy layer device will ignore the additional reads. figure 20 illustrates the receive fifo near empty option. rca transitions low four words before the last word of the last cell is read from the s/uni-ultra. rca remains low for a minimum of one rfclk clock cycle and then can transition high to indicate that there are additional cells available from the phy layer device. once rca is deasserted and has been sampled, the atm layer device can issue no more than four reads. if the atm layer device issues more reads than the allowable number, and rca remains deasserted throughout, the phy layer device will ignore the additional reads. figure 21 - receive gfc serial link rclk rgfce [ 3:0 ] =1010b rgfc rcp gfc[3] cell n gfc[2] cell n gfc[1] cell n rgfce [ 3:0 ] =1111b gfc[0] cell n 1-14 rclk c y cles rgfc rcp gfc[3] cell n gfc[1] cell n 1-14 rclk c y cles the receive gfc serial link diagram (figure 21) illustrates the operation of the receive generic flow control, rgfc, and receive gfc control pulse, rcp,
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 156 outputs. the first rgfc bit position, which is coincident with the rcp being high, contains the first gfc bit received and corresponds to the first bit of the cell. the rcp pulse width varies between 1 and 14 rclk cycles depending on the alignment of the atm cell and the sonet/sdh transport and path overheads. extraction of the gfc[3:0] bits is controlled by the four rgfc enable (rgfce[3:0]) bits in the racp configuration register. the output value in each gfc bit position can be forced low by setting the corresponding rgfce bit to zero. the serial link is inactive (forced low) if the s/uni-ultra is out of cell delineation or if the current cell contains an uncorrectable header. 9.12 drop side transmit interface figure 22 - transmit fifo twrenb tsoc ???? tfclk ???? ???? tdat [ 7:0 ] w2 w3 ???? w1 w1 w(n-2) w(n-3) w(n-4) w(n-1) w(n) txprty ???? tca ???? xx xx xx as shown in figure 22, the s/uni-ultra indicates that there is space available for a full cell in its internal fifo by asserting the transmit cell available signal, tca. tca remains asserted until the transmit fifo is almost full. almost full implies that the s/uni-ultra can accept at most an additional four writes after the current write. if tca is asserted and the atm layer device is ready to write a byte, it should assert twrenb low and present the byte on the tdat[7:0] bus. if the presented byte is the first byte of a cell, the atm layer device should also assert signal tsoc. at any time, if the atm layer device does not have a byte to write, it can deassert twrenb.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 157 when tca is deasserted and it has been sampled, the atm layer device can write no more than four bytes to the phy layer device. if the atm layer writes more than four bytes and tca remains deasserted throughout, the s/uni-ultra will indicate an error condition and ignore additional writes until it asserts tca again. figure 23 - transmit gfc serial link tclk tcp gfc[3] gfc[2] gfc[1] gfc[0] tgfc xx figure 23 illustrates the transmit gfc serial link which provides the ability to insert flow control information downstream of the transmit fifo. the tcp output pulses high once per transmitted cell to initiate the transfer on the gfc bits. gfc[3] is the most significant bit and is transmitted first. the tacp configuration register controls the insertion of each serial bit. if the insertion is disabled, the default gfc value is inserted. for unassigned cells, the default is the contents of the tacp idle/unassigned cell header pattern register. for assigned cells, the default is the value received from tdat[7:0].
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 158 10 absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. ambient temperature under bias 0c to +70c storage temperature -40c to +125c supply voltage -0.5v to +6.0v voltage on any pin -0.5v to v dd +0.5v static discharge voltage 1000 v latch-up current 100 ma dc input current 20 ma lead temperature +300c junction temperature +150c
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 159 11 d.c. characteristics t a = 0c to +70c, v dd = 5 v 10% (typical conditions: t a = 25c, v dd = 5 v) symbol parameter min typ max units conditions v il input low voltage (ttl only) -0.5 0.8 volts guaranteed input low voltage v ih input high voltage (ttl only) 2.0 v dd +0.5 volts guaranteed input high voltage v pil input low voltage (rxd+/-, sd pecl mode only) avd -1.81 avd -1.48 volts guaranteed pecl input low voltage referenced to ravd3. note 6. v pih input high voltage (rxd+/-, sd pecl mode only) avd -1.17 avd -0.88 volts guaranteed pecl input high voltage referenced to ravd3. note 6. v poh output high voltage (txd+/-, pecl mode only) avd -1.00 avd -0.95 avd -0.90 volts output high voltage assuming pecl application as illustrated in figure 15. v pol output low voltage (txd+/-, pecl mode only) avd - 1.80 avd - 1.70 avd -1.60 volts output swing assuming pecl application as illustrated in figure 15.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 160 symbol parameter min typ max units conditions v tpocm output common mode voltage (txd+/-, twisted-pair mode only) avd - 0.5 avd -0.231 volts output common mode voltage assuming twisted- pair application as illustrated in figure 17. v tposw ing output swing (txd+/-, twisted-pair mode only) 0.475 0.500 0.525 volts output swing (single-ended) assuming twisted- pair application as illustrated in figure 17. note 7. v ol output or bidirectional low voltage 0.1 0.4 volts v dd = min, i ol = - 4 ma for rdat[7:0], rxprty, rcp, rgfc, rsoc, rca, tca, tcp, tclk, and rclk, and -2 ma for all others, note 3 v oh output or bidirectional high voltage 2.4 4.7 volts v dd = min, i oh = 4 ma for rdat[7:0], rxprty, rcp, rgfc, rsoc, rca, tca, tcp, tclk, and rclk, and 2 ma for all others, note 3 v t+ input high voltage (ttl schmitt trigger inputs only) 3.5 volts rstb and csb inputs. v t- input low voltage (ttl schmitt trigger inputs only) 0.8 volts rstb and csb inputs.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 161 symbol parameter min typ max units conditions v th schmitt trigger input hysteresis voltage 1.0 volts rstb and csb inputs. i ilpu input low current 30 300 a v il = gnd, notes 1, 3 i ihpu input high current -10 +10 a v ih = v dd , notes 1, 3 i il input low current -10 +10 a v il = gnd, notes 2, 3 i ih input high current -10 +10 a v ih = v dd , notes 2, 3 c in input capacitance 5 pf excluding package, package typically 2 pf c out output capacitance 5 pf excluding package, package typically 2 pf c io bidirectional capacitance 5 pf excluding package, package typically 2 pf
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 162 symbol parameter min typ max units conditions p op operating power consumption processing cells (digital + analog circuitry) 0.92 0.74 1.54 1.16 w w outputs loaded, utp-5 mode, txd+/- = rxd+/- =155.52 mbit/s, pecl mode txd+/- = rxd+/- =155.52 mbit/s 0.80 0.62 1.41 1.03 w w outputs unloaded, utp-5 mode, txd+/- = rxd+/- =155.52 mbit/s, pecl mode txd+/- = rxd+/- =155.52 mbit/s 180 150 280 210 ma ma outputs loaded, utp-5 mode, txd+/- = rxd+/- =155.52 mbit/s, pecl mode txd+/- = rxd+/- =155.52 mbit/s i ddop operating current processing cells (digital + analog circuitry) 160 120 260 190 ma ma outputs unloaded, utp-5 mode, txd+/- = rxd+/- =155.52 mbit/s, pecl mode txd+/- = rxd+/- =155.52 mbit/s notes on d.c. characteristics: 1. input pin or bidirectional pin with internal pull-up resistor. 2. input pin or bidirectional pin without internal pull-up resistor
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 163 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. input pin or bidirectional pin with internal pull-down resistor. 5. typical values are not production tested. 6. when operating the device in pecl mode, the v cm (common-mode voltage) of the sd input must match the v cm of the rxd+/- differential inputs. the rxd+/- inputs are truly differential. their common mode voltage is extracted and used as the reference voltage for the sd single ended pecl input. 7. the given value is the single ended output swing. this number must be doubled to obtain the differential output swing.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 164 12 external components symbol parameter min typ max units specification v ref external reference voltage (pecl mode only) 1.23 volts +/- 3% r ref reference resistor, using internal reference voltage (pecl mode only) 1.30 k w +/- 1%, 1/8 w r ref reference resistor, using external reference voltage (pecl mode only) 1.30 k w +/- 1%, 1/8 w v ref external reference voltage (twisted- pair mode only) 1.23 volts +/- 3% r ref reference resistor, using internal reference voltage (twisted-pair mode only) 100 0 976 953 931 w w w w +/- 1%, 1/8 w , note 3 insertion loss: 0.0 C 0.1 db 0.2 C 0.3 db 0.4 C 0.5 db 0.6 C 0.7 db r ref reference resistor, using external reference voltage (twisted-pair mode only) 976 953 931 909 w w w w +/- 1%, 1/8 w , note 3 insertion loss: 0.0 C 0.1 db 0.2 C 0.3 db 0.4 C 0.5 db 0.6 C 0.7 db
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 165 symbol parameter min typ max units specification r x external receiver resistor (pecl mode only) 63.4 w +/- 1%, 1/8 w r term line termination resistors w +/- 1%, 1/8w values depend on application tm ocl transformer module open circuit inductance 350 m h at 100 khz tm rt transformer module rise time 2.5 ns at 10% C 90% tm il transformer module insertion loss -1.0 db at 100 khz C 155 mhz tm il transformer module return loss 16 note 2 10 db at 2 mhz C 30 mhz at 30 mhz C 60 mhz at 60 mhz C 100 mhz tm cdr transformer module common mode to differential mode rejection -40 db at 100khz C 155 mhz tm dcr transformer module differential mode to common mode rejection -32 db at 100khz C 155 mhz tm ccr transformer module common mode to common mode rejection -30 db at 100khz C 155 mhz tm ratio transformer module ratio (utp- 5) 1:1 +/- 5%
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 166 symbol parameter min typ max units specification tm ct transformer module crosstalk -35 db this applies only to integrated rx and tx modules notes on external components: 1. the above specification applies only to the recommended applications as described in the operation section and are designed to optimize the typical performance of the system. 2. the following equation must be used: 16 db - 20 log( f 30 mhz ) . 3. in twisted pair mode of operation, the appropriate r ref value is a function of the transformer insertion loss since the required output amplitude is specified at the aoi. the r ref value is chosen to meet the amplitude tolerance.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 167 13 microprocessor interface timing characteristics (t a = 0c to +70c, v dd = 5 v 10%) table 1 - microprocessor interface read access (figure 24) symbol parameter min max units ts ar address to valid read set-up time 25 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 20 ns th alr address to latch hold time 10 ns tv l valid latch pulse width 20 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 80 ns tz rd valid read negated to data output tri-state 20 ns tz inth valid read negated to interrupt output tri-state 50 ns
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 168 figure 24 - microprocessor interface read timing intb tz inth (csb+rdb) valid data d[7:0] tp rd tz rd ts ar th ar valid address a[7:0] ale ts alr tv l ts lr th alr th lr notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. microprocessor interface timing applies to normal mode register accesses only.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 169 5. in a non-multiplexed address/data bus architecture, ale should be held high, parameters ts alr , th alr , tv l , and ts lr are not applicable. 6. parameters th ar and ts ar are not applicable if address latching is used. 7. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 8. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. table 2 - microprocessor interface write access (figure 25) symbol parameter min max units ts aw address to valid write set-up time 25 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 20 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 20 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 170 figure 25 - microprocessor interface write timing th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+wrb) a[7:0] valid address ale tv l ts alw ts lw th alw th lw notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. microprocessor interface timing applies to normal mode register accesses only. 3. in a non-multiplexed address/data bus architecture, ale should be held high, parameters ts alw , th alw , tv l , and ts lw are not applicable. 4. parameters th aw and ts aw are not applicable if address latching is used. 5. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 6. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 171 14 s/uni-ultra timing characteristics (t a = 0c to +70c, v dd = 5 v 10%) table 3 - line side reference clock symbol description min max units refclk duty cycle 19.44 30 70 % refclk frequency tolerance -50 +50 ppm table 4 - line side receive interface (figure 26) symbol description min max units t p rfp rclk high to rfp valid 0 10 ns figure 26 - receive frame pulse output timing rclk tp rfp rfp
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 172 table 5 - line side transmit interface (figure 27) symbol description min max units t s tfp tfp to tclk high setup (tfp_in bit is logic 1) 10 ns t h tfp tclk high to tfp hold (tfp_in bit is logic 1) 10 ns t p tfp tclk high to tfp valid (tfp_in bit is logic 0) 010ns figure 27 - line side transmit interface timing tclk tp tfp tfp ( output ) th tfp tfp ( input ) ts tfp table 6 - drop side receive synchronous interface (tsen = 0) (figure 28) symbol description min max units rfclk frequency 50 mhz rfclk duty cycle 40 60 % t s rrdenb rrdenb to rfclk high setup 4 ns t h rrdenb rfclk high to rrdenb hold 1 ns
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 173 symbol description min max units t p rdat rfclk high to rdat[7:0] valid 2 14 ns t p rxp rfclk high to rxprty valid 2 14 ns t p rca rfclk high to rca valid 2 14 ns t p rsoc rfclk high to rsoc valid 2 14 ns figure 28 - drop side receive synchronous interface timing (tsen = 0) tp rxp rxprty tp rdat rdat [ 7:0 ] rfclk tp rca rca tp rsoc rsoc rrdenb th rrdenb ts rrdenb
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 174 table 7 - drop side receive synchronous interface (tsen = 1) (figure 29) symbol description min max units rfclk frequency 50 mhz rfclk duty cycle 40 60 % t s rrdenb rrdenb to rfclk high setup 4 ns t h rrdenb rfclk high to rrdenb hold 1 ns t p rdat rfclk high to rdat[7:0] valid 2 14 ns t z rdat rfclk high to rdat[7:0] tristate 2 14 ns t p rxp rfclk high to rxprty valid 2 14 ns t z rxp rfclk high to rxprty tristate 2 14 ns t p rca rfclk high to rca valid 2 14 ns t p rsoc rfclk high to rsoc valid 2 14 ns t z rsoc rfclk high to rsoc tristate 2 14 ns
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 175 figure 29 - drop side receive synchronous interface timing (tsen = 1) tp rxp rxprty tz rxp tp rdat rdat [ 7:0 ] rfclk tp rca rca tp rsoc rsoc rrdenb th rrdenb ts rrdenb tz rdat tz rsoc
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 176 table 8 - gfc extract port (figure 30) symbol description min max units t p rgfc rclk high to rgfc valid -1 10 ns t p rcp rclk high to rcp valid -1 10 ns figure 30 - gfc extract port timing tp rgfc rgfc rclk tp rcp rcp table 9 - drop side transmit synchronous interface (figure 31) symbol description min max units tfclk frequency 50 mhz tfclk duty cycle 40 60 % ts twrenb twrenb set-up time to tfclk 4 ns th twrenb twrenb hold time to tfclk 1 ns t s tdat tdat[7:0] set-up time to tfclk 4 ns t h tdat tdat[7:0] hold time to tfclk 1 ns t s txp txprty set-up time to tfclk 4 ns t h txp txprty hold time to tfclk 1 ns
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 177 symbol description min max units t s tsoc tsoc set-up time to tfclk 4 ns t h tsoc tsoc hold time to tfclk 1 ns t p tca tfclk to tca valid 2 14 ns figure 31 - drop side transmit synchronous interface ts txp th txp txprty ts twrenb th twrenb twrenb ts tdat th tdat tdat [ 7:0 ] ts tsoc th tsoc tsoc tca tp tca tfclk
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 178 table 10 - gfc insert port (figure 32) symbol description min max units t s tgfc tgfc set-up time to tclk 10 ns t h tgfc tgfc hold time to tclk 1 ns t p tcp tclk high to tcp valid -1 10 ns figure 32 - gfc insert port timing th tgfc tgfc tclk tp tcp tcp ts tgfc notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 179 2. output propagation delays for rca, tca, rsoc, rxprty and rdat[7:0] are measured with a 30 pf load on the output. other output propagation delays are measured with a 50 pf load on the outputs.
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 180 15 ordering and thermal information table 11 - s/uni-ultra ordering information pa rt n o description PM5350-RC 128 pin copper leadframe plastic quad flat pack (pqfp) table 12 - s/uni-ultra thermal information part no. ambient temperature theta ja theta jc PM5350-RC 0c to 70c 36 c/w 25 c/w figure 33 - theta ja vs. air flow air flow (lfm) 25 27 29 31 33 35 37 39 0 100 200 300 400
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 181 16 mechanical information 128 pin copper leadframe rectangular plastic quad flat pack (r suffix) e 1 d e1 d1 e 128 8-12 deg a 8-12 deg a2 pin 1 designator nom. min. max. dim. aa1 a2 d d1 e e1 l e b ccc package type: body size: 14.10 14.00 13.90 0.73 0.88 1.03 0.10 14 x 20 x 2.7 mm 2.82 3.40 0.25 0.53 2.57 2.70 2.87 22.95 23.20 23.45 19.90 20.00 20.10 16.95 17.20 17.45 0.50 0.17 0.22 0.27 see detail a 128 pin metric rectangular plastic quad flatpack-mqfp gage plane, 0.25 above seating plane. detail a 0-7 deg plane seating 0.13-0.23 c l .25 a 0-10 deg. ccc c lead coplanarity notes: 1) all dimensions in millimeter. b standoff a1 3) foot length "l" is measured at c with tolerances as indicated. 2) dimensions shown are nominal
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 182 notes
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface proprietary and confidential to pmc-sierra, inc., and for its customers internal use 183 notes
pm5350 s/uni-ultra data sheet pmc-960924 issue 5 saturn user network interface none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 1998 pmc-sierra, inc. pmc-960924 (r5) ref pmc-960489 (r7) issue date: june 1998 proprietary and confidential to pmc-sierra, inc., and for its customers internal use contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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