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? 2009 microchip technology inc. ds21948e-page 1 MCP3905/06 features ? supplies active (real) power measurement for single-phase, residential energy-metering ? supports the iec 62053 international energy metering specification and legacy iec 1036/ 61036/687 specifications ? two multi-bit, digital-to-analog converters (dacs), second-order, 16-bit, delta-sigma analog-to-digital converters (adcs) ? 0.1% typical measurement error over 500:1 dynamic range (MCP3905) ? 0.1% typical measurement error over 1000:1 dynamic range (mcp3906) ? programmable gain amplifier (pga) for small- signal inputs supports low-value shunt current sensor - 16:1 pga - MCP3905 - 32:1 pga - mcp3906 ? ultra-low drift on-chip reference: 15 ppm/c (typical) ? direct drive for electromagnetic mechanical counter and two-phase stepper motors ? low i dd of 4 ma (typical) ? tamper output pin for negative power indication ? industrial temperature range: -40c to +85c ? supplies instantaneous active (real) power on hf out for meter calibration us patents pending description the MCP3905/06 devices are energy-metering ics designed to support the iec 62053 international metering standard specification. they supply a frequency output proportional to the average active (real) power, as well as a higher-frequency output proportional to the instantaneous power for meter calibration. they include two 16-bit, delta-sigma adcs for a wide range of i b and i max currents and/or small shunt (< 200 ohms) meter designs. it includes an ultra-low drift voltage reference with < 15 ppm/c through a specially designed band gap temperature curve for the minimum gradient across the industrial temperature range. a fixed-function dsp block is on-chip for active (real) power calculation. strong output drive for mechanical counters are on-chip to reduce field failures and mechanical counter sticking. a no-load threshold block prevents any current creep measurements. a power-on reset (por) block restricts meter performa nce during low-voltage situations. these accurate energy-metering ics with high field reliability are available in the industry- standard pinout. package type functional block diagram f out0 d gnd neg 1 2 3 4 24 23 22 21 20 19 18 17 5 6 7 8 f out1 nc osc2 osc1 dv dd hpf av dd nc ch0+ ch0- ch1- ch1+ hf out 16 9 g0 mclr 15 14 10 11 g1 f0 refin/out a gnd 13 12 f1 f2 24-pin ssop 16-bit ? adc mclr + ? ch0+ ch0- reference 2.4v + ? ch1+ ch1- hpf1 lpf1 e-to-f conversion refin/ f out1 hf out g0 g1 f2 f1 f out0 osc1 osc2 out neg hpf f0 multi-level 16-bit ? adc multi-level x hpf1 pga por energy-metering ics with active (real) power pulse output obsolete device replacement device: MCP3905a/mcp3906a
MCP3905/06 ds21948e-page 2 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds21948e-page 3 MCP3905/06 1.0 electrical characteristics absolute maximum ratings ? v dd ...................................................................................7.0v digital inputs and outputs w.r.t. a gnd ........ -0.6v to v dd +0.6v analog input w.r.t. a gnd ..................................... ....-6v to +6v v ref input w.r.t. a gnd .............................. -0.6v to v dd +0.6v storage temperature .....................................-65c to +150c ambient temp. with power applied ................-65c to +125c soldering temperature of leads (10 seconds) ............. +300c esd on the analog inputs (hbm,mm) .................5.0 kv, 500v esd on all other pins (hbm,mm) ........................5.0 kv, 500v ? notice: stresses above those listed under "maximum ratings" may cause permanent dam age to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specif ication is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. electrical characteristics electrical specifications: unless otherwise indicated, all parameters apply at av dd = dv dd = 4.5v ? 5.5v, internal v ref , hpf turned on (ac mode), a gnd , d gnd = 0v, mclk = 3.58 mhz; t a = -40c to +85c. parameter sym min typ. max units comment overall measurement accuracy energy measurement error e ? 0.1 ? % f out channel 0 swings 1:500 range, MCP3905 only ( note 1 , note 4 ) ? 0.1 ? % f out channel 0 swings 1:1000 range, mcp3906 only ( note 1 , note 4 ) no-load threshold/ minimum load nlt ? 0.0015 ? % f out max. disabled when f2, f1, f0 = 0, 1, 1 ( note 5, note 6 ) phase delay between channels ? ? 1/mclk s hpf = 0 and 1, < 1 mclk ( note 4, note 6, note 7 ) ac power supply rejection ratio (output frequency variation) ac psrr ? 0.01 ? % f out f2, f1, f0 = 0, 1, 1 ( note 3 ) dc power supply rejection ratio (output frequency variation) dc psrr ? 0.01 ? % f out hpf = 1, gain = 1 ( note 3 ) system gain error ? 3 10 % f out note 2, note 5 adc/pga specifications offset error v os ? 2 5 mv referred to input gain error match ? 0.5 ? % f out note 8 internal voltage reference voltage ? 2.4 ? v tolerance ? 2 ? % tempco ? 15 ? ppm/c note 1: measurement error = (energy measured by device - true energy)/true energy * 100%. accuracy is measured with signal (660 mv) on channel 1. f out0 , f out1 pulse outputs. valid from 45 hz to 65 hz. see section 2.0 ?typical performance curves? for higher frequencies and increased dynamic range. 2: does not include internal v ref . gain = 1, ch0 = 470 mvdc, ch1 = 660 mvdc, difference between measured output frequency an d expected transfer function. 3: percent of hf out output frequency variation; includes external v ref = 2.5v, ch1 = 100 mvrms @ 50 hz, ch2 = 100 mvrms @ 50 hz, av dd = 5v + 1v pp @ 100 hz. dc psrr: 5v 500 mv. 4: error applies down to 60 lead (pf = 0.5 capacitive) and 60 lag (pf = 0.5 inductive). 5: refer to section 4.0 ?device overview? for complete description. 6: specified by characterization, not production tested. 7: 1 mclk period at 3.58 mhz is equivalent to less than <0.005 degrees at 50 or 60 hz. 8: gain error match is measured from ch0 g = 1 to any other gain setting.
MCP3905/06 ds21948e-page 4 ? 2009 microchip technology inc. temperature characteristics reference input input range 2.2 ? 2.6 v input impedance 3.2 ? ? k input capacitance ? ? 10 pf analog inputs maximum signal level ? ? 1 v ch0+,ch0-,ch1+,ch1- to a gnd differential input voltage range channel 0 ? ? 470/g mv g = pga gain on channel 0 differential input voltage range channel 1 ??660mv input impedance 390 ? ? k proportional to 1/mclk frequency bandwidth (notch frequency) ? 14 ? khz proportional to mclk frequency, mclk/256 oscillator input frequency range mclk 1 ? 4 mhz power specifications operating voltage 4.5 ? 5.5 v av dd, dv dd i dd,a i dd,a ?2.7 3.0 maav dd pin only i dd,d i dd,d ?1.2 2.0 madv dd pin only electrical specifications: unless otherwise indicated, v dd = 4.5v ? 5.5v, a gnd , d gnd = 0v. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +85 c operating temperature range t a -40 ? +125 c note storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 24l-ssop ja ?73?c/w note: the MCP3905/06 operate over this extended temperat ure range, but with reduced performance. in any case, the junction temperature (t j ) must not exceed the absolute maximum specification of +150c. electrical character istics (continued) electrical specifications: unless otherwise indicated, all parameters apply at av dd = dv dd = 4.5v ? 5.5v, internal v ref , hpf turned on (ac mode), a gnd , d gnd = 0v, mclk = 3.58 mhz; t a = -40c to +85c. parameter sym min typ. max units comment note 1: measurement error = (energy measured by device - true energy)/true energy * 100%. accuracy is measured with signal (660 mv) on channel 1. f out0 , f out1 pulse outputs. valid from 45 hz to 65 hz. see section 2.0 ?typical performance curves? for higher frequencies and increased dynamic range. 2: does not include internal v ref . gain = 1, ch0 = 470 mvdc, ch1 = 660 mvdc, difference between measured output frequency an d expected transfer function. 3: percent of hf out output frequency variation; includes external v ref = 2.5v, ch1 = 100 mvrms @ 50 hz, ch2 = 100 mvrms @ 50 hz, av dd = 5v + 1v pp @ 100 hz. dc psrr: 5v 500 mv. 4: error applies down to 60 lead (pf = 0.5 capacitive) and 60 lag (pf = 0.5 inductive). 5: refer to section 4.0 ?device overview? for complete description. 6: specified by characterization, not production tested. 7: 1 mclk period at 3.58 mhz is equivalent to less than <0.005 degrees at 50 or 60 hz. 8: gain error match is measured from ch0 g = 1 to any other gain setting.
? 2009 microchip technology inc. ds21948e-page 5 MCP3905/06 figure 1-1: output timings for pulse out puts and negative power pin. timing characteristics electrical specifications: unless otherwise indicated, all parameters apply at av dd = dv dd = 4.5v ? 5.5v, a gnd , d gnd = 0v, mclk = 3.58 mhz; t a = -40c to +85c. parameter sym min typ max units comment frequency output f out0 and f out1 pulse width (logic-low) t fw ? 275 ? ms 984376 mclk periods (note 1) hf out pulse width t hw ? 90 ? ms 322160 mclk periods (note 2) f out0 and f out1 pulse period t fp refer to equation 4-1 s hf out pulse period t hp refer to equation 4-2 s f out0 to f out1 falling-edge time t fs2 ? 0.5 t fp ? f out0 to f out1 min separation t fs ? 4/mclk ? f out0 and f out1 output high voltage v oh 4.5 ?? vi oh = 10 ma, dv dd = 5.0v f out0 and f out1 output low voltage v ol ?? 0.5 v i ol = 10 ma, dv dd = 5.0v hf out output high voltage v oh 4.0 ?? vi oh = 5 ma, dv dd = 5.0v hf out output low voltage v ol ?? 0.5 v i ol = 5 ma, dv dd = 5.0v high-level input voltage (all digital input pins) v ih 2.4 ?? vdv dd = 5.0v low-level input voltage (all digital input pins) v il ?? 0.85 v dv dd = 5.0v input leakage current ?? 3 a v in = 0, v in = dv dd pin capacitance ?? 10 pf note 3 note 1: if output pulse period (t fp ) falls below 984376*2 mclk periods, then t fw = 1/2 t fp . 2: if output pulse period (t hp ) falls below 322160*2 mclk periods, then t hw = 1/2 t hp . 3: specified by characterization, not production tested. f out0 t fp f out1 hf out t fw t hp t hw t fs t fs2 neg
MCP3905/06 ds21948e-page 6 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds21948e-page 7 MCP3905/06 2.0 typical performance curves note: unless otherwise specified, dv dd , av dd = 5v; a gnd , d gnd = 0v; v ref = internal, hpf = 1 (ac mode), mclk = 3.58 mhz. figure 2-1: measurement error, gain = 8, pf = 1. figure 2-2: measurement error, gain = 16, pf = 1. figure 2-3: measurement error, gain = 32, pf = 1. figure 2-4: measurement error, gain = 8, pf = 0.5. figure 2-5: measurement error, gain = 16, pf = 0.5. figure 2-6: measurement error, gain = 32, pf = 0.5. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.0000 0.0001 0.0010 0.0100 0.1000 ch1 vp-p amplitude (v) measurement error +85c +25c -40c -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.0000 0.0001 0.0010 0.0100 0.1000 ch1 vp-p amplitude (v) measurement error +85c +25c - 40c -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 0.0000 0.0001 0.0010 0.0100 0.1000 ch1 vp-p amplitude (v) measurement error +85c +25c - 40c -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.0000 0.0001 0.0010 0.0100 0.1000 ch1 vp-p amplitude (v) measurement error +85c +25c -40c -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0000 0.0001 0.0010 0.0100 0.1000 ch1 vp-p amplitude (v) measurement error +85c +25c -40c -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0.0000 0.0001 0.0010 0.0100 0.1000 ch1 vp-p amplitude (v) measurement error +85c +25c -40c
MCP3905/06 ds21948e-page 8 ? 2009 microchip technology inc. note: unless otherwise specified, dv dd , av dd = 5v; a gnd , d gnd = 0v; v ref = internal, hpf = 1 (ac mode), mclk = 3.58 mhz. figure 2-7: measurement error, gain = 1, pf = 1. figure 2-8: measurement error, gain = 2, pf = 1. figure 2-9: measurement error, gain = 1, pf = + 0.5. figure 2-10: measurement error, gain = 2, pf = + 0.5. -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.0001 0.0010 0.0100 0.1000 1.0000 ch0 vp-p amplitude (v) measurement error +85c +25c - 40c -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.0001 0.0010 0.0100 0.1000 1.0000 ch0 vp-p amplitude (v) measurement error +85c +25c - 40c -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.0001 0.0010 0.0100 0.1000 1.0000 ch1 vp-p amplitude (v) measurement error +85c +25c -40c -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.0001 0.0010 0.0100 0.1000 1.0000 ch1 vp-p amplitude (v) measurement error +85c +25c -40c
? 2009 microchip technology inc. ds21948e-page 9 MCP3905/06 note: unless otherwise specified, dv dd , av dd = 5v; a gnd , d gnd = 0v; v ref = internal, hpf = 1 (ac mode), mclk = 3.58 mhz. figure 2-11: measurement error vs. input frequency. figure 2-12: channel 0 offset error (dc mode, hpf off), g = 1. figure 2-13: channel 0 offset error (dc mode, hpf off), g = 8. figure 2-14: channel 0 offset error (dc mode, hpf off), g = 16. figure 2-15: measurement error vs. v dd (g = 16). figure 2-16: measurement error vs. v dd , g = 16, external v ref . -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 45 50 55 60 65 70 75 frequency (hz) % error pf = 1.0 pf = 0.5 0 500 1000 1500 2000 2500 3000 -1.75 -1.70 -1.65 -1.61 -1.56 -1.52 -1.47 -1.43 -1.38 channel 0 offset (mv) occurance 16384 samples mean = -1.57 mv std. dev = 52.5 v 0 200 400 600 800 1000 1200 -1.71 -1.69 -1.68 -1.67 -1.66 -1.65 -1.64 -1.63 -1.62 -1.60 -1.59 channel 0 offset (mv) occurance 16384 samples mean = -1.64 mv std. dev = 17.4 v 0 500 1000 1500 2000 2500 3000 3500 4000 -1.38e-03 -1.37e-03 -1.36e-03 -1.35e-03 -1.34e-03 -1.33e-03 -1.32e-03 -1.31e-03 -1.30e-03 -1.29e-03 -1.28e-03 -1.27e-03 -1.26e-03 -1.25e-03 -1.24e-03 -1.23e-03 -1.22e-03 bin (mv) occurance 16384 samples mean = - 1.28 mv std. dev = - 18.1 v -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.0001 0.0010 0.0100 0.1000 1.0000 ch0 vp-p amplitude (v) measurement error v dd =4.75v v dd =5.0v v dd =4.5v v dd =5.25v v dd =5.5v -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.0001 0.0010 0.0100 0.1000 1.0000 ch0 vp-p amplitude (v) measurement error v dd =4.5v v dd =4.75v v dd =5.0v v dd =5.25v v dd =5.5v
MCP3905/06 ds21948e-page 10 ? 2009 microchip technology inc. note: unless otherwise specified, dv dd , av dd = 5v; a gnd , d gnd = 0v; v ref = internal, hpf = 1 (ac mode), mclk = 3.58 mhz. figure 2-17: measurement error with external v ref , (g = 1). figure 2-18: measurement error with external v ref , (g = 8). figure 2-19: measurement error with external v ref (g = 16). -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.0001 0.0010 0.0100 0.1000 1.0000 ch0 vp-p amplitude (v) measurement error +85c +25c - 40c -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.0000 0.0001 0.0010 0.0100 0.1000 ch1 vp-p amplitude (v) measurement error +85c +25c -40c -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.0000 0.0001 0.0010 0.0100 0.1000 ch1 vp-p amplitude (v) measurement error +85c +25c - 40c
? 2009 microchip technology inc. ds21948e-page 11 MCP3905/06 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 digital v dd (dv dd ) dv dd is the power supply pin for the digital circuitry within the MCP3905/06. dv dd requires appropriate bypass capacitors and should be maintained to 5v 10% for specified operation. please refer to section 5.0 ?applications information? . 3.2 high-pass filter input logic pin (hpf) hpf controls the state of the high-pass filter in both input channels. a logic ? 1 ? enables both filters, removing any dc offset coming from the system or the device. a logic ? 0 ? disables both filters, allowing dc voltages to be measured. 3.3 analog v dd (av dd ) av dd is the power supply pin for the analog circuitry within the MCP3905/06. av dd requires appropriate bypass capacitors and should be maintained to 5v 10% for specified operation. please refer to section 5.0 ?applications information? . MCP3905/06 symbol definition ssop-24 1dv dd digital power supply pin 2 hpf high-pass filters control logic pin 3av dd analog power supply pin 4 nc no connect 5 ch0+ non-inverting analog input pin for channel 0 (current channel) 6 ch0- inverting analog input pin for channel 0 (current channel) 7 ch1- inverting analog input pin for channel 1 (voltage channel) 8 ch1+ non-inverting analog input pin for channel 1 (voltage channel) 9mclr master clear logic input pin 10 refin/out voltage refe rence input/output pin 11 a gnd analog ground pin, return path for internal analog circuitry 12 f2 frequency control for hf out logic input pin 13 f1 frequency control for f out0/1 logic input pin 14 f0 frequency control for f out0/1 logic input pin 15 g1 gain control logic input pin 16 g0 gain control logic input pin 17 osc1 oscillator crystal connection pin or clock input pin 18 osc2 oscillator crystal connection pin or clock output pin 19 nc no connect 20 neg negative power logic output pin 21 d gnd digital ground pin, return path for internal digital circuitry 22 hf out high-frequency logic output pin (intended for calibration) 23 f out1 differential mechanical counter logic output pin 24 f out0 differential mechanical counter logic output pin
MCP3905/06 ds21948e-page 12 ? 2009 microchip technology inc. 3.4 current channel (ch0-, ch0+) ch0- and ch0+ are the fully differential analog voltage input channels for the current measurement, containing a pga for small-signal input, such as shunt current- sensing. the linear and specified region of this channel is dependant on the pga gain. this corresponds to a maximum differential voltage of 470 mv/gain and maximum absolute voltage, with respect to a gnd , of 1v. up to 6v can be applied to these pins without the risk of permanent damage. refer to section 1.0 ?electrical characteristics? . 3.5 voltage channel (ch1-,ch1+) ch1- and ch1+ are the fully differential analog voltage input channels for the voltage measurement. the linear and specified region of these channels have a maximum differential voltage of 660 mv and a maximum absolute voltage of 1v, with respect to a gnd . up to 6v can be applied to these pins without the risk of permanent damage. refer to section 1.0 ?electrical characteristics? . 3.6 master clear (mclr ) mclr controls the reset for both delta-sigma adcs, all digital registers, the sinc filters for each channel and all accumulators post multiplier. a logic ? 0 ? resets all registers and holds both adcs in a reset condition. the charge stored in both adcs is flushed and their output is maintained to 0x0000h. the only block consuming power on the digital power supply during reset is the oscillator circuit. 3.7 reference (refin/out) refin/out is t he output for the internal 2.4v reference. this reference has a typical temperature coefficient of 15 ppm/c and a tolerance of 2%. in addition, an external reference can also be used by applying voltage to this pin within the specified range. refin/out requires appropriate bypass capacitors to a gnd , even when using the internal reference only. refer to section 5.0 ?applications information? . 3.8 analog ground (a gnd ) a gnd is the ground connection to the internal analog circuitry (adcs, pga, band gap reference, por). to ensure accuracy and noise cancellation, this pin must be connected to the same ground as d gnd , preferably with a star connection. if an analog ground plane is available, it is recommended that this device be tied to this plane of the printed circuit board (pcb). this plane should also reference all other analog circuitry in the system. 3.9 frequency control logic pins (f2, f1, f0) f2, f1 and f0 select the high-frequency output and low-frequency output pin ra nges by changing the value of the constants f c and h fc used in the device transfer function. f c and h fc are the frequency constants that define the period of the out put pulses for the device. 3.10 gain control logic pins (g1, g0) g1 and g0 select the pga gain on channel 0 from three different values: 1, 8 and 16. 3.11 oscillator (osc1, osc2) osc1 and osc2 provide the master clock for the device. a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. the typical clock frequency specified is 3.579545 mhz. however, the clock frequency can be with the range of 1 mhz to 4 mhz without disturbing measur ement error. appropriate load capacitance should be connected to these pins for proper operation. a full-swing, single-ended clock source may be connected to osc1 with proper resistors in series to ensure no ringing of the clock source due to fast transient edges. 3.12 negative power output logic pin (neg) neg detects the phase difference between the two channels and will go to a logic ? 1 ? state when the phase difference is greater than 90 (i.e., when the measured active (real) power is negative). the output state is synchronous with the rising-edge of hf out and maintains the logic ? 1 ? until the active (real) power becomes positive again and hf out shows a pulse. 3.13 ground connection (d gnd ) d gnd is the ground connection to the internal digital circuitry (sinc filters, multip lier, hpf, lpf, digital-to- frequency (dtf) converter and oscillator). to ensure accuracy and noise cancellation, d gnd must be connected to the same ground as a gnd , preferably with a star connection. if a digital ground plane is available, it is recommended that this device be tied to this plane of the pcb. this plane should also reference all other digital circuitry in the system.
? 2009 microchip technology inc. ds21948e-page 13 MCP3905/06 3.14 high-frequency output (hf out ) hf out is the high-frequency output of the device and supplies the instantaneous real-power information. the output is a periodic pulse output, with its period proportional to the measured active (real) power, and to the hf c constant defined by f0, f1 and f2 pin logic states. this output is the preferred output for calibration due to faster output fr equencies, giving smaller calibration times. since this output gives instantaneous active (real) power, the 2 ripple on the output should be noted. however, the average period will show minimal drift. 3.15 frequency output (f out0 , f out1 ) f out0 and f out1 are the frequency outputs of the device that supply the average real-power information. the outputs are periodic pulse outputs, with its period proportional to the measured active (real) power, and to the f c constant, defined by the f0 and f1 pin logic states. these pins include high-output drive capability for direct use of electromechanical counters and 2-phase stepper motors. since this output supplies average active (real) power, any 2 ripple on the output pulse period is minimal.
MCP3905/06 ds21948e-page 14 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds21948e-page 15 MCP3905/06 4.0 device overview the MCP3905/06 is an energy-metering ic that supplies a frequency output proportional to active (real) power, and higher frequency output proportional to the instantaneous power for meter calibration. both channels use 16-bit, second-order, delta-sigma adcs that oversample the input at a frequency equal to mclk/4, allowing for wide dynamic range input signals. a programmable gain amplif ier (pga) increases the usable range on the current input channel (channel 0). the calculation of the active (real) power, as well as the filtering associated with this calculation, is performed in the digital domain, ensuring better stability and drift performance. figure 4-1 represents the simplified block diagram of the MCP3905/06, detailing its main signal-processing blocks. two digital high-pass filters cancel the system offset on both channels such that the real-power calculation does not include any circuit or system offset. after being high-pass filtered, the voltage and current signals are multiplied to give the instantaneous power signal. this signal does not contain the dc offset components, such that the averaging technique can be efficiently used to give the desired active (real) power output. the instantaneous power signal contains the real- power information; it is the dc component of the instantaneous power. the averaging technique can be used with both sinusoidal and non-sinusoidal waveforms, as well as for all power factors. the instantaneous power is thus low-pass filtered in order to produce the instantaneous real-power signal. a dtf converter accumulates the instantaneous active (real) power information to produce output pulses with a frequency proportional to the average active (real) power. the low-frequency pulses presented at the f out0 and f out1 outputs are designed to drive electromechanical counters and two-phase stepper motors displaying the real-power energy consumed. each pulse corresponds to a fixed quantity of real energy, selected by the f2, f1 and f0 logic settings. the hf out output has a higher frequency setting and lower integration period such that it can represent the instantaneous active (real) power signal. due to the shorter accumulation time, it enables the user to proceed to faster calibration under steady load conditions (refer to section 4.7 ?f out0/1 and hf out output frequencies? ). figure 4-1: simplified MCP3905/06 block diagram with frequency contents. hpf ... 1 0 1 0 .. dtf C + adc C + pga lpf hpf x ch0+ ch0- ch1+ ch1- adc f out0 f out1 hf out 0 0 MCP3905/06 0 0 0 frequency content ? ? adc output code contains system and adc offset dc offset removed by hpf instantaneous power analog digital instantaneous active (real) power input signal with system offset and line frequency
MCP3905/06 ds21948e-page 16 ? 2009 microchip technology inc. 4.1 analog inputs the MCP3905/06 analog inputs can be connected directly to the current and voltage transducers (such as shunts or current transformers). each input pin is protected by specialized electrostatic discharge (esd) structures that are cert ified to pass 5 kv hbm and 500v mm contact charge. these structures also allow up to 6v continuous voltage to be present at their inputs without the risk of permanent damage. both channels have fully differential voltage inputs for better noise performance. the absolute voltage at each pin relative to a gnd should be maintained in the 1v range during operation in order to ensure the measure- ment error performance. the common mode signals should be adapted to respect both the previous conditions and the differential input voltage range. for best performance, the common mode signals should be referenced to a gnd . the current channel comprises a pga on the front-end to allow for smaller signals to be measured without additional signal conditioning. the maximum differential voltage specified on channel 0 is equal to 470 mv/gain (see table 4-1 ). the maximum peak voltage specified on channel 1 is equal to 660 mv. 4.2 16-bit delta-sigma adcs the adcs used in the MCP3905/06 for both current and voltage channel measurements are delta-sigma adcs. they comprise a second-order, delta-sigma modulator using a multi-bit dac and a third-order sinc filter. the delta-sigma archit ecture is very appropriate for the applications target ed by the MCP3905, because it is a waveform-oriented c onverter architecture that can offer both high linearity and low distortion performance throughout a wi de input dynamic range. it also creates minimal requirements for the anti-aliasing filter design. the multi-bit architecture used in the adc minimizes quantization nois e at the output of the converters without di sturbing the linearity. both adcs have a 16-bit resolution, allowing wide input dynamic range sensing. the oversampling ratio of both converters is 64. both c onverters are continuously converting during normal operation. when the mclr pin is low, both converters will be in reset and output code 0x0000h. if the voltage at the inputs of the adc is larger than the specified range, the linearity is no longer specified. however, the co nverters will continue to produce output codes until their saturation point is reached. the dc saturation point is around 700 mv for channel 0 and 1v for channel 1, using internal voltage reference. the clocking signals for the adcs are equally distributed between the two channels in order to minimize phase delays to less than 1 mclk period (see section 3.2 ?high-pass filter input logic pin (hpf)? ). the sinc filters main notch is positioned at mclk/256 (14 khz with mclk = 3.58 mhz), allowing the user to be able to m easure wide harmonic content on either channel. the magnitude response of the sinc filter is shown in figure 4-2 . figure 4-2: sinc filter magnitude response (mclk = 3.58 mhz). 4.3 ultra-low drift v ref the MCP3905/06 contains an internal voltage reference source specially designed to minimize drift over temperature. this internal v ref supplies reference voltage to both current and voltage channel adcs. the typical value of this voltage reference is 2.4v, 100 mv. the internal reference has a very low typical temperature coefficient of 15 ppm/c, allowing the output frequencies to have minimal variation with respect to temperature since they are proportional to (1/v ref )2. refin/out is the output pin for the voltage reference. appropriate bypass capacitors must be connected to the refin/out pin for proper operation (see section 5.0 ?applications information? ). the voltage reference source impedance is typically 4 k , which enables this voltage reference to be overdriven by an external voltage reference source. table 4-1: MCP3905 gain selections g1 g0 ch0 gain maximum ch0 voltage 00 1470mv 01 2235mv 10 860mv 11 16 30 mv table 4-2: mcp3906 gain selections g1 g0 ch0 gain maximum ch0 voltage 00 1470mv 01 32 15 mv 10 860mv 11 16 30 mv -120 -100 -80 -60 -40 -20 0 0 5 10 15 20 25 30 frequency (khz) normal mode rejection (db)
? 2009 microchip technology inc. ds21948e-page 17 MCP3905/06 if an external voltage reference source is connected to the refin/out pin, the ex ternal voltage will be used as the reference for both current and voltage channel adcs. the voltage across the source resistor will then be the difference between the internal and external voltage. the allowed input range for the external voltage source goes from 2.2v to 2.6v for accurate measurement error. a v ref value outside of this range will cause additional heating and power consumption due to the source resistor, which might affect measurement error. 4.4 power-on reset (por) the MCP3905/06 contains an internal por circuit that monitors analog supply voltage av dd during operation. this circuit ensures correct device startup at system power-up/power-down events. the por circuit has built-in hysteresis and a timer to give a high degree of immunity to potential ripple and noise on the power supplies, allowing proper settling of the power supply during power-up. a 0.1 f decoupling capacitor should be mounted as close as possible to the av dd pin, providing additional transient immunity (see section 5.0 ?applications information? ). the threshold voltage is typically set at 4v, with a tolerance of about 5%. if the supply voltage falls below this threshold, the MCP3905/06 will be held in a reset condition (equivalent to applying logic ? 0 ? on the mclr pin). the typical hysteresis value is approximately 200 mv in order to prevent glitches on the power supply. once a power-up event has occurred, an internal timer prevents the part from outputting any pulse for approximately 1s (with mclk = 3.58 mhz), thereby preventing potential metast ability due to intermittent resets caused by an unsettled regulated power supply. figure 4-3 illustrates the different conditions for a power-up and a power-down event in the typical conditions. figure 4-3: power-on reset operation. 4.5 high-pass filters and multiplier the active (real) power value is extracted from the dc instantaneous power. therefore, any dc offset component present on channel 0 and channel 1 affects the dc component of the instantaneous power and will cause the real-power calculation to be erroneous. in order to remove dc offset components from the instantaneous power signal, a high-pass filter has been introduced on each channel. since the high-pass filtering introduces phase delay, identical high-pass filters are implemented on both channels. the filters are clocked by the same digital signal, ensuring a phase difference between the two channels of less than one mclk period. under typical conditions (mclk = 3.58 mhz), this phase difference is less than 0.005, with a line frequency of 50 hz. the cut-off frequency of the filter (4.45 hz) has been chosen to induce minimal gain error at typical line frequencies, allowing sufficient settling time for the desired applications. the two high-pass filters can be disabled by applying a logic ? 0 ? to the hpf pin. figure 4-4: hpf magnitude response (mclk = 3.58 mhz). the multiplier output gives the product of the two high- pass-filtered channels, corresponding to instantaneous active (real) power. multiplying two sine wave signals by the same frequency gives a dc component and a 2 component. the instantaneous power signal contains the active (real) power of its dc component, while also containing 2 components coming from the line frequency multiplication. these 2 components come for the line frequency (and its harmonics) and must be removed in order to extract the real-power information. this is accomplished using the low-pass filter and dtf converter. av dd 5v 4.2v 4v 0v device mode reset proper operation reset no pulse out time 1s -40 -35 -30 -25 -20 -15 -10 -5 0 0.1 1 10 100 1000 frequency (hz) normal mode rejection (db)
MCP3905/06 ds21948e-page 18 ? 2009 microchip technology inc. 4.6 low-pass filter and dtf converter the MCP3905/06 low-pass filter is a first-order iir filter that extracts the active (real) power information (dc component) from the instantaneous power signal. the magnitude response of this filter is detailed in figure 4-5 . due to the fact that the instantaneous power signal has harmonic content (coming from the 2 components of the inputs), and since the filter is not ideal, there will be some ripple at the output of the low-pass filter at the harmonics of the line frequency. the cut-off frequency of the filter (8.9 hz) has been chosen to have sufficient rejection for commonly-used line frequencies (50 hz and 60 hz). with a standard input clock (mclk = 3.58 mhz) and a 50 hz line frequency, the rejection of the 2 component (100 hz) will be more than 20 db. this equates to a 2 component containing 10 times less power than the main dc component (i.e., the average active (real) power). figure 4-5: lpf magnitude response (mclk = 3.58 mhz). the output of the low-pass f ilter is accumulated in the dtf converter. this accumulation is compared to a different digital threshold for f out0/1 and hf out , representing a quantity of r eal energy measured by the part. every time the digital threshold on f out0/1 or hf out is crossed, the part will output a pulse (see section 4.7 ?f out0/1 and hf out output frequencies? ). the equivalent quantity of real energy required to output a pulse is much larger for the f out0/1 outputs than the hf out . this is such that the integration period for the f out0/1 outputs is much larger. this larger integration period acts as anot her low-pass filter so that the output ripple due to the 2 components is minimal. however, these components are not totally removed, since realized low-pass filters are never ideal. this will create a small jitter in the output frequency. averaging the output pulses with a co unter or a microcontroller unit (mcu) in the application will then remove the small sinusoidal content of the out put frequency and filter out the remaining 2 ripple. hf out is intended to be used for calibration purposes due to its instantaneous power content. the shorter integration period of hf out demands that the 2 component be given more attention. since a sinusoidal signal average is zero, averaging the hf out signal in steady-state conditions will give the proper real energy value. -40 -35 -30 -25 -20 -15 -10 -5 0 0.1 1 10 100 1000 frequency (hz) normal mode rejection (db)
? 2009 microchip technology inc. ds21948e-page 19 MCP3905/06 4.7 f out0/1 and hf out output frequencies the thresholds for the accumulated energy are different for f out0/1 and hf out (i.e., they have differ- ent transfer functions). the f out0/1 allowed output frequencies are quite low in order to allow superior integration time (see section 4.6 ?low-pass filter and dtf converter? ). the f out0/1 output frequency can be calculated with the following equation: equation 4-1: f out frequency output equation for a given dc input v, the dc and rms values are equivalent. for a given ac input signal with peak-to- peak amplitude of v, the equivalent rms value is v/ sqrt(2), assuming purely sinusoidal signals. note that since the active (real) power is the product of two rms inputs, the output frequencies of an ac signal is half that of the dc equivalent signal, again assuming purely sinusoidal ac signal s. the constant f c depends on the f out0 and f out1 digital settings. ta b l e 4 - 3 shows f out0/1 output frequencies for the different logic settings. f out hz () 8.06 v 0 v 1 gf c v ref () 2 ----------------------------------------------------------- = where: v 0 = the rms differential voltage on channel 0 v 1 = the rms differential voltage on channel 1 g = the pga gain on channel 0 (current channel) f c = the frequency constant selected v ref = the voltage reference table 4-3: output frequency constant fc for fout0/1 (v ref =2.4v) f1 f0 f c (hz) f c (hz) (mclk = 3.58 mhz) f out frequency (hz) with full-scale dc inputs f out frequency (hz) with full-scale ac inputs 00 mclk/2 21 1.71 0.74 0.37 01 mclk/2 20 3.41 1.48 0.74 10 mclk/2 19 6.83 2.96 1.48 11 mclk/2 18 13.66 5.93 2.96
MCP3905/06 ds21948e-page 20 ? 2009 microchip technology inc. the high-frequency output hf out has lower integration times and, thus, higher frequencies. the output frequency value can be calculated with the following equation: equation 4-2: hf out frequency output equation the constant hf c depends on the f out0 and f out1 digital settings with the ta b l e 4 - 4 . the detailed timings of the output pulses are described in the timing characteristics table (see section 1.0 ?electrical characteristics? and figure 1-1 ). minimal output frequency for no-load threshold the MCP3905/06 also includes, on each output frequency, a no-load threshold circuit that will eliminate any creep effects in the meter. the outputs will not show any pulse if the output frequency falls below the no-load threshold. the minimum output frequency on f out0/1 and hf out is equal to 0.0015% of the maximum output frequency (respectively f c and hf c ) for each of the f2, f1 and f0 selections (see table 4-3 and table 4-4 ); except when f2, f1, f0 = 011 . in this last configuration, the no -load threshold feature is disabled. the selection of f c will determine the start-up current load. in order to respect the iec standards requirements, the meter will have to be designed to allow start-up currents compatible with the standards by choosing the fc value matching these requirements. for additional applications information on no-load threshold, startup current and other meter design points, refer to an994, "iec compliant active energy meter design using the MCP3905/6? , (ds00994). table 4-4: output frequency constant hf c for hf out (v ref =2.4v) hf out hz () 8.06 v 0 v 1 g hf c v ref () 2 --------------------------------------------------------------- - = where: v 0 = the rms differential voltage on channel 0 v 1 = the rms differential voltage on channel 1 g = the pga gain on channel 0 (current channel) f c = the frequency constant selected v ref = the voltage reference f2 f1 f0 hf c hf c (hz) hf c (hz) (mclk = 3.58 mhz) hf out frequency (hz) with full-scale ac inputs 000 64 x f c mclk/2 15 109.25 27.21 001 32 x f c mclk/2 15 109.25 27.21 010 16 x f c mclk/2 15 109.25 27.21 011 2048 x f c mclk/2 7 27968.75 6070.12 100 128 x f c mclk/2 16 219.51 47.42 101 64 x f c mclk/2 16 219.51 47.42 110 32 x f c mclk/2 16 219.51 47.42 111 16 x f c mclk/2 16 219.51 47.42
? 2009 microchip technology inc. ds21948e-page 21 MCP3905/06 5.0 applications information 5.1 meter design using the MCP3905/06 for all applications information, refer to an994, "iec compliant active energy meter design using the MCP3905/6? (ds00994). this application note includes all required energy meter design information, including the following: ? meter rating and current sense choices ? shunt design ? pga selection ? f2, f1, f0 selection ? meter calibration ? anti-aliasing filter design ? compensation for parasitic shunt inductance ?emc design ? power supply design ? no-load threshold ? start-up current ? accuracy testing results from MCP3905-based meter ? emc testing results from MCP3905-based meter
MCP3905/06 ds21948e-page 22 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds21948e-page 23 MCP3905/06 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xxxxxxxxxxxx yywwnnn 24-lead ssop examples: xxxxxxxxxxxx MCP3905l 0906256 i/ss ^^ 3 e
MCP3905/06 ds21948e-page 24 ? 2009 microchip technology inc.
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? 2009 microchip technology inc. ds21948e-page 25 MCP3905/06 appendix a: revision history revision e (june 2009) the following is the list of modifications: 1. document marked ?obsolete device?. 2. updated packaging outline drawings. revision d (february 2007) the following is the list of modifications: 1. updates to the packaging diagrams. revision c (october 2005) the following is the list of modifications: 1. added references to MCP3905/06 throughout document. revision b (august 2005) the following is the list of modifications: 1. replace figures 2-1 thru 2-6 in section 2.0 ?typical performance curves? revision a (july 2005) ? original release of this document.
MCP3905/06 ds21948e-page 26 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds21948e-page 27 MCP3905/06 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device: MCP3905l:energy-metering ic MCP3905lt:energy-metering ic (tape and reel) mcp3906: energy-metering ic mcp3906t: energy-metering ic (tape and reel) temperature range: i = -40c to +85c package: ss = plastic shrink small outline (209 mil body), 24-lead examples: a) MCP3905l-i/ss: industrial temperature, 24ld ssop. b) MCP3905lt-i/ss:tape and reel, industrial temperature, 24ld ssop. a) mcp3906-i/ss: industrial temperature, 24ld ssop. b) mcp3906t-i/ss: tape and reel, industrial temperature, 24ld ssop.
MCP3905/06 ds21948e-page 28 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds21948e-page 29 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, nanowatt xlp, omniscient code generation, picc, picc-18, pickit, picdem, picdem.net, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, wiperlock and zena are trademarks of microc hip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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