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1/21 rev. d structure silicon monolithic integrated circuit product series 7-channel switching regulator controller for digital camera type ? package fig. 1 (plastic mold) hqfn-48u package pin assignment fig. 2 block diagram fig. 3 application circuit fig. 4 features 1.5v minimum input operating. controls up to 7 switching regulators. st ep up converter (1channel), step-down converter (1channel), configurable for step-up or step-down conversion (3channels), positive to negative converter (1channel), step-up converter for led (1channel). synchronous rectifying action mode (4channel), built-in fet transistor. step-up converter for ccd,built-in fet transistor. internal compensation. operating frequency 1.2mhz(ch1 4), 600khz(ch5 7). short circuit protection(sc p) for over load condition. built-in load switch with soft-start for step-up converter(ch6,7). back gate control synchronous re ctified dc/dc for step-up(ch1,2,4). thermally enhanced qfn48 package. ( 7mmx 7mm 0.4mm pitch ) absolute maximum ratings ta 25 parameter symbol limits units power supply voltage vbat, vcc, pvcc 0.37 v power input voltage pvcc5, hs6h, hs7h 0.37 v vhx14 0.37 v vlx14 0.37 v vlx6 0.318 v output current iomaxlx1 1.8 a iomaxlx24 1.5 a power dissipation pd 0.65(*1) w 1.50(*2) w operating temperature topr 25+85 storage temperature tstg 55+150 junction temperature tjmax +150 (*1) without external heat sink, the power dissipation reduces by 5.2mw/ over25 . (*2) reduced by 12mw/ over 25 , when mounted on a pcb (70.0mm 70.0mm 1.6mm). recommended operating conditions parameter symbol spec. units power supply voltage vbat 1.5 5.5 v vcc, pvcc 2.5 5.5 v
2/21 rev. d recommended operating conditions parameter symbol standard value units conditions min typ max vref pin connect capacitor cvref 0.47 1.0 4.7 f vrega pin connect capacitor cvrega 0.47 1.0 4.7 f scp pin connect capacitor cscp - - 0.47 f oscillator oscillator frequency fosc 0.6 1.2 1.5 mhz osc timing resistor r t 47 62 120 k driver p-channel drain current(ch1 4) idpl - - 1.5 a n-channel drain current(ch1 4) idnl - - 1.5 a n-channel drain current (ch6) idnh - - 1.0 a p-channel drain current (load sw of ch6 7) idpr - - 1.5 a driver peak current (ch5, 7) idpeak - - 500 ma
3/21 rev. d electrical characteristics ta = 2 5 vbat=3v, vcc=5v, rt=62kohm, stb1 7=3v parameter symbol spec. units conditions. te s t min. typ. max circuit reference voltage for ch5 reference voltage vref5 0.99 1.00 1.01 v stb5=3v line regulation dvli - 4.0 12.5 mv vcc=2.8v 5.5v load regulation dvlo - 1.0 7.5 mv iref=10 a 100 a short circuit output current ios 0.2 1 - ma vref=0v internal regulator rega output voltage vrega 2.4 2.5 2.6 v ireg=5ma low voltage input prevented operation faults circuit threshold voltage 2 vstd2 2.3 2.4 2.5 v vcc monitor hysteresis width 2 vst2 100 200 300 mv threshold voltage 3 vstd3 1.6 2.0 2.3 v vrega monitor hysteresis width 3 vst3 100 200 300 mv start up circuit oscillator frequency fstart 150 300 600 khz minimum vbat voltage vst1 1.5 - - v soft-start time tss1 2.6 4.2 7.4 msec soft-start soft-start time (ch2 4,ch6,7) tss4 6.8 8.5 10.2 msec soft-start time ch5 tss3 5.8 7.7 9.6 msec vref5monitor protection circuit timer start threshold voltage vtcfb 2.1 2.2 2.3 v error amp output monitor ch1,5 7 timer start threshold voltage vtcinv 0.56 0.64 0.72 v inv monitor ch2 4 scp standby voltage vssc - 22 170 mv scp output current iscp 2 4 6 a vscp=0.1v scp threshold voltage vscp 0.9 1.0 1.1 v triangular wave oscillator oscillator frequency ch1 4 osc1 1.0 1.2 1.4 mhz rt=62kohm oscillator frequency ch5 7 osc2 500 600 700 khz rt=62kohm error amp input bias current iinv -5 0 5 a inv1~4,6,7,7i,non5=7.0v inv threshold vinv 0.79 0.80 0.81 v ch1 4,ch6,7v non5 threshold vinv5 -12 0 12 mv ch5 inv7i threshold vinv7i 380 400 420 mv ch7i pwm comparator max duty1, 2,3,4 dmax2 86 92 97 % max duty5, 6,7 dmax4 77 85 93 % this product is not designed for normal operat ion within a radioactive environment.
4/21 rev. d electrical characteristics ta = 2 5 vbat=3v, vcc=5v, rt=62kohm, stb1 7=3v parameter symbol spec. units conditions te s t min typ. max. circuit output circuit ch1,2,3,4 pch fet on resistor ronlp - 250 350 m hx=5v ch1 nch fet on resistor ron1n - 80 120 m pvcc=5v ch2,3,4 nch fet on resistor ron2n - 130 200 m pvcc=5v ch6,7 load sw on resistor ronl - 250 350 m hs6, 7h=5v ch6 nch fet on resistor ronh - 450 700 m pvcc=5v out5 high-level output voltage on driving vout5h pvcc5 -1.0 pvcc5 -0.5 - v pvcc5=5v,iout5=50ma non5=0.2v out5 low-level output voltage on driving vout5h - 0.5 1.0 v pvcc5=5v,iout5= - 50ma non5=-0.2v out7 high-level output voltage on driving vout7h pvcc -1.0 pvcc -0.5 - v pvcc=5v,iout7=50ma inv7i=0v,inv7=0.4v out7 low-level output voltage on driving vout7h - 0.5 1.0 v pvcc=5v,iout7= - 50ma inv7i=0.6v,inv7=1.2v step-up / down selection udsel12, udsel3 control voltage step down vuddo vbat 0.7 - vbat v step up vudup 0 - vbat 0.3 v 1 7 stbcontrol voltage on vstbh1 1.5 - 5.5 v off vstbl1 -0.3 - 0.3 v stb pull-down resistor rstb1 250 400 700 k circuit current stand by current vbat istb1 - - 5 a vcc, pvcc istb2 - - 5 a hx istb3 - - 5 a step-down udsel1, 2,4=vbat lx istb4 - - 5 a step-up udsel1, 2,4=0v start up current (vbat sink current) ist - 300 1000 a vbat=1.5v circuit current on driving 1 (vbat sink current) icc1 - 200 400 a vbat=3.0v circuit current on driving 2 vcc,pvcc sink current icc2 - 4.8 8.5 ma stb1 7=3v inv=2.5v this product is not designed for normal operat ion within a radioactive environment.
5/21 rev. d fig. 1 package fig. 2 pin assignment ? ? 1pin notice : do not use the dotted line area for soldering
6/21 rev. d pin description pin no. name i / o description notes 22 vbat - power supply for the start-up circuit drive over 1.5v 31 vcc - power supply drive over 2.5v 21 pvcc - power supply for nch driver drive over 2.5v 2 pvcc5 - power supply for ch5 pch driver. 33 gnd - ground 17-18,6-7,43 pgnd12,34,567 - power ground for the built-in fet. 30 vrega o output of rega output voltage=2.5v 34 vref o output of ch5 reference. output voltage=1.0v 1 out5 o connect to the gate of ch5 external pch fet. 42 out7 o connect to the gate of ch7 external nch fet. 14,20,9,4 hx1,2,3,4 o power supply for built-in pch fet. 15-16,19,8,5,44 lx1,2,3,4,6 o connect to the inductor. 46,40 hs6h, hs7h i power supply for built-in high side-sw. 45,41 hs6l, hs7l o output of built-in high side-sw. 26,25,27,28,36,38 inv1,2,3,4,6,7 i error amp inverted input. 35 non5 i error amp non-inverted input. 37 inv7i i error amp inverted input. for current feed back 29 rt - a resistor is placed to set the osc frequency. output voltage=1.0v clk frequency 1.2mhz connecting 62k to gnd. 32 scp - connect to a capacitor to set up the delay time of the scp. charge up current 4 a until 1.0v. 23,24,3 udsel1,2,4 i step-up/down switching mode selection h: step-down l: step-up 13,12,11,10,48,47,39 stb1,2,3,4,5,6,7 i on/off sw h: operating over 1.5v all low; stand-by
7/21 rev. d fig. 3 block diagram 30.vrega reg a u.v.l.o timer s q r latch to driver + - - - - 2.2v scp cmom1,5,6,7 to control block start-up osc vbat ss stb1 + - + + - errcomp1 erramp1 step up/down selector1 + - + + - pch driver nch driver pvcc ch1 step up /down current mode control pch driver nch driver pvcc scpcomp2 erramp2 step up/down selector2 + - + + - pch driver nch driver pvcc erramp3 scpcomp3 udsel2 step up/down selector4 + - + + - pch driver nch driver pvcc erramp4 to erramp udsel4 voltage referennce ss5 + + - vrega + - pch driver erramp5 rood sw + + - vrega nch driver rood sw + + - erramp6 pwm comp5 pwm comp6 vrega nch driver + + - erramp7v pwm comp7 pvcc + + - + + + - uvlo 7v,7i priority l soft start stb ss_clk osc on/off logic 14.hx1 15-16.lx1 17-18.pgnd12 21.pvcc 20.hx2 9.hx3 22.vbat 19.lx2 8.lx3 4.hx4 5.lx4 6-7.pgnd34 2.pvcc5 1.out5 46.hs6h 44.lx6 43.pgnd567 40.hs7h 41.hs7l 42.out7 45.hs6l 32.scp 33.gnd 31.vcc 26.inv1 25.inv2 27.inv3 28.inv4 34.vref 35.non5 36.inv6 38.inv7 37.inv7i 29.rt 13.stb1 12.stb2 11.stb3 10.stb4 48.stb5 47.stb6 39.stb7 23.udsel1 24.udsel2 3.udsel4 ch2 step up /down current mode control ch3 step down current mode control ch4 step up /down current mode control bg ctl pvcc bg ctl bg ctl udsel1 scp comp4 pvcc erramp7i 0.8v 0.8v 0.8v 0.8v 0.8v 0.8v 0.4v
8/21 rev. d vrega reg a u.v.l.o timer s q r latch to driver + - - - - 2.2v scp cmom1,5,6,7 to control block start-up osc vbat ss stb1 + - + + - errcomp1 erramp1 step up/down selector1 + - + + - pch driver nch driver pvcc ch1 step up /down current mode control pch driver nch driver pvcc scpcomp2 erramp2 step up/down selector2 + - + + - pch driver nch driver pvcc erramp3 scpcomp3 udsel2 step up/down selector4 + - + + - pch driver nch driver pvcc erramp4 to erramp udsel4 voltage referennce ss5 + + - vrega + - pch driver erramp5 rood sw + + - vrega nch driver rood sw + + - erramp6 pwm comp5 pwm comp6 vrega nch driver + + - erramp7v pwm comp7 pvcc + + - + + + - uvlo 7v,7i priority l soft start stb ss_clk osc on/off logic hx1 lx1 pgnd12 pvcc hx2 hx3 vbat lx2 lx3 hx4 lx4 pgnd34 pvcc5 out5 hs6h lx6 pgnd567 hs7h hs7l out7 hs6l scp gnd vcc inv1 inv2 inv3 inv4 vref non5 inv6 inv7 inv7i rt stb1 stb2 stb3 stb4 stb5 stb6 stb7 udsel1 udsel2 udsel4 ch2 step up /down current mode control ch3 step down current mode control ch4 step up /down current mode control 5.0v for analog,ic unreg 1.83.0v vo1 (feed back 1ch) vo2 (feed back 2ch) 2.8v for digital vo3 (feed back 3ch) 1.2v for asic vo4 (feed back 4ch) 3.4v for analog vo5 (feed back 5ch) -8v for ccd vo6 (feed back 6ch) 12v for ccd vo7 (feed back 7ch) for back light led inv7i vo7 vo6 vo5 vo4 vo3 vo2 vo1 pvcc bg ctl bg ctl bg ctl udsel1 scpcomp4 erramp7i pvcc 0.8v 0.8v 0.8v 0.8v 0.8v 0.8v 0.4v vbat fig. 4 application circuit for nih 2 2cell note the following application circuit is recommended. make sure to confirm its characteristics. when making changes to the external components, make sure to leave adequate margin such as static and transitional characteristics, as well as dispersion of the ic.
9/21 rev. d fig. 4 2 application circuit for li battery 1cell note the following application circuit is recommended. make sure to confirm its characteristics. when making changes to the external components, make sure to leave adequate margin such as static and transitional characteristics, as well as dispersion of the ic. vrega reg a u.v.l.o timer s q r latch to driver + - - - - 2.2v scp cmom1,5,6,7 to control block start-up osc vbat ss stb1 + - + + - errcomp1 erramp1 step up/down selector1 + - + + - pch driver nch driver pvcc ch1 step up /down current mode control pch driver nch driver pvcc scpcomp2 erramp2 step up/down selector2 + - + + - pch driver nch driver pvcc erramp3 scpcomp3 udsel2 step up/down selector4 + - + + - pch driver nch driver pvcc erramp4 to erramp udsel4 voltage referennce ss5 + + - vrega + - pch driver erramp5 rood sw + + - vrega nch driver rood sw + + - erramp6 pwm comp5 pwm comp6 vrega nch driver + + - erramp7v pwm comp7 pvcc + + - + + + - uvlo 7v,7i priority l soft start stb ss_clk osc on/off logic hx1 lx1 pgnd12 pvcc hx2 hx3 vbat lx2 lx3 hx4 lx4 pgnd34 pvcc5 out5 hs6h lx6 pgnd567 hs7h hs7l out7 hs6l scp gnd vcc inv1 inv2 inv3 inv4 vref non5 inv6 inv7 inv7i rt stb1 stb2 stb3 stb4 stb5 stb6 stb7 udsel1 udsel2 udsel4 ch2 step up /down current mode control ch3 step down current mode control ch4 step up /down current mode control 5.0v for analog,ic unreg 2.54.2v vo1 (feed back 1ch) vo2 (feed back 2ch) 2.8v for digital vo3 (feed back 3ch) 1.2v for asic vo4 (feed back 4ch) 3.4v for analog vo5 (feed back 5ch) -8v for ccd vo6 (feed back 6ch) 12v for ccd vo7 (feed back 7ch) for back light led inv7i vo7 vo6 vo5 vo4 vo3 vo2 vo1 pvcc bg ctl bg ctl bg ctl udsel1 scpcomp4 erramp7i pvcc 0.8v 0.8v 0.8v 0.8v 0.8v 0.8v 0.4v vbat
10/21 rev. d i/o equivalent circuit diagrams pin. no pin name input / output description pin circuit note 26 25 27 28 36 38 37 inv1 inv2 inv3 inv4 inv6 inv7 inv7i i i i i i i i error amp inverting input pin. vcc 35 non5 i error amp non-inverting input pin. vcc 29 rt connect to resistor to set up the osc frequency. vcc rt 32 scp connect to capacitor to set up the delay time for the timer-latch. vcc scp
11/21 rev. d pin. no pin name input / output description pin circuit note 30 vrega o rega output voltage vcc vcc vrega 34 vref o reference voltage for ch5. vrega vcc vref 23 24 3 22 udsel1 udsel2 udsel4 vbat i i i - step-up/down switching mode selection h= step-down l= step-up battery input. vbat udsel 13 12 11 10 48 47 39 stb1 stb2 stb3 stb4 stb5 stb6 stb7 i i i i i i i ch17 on/off switches, high = operating vcc stb
12/21 rev. d pin. no pin name input / output description pin circuit note 14,20,4 15, -16,19,5 17-18,6-7 hx1, 2,4 lx1, 2,4 pgnd12, 34 o o - pch fet source. nch, pch fet drain. ground. vcc pgnd lx hx 9 8 hx3 lx3 o o pch fet source nch, pch fet drain vcc pgnd34 lx3 hx3 21 42 43 pvcc out7 pgnd567 - o - power supply for nch driver. connect to the gate of ch7 external nch fet. ground. vcc pgnd567 out7 pvcc vcc vcc
13/21 rev. d pin. no pin name input / output description pin circuit note 2 1 43 pvcc5 out5 pgnd567 - o - power supply for driver. connect to the gate of ch5 external pch fet. ground. pgnd567 out5 pvcc5 44 45 lx6 pgnd567 o - nch fet drain. lx6 pgnd567 46,40 45,41 hs6h, 7h hs6l, 7l i o input of pmos high-side sw. output of pmos high-side sw. hs6h,7h hs6l,7l vcc vcc
14/21 rev. d block description 1. rega this is an internal regulator that gener ates a 2.5v regulated output voltage. rega supplies power for all th e remaining circuit blocks. the output voltage can be supplied to external devices from vrega (30pin). to prevent any oscillations at the output, a 1 f external capacitor is recommended. 2 short circuit protect, timer latch when error amp?s output of ch1,5 7 voltages rise beyond 2.2 v, or inv pin voltage of ch2,3,4 fall under 80% of reference, the timer circuit is activated. this will charge up the ca pacitor connected to scp (32pin) by approximately 4 a current. when the voltage reaches 1.0 v, the latch circuit is activated. while this protection circuit is activated, the entire channel?s output is turned off. in order to reset the latch circuit, two methods can be used: 1) disable the stb pin before enabling it. 2) removing or refreshing the power supply voltage. 3 u.v.l.o this circuit protects the ic from a transient surge at power-on or a momentary drop of the power supply voltage. under voltage lockout is activated when the vcc pin voltage falls below 2.4v. during activation, the output drive pi ns for all channels is turned off. 4 voltage reference (vref) the reference voltage circuit for ch5 generates a 1.0v output voltage. the reference voltage can be supplied from vref (34pin). this reference voltage is used to set the output voltag e of ch5. when stb5 is enable, the reference is ramping to 1v. inverting voltage of ch5 is following this reference. to prevent any oscillations at the output, a 1 f external capacitor is recommended. 5 osc the BD9745EKN include a triangular waveform oscillator for voltage-mode pwm controllers, and slope oscillator for current-mode pwm controllers. to set the oscillator frequency, connect a timing resistor to the rt (29 pin). w hen the resistor is 62k, it is set 1.2mhz(ch14), 600khz(ch57 ).
15/21 rev. d 6soft start , ss1 the circuit prevents inrush current in startup by ramping dc/dc output voltage. the soft-start time of each channel is designed below. a. ch1 ??????? typical ic design?s output startup time is 4.2msec. only ch1, the startup time doesn?t depend on osc frequency. b. ch5 ??????? the soft start function of ch5 is accomplished by ramping the vref pin (30pin) from 0v to 1v over period of about 10000 slope cycle(7.7msec at 1.2mhz). c. ch2,3,4,6,7 ??? the soft start function of these channel is accomplished by internal reference over period of about 10000 slope cycle(8.5msec at 1.2mhz). 7 erramp 1 7 this amplifier monitors the output voltage of the switching regulator channels and outputs a pwm controlled signal accordingly. erramp1, 2,3,4,6,7?s reference voltage is set by applying voltage of 0.8v. erramp5?s reference voltage connected to gnd, erramp7i?s reference voltage is set to 0.4v. and all channels have the r-c component for internal compensation. 8 errcomp , start up osc the error comparator monitors the output voltage of the switching regulator and outputs a pfm controlled signal accordingly. the start up osc operates when power supply voltage reaches 1.5v, and is switched on/off by output of errcomp. this osc oscillates at around 300khz. when vcc voltage is above 2.6v, or ch1 soft-start time is over, this circuit stops to oscillate. 9 current mode control block dc/dc converter of ch1 4 operates on current-mode pwm. in curr ent-mode pwm controll er, main fet turn on to detect clk edge, and turn off to detect a peak current of inductor. using udsel pins, dc/dc converter of ch1 4 is switched to step-up converter or step-down converter. 10 pwm comp the pwm comparators are voltage - pulse width converters that control the output pulse on time according to the input voltage. the circuit supplies a pulse width controlled signal to the driver, by comparing the triangular wave oscillator with the error amplifier?s output voltage. the maximum on-duty is established internally at approximately 85%.
16/21 rev. d 11 nch driver this cmos inverting output circuit is a driver block with built-in and external nch fet. pvcc pin voltage for driver must have same voltage with vcc pin voltage for main block. 12 pch driver this cmos inverting output circuit is a driver block with built-in and external pch fet. 13 road sw this circuit controls high-side load switch with ch6, 7. hs6h, 7h (40,46pin) is input, and hs6l, 7l (41,45) is output. this circuit controls by ramping the hs6l, 7l voltage on startup to decrease in-rush current. 14 back gate control this circuit controls to switch back-ga te voltage of built-in pch-fet. (ch1, 2,4) in monolithic ic of p-sub, the parasitic diode remains between back-gate (cathode), and source, drain (anode). this circuit cut current pass through the parasitic diode in step-up situation on stb off. 15 on/off logic the output of each channel can be turned on and off by the input voltage applied on the stb pin. the channel is ?on? when the voltage of the stb pin is above 1.5 v. the channel is ?off? when the voltage applied at stb pin is 0 v or the pin is left open. when all channels are ?off?, the device is at stand-by state. each logic pin is connected to gnd via a 400k pull-down resistor. 16 udsel logic the output of ch1, 2, 4 can be switched step-d own/up by input voltage applied on the udsel pin. the output is at step-up mode when udsel is gnd, and step-down mode when udsel is vbat. udsel pin must be connected to gnd or vbat to prev ent unstable logic state, due to this logic is cmos inverter powered vbat.
17/21 rev. d application information .) ch1 start up sequence. using step up function in ch1, please take below measure to prevent operation faults and destruction on start-up. ? ch1 output input to vcc it must be put schottky di between lx1 and hx1 to clamp lx1 voltage the input of vbat pin must short to vcc line and input thro ugh c-r filter. (ref fig-7) ? a battery input to vcc, or external power supply input to vcc. fig 5 the errcomp circuit that adjust ch1 output voltage on uvlo condition, switches lx1 nmos on/off to compare inv1 and soft -start output. in this circuit, if it is late to switch from start up osc to main current mode control, it is possible that the output voltag e is overshot (ref, fig 6) as a rule, vcc voltage is applied before applying stb voltage, or applied at the same time. at the worst, when vcc voltage is a pplied late from stb, uvlo function must be canceled within 1msec from applying stb voltage. fig 5 vcc stb1 0 2.6v within 1msec ss stb1 errcomp erramp hx1 uvlo ? on 0.8v inv1 start-up osc on/off + + - current mode control block + - nch driver pch driver lx1 pgnd12 uvlo and udsel ? on stb,uvlo errcomp: to compare ss and inv1 fig - 6 ch1 block diagram: start up circuit fig ? 7. recommended application circuit of ch1 vcc pch driver nch driver pvcc ch1 step up /down current mode control hx1 lx1 pgnd12 pvcc vbat 5.0v unreg vo1 (feed back 1ch) bg ctl udsel udsel pin of l c rb551v-30 r a parameter of c-r c step-down short to vbat vbat pin connect to vcc,pvcc line capacitance[uf] 10 4.7 1 110 2.210 10 resistance[]
18/21 rev. d .) applying condition of vbat voltage. the up/down selector udsel1,2,4 is constructed by inverter circuit whose power is vbat, therefore it is possible that operation faults is happen to apply stb voltage without applying vbat voltage. as a rule, vbat voltage is applied before applying stb voltage, or applied at the same time. at the worst, when vbat voltage is applied late from stb, vbat voltage must be applied within 50 sec from applying stb voltage. .) recommended operating condition of using back-gate control. the dc/dc converters of ch1,2,4 have back-gate control to cut th e current pass of pmos parasitic diode. using the back-gate con trol, it is limited by the ability of pmos parasi tic diode and pmos switching back-gate position. when synchronous rectifying fet is off in normal operation and stb off, the inductor current flows to hx through pmos parasit ic diode (d2) and pmos switching back-gate position (m2). as a result, the voltage of lx increase to ?output voltage + d2 forward voltage vf + voltage drop of m2?. when hx voltage is set to 5v, this voltage exceed absolute maximum voltage of lx by increasing input current to about 1.2a. so that it is possible to break built-in fet. fig-10 shows recommended operating area of using back-gate control. when the relation between output voltage and input curren t is out of range, it must be added schottky barrier diode between lx and hx. using schottky barrier diode, back-gate control can be used not to e xceed absolute maximum voltage of lx. the dc/dc converter of ch1 must be added schottky barrier diode as it is explained in item 1). .) setting the detection time for the short-circuit-protector (scp). the detection time for the scp is user-adjustable by varying the capacitor connected at scp (pin32). the detection time [sec] = cscp vtsc / iscp (cscp : the capacitance vtsc : the threshold voltage scp iscp :the scp output current) ex cscp = 0.1 f the detection time = 0.1 10 -6 1 / {4 10 -6 } = 25msec as the built-in fet breaks by heat in shorting output, it is recommended that the scp capacitor is used below 0.47 f. stb vbat within 50 sec fig-8 fig - 9 back gate control ( ) ( ) hx lx pgnd normally l normally h on off d1 d2 forward voltagevf m2 m3 m1 m4 m2 drop due to on resistance v input current d2 ( ) 0.0 0.5 1.0 1.5 2.0 0123456 output voltage [v] input current [a] 1.2a @4.2v 1.5a @3.6v fig - 10 recommended operating area of using back-gate recommended region 0.8a @5.0v
19/21 rev. d .) built-in pch fet(ch1 4,ch67),the drop of current ability in low battery voltage situation the on resistance of the built-in pch fet increase because the fet operates in the saturation region below vgs=1.3v. therefore when ch6, 7 step-up converter or step-down channel from a battery is used below 1.8v, the drop is must be considered. if operating condition below 1.8v should be anticipated, it is recommended that the converter is formed from other channel?s ou tput and is not used high side switch. .) setting the oscillator frequency. the oscillator frequency is user-adjustable by varyi ng the resistor co nnected to rt (29pin). the ch1 4 frequency is set 1.2mhz to connect 62k ,and the rt value is inverse proportional relation to the frequency. the ch5 7 frequency is set half value of the ch1 4 frequency. fig.12 shows the relation the rt value and the frequency. 0.1 1 10 100 012345 gate - source voltage v gs [v] pmos on resistance[] i ds =200ma 0.1 1 10 100 012345 gate - source voltage v gs [v] pmos on resistance[] i ds =200ma fig - 11 built-in pm os on resistance - v gs a. ch b. ch highside switch fig -12 oscillator frequency ? rt resister (ex) 100 1000 10000 10 100 1000 r t [ k ] oscillator frequency [khz] ch14 ch56 recommended region recommended region
20/21 rev. d .) setting the output voltage. a. setting for positive to negative converter (ch5). the reference of ch5 error amp is internally connected to ground. so the high accuracy regulator can be formed up to set up a r esistor divider to fig.13, it is recommended that r1 resistance is over 20k , because current ability of vref is about 100 a. ch5 output b. setting the feed back of ch7 ch7 has two erroramp whose reference is different. error amp 7i controls constant current feed back for led back light, and erroramp7v controls over voltage feed back and constant voltage feedback. each erroramp setting shows below formula. the lower output of two erramp controls the dc/dc output. there fore, if it is used only one erroramp, other erroramp input mus t be shorted to gnd. ef non5 error amp5 ch5 output fig-13 setting for ch5 feed back resistor non is connected to gnd . vref = 1v r2 r1 (example) r1 = 20k , r2 = 160k ch5 output = -8.0v = r2 r1 = fig -14 setting for voltage and current of ch7. + - + - ch7 output io7 r3 r1 r2 vo7 inv7 inv7i error amp7v error amp7i 0.8v 0.4v priority l ch7 output current = example r3 = 20 ? io7 = 20ma 0.4v r3 ch7 output voltage = 0.8v example r1 =180k , r2=15k ? vo7=13v r1+r2 r2
21/21 rev. d operation notes .) absolute maximum ratings this product is produced with strict quality control. however, the ic may be destroyed if operated beyond its absolute maximum ratings. if the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (e.g. short mode, open mode) therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. .) gnd potential make sure gnd is connected at lowest potential. all pins except non5, must not have voltage below gnd. also, non5 pin must not have voltage below - 0.3v on start up. .) setting of heat make sure that power dissipation does not exceed maximum ratings. .) pin short and mistake fitting avoid placing the ic near hot part of the pcb. this may cause damage to ic. also make sure that the output-to-output and output to gnd condition will not happen because this may damage the ic. .) actions in str ong magnetic field exposing the ic within a strong magnetic field area may cause malfunction. .) mutual impedance use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. use inductor and capacitor network to keep the ripple voltage minimum. .) voltage of stb pin the threshold voltages of stb pin are 0.3v and 1.5v. stb state is set below 0.3v while action state is set beyond 1.5v. the region between 0.3v and 1.5v is not recommended and may cause improper operation. the rise and fall time must be under 10msec. in case to put capacitor to stb pin, it is recommended to use under 0.01 f. .) thermal shutdown circuit (tsd circuit) the ic incorporates a built-in thermal shutdown circuit (tsd circuit). the thermal shutdown circuit (tsd circuit) is designed only to shut the ic off to prevent runaway thermal operation. it is not designed to protect the ic or guarantee its operation. do not continue to use the ic after operating this circuit or use the ic in an environment where the operation of this circuit is assumed. .)ic terminal input this ic is a monolithic ic that has a p- board and p+ isolation for the purpose of keeping distance between elements. a p -n junction is formed between the p-layer and the n-layer of each element, and various types of parasitic elements are then formed. for example, an application where a resistor and a transistor are connected to a terminal (shown in fig.15): when gnd > (terminal a) at the resistor and gnd > (terminal b) at the transistor (npn), the p-n junction operates as a parasitic diode. when gnd > (terminal b) at the transistor (npn), a parasitic npn transistor operates as a result of the nhayers of other elements in the proximity of the aforementioned parasitic diode. parasitic elements are structurally inevitable in the ic due to electric potential relationships. the operation of parasi tic elements induces the interference of circuit operations, causing malfunctions and possibly the destruction of the ic. please be careful not to u se the ic in a way that would cause parasitic elements to operate. for example, by applying a voltage that is lower than the gnd (p-board) t o the input terminal. terminal ? gnd parasitic element parasitic element terminal b transistor (npn) gnd p-board n p n p p b n e c gnd p-board n p n n p p terminal a parasitic element resistor fig - 15 simplified structure of a bipolar ic
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