system-on-chip product letter system-on-chip lite (soclite) is nec?s new approach to low- to mid-volume system-on- chip projects. soclite is based on standard asic technology and consists of two blocks: an arm7tdmi ? based subsystem and a sea-of-gates area. the arm ? subsystem is fully designed and verified as a supermacro. it frees the user from the task of developing a complete risc computer system. the sea-of-gates area allows the user to implement custom logic or special peripheral functions. soclite is designed for embedded control applications. to maintain flexibility, soclite is not realized as an assp (application-specific standard product); this means that it can be used for a wide range of different applications. once the customer functions are implemented into the sea-of-gates, it becomes a custom soc. the soclite concept is especially interesting for the industrial and telecommunication market. target applications are factory automation, industrial bus systems, card readers, business phones, terminals and home communication. because of its low unit cost, low nre cost and short prototyping turnaround times, soclite is also an ideal solution for emerging applications with uncertain market acceptance. description applications features block diagram arm7tdmi ? core 32-bit arm ? and 16-bit thumb ? instruction set 32-bit x 8-bit multiplier ram: 8 kbytes bootstrap rom: 2 kbytes memory controller supporting: flash, sram and rom programmable interrupt controller: 32 interrupts, 8 priority levels s ystem - on -c hip l ite gate array with arm7tdmi ? subsystem system@ic solutions on a chip peripherals: uart, timer, reset, watchdog, pll, oscillator jtag test and debug interface sea-of-gates: up to 190k raw gates available for user defined logic apb interconnection to the udl operating frequency: 35 mhz operating voltage: 3.3 v + 0.3 v temperature range: -40 to +85c 256-pin pbga package jtag interrupt controller uart system decoder ahb wrapper internal ram/rom arbiter tic memory bus interface timer reset watchdog osc pll clk generator arm7tdmi ahb-if memory controller ahb to abp bridge external memory ahb apb gnt/req select u ser d efined l ogic irq firq re-map ?
functional block description the soclite cpu is the popular arm7tdmi ? , an arm7 tm 32-bit risc processor core with the thumb ? extension, on-chip debugging and 32 x 8 multiplier. thumb ? offers 32-bit risc performance at 16-bit system cost through ?compression? of the original arm ? instruction set, resulting in excellent code density and thus saving memory space. the thumb ? instructions are ?decompressed? on the fly into full 32-bit arm ? instructions. it is also possible to select between arm ? and thumb ? modes during instruction execution. the arm7tdmi ? subsystem includes a fully amba tm compliant bus system structure. two main buses ? ahb and apb ? connect the different macros. the ahb is a high-speed multimaster bus for connection to high-speed macros like cpu and memory controller. the apb is a lower speed bus for peripherals like uart, timer, etc. both buses are 32 bits wide. the apb and any additional signals required for interrupts and reset are made available to the udl. soclite clock generation has three parts: an oscillator, a programmable pll and a programmable clock divisor. the recommended operating frequency is selectable between 15 and 35 mhz. the memory subsystem features an internal 8-kbyte ram and a small 2-kbyte rom. the rom contains a bootstrap loader program, selectable via an external pin, for device start-up. the soclite memory controller supports static memory-mapped devices including sram, rom, flash and burst rom. the address range per chip select is 64 mbytes with a 32-bit external memory data path. the interrupt controller supports up to 32 interrupts: 29 interrupts from the udl and 3 from the arm ? subsystem. all interrupts are priority controlled, individually or globally maskable and selectable by triggering the irq of the arm ? core. the subsystem contains a simple uart and a timer consisting of a 32-bit down counter with load registers. a configurable prescaler generates the timer clock frequency. a second timer is used as a watchdog timer, generating a reset on overflow. the sea-of-gates area for the user defined logic has a size of 190k raw gates. the udl area is connected via the apb bus with the arm ? subsystem. the udl is for user-developed functions. these can be additional peripheral blocks or hardwired logic functions for reducing the cpu load. the custom logic is implemented into the soclite chip using the nec gate array design flow. in addition nec supports fpga conversion services for customers not familiar with standard asic design flow. for further information refer to the product letters ?soclite development board? and ?soclite design flow?. cpu bus system clock generation udl interrupt controller peripherals memory memory controller
ordering information devices documentation tools part number package brand name pd65977s1-xxx-b6 256-pin pbga system-on-chip lite note: three digits (xxx) are used for the customer suffix number for further information on nec products visit our european website at www.nec.de doc number topic type a15046ee2v0pl00 development board product letter a15047ee1v0pl00 d esign flow product letter to be defined development board user?s manual to be defined system-on-chip lite data sheet to be defined design flow design manual order number vendor description eb-soclite-xi-2000e-6 nec development board (feat. xilinx ? fpga) eb-soclite-ai-1000e-2x nec development board (feat. altera ? fpga) see www.arm.com arm ltd.* arm developer suite (ads) v1.1 and debugging tools see www.lauterbach.de lauterbach* in-circuit debugger/in-circuit emulator see www.agilent.com agilent* debug system * contact vendor directly s ystem - on -c hip l ite gate array with arm7tdmi ? subsystem
nec electronics (europe) gmbh, oberrather str. 4, d-40472 dsseldorf, tel. (02 11) 65 03 01, fax (02 11) 65 03-3 27 nec electronics (germany) gmbh, kanzlerstr. 2, d-40472 dsseldorf, tel. (02 11) 65 03 02, fax (02 11) 65 03-4 90 - podbielskistr. 164, d-30177 hannover, tel. (05 11) 3 34 02-0, fax (05 11) 3 34 02-34 - arabellastr. 17, d-81925 mnchen, tel. (0 89) 92 10 03-0, fax (0 89) 92 10 03-15 - industriestr. 3, d-70565 stuttgart, tel. (07 11) 9 90 10-0, fax (07 11) 9 90 10-19 nec electronics (bnl) - boschdijk 187a, nl-5612 hb eindhoven, tel. (0 40) 2 44 58 45, fax (0 40) 2 44 45 80 nec electronics (scandinavia) - t?by centrum, entrance s (7th floor), s-18322 t?by, tel. (08) 6 38 08 20, fax (08) 6 38 03 88 nec electronics (france) s.a., 9, rue paul dautier, b.p. 187, f-78142 vlizy-villacoublay cdex, tl. (01) 30 67 58 00, fax (01) 30 67 58 99 nec electronics (france) s.a., representacion en espana, juan esplandiu 15, e-28007 madrid, tel. (091) 5 04 27 87, fax (091) 5 04 28 60 nec electronics italiana s.r.l., via fabio filzi, 25a, i-20124 milano, tel. (02) 66 75 41, fax (02) 66 75 42 99 - rome office, via monte cervialto, 131, i-00139 roma, tel. (06) 8 86 22 91/2, fax (06) 8 86 22 39 nec electronics (uk) ltd., cygnus house, sunrise parkway, linford wood, milton keynes, gb-mk14 6np, tel. (0 19 08) 69 11 33, fax (0 19 08) 67 02 90 - scotland office, block 3, carfin industrial estate, motherwell gb-ml1 4ul, tel. (0 16 98) 73 22 21, fax (0 16 98) 83 38 68 ? published by nec electronics (europe) gmbh, printed in germany, may 2001 document no. a15045ee4v0pl00 arm7, arm and thumb are registered trademarks of arm limited. arm7tdmi and amba are trademarks of arm limited. altera is a registered trademark of altera corporation. xilinx is a registered trademark of xilinx, inc. nec offices with compliments nec makes no warranty with respect to this documentation and disclaims any implied warranties of merchantability or fitness for particular purpose. nec does not assume any responsibility for circuits shown or claim that they are free from patent infringement. produc t specifications are subject to change without notice. to ensure that you have the latest product data, please contact your local nec sales office. ? nec electronics (europe) gmbh s ystem - on -c hip l ite gate array with arm7tdmi ? subsystem
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