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1998 data sheet mos integrated circuit document no. u13732ej1v0ds00 (1st edition) date published april 2001 n cp(k) printed in japan pd780065 8-bit single-chip microcontroller description the pd780065 is a product of the pd780065 subseries in the 78k/0 series. it is ideal for controlling cd- text supporting audio equipment. since it incorporates 5 kb of ram, it is also ideal for control operations that require memory. a flash memory version ( pd78f0066) that can be operated using the same power supply voltage range as that of the mask rom version as well as a variety of development tools are also available. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. pd780065 subseries user? manual: u13420e 78k/0 series user? manual instructions: u12326e features internal rom: 40 kb internal high-speed ram: 1024 bytes internal expansion ram: 4096 bytes buffer ram: 32 bytes minimum instruction execution time can be changed from high speed (0.24 s) to ultra-low speed (122 s). i/o ports: 60 8-bit resolution a/d converter: 8 channels serial interface: 4 channels 3-wire serial i/o mode: 1 channel 3-wire serial i/o mode (a maximum 32-byte automatic transmit/receive function is incorporated.): 1 channel 2-wire serial i/o mode: 1 channel uart mode: 1 channel timer: 5 channels 16-bit timer/event counter: 1 channel 8 bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel power supply voltage: v dd = 2.7 to 5.5 v applications cd-text supported car audios the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points.
data sheet u13732ej1v0ds ordering information part number package pd780065gc- -8bt 80-pin plastic qfp (14 14) remark indicates rom code suffix.
data sheet u13732ej1v0ds pd78054 with added iebus tm controller. emi-noise reduced. 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with added uart and d/a converter and enhanced i/o pd780034a pd780988 pd780034ay 64-pin ram capacity of the pd780024a increased pd780024a with enhanced a/d converter on-chip inverter controller and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and increased rom, ram capacity emi-noise reduced version of the pd78064 basic subseries for lcd drive, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42-/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin pd78054 with enhanced serial i/o 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. pd78054 with added timer and enhanced external interface rom-less version of the pd78078 100-pin pd78078y with enhanced serial i/o and limited function 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780824 for automobile meter driver. on-chip d-can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin pd780701y on-chip d-can/iebus controller 80-pin pd780833y on-chip controller compliant with j1850 (class 2) pd780948 on-chip d-can controller 64-pin pd780078 pd780078y pd780034a with added timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd and c/d. display output total: 53 pd78044f with added n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for vfd drive. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip a (fluorescent indicator panel) in some documents, but the functions of the two are same.
pd780065 4 data sheet u13732ej1v0ds the major functional differences between the subseries are listed below. function rom timer 8-bit 10-bit 8-bit v dd external serial interface i/o min. subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control vfd drive pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd drive pd780338 48 k to 60 k 3 ch 2 ch 1 ch 1 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 1.8 v pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus interface pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v supported pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash board pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v control pd780824 32 k to 60 k 2 ch (uart: 1 ch) 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel
data sheet u13732ej1v0ds overview of functions item function internal rom 40 kb memory high-speed ram 1024 bytes expansion ram 4096 bytes buffer ram 32 bytes memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time on-chip minimum instruction execution time variable function when main system 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (at 8.38 mhz operation) clock selected when subsystem 122 s (at 32.768 khz operation) clock selected instruction set 16-bit operation multiplication/division (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, boolean operation) bcd correction, etc. i/o ports cmos i/o: 60 a/d converter 8-bit resolution 8 channels serial interface 3-wire serial i/o mode: 1 channel 3-wire serial i/o mode (max. 32-byte on-chip automatic transmission/ reception function): 1 channel 2-wire serial i/o mode: 1 channel uart mode: 1 channel timer 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 3 (8-bit pwm output capable: 2) clock output 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (main system clock: at 8.38 mhz operation) 32.768 khz (subsystem clock: at 32.768 khz operation) vectored interrupt maskable internal: 14, external: 4 sources non-maskable internal: 1 software 1 power supply voltage v dd = 2.7 to 5.5 v operating ambient temperature t a = e 40 to +85 c package 80-pin plastic qfp (14 14)
data sheet u13732ej1v0ds contents 1. pin configuration (top view) ................................................................................................ 7 2. block diagram ................................................................................................................ ........... 9 3. pin functions ................................................................................................................ .............. 10 3.1 port pins ................................................................................................................... ............................... 10 3.2 non-port pins ............................................................................................................... ........................... 11 3.3 pin i/o circuits and recommended connection of unused pins ...................................................... 13 4. memory space ............................................................................................................... ............... 15 5. features of peripheral hardware .................................................................................... 16 5.1 ports ....................................................................................................................... .................................. 16 5.2 clock generator ............................................................................................................. ......................... 16 5.3 timer/event counter ......................................................................................................... ...................... 17 5.4 clock output controller ..................................................................................................... .................... 21 5.5 a/d converter ............................................................................................................... ........................... 22 5.6 serial interface ............................................................................................................ ............................ 23 6. interrupt functions .......................................................................................................... ..... 28 7. external device expansion function .............................................................................. 31 8. standby function ............................................................................................................. ........ 31 9. reset function ............................................................................................................... ........... 31 10. instruction set ............................................................................................................. ............ 32 11. electrical specifications ................................................................................................... .34 12. package drawing............................................................................................................. ......... 54 13. recommended soldering conditions ............................................................................... 55 appendix a. development tools ............................................................................................... 56 appendix b. related documents .............................................................................................. 59
data sheet u13732ej1v0ds 1. pin configuration (top view) 80-pin plastic qfp (14 when the pd780065 is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ani7 ani6 ani5 ani4 ani3 ani2 ani1 ani0 av ref reset xt1 xt2 ic x1 x2 v dd1 v ss1 p90/sck31 p91/so31 p92/si31 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v dd0 v ss0 p37 p36 p35 p34 p00/intp0 p01/intp1 p02/intp2 p03/intp3 p04 p05 p06 p07 p20/ti00/to0 p21/ti01 p22/ti50/to50 p23/ti51/to51 p24 p25 p26 p27 p30 p31 p32 p33 av ss p84/si1 p83/so1 p82/sck1 p81/busy p80/stb p77 p76 p75/sdio30 p74/sck30 p73/rxd0 p72/txd0 p71/asck0 p70/pcl p64/rd p65/wr p66/wait p67/astb p40/ad0 p41/ad1 80 79 78 77 76 75 74 73 72 71 70 69 68 64 63 62 61 67 66 65 21 22 23 24 25 26 27 28 29 30 31 32 33 37 38 39 40 34 35 36
data sheet u13732ej1v0ds pcl: programmable clock rd: read strobe reset: reset rxd0: receive data sck1, sck30, sck31: serial clock sdio30: serial data input/output si1, si31: serial input so1, so31: serial output stb: strobe ti00, ti01, ti50, ti51: timer input to0, to50, to51: timer output txd0: transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) a8 to a15: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input asck0: asynchronous serial clock astb: address strobe av ref : analog reference voltage av ss : analog ground busy: busy ic: internally connected intp0 to intp3: external interrupt input p00 to p07: port 0 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p64 to p67: port 6 p70 to p77: port 7 p80 to p84: port 8 p90 to p92: port 9
data sheet u13732ej1v0ds 2. block diagram 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer watch timer interrupt control clock output control serial interface 1 serial interface 30 serial interface 31 uart0 a/d converter ti00/to0/p20 ti50/to51/p22 ti51/to51/p23 si1/p84 so1/p83 sck1/p82 busy/p81 stb/p80 si31/p92 so31/p91 sck31/p90 rxd0/p73 txd0/p72 asck0/p71 ani0 to ani7 av ss pcl/p70 av ref intp0/p00 to intp3/p03 sdio30/p75 sck30/p74 ti01/p21 v dd0 ic v ss1 v ss0 v dd1 ram (5 kb) 78k/0 cpu core rom (40 kb) port 0 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 external access system control p00 to p07 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p64 to p67 p70 to p77 p80 to p84 p90 to p92 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1 xt2
pd780065 10 data sheet u13732ej1v0ds 3. pin functions 3.1 port pins pin name i/o function after alternate reset function p00 to p03 i/o port 0 input intp0 to 8-bit i/o port. intp3 p04 to p07 input/output can be specified in 1-bit units. ? use of an on-chip pull-up resistor can be specified by software. p20 i/o port 2 input ti00/to0 p21 8-bit i/o port. ti01 p22 input/output can be specified in 1-bit units. ti50/to50 p23 use of an on-chip pull-up resistor can be specified by software. ti51/to51 p24 to p27 ? p30 to p37 i/o port 3 input ? 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by software. p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by software. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by software. p64 i/o port 6 input rd p65 4-bit i/o port. wr p66 input/output can be specified in 1-bit units. wait p67 use of an on-chip pull-up resistor can be specified by software. astb p70 i/o port 7 input pcl p71 8-bit i/o port. asck0 p72 input/output can be specified in 1-bit units. txd0 p73 use of an on-chip pull-up resistor can be specified by software. rxd0 p74 sck30 p75 sdio30 p76, p77 ? p80 i/o port 8 input stb p81 5-bit i/o port. busy p82 input/output can be specified in 1-bit units. sck1 p83 use of an on-chip pull-up resistor can be specified by software. so1 p84 si1 p90 i/o port 9 input sck31 p91 3-bit i/o port. so31 p92 input/output can be specified in 1-bit units. si31 use of an on-chip pull-up resistor can be specified by software.
pd780065 11 data sheet u13732ej1v0ds 3.2 non-port pins (1/2) pin name i/o function after alternate reset function intp0 to input external interrupt request input by which the valid edge (rising edge, falling input p00 to p03 intp3 edge, or both rising edge and falling edge) can be specified ti00 input external count clock input to 16-bit timer/event counter 0 input p20/to0 capture trigger signal input to capture register (cr01) of 16-bit timer/event counter ti01 capture trigger signal input to capture register (cr00) of 16-bit timer/event p21 counter ti50 external count clock input to 8-bit timer/event counter 50 p22/to50 ti51 external count clock input to 8-bit timer/event counter 51 p23/to51 to0 output 16-bit timer/event counter 0 output input p20/ti00 to50 8-bit timer/event counter 50 output (can be used for 8-bit pwm output) p22/ti50 to51 8-bit timer/event counter 51 output (can be used for 8-bit pwm output) p23/ti51 si1 input serial interface sio1 serial data input input p84 si31 input serial interface sio31 serial data input p92 so1 output serial interface sio1 serial data output input p83 so31 output serial interface sio31 serial data output p91 sdio30 i/o serial interface sio30 serial data input/output input p75 sck1 i/o serial interface sio1 serial clock input/output input p82 sck30 serial interface sio30 serial clock input/output input p74 sck31 serial interface sio31 serial clock input/output input p90 busy input busy input for serial interface sio1 automatic transmission/reception input p81 stb output strobe output for serial interface sio1 automatic transmission/reception input p80 rxd0 input serial data input for asynchronous serial interface input p73 txd0 output serial data output for asynchronous serial interface input p72 asck0 input serial clock input for asynchronous serial interface input p71 pcl output clock output (for trimming of main system clock and subsystem clock) input p70 ad0 to ad7 i/o lower address/data bus for expanding memory externally input p40 to p47 a8 to a15 output higher address bus for expanding memory externally input p50 to p57 rd output strobe signal output for read operation of external memory input p64 wr output strobe signal output for write operation of external memory input p65 wait input inserting wait for accessing external memory input p66 astb output strobe output which externally latches address information output to port 4 input p67 and port 5 to access external memory ani0 to ani7 input a/d converter analog input input
data sheet u13732ej1v0ds 3.2 non-port pins (2/2) pin name i/o function after alternate reset function av ref output a/d converter reference voltage input (can be used for analog power supply) ?? av ss ? a/d converter ground potential. make this pin the same potential as v ss0 or ?? v ss1 . reset input system reset input ?? x1 input connecting crystal resonator for main system clock oscillation ?? x2 ? ?? xt1 input connecting crystal resonator for subsystem clock oscillation ?? xt2 ? ?? v dd0 ? positive power supply for ports ?? v dd1 ? ground potential of ports ?? v ss0 ? positive power supply (except ports) ?? v ss1 ? ground potential (except ports) ?? ic ? internally connected. connect this pin directly to v ss0 or v ss1 . ??
pd780065 13 data sheet u13732ej1v0ds 3.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connections of unused pins are shown in table 3-1. for the i/o circuit configuration of each type, refer to figure 3-1. table 3-1. pin i/o circuit types and recommended connection of unused pins pin name i/o circuit i/o recommended connections of unused pins type p00/intp0 to p03/intp3 8-c i/o input: independently connect to v ss0 via a resistor. p04 to p07 output: leave open. p20/t100/to0 input: independently connect to v dd0 or v ss0 via a p21/t101 resistor. p22/ti50/to50 output: leave open. p23/ti51/to51 p24 to p27 p30 to p37 p40/ad0 to p47/ad7 5-h input: independently connect to v dd0 via a resistor. output: leave open. p50/a8 to p57/a15 input: independently connect to v dd0 or v ss0 via a p64/rd resistor. p65/wr output: leave open. p66/wait p67/astb p70/pcl p71/asck0 8-c p72/txd0 5-h p73/rxd0 8-c p74/sck30 p75/sdio30 5-h p76, p77 8-c p80/stb 5-h p81/busy 8-c p82/sck1 p83/so1 5-h p84/si1 8-c p90/sck31 p91/so31 5-h p92/si31 8-c ani0 to ani7 7-b input independently connect to v dd0 or v ss0 . xt1 16 connect to v dd0 . xt2 leave open. reset 2 input av ref connect to v ss0 or v ss1 . av ss ic directly connect to v ss0 or v ss1 .
data sheet u13732ej1v0ds figure 3-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pull-up enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pull-up enable type 16 type 7-b v ss0 v ss0 p-ch feedback cut-off xt1 xt2 in comparator p-ch n-ch av ss v ref (threshold voltage) + e
data sheet u13732ej1v0ds 4. memory space figure 4-1 shows the memory map of the pd780065. figure 4-1. memory map special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits reserved reserved internal buffer ram 32 8 bits internal expansion ram 4096 8 bits external memory 18432 8 bits internal rom 40960 8 bits ffffh program memory space data memory space callt table area callf entry area ff00h feffh fee0h fedfh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh e800h e7ffh a000h 9fffh 0000h 0040h 003fh 0000h 0080h 007fh 0800h 07ffh 1000h 0fffh 9fffh program area program area vector table area
data sheet u13732ej1v0ds 5. features of peripheral hardware 5.1 ports there are 60 cmos i/o ports. table 5-1. port functions name pin name function port 0 p00 to p07 i/o port. input/output can be specified in 1-bit units. port 2 p20 to p27 use of an on-chip pull-up resistor can be specified by software. port 3 p30 to p37 port 4 p40 to p47 port 5 p50 to p57 port 6 p64 to p67 port 7 p70 to p77 port 8 p80 to p84 port 9 p90 to p92 5.2 clock generator a system clock generator is incorporated. the minimum instruction execution time can be changed. 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (main system clock: at 8.38 mhz operation) 122 s (subsystem clock: at 32.768 khz operation) figure 5-1. block diagram of clock generator xt1 xt2 x1 x2 f xt f x subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller 2 f x 2 2 f x 2 3 f x 2 4 f x f xt 2 prescaler selector stop 2 1
17 data sheet u13732ej1v0ds 5.3 timer/event counter five timer/event counter channels are incorporated. 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel table 5-2. operations of timer/event counter 16-bit timer/ 8-bit timer/ watch timer watchdog timer event counter 0 event counter 50, 51 operation mode interval timer 1 channel 2 channels 1 channel note 1 1 channel note 2 external event counter 1 channel 2 channels ?? function timer output 1 output 2 outputs ?? pwm output ? 2 outputs ?? ppg output 1 output ??? pulse width measurement 2 inputs ??? square wave output 1 output 2 outputs ?? interrupt source 2 2 2 1 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or the interval timer function.
18 data sheet u13732ej1v0ds figure 5-2. block diagram of 16-bit timer/event counter 0 internal bus ti01/p21 f x f x /2 2 f x /2 6 f x /2 3 ti00/to0/p20 16-bit capture/compare register 01 (cr01) match match 16-bit timer counter 0 (tm0) clear noise elimi- nator inttm00 to0/ti00/p20 inttm01 internal bus selector 16-bit capture/compare register 00 (cr00) selector selector selector noise elimi- nator noise elimi- nator output controller
19 data sheet u13732ej1v0ds figure 5-3. block diagram of 8-bit timer/event counter 50 figure 5-4. block diagram of 8-bit timer/event counter 51 internal bus 8-bit compare register 50 (cr50) ti50/to50/p22 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 invert level timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p22 selector 8-bit timer counter 50 (tm50) selector internal bus ti51/to51/p23 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 match mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock select register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 invert level timer mode control register 51 (tmc51) s r q r inv selector inttm51 to51/ti51/p23 selector selector selector 8-bit compare register 51 (cr51) 8-bit timer counter 51 (tm51) s
20 data sheet u13732ej1v0ds figure 5-5. block diagram of watch timer figure 5-6. block diagram of watchdog timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 0 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector selector oscillation stabilization time select register (osts) clock input controller intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 internal bus divider divided clock select circuit output controller division mode select circuit run wdtm4 wdtm3 watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) run f x /2 8 f x
21 data sheet u13732ej1v0ds 5.4 clock output controller a clock output controller (cku) is incorporated. clocks with the following frequencies can be output as a clock output. 65.5 khz/131 khz/262 khz/524 khz/1.05 mhz/2.10 mhz/4.19 mhz/8.38 mhz (main system clock: at 8.38 mhz operation) 32.768 khz (subsystem clock: at 32.768 khz operation) figure 5-7. block diagram of clock output controller cku prescaler f x f xt 8 clock controller pcl/p70 f x to f x /2 7 selector cloe cloe ccs3 ccs2 ccs1 ccs0 internal bus clock output select register (cks)
22 data sheet u13732ej1v0ds 5.5 a/d converter an a/d converter of 8-bit resolution 8 channels is incorporated. figure 5-8. block diagram of a/d converter tap selector intad0 internal bus av ref (can be used for analog power supply) a/d conversion result register 0 (adcr0) controller succesive approximation register (sar) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 selector sample & hold circuit voltage comparator series resistor string av ss
23 data sheet u13732ej1v0ds 5.6 serial interface four serial interface channels are incorporated. serial interface uart0: 1 channel serial interface sio1: 1 channel serial interface sio30: 1 channel serial interface sio31: 1 channel (1) serial interface uart0 serial interface uart0 has two modes, asynchronous serial interface (uart) mode and infrared data transfer mode. asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit. the on-chip dedicated uart baud rate generator enables communication using a wide range of selectable baud rates. in addition, a baud rate can be also defined by dividing the clock input to the asck0 pin. the dedicated uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). infrared data transfer mode this mode enables pulse output and pulse reception in data format. this mode can be used for office equipment applications such as personal computers. figure 5-9. block diagram of serial interface uart0 internal bus receive buffer register 0 rxb0 rxd0/p73 txd0/p72 receive shift register 0 pe0 fe0 ove0 asynchronous serial interface status register 0 (asis0) txs0 intser0 intst0 baud rate generator f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 asynchronous serial interface mode register 0 (asim0) intsr0 receive controller (parity check) transmit shift register transmit controller (parity addition) rx0 p71/asck0
24 data sheet u13732ej1v0ds (2) serial interface sio1 serial interface sio1 has a 3-wire serial i/o mode and a 3-wire serial i/o mode with an auto-transmit/receive function. 3-wire serial i/o mode (msb/lsb-first switching is possible) this mode performs 8-bit data transfer via 3 lines: a serial clock line (sck1), serial output line (so1), and serial input line (si1). this mode can transmit and receive data simultaneously and allows the processing time of data transfer to be reduced. since msb-first or lsb-first is supported for the first bit of the 8-bit data for serial transfer, it is possible to connect the pd780065 to both msb-first devices and lsb-first devices. 3-wire serial i/o mode is effective when connecting to a peripheral i/o that incorporates a clock synchronous serial interface or a display controller, etc. 3-wire serial i/o mode with auto-transmit/receive function this mode has the same functions as the 3-wire serial i/o mode above, but with an added auto transmit/ receive function. a maximum of 32 bytes of data can be transmitted/received in this mode. this function allows hardware- based data transmission/reception to and from devices for osd (on screen display) and devices that incorporate display controllers/drivers independently from the cpu. this mode, therefore, can reduce the burden on software.
25 data sheet u13732ej1v0ds figure 5-10. block diagram of serial interface sio1 selector serial clock counter serial clock controller interrupt request signal generator si1/p84 so1/p83 sck1/p82 f x /2 3 to f x /2 5 intcsi1 stb/p80 busy/p81 automatic data transmit/receive address pointer (adtp) buffer ram serial i/o shift register 1 (sio1) match automatic data transmit/receive interval specification register (adti) 5-bit counter handshake controller internal bus
26 data sheet u13732ej1v0ds (3) serial interface sio30 serial interface sio30 has a 2-wire serial i/o mode. 2-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using two lines: a serial clock line (sck30) and a data i/o line (sdio30). the first bit in 8-bit data in the serial transfer is fixed as msb. the 2-wire serial i/o mode is useful for connection to a peripheral i/o that incorporates a clocked serial interface, a display controller, etc. figure 5-11. block diagram of serial interface sio30 internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 30 (sio30) sdio30/p75 sck30/p74 intcsi30 f x /2 5 f x /2 6 f x /2 7
27 data sheet u13732ej1v0ds (4) serial interface sio31 serial interface sio31 has a 3-wire serial i/o mode. 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck31), serial output line (so31), and serial input line (si31). since simultaneous transmit and receive operations are enabled in the 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in 8-bit data in the serial transfer is fixed as msb. the 3-wire serial i/o mode is useful for connection to a peripheral i/o device that incorporates a clocked serial interface, a display controller, etc. figure 5-12. block diagram of serial interface sio31 internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 31 (sio31) si31/p92 so31/p91 sck31/p90 intcsi31 f x /2 3 f x /2 4 f x /2 5
28 data sheet u13732ej1v0ds 6. interrupt functions the interrupt function consists of 20 interrupt sources and three interrupt types, as shown below. non-maskable: 1 maskable: 18 software: 1 table 6-1. interrupt source list interrupt default interrupt source internal/ vector table type priority note 1 name trigger external address non- ? intwdt watchdog timer overflow (watchdog timer internal 0004h (a) maskable mode 1 selected) maskable 0 intwdt watchdog timer overflow (interval timer mode (b) selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 generation of serial interface uart0 internal 000eh (b) reception error 6 intsr0 end of serial interface uart0 reception 0010h 7 intst0 end of serial interface uart0 transmission 0012h 8 intcsi30 end of serial interface sio30 transfer 0014h 9 intcsi31 end of serial interface sio31 transfer 0016h 10 intcsi1 end of serial interface sio1 transfer 0018h 11 inttm00 match of tm0 and cr00 (when cr00 is 001ah specified as compare register) or ti01 pin valid edge detection (when cr00 is specified as capture register) 12 inttm01 match of tm0 and cr01 (when cr01 is 001ch specified as compare register) or ti00 pin valid edge detection (when cr01 is specified as capture register) 13 inttm50 match of tm50 and cr50 001eh 14 inttm51 match of tm51 and cr51 0020h 15 intwti reference time interval signal from watch timer 0022h 16 intwt watch timer overflow 0024h 17 intad0 end of conversion by a/d converter 0026h software ? brk brk instruction execution ? 003eh (d) notes 1. the default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest and 17 is the lowest. 2. basic configuration types (a) to (d) correspond to (a) to (d) in figure 6-1, respectively. remark two watchdog timer interrupt sources (intwdt): a non-maskable interrupt and a maskable interrupt (internal), are available, either of which can be selected. basic configuration type note 2
29 data sheet u13732ej1v0ds figure 6-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp3) mk internal bus ie pr isp if priority controller vector table address generator standby release signal interrupt request mk ie pr isp if priority controller vector table address generator external interrupt edge enable register (egp, egn) edge detector internal bus standby release signal interrupt request internal bus priority controller vector table address generator standby release signal interrupt request
30 data sheet u13732ej1v0ds figure 6-1. basic configuration of interrupt function (2/2) (d) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag priority controller vector table address generator internal bus interrupt request
31 data sheet u13732ej1v0ds 7. external device expansion function the external device expansion function is for connecting external devices to areas other than the internal rom, ram, and sfrs. ports 4 to 6 are used for external device connection. 8. standby function the following two standby modes are available for further reduction of system current consumption. halt mode: in this mode, the cpu operation clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. stop mode: in this mode, oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. this can be used only when the main system clock is operating (the subsystem clock oscillation cannot be stopped). figure 8-1. standby function note the current consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set bit 7 (mcc) of the processor clock control register (pcc). the stop instruction cannot be used. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 9. reset function the following two reset methods are available. external reset by reset signal input internal reset by watchdog timer program loop time detection main system clock operation stop mode main system clock operation is stopped interrupt request interrupt request halt instruction halt instruction interrupt request stop instruction css = 1 css = 0 subsystem clock operation note halt mode halt mode note clock supply for cpu is stopped, oscillation is maintained clock supply for cpu is stopped, oscillation is maintained
32 data sheet u13732ej1v0ds 10. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
33 data sheet u13732ej1v0ds (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instruction/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz
pd780065 34 data sheet u13732ej1v0ds 11. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v av ref ?.3 to v dd + 0.3 v av ss ?.3 to +0.3 v input voltage v i p00 to p07, p20 to p27, p30 to p37, p40 to p47, ?.3 to v dd + 0.3 v p50 to p57, p64 to p67, p70 to p77, p80 to p84, p90 to p92, x1, x2, xt1, xt2, reset output voltage v o ?.3 to v dd + 0.3 v analog input voltage v an ani0 to ani7 analog input pin av ss ?0.3 to av ref0 + 0.3 v and ?0.3 to v dd + 0.3 output current, i oh per pin ?0 ma high total for p00 to p07, p20 to p27, p30 to p37, p40 to p47, ?5 ma p50 to p57, p64 to p67, p80 to p84, p90 to p92 total for p70 to p77 ?5 ma output current, i ol note per pin for p00 to p07, peak value 20 ma low p20 to p27, p30 to p37, p40 to p47, p64 to p67, rms value 10 ma p70 to p77, p80 to p84, p90 to p92 per pin for p50 to p57 peak value 30 ma rms value 15 ma total for p00 to p07, p20 to p27, peak value 50 ma p30 to p37, p40 to p47, p64 to p67, p80 to p84, rms value 20 ma p90 to p92 total for p70 to p77 peak value 20 ma rms value 10 ma total for p50 to p57 peak value 100 ma rms value 70 ma operating ambient t a ?0 to +85 note the rms value should be calculated as follows: [rms value] = [peak value] caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
pd780065 35 data sheet u13732ej1v0ds capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p07, p20 to p27, 15 pf capacitance unmeasured pins p30 to p37, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p77, p80 to p84, p90 to p92 remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation v dd = 4.5 to 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation v dd = 4.5 to 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.0 5.0 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 2 30 external x1 input v dd = 4.5 to 5.5 v 1.0 8.38 mhz clock frequency (f x ) note 1 5.0 x1 input v dd = 4.5 to 5.5 v 50 500 ns high-/low-level width 85 500 (t xh , t xl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. c2 x1 x2 ic c1 c2 x1 x2 ic c1 x2 x1 pd74hcu04
data sheet u13732ej1v0ds subsystem clock oscillator characteristics (t a = 40 to +85 resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillation 32 32.768 35 khz resonator frequency (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.2 2 s stabilization time note 2 10 external xt1 input 32 38.5 khz clock frequency (f xt ) note 1 xt1 input 5 15 s high-/low-level width (t xth , t xtl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. c3 xt2 xt1 ic r c4 xt1 xt2 pd74hcu04
data sheet u13732ej1v0ds recommended oscillator constant main system clock: ceramic resonator (t a = 40 to +85 manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. csb1000j 1.00 100 100 2.7 5.5 co., ltd. csa2.00mg040 2.00 100 100 2.7 5.5 cst2.00mg040 2.00 on-chip on-chip 2.7 5.5 csa3.58mg 3.58 30 30 2.7 5.5 cst3.58mgw 3.58 on-chip on-chip 2.7 5.5 csa4.19mg 4.19 30 30 2.7 5.5 cst4.19mgw 4.19 on-chip on-chip 2.7 5.5 csa5.00mg 5.00 30 30 2.7 5.5 cst5.00mgw 5.00 on-chip on-chip 2.7 5.5 csa8.00mtz 8.00 30 30 2.7 5.5 cst8.00mtw 8.00 on-chip on-chip 2.7 5.5 csa8.00mtz093 8.00 30 30 2.7 5.5 cst8.00mtw093 8.00 on-chip on-chip 2.7 5.5 csa8.38mtz 8.38 30 30 2.7 5.5 cst8.38mtw 8.38 on-chip on-chip 2.7 5.5 csa8.38mtz093 8.38 30 30 2.7 5.5 cst8.38mtw093 8.38 on-chip on-chip 2.7 5.5 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, contact directly the manufacturer of the resonator used.
data sheet u13732ej1v0ds dc characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit output current, i oh per pin e 1ma high all pins e 15 ma output current, i ol per pin for p00 to p07, p20 to p27, p30 to p37, 10 ma low p40 to p47, p64 to p67, p70 to p77, p80 to p84, p90 to p92 per pin for p50 to p57 15 ma total for p00 to p07, p20 to p27, p30 to p37, 20 ma p40 to p47, p64 to p67, p80 to p84, p90 to p92 total for p50 to p57 70 ma total for p70 to p77 10 ma input voltage, v ih1 p04 to p07, p20 to p27, p30 to p37, p40 to p47, 0.7v dd v dd v high p50 to p57, p64 to p67, p70, p72, p76, p77, p80, p81, p83, p91 v ih2 p00 to p03, p71, p73 to p75, p82, p84, p90, p92, 0.8v dd v dd v reset v ih3 x1, x2 v dd e 0.5 v dd v v ih4 xt1, xt2 v dd = 4.5 to 5.5 v 0.8v dd v dd v 0.9v dd v dd v input voltage, v il1 p04 to p07, p20 to p27, p30 to p37, p40 to p47, 0 0.3v dd v low p50 to p57, p64 to p67, p70, p72, p76, p77, p80, p81, p83, p91 v il2 p00 to p03, p71, p73 to p75, p82, p84, p90, p92, 0 0.2v dd v reset v il3 x1, x2 0 0.4 v v il4 xt1, xt2 v dd = 4.5 to 5.5 v 0 0.2v dd v 0 0.1v dd v output voltage, v oh1 v dd = 4.5 to 5.5 v, i oh = e 1 ma v dd e 1.0 v dd v high i oh = e 100 a v dd e 0.5 v dd v output voltage, v ol1 p50 to p57 v dd = 4.5 to 5.5 v, 0.4 2.0 v low i ol = 15 ma p00 to p07, p20 to p27, v dd = 4.5 to 5.5 v, 0.4 v p30 to p37, p40 to p47, i ol = 1.6 ma p64 to p67, p70 to p77, p80 to p84, p90 to p92 v ol2 i ol = 400 a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u13732ej1v0ds dc characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p07, p20 to p27, 3 a current, high p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p84, p90 to p92, reset i lih2 x1, x2, xt1, xt2 20 a input leakage i lil1 v in = 0 v p00 to p07, p20 to p27, e 3 a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p84, p90 to p92, reset i lil2 x1, x2, xt1, xt2 e 20 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v e 3 a current, low software pull-up r v in = 0 v, 15 30 90 k ? resistance p00 to p07, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p80 to p84, p90 to p92 remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
data sheet u13732ej1v0ds dc characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit power supply i dd1 8.38 mhz v dd = 5.0 v 10% note 2 when a/d converter is 5.5 11 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 6.5 13 ma operating 5.00 mhz v dd = 3.0 v 10% note 2 when a/d converter is 2 4 ma crystal oscillation stopped operating mode when a/d converter is 3 6 ma operating i dd2 8.38 mhz v dd = 5.0 v 10% note 2 when peripheral 1.1 2.2 ma crystal oscillation functions are stopped halt mode when peripheral 4.7 ma functions are operating 5.00 mhz v dd = 3.0 v 10% note 2 when peripheral 0.35 0.7 ma crystal oscillation functions are stopped halt mode when peripheral 1.7 ma functions are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 3 v dd = 3.0 v 10% 20 40 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 3 v dd = 3.0 v 10% 6 18 a i dd5 xt1 = v dd stop mode v dd = 5.0 v 10% 0.1 30 a when feedback resistor is not used v dd = 3.0 v 10% 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ), including the peripheral operation current (except the current through pull-up resistors of ports and the av ref pin). 2. when the processor clock control register (pcc) is set to 00h. 3. when main system clock operation is stopped.
pd780065 41 data sheet u13732ej1v0ds ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with 4.5 v note 1 122 125 note 2 2.7 v note 2 ti50, ti51 input f ti5 0 4 mhz frequency ti50, ti51 input t tih5 , t til5 100 ns high-/low-level width interrupt request t inth , t intl intp0 to intp3 1 notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register 0 (prm0). however, if the ti00 valid edge is selected as the count clock, the value becomes f sam = f x /8.
data sheet u13732ej1v0ds t cy vs. v dd (main system clock operation) 16.0 5.0 1.0 2.0 0.4 0.24 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 operation guaranteed range 4.5
pd780065 43 data sheet u13732ej1v0ds (2) read/write operation (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) (1/2) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n) t cy ?54 ns t add2 (3 + 2n) t cy ?60 ns address output time from rd remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
data sheet u13732ej1v0ds (2) read/write operation (t a = 40 to +85 (2/2) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n) t cy e 108 ns t add2 (3 + 2n) t cy e 120 ns output time from rd to address t rdad 0 200 ns input time from rd to data t rdd1 (2 + 2n) t cy e 148 ns t rdd2 (3 + 2n) t cy e 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n) t cy e 40 ns t rdl2 (2.5 + 2n) t cy e 40 ns input time from rd to wait t rdwt1 t cy e 75 ns t rdwt2 t cy e 60 ns input time from wr to wait t wrwt t cy e 50 ns wait low-level width t wtl (0.5 + 2n) t cy + 10 (2 + 2n) t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n) t cy e 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy e 30 ns delay time from t rdast 0.8t cy e 30 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy e 30 1.2t cy + 60 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy e 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.)
pd780065 45 data sheet u13732ej1v0ds (3) serial interface (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) (a) sio3n 3-wire serial i/o mode (sck3n... internal clock output) parameter symbol conditions min. typ. max. unit sck3n cycle time t kcy1 v dd = 4.5 to 5.5 v 954 ns 1600 ns sck3n high-/ t kh1 , t kl1 v dd = 4.5 to 5.5 v t kcy1 /2 ?50 ns low-level width t kcy1 /2 ?100 ns si3n setup time t sik1 v dd = 4.5 to 5.5 v 100 ns (to sck3n note 300 ns sck3n note c is the load to so3n output capacitance of the sck3n and so3n output lines. (b) sio3n 3-wire serial i/o mode (sck3n... external clock input) parameter symbol conditions min. typ. max. unit sck3n cycle time t kcy2 v dd = 4.5 to 5.5 v 800 ns 1600 ns sck3n high-/ t kh2 , t kl2 v dd = 4.5 to 5.5 v 400 ns low-level width 800 ns si3n setup time t sik2 100 ns (to sck3n note 300 ns sck3n note c is the load capacitance of the so3n output line. remark n = 0, 1
pd780065 46 data sheet u13732ej1v0ds (3) serial interface (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) (c) sio1 3-wire serial i/o mode (sck1... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy3 800 ns sck1 high-/ t kh3 , t kl3 t kcy1 /2 ?50 ns low-level width si1 setup time t sik3 100 ns (to sck1 ) si1 hold time t ksi3 400 ns (from sck1 ) delay time from t kso3 c = 100 pf note 300 ns sck1 to so1 output note c is the load capacitance of the sck1 and so1 output lines. (d) sio1 3-wire serial i/o mode (sck1... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy4 800 ns sck1 high-/ t kh4 , t kl4 400 ns low-level width si1 setup time t sik4 100 ns (to sck1 ) si1 hold time t ksi4 400 ns (from sck1 ) delay time from t kso4 c = 100 pf note 300 ns sck1 to so1 output sck1 rise/fall time t r , t f 1 s note c is the load capacitance of the so1 output line.
pd780065 47 data sheet u13732ej1v0ds (e) uart mode (dedicated baud-rate generator output) parameter symbol conditions min. typ. max. unit transfer rate v dd = 4.5 to 5.5 v 131031 bps 78125 bps (f) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy5 v dd = 4.5 to 5.5 v 800 ns 1600 ns asck0 high-/low-level width t kh5 ,v dd = 4.5 to 5.5 v 400 ns t kl5 800 ns transfer rate v dd = 4.5 to 5.5 v 39063 bps 19531 bps (g) uart mode (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate v dd = 4.5 to 5.5 v 131031 bps bit rate allowable error v dd = 4.5 to 5.5 v 0.87 % output pulse width v dd = 4.5 to 5.5 v 1.2 0.24/fbr note s input pulse width v dd = 4.5 to 5.5 v 4/f x s note fbr: specified baud rate
data sheet u13732ej1v0ds ac timing measurement points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih3 (min.) v il3 (max.) t xtl t xth 1/f xt v ih4 (min.) v il4 (max.) x1 input xt1 input t til0 t tih0 ti00, ti01 1/f t5 t tih5 t til5 ti50, ti51 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd intp0 to intp3 t intl t inth interrupt request input timing
data sheet u13732ej1v0ds read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd t rsl reset reset input timing
data sheet u13732ej1v0ds external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z
pd780065 51 data sheet u13732ej1v0ds serial transfer timing sio3n 3-wire serial i/o mode: remark n = 0, 1 sio1 3-wire serial i/o mode: t kcy1, 2 t kl1, 2 t kh1, 2 sck3n si3n so3n t sik 1, 2 t ksi 1, 2 t kso 1, 2 input data output data t kcy3, 4 t kl3, 4 t kh3, 4 t f sck1 si1 so1 t sik 3, 4 t ksi 3, 4 t kso 3, 4 input data output data t r
pd780065 52 data sheet u13732ej1v0ds uart mode (external clock input): a/d converter characteristics (t a = ?0 to +85 c, v dd = av dd = av ref = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error note 0.6 %fsr conversion time t conv 19 96 s analog input voltage v ian 0av ref v resistance between av ref r ref when a/d converter not operating 20 40 k ? and av ss note excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value. analog input pin input impedance [equivalent circuit] [parameter value] [typ.] av dd [v] r1 [k ? ] r2 [k ? ] c1 [pf] c2 [pf] c3 [pf] 2.7 12 8.0 3.0 3.0 2.0 4.5 4 2.7 3.0 1.4 2.0 t kcy5 t kh5 t kl5 asck0 c3 c2 c1 r1 r2
pd780065 53 data sheet u13732ej1v0ds t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr subsystem clock stop (xt1 = v dd ) 0.1 30 a supply current and feedback resistor disconnected release signal set time t srel 0 s oscillation stabilization time t wait release by reset 2 17 /f x s release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
data sheet u13732ej1v0ds 12. package drawing remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
pd780065 55 data sheet u13732ej1v0ds 13. recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 13-1. surface mounting type soldering conditions pd780065gc- -8bt: 80-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 caution do not use different soldering methods together (except for partial heating).
pd780065 56 data sheet u13732ej1v0ds appendix a. development tools the following development tools are available for developing systems using the pd780065 subseries. refer to (5) cautions on using development tools. (1) language processing software ra78k0 assembler package common to the 78k/0 series cc78k0 c compiler package common to the 78k/0 series df780066 device file for the pd780065 subseries cc78k0-l c compiler library source file common to the 78k/0 series (2) flash memory writing tools flashpro iii dedicated flash programmer for microcontrollers incorporating flash memory (part number: fl-pr3, pg-fp3) fa-80gc adapter for flash memory writing (3) debugging tools when using ie-78k0-ns in-circuit emulator ie-78k0-ns in-circuit emulator common to the 78k/0 series ie-70000-mc-ps-b power supply unit for the ie-78k0-ns ie-78k0-ns-pa performance board to enhance/extend the functions of the ie-78k0-ns ie-70000-98-if-c adapter necessary when a pc-9800 series computer (except notebook-type pc) is used as the host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable necessary when a pc-9800 series notebook-type pc is used as the host machine (pcmcia socket supported) ie-70000-pc-if-c adapter necessary when an ibm pc/at tm compatible is used as the host machine (isa bus supported) ie-70000-pci-if-a adapter necessary when a pc incorporating a pci bus is used as the host machine ie-780066-ns-em4 note emulation board to emulate the pd780065 subseries ie-78k0-ns-p01 i/o board necessary when emulating the pd780065 subseries np-80gc emulation probe for an 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 conversion socket to connect the board of the target system for an 80-pin plastic qfp (gc-8bt type) and np-80gc id78k0-ns integrated debugger for the ie-78k0-ns sm78k0 system simulator common to the 78k/0 series df780066 device file for the pd780065 subseries note under development
data sheet u13732ej1v0ds when using ie-78001-r-a in-circuit emulator ie-78001-r-a in-circuit emulator common to the 78k/0 series ie-70000-98-if-c adapter necessary when a pc-9800 series computer (except notebook-type pc) is used as the host machine (c bus supported) ie-70000-pc-if-c adapter necessary when an ibm pc/at compatible is used as the host machine (isa bus supported) ie-70000-pci-if-a adapter necessary when a pc incorporating a pci bus is used as the host machine ie-78000-r-sv3 interface adapter and cable necessary when an ews is used as the host machine ie-780066-ns-em4 note emulation board to emulate the pd780065 subseries ie-78k0-ns-p01 i/o board necessary when emulating the pd780065 subseries ie-78k0-r-ex1 emulation probe conversion board necessary when the ie-780066-ns-em4 + ie-78k0-ns-p01 is used in the ie-78001-r-a ep-78230gc-r emulation probe for an 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 conversion socket to connect the board of the target system for an 80-pin plastic qfp (gc-8bt type) and ep-78230gc-r id78k0 integrated debugger for the ie-78001-r-a sm78k0 system simulator common to the 78k/0 series df780066 device file for the pd780065 subseries note under development (4) real-time os rx78k0 real-time os for the 78k/0 series mx78k0 os for the 78k/0 series
data sheet u13732ej1v0ds (5) cautions on using development tools the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780066. the cc78k0 and rx78k0 are used in combination with the ra78k0 and df780066. fl-pr3, fa-80gc, and np-80gc are products of naito densei machida mfg. co., ltd. (tel: +81-44-822- 3813). refer to the single-chip microcontroller development tool selection guide (u11069e) for information on third party development tools. host machines and oss compatible with the software are as follows: host machine [os] pc ews pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatibles sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k0 cc78k0 id78k0-ns id78k0 ? sm78k0 rx78k0 mx78k0 dos based software
pd780065 59 data sheet u13732ej1v0ds appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780065 subseries user? manual under preparation pd780065 data sheet this document pd78f0066 data sheet under preparation 78k/0 series user? manual instruction u12326e documents related to development tools (user? manuals) document name document no. ra78k0 assembler package operation u11802e language u11801e structured assembly language u11789e cc78k/0 c compiler operation u11517e language u11518e ie-78k0-ns in-circuit emulator u13731e ie-78001-r-a in-circuit emulator to be prepared ie-780066-ns-em4 emulation board to be prepared ep-78230 emulation probe eeu-1515 sm78k0s, sm78k0 system simulator ver. 2.10 or operation u14611e later windows based sm78k series system simulator ver. 2.10 or later external part user open interface specifications to be prepared id78k0-ns integrated debugger ver. 2.00 or later operation u14379e windows based id78k0-ns, id78k0s-ns integrated operation u14910e ver. 2.20 or later windows based id78k0 integrated debugger ews based reference id78k0 integrated debugger windows based reference u11539e guide u11649e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
pd780065 60 data sheet u13732ej1v0ds documents related to embedded software (user? manuals) document name document no. 78k/0 series real-time os basics u11537e installation u11536e os for 78k/0 series mx78k0 basics u12257e other related documents document name document no. semiconductor selection guide - products & packages - (cd-rom) x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u13732ej1v0ds [memo]
data sheet u13732ej1v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip and iebus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos and solaris are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
data sheet u13732ej1v0ds regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of january, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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