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1999 preliminary product information data sheet description the pd780076 and 780078 are products in the pd780078 subseries within the 78k/0 series. they are based on the existing pd780034a subseries, with an enhanced timer and serial interface and greater rom and ram capacities. the pd780076y and 780078y are products based on the pd780078 subseries, with an i 2 c bus interface supporting multimaster. a flash memory version, the pd78f0078 and 78f0078y, and various development tools are available. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. pd780076, 780078, 780076y, 780078y subseries user? manual: u14260e 78k/0 series user? manual ?instructions: u12326e features internal large capacity rom and ram item program memory data memory package internal rom internal high- internal expansion part number speed ram ram pd780076, 780076y 48 kb 1024 bytes 1024 bytes ? 64-pin plastic qfp (14 14) pd780078, 780078y 60 kb ? 64-pin plastic tqfp (12 12) minimum instruction execution time: 0.24 s (at f x = 8.38 mhz operation) i/o ports: 52 (n-ch open-drain 5 v withstand voltage: 4) 10-bit resolution a/d converter: 8 channels serial interface: 3 channels ( pd780078 subseries) 4 channels ( pd780078y subseries) timer: 6 channels power supply voltage: v dd = 1.8 to 5.5 v applications personal computers, air conditioners, dash boards, air bags, car audios, etc. 8-bit single-chip microcontrollers document no. u14259ej1v0ds00 (1st edition) date published april 2001 n cp(k) printed in japan mos integrated circuit pd780076, 780078, 780076y, 780078y the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 2 ordering information part number package pd780076gc- -ab8 64-pin plastic qfp (14 14) pd780076gk- -9et 64-pin plastic tqfp (12 12) pd780078gc- -ab8 64-pin plastic qfp (14 14) pd780078gk- -9et 64-pin plastic tqfp (12 12) pd780076ygc- -ab8 64-pin plastic qfp (14 14) pd780076ygk- -9et 64-pin plastic tqfp (12 12) pd780078ygc- -ab8 64-pin plastic qfp (14 14) pd780078ygk- -9et 64-pin plastic tqfp (12 12) remark indicates rom code suffix.
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 3 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with enhanced uart and d/a converter and enhanced i/o pd780034a pd780988 pd780034ay 64-pin ram capacity of the pd780024a increased. pd780024a with enhanced a/d converter on-chip inverter controller and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and increased rom, ram capacity emi-noise reduced version of the pd78064 basic subseries for lcd drive, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42-/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin pd78054 with enhanced serial i/o 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. pd78054 with added timer and enhanced external interface rom-less version of the pd78078 100-pin pd78078y with enhanced serial i/o and limited function 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b pd78054 with added iebus tm controller. 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip d-can controller 100-pin pd780958 pd780816 pd780703y pd780833y pd780702y for industrial meter control on-chip automobile meter controller/driver meter control 80-pin 80-pin on-chip iebus controller 80-pin 64-pin on-chip d-can controller on-chip controller compliant with j1850 (class 2) specialized for d-can controller function pd780948 on-chip d-can controller 64-pin pd780078 pd780078y pd780034a with added timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd and c/d. display output total: 53 pd78044f with added n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for vfd drive. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 4 the major functional differences among the subseries are shown below. non y subseries function timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780338 48 k to 60 k 3 ch 2 ch 1 ch 1 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 1.8 v drive pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v interface supported pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v pd780816 32 k to 64 k 2 ch 12 ch 2 ch (uart: 1 ch) 46 4.0 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v board control pd780828b 32 k to 60 k 2 ch (uart: 1 ch) 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value rom capacity (bytes)
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 5 y subseries function timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78078y 48 k to 60 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch, 88 1.8 v pd78070ay i 2 c: 1 ch) 61 2.7 v pd780018ay 48 k to 60 k 3 ch (i 2 c: 1 ch) 88 pd780058y 24 k to 60 k 2 ch 2 ch 3 ch (time division 68 1.8 v uart: 1 ch, i 2 c: 1 ch) pd78058fy 48 k to 60 k 3 ch (uart: 1 ch, 69 2.7 v pd78054y 16 k to 60 k i 2 c: 1 ch) 2.0 v pd780078y 48 k to 60 k 2 ch 8 ch 4 ch (uart: 2 ch, 52 1.8 v i 2 c: 1 ch) pd780034ay 8 k to 32 k 1 ch 3 ch (uart: 1 ch, 51 pd780024ay 8 ch i 2 c: 1 ch) pd78018fy 8 k to 60 k 2 ch (i 2 c: 1 ch) 53 lcd pd780308y 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 3 ch (time division 57 2.0 v drive uart: 1 ch, i 2 c: 1 ch) pd78064y 16 k to 32 k 2 ch (uart: 1 ch, i 2 c: 1 ch) for bus pd780702y 60 k 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (uart: 1 ch, 67 3.5 v interface pd780703y i 2 c: 1 ch) pd780833y 65 4.5 v remark the functions of non y subseries and y subseries products are the same, except for the serial interface. v dd min. value rom capacity (bytes)
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 6 function overview part number pd780076 pd780078 item pd780076y pd780078y internal rom 48 kb 60 kb memory high-speed ram 1024 bytes expansion ram 1024 bytes memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time on-chip variable function of minimum instruction execution time when main system 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (at 8.38 mhz operation) clock selected when subsystem 122 s (at 32.768 khz operation) clock selected instruction set ?16-bit operation ?multiply/divide (8 bits 8 bits,16 bits 8 bits) ?bit manipulate (set, reset, test, boolean operation) ?bcd adjust, etc. i/o ports total: 52 ?cmos input: 8 ?cmos i/o: 40 ?n-ch open-drain i/o: 4 a/d converter ?10-bit resolution 8 channels ?low-voltage operation available: av dd = 2.2 to 5.5 v serial interface ?3-wire serial i/o mode: 1 channel ?uart mode: 1 channel ?3-wire serial i/o/uart mode selectable note : 1 channel ?i 2 c bus mode ( pd780078y subseries only): 1 channel timer ?16-bit timer/event counter: 2 channels ?8-bit timer/event counter: 2 channels ?watch timer: 1 channel ?watchdog timer: 1 channel timer output 4 (8-bit pwm output capable: 2) clock output ?65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (at 8.38 mhz operation with main system clock) ?32.768 khz (at 32.768 khz operation with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (at 8.38 mhz operation with main system clock) vectored maskable internal: 18 ( pd780078 subseries) interrupt 19 ( pd780078y subseries) source external: 5 non-maskable internal: 1 software 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ?0 to +85 c package ?64-pin plastic qfp (14 14) ?64-pin plastic tqfp (12 12) note pins are multiplexed. select either of these interfaces.
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 7 contents 1. pin configuration (top view) ................................................................................................... 8 2. block diagram .............................................................................................................................10 3. pin functions ................................................................................................................ ................ 11 3.1 port pins ............................................................................................................................... ..................... 11 3.2 non-port pins ............................................................................................................................... ............. 12 3.3 pin i/o circuits and recommended connection of unused pins ..................................................... 14 4. memory space ............................................................................................................... .................16 5. peripheral hardware function features .......................................................................17 5.1 ports ............................................................................................................................... ............................ 17 5.2 clock generator ............................................................................................................................... ......... 18 5.3 timer/event counter ............................................................................................................................... .18 5.4 clock output/buzzer output controller ................................................................................................ 22 5.5 a/d converter ............................................................................................................................... ............ 23 5.6 serial interface ............................................................................................................................... ........... 24 6. interrupt functions .......................................................................................................... .......29 7. external device expansion functions .............................................................................33 8. standby function .......................................................................................................................33 9. reset function ............................................................................................................................34 10. mask option ............................................................................................................................... ....34 11. instruction set ............................................................................................................. ..............35 12. electrical specifications ......................................................................................................37 13. package drawings .....................................................................................................................61 14. recommended soldering conditions ................................................................................63 appendix a. development tools ................................................................................................65 appendix b. related documents ...............................................................................................68
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 8 1. pin configuration (top view) 64-pin plastic qfp (14 14) pd780076gc- - ab8, 780078gc- -ab8, 780076ygc- -ab8, 780078ygc- -ab8 64-pin plastic tqfp (12 12) pd780076gk- -9et, 780078gk- -9et, 780076ygk- -9et, 780078ygk- -9et note sda0 and scl0 are only provided on the pd780078y subseries. cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz/ti001/to01 p74/pcl/ti011 p73/ti51/to51 p72/ti50/to50 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 p36/sck3/asck2 p20/si1 p21/so1 p22/sck1 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p71/ti010 p70/ti000/to00 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic xt1 xt2 reset p80/ss1 av ref p10/ani0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 note p33/scl0 note p34/si3/txd2 p35/so3/rxd2 32
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 9 pcl: programmable clock rd: read strobe reset: reset rxd0, rxd2: receive data sck1, sck3, scl0: serial clock sda0: serial data si1, si3: serial input so1, so3: serial output ss1: serial interface chip select input ti000, ti010, ti001, ti011, ti50, ti51: timer input to00, to01, to50, to51: timer output txd0, txd2: transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) a8 to a15: address bus ad0 to ad7: address/data bus adtrg: ad trigger input ani0 to ani7: analog input asck0, asck2: asynchronous serial clock astb: address strobe av ref : analog reference voltage av ss : analog ground buz: buzzer output ic: internally connected intp0 to intp3: external interrupt input p00 to p03: port 0 p10 to p17: port 1 p20 to p25: port 2 p30 to p36: port 3 p40 to p47: port 4 p50 to p57: port 5 p64 to p67: port 6 p70 to p75: port 7 p80: port 8
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 10 2. block diagram note i 2 c bus is only provided on the pd780078y subseries. remark the internal rom capacity depends on the product. 16-bit timer/event counter 00 16-bit timer/event counter 01 8-bit timer/event counter 50 8-bit timer/event counter 51 ti000/to00/p70 ti010/p71 si1/p20 so1/p21 sck1/p22 si3/txd2/p34 so3/rxd2/p35 sck3/asck2/p36 rxd0/p23 txd0/p24 asck0/p25 ani0/p10 to ani7/p17 i 2 c bus note serial interface uart0 interrupt control scl0/p33 sda0/p32 ti001/to01/buz/p75 ti011/pcl/p74 ti50/to50/p72 ti51/to51/p73 watch timer watchdog timer 8 a/d converter 78k/0 cpu core internal high-speed ram 1024 bytes internal expansion ram 1024 bytes rom port 0 p00 to p03 4 port 1 p10 to p17 port 2 p20 to p25 6 port 3 p30 to p36 7 port 4 p40 to p47 8 port 5 p50 to p57 8 port 6 p64 to p67 4 port 7 p70 to p75 6 port 8 external access p80 wr/p65 a8/p50 to a15/p57 rd/p64 wait/p66 system control reset x1 8 ad0/p40 to ad7/p47 x2 x1 x2 8 rxd2/so3/p35 txd2/si3/p34 asck2/sck3/p36 serial interface uart2 serial interface sio3 serial interface csi1 ss1/p80 v dd1 v ss0 ic v dd0 v ss1 wr/p65 astb/p67 8 clock/buzzer output control pcl/ti011/p74 buz/ti001/to01/p75 adtrg/intp3/p03 av ref av ss intp0/p00 to intp3/p03 4
data sheet u14259ej1v0ds 11 3. pin functions 3.1 port pins (1/2) pin name i/o function after alternate reset function p00 i/o input intp0 p01 intp1 p02 intp2 p03 intp3/adtrg p10 to p17 input input ani0 to ani7 p20 i/o input si1 p21 so1 p22 sck1 p23 rxd0 p24 txd0 p25 asck0 p30, p31 i/o input p32 sda0 note 2 p33 scl0 note 2 p34 si3/txd2 p35 so3/rxd2 p36 sck3/asck2 p40 to p47 i/o input ad0 to ad7 p50 to p57 i/o input a8 to a15 p64 i/o input rd p65 wr p66 wait p67 astb notes 1. with the pd780078y subseries, on-chip pull-up resistors can be specified using a mask option for p30 and p31. 2. these pins are only provided on the pd780078y subseries. port 0 4-bit input/output port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 1 8-bit input only port. port 2 6-bit input/output port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 3 n-ch open-drain input/output port. 7-bit input/output port. on-chip pull-up resistors can be specified input/output can be specified by the mask option note 1 . in 1-bit units. leds can be driven directly. an on-chip pull-up resistor can be specified by a software setting. port 4 8-bit input/output port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. interrupt request flag (krif) is set to 1 by falling edge detection. port 5 8-bit input/output port. leds can be driven directly. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 6 4-bit input/output port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting.
data sheet u14259ej1v0ds 12 3.1 port pins (2/2) pin name i/o function after alternate reset function p70 i/o input ti000/to00 p71 ti010 p72 ti50/to50 p73 ti51/to51 p74 ti011/pcl p75 ti001/to01/ buz p80 i/o input ss1 3.2 non-port pins (1/2) pin name i/o function after alternate reset function intp0 to intp2 input external interrupt request input for which the valid edge (rising edge, input p00 to p02 intp3 falling edge, or both rising edge and falling edge) can be specified. p03/adtrg si1 input serial interface serial data input. input p20 si3 p34/txd2 so1 output serial interface serial data output. input p21 so3 p35/rxd2 sda0 note i/o serial interface serial data input/output. input p32 sck1 i/o serial interface serial clock input/output. input p22 sck3 p36/asck2 scl0 note p33 ss1 input serial interface chip select input. input p80 rxd0 input serial data input for asynchronous serial interface. input p23 rxd2 p35/so3 txd0 output serial data output for asynchronous serial interface. input p24 txd2 p34/si3 asck0 input serial clock input for asynchronous serial interface. input p25 asck2 p36/sck3 ti000 input external count clock input to 16-bit timer/event counter 00. input p70/to00 capture trigger input to capture register 000, 010 of 16-bit timer/event counter 00. ti010 capture trigger input to capture register 000 of 16-bit timer/event counter 00. p71 ti001 external count clock input to 16-bit timer/event counter 01. p75/to01/ capture trigger input to capture register 001, 011 of 16-bit timer/event counter 01. buz ti011 capture trigger input to capture register 001 of 16-bit timer/event counter 01. p74/pcl ti50 external count clock input to 8-bit timer/event counter 50. p72/to50 ti51 external count clock input to 8-bit timer/event counter 51. p73/to51 note these pins are only provided on the pd780078y subseries. port 7 6-bit input/output port. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 8 1-bit input/output port. input/output can be specified in 1-bit units. on-chip pull-up resistor can be specified by a software setting.
data sheet u14259ej1v0ds 13 3.2 non-port pins (2/2) pin name i/o function after alternate reset function to00 output 16-bit timer/event counter 00. input p70/ti000 to01 16-bit timer/event counter 01. p75/ti001/ buz to50 8-bit timer/event counter 50. p72/ti50 to51 8-bit timer/event counter 51. p73/ti51 pcl output clock output (for trimming of main system clock and subsystem clock). input p74/ti011 buz output buzzer output. input p75/ti001/ to01 ad0 to ad7 i/o lower address/data bus for extending memory externally. input p40 to p47 a8 to a15 output higher address bus for extending memory externally. input p50 to p57 rd output strobe signal output for read operation of external memory. input p64 wr strobe signal output for write operation of external memory. p65 wait input inserting wait for accessing external memory. input p66 astb output strobe output which externally latches address information output to input p67 port 4 and port 5 to access external memory. ani0 to ani7 input a/d converter analog input. input p10 to p17 adtrg input a/d converter trigger signal input. input p03/intp3 av ref input a/d converter reference voltage and analog power supply. av ss a/d converter ground potential. set the same potential as that of v ss0 or v ss1 . x1 input connecting crystal resonator for main system clock oscillation. x2 xt1 input connecting crystal resonator for subsystem clock oscillation. xt2 reset input system reset input. input v dd0 positive power supply for ports. v dd1 positive power supply (except ports). v ss0 ground potential of ports. v ss1 ground potential (except ports). ic internally connected. connect directly to v ss0 or v ss1 .
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 14 3.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the i/o circuit configuration of each type, see figure 3-1. table 3-1. types of pin i/o circuits pin name i/o i/o recommended connection of unused pins circuit type p00/intp0 to p02/intp2 8-c i/o input: independently connect to v ss0 via a resistor. p03/intp3/adtrg output: leave open. p10/ani0 to p17/ani7 25 input connect to v dd0 or v ss0 . p20/si1 8-c i/o input: independently connect to v dd0 or v ss0 via a resistor. p21/so1 5-h output: leave open. p22/sck1 8-c p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q input: independently connect to v dd0 via a resistor. p32, p33 output: leave open. ( pd780078 subseries only) p32/sda0 13-r ( pd780078y subseries only) p33/scl0 ( pd780078y subseries only) p34/si3/txd2 8-c input: independently connect to v dd0 or v ss0 via a resistor. p35/so3/rxd2 output: leave open. p36/sck3/asck2 p40/ad0 to p47/ad7 5-h input: independently connect to v dd0 via a resistor. output: leave open. p50/a8 to p57/a15 input: independently connect to v dd0 or v ss0 via a resistor. p64/rd output: leave open. p65/wr p66/wait p67/astb p70/ti000/to00 8-c p71/ti010 p72/ti50/to50 p73/ti51/to51 p74/ti011/pcl p75/ti001/to01/buz p80/ss1 input: independently connect to v ss0 via a resistor. output: leave open. reset 2 input xt1 16 connect to v dd0 . xt2 leave open. av ref connect to v ss0 . av ss ic connect directly to v ss0 or v ss1 .
data sheet u14259ej1v0ds 15 figure 3-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pull-up enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pull-up enable type 13-q data output disable in/out n-ch v dd0 mask option ? ? ? ? ? ? type 13-r input enable v ss0 type 25 v ss0 v ss0 data output disable in/out n-ch v ss0 p-ch feedback cut-off xt1 xt2 type 16 input enable comparator + p-ch n-ch v ref (threshold voltage) v ss0 in
data sheet u14259ej1v0ds 16 4. memory space figure 4-1 shows the memory map of the pd780076, 780078, 780076y, and 780078y. figure 4-1. memory map note the internal rom capacity depends on the products (see the following table). part number internal rom last address internal rom capacity nnnnh pd780076, 780076y bfffh 49152 8 bits pd780078, 780078y efffh 61440 8 bits ffffh ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh nnnnh f400h f3ffh 0000h nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h nnnnh+1 special function registers (sfr) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram 1024 8 bits reserved data memory space external memory internal expansion ram 1024 8 bits internal rom note program memory space program area callf entry area program area callt table area vector table area
data sheet u14259ej1v0ds 17 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. cmos input (port 1): 8 cmos input/output (port 0, 2, p34 to p36, port 4 to 8): 40 n-channel open-drain input/output (p30 to p33): 4 total: 52 table 5-1. port functions name pin name function port 0 p00 to p03 input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 1 p10 to p17 input-only port pins. port 2 p20 to p25 input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 3 p30 to p33 n-ch open-drain input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a mask option note . leds can be driven directly. p34 to p36 input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 4 p40 to p47 input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. test input flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. leds can be driven directly. port 6 p64 to p67 input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 7 p70 to p75 input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. port 8 p80 input/output port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be specified by a software setting. note with the pd780078y subseries, on-chip pull-up resistors can be specified using a mask option for p30 and p31.
data sheet u14259ej1v0ds 18 5.2 clock generator a system clock generator is incorporated. the minimum instruction execution time can be changed. 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (at 8.38 mhz operation with main system clock) 122 s (at 32.768 khz operation with subsystem clock) figure 5-1. block diagram of clock generator xt1 xt2 x1 x2 f xt f x subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller 2 f x 2 2 f x 2 3 f x 2 4 f x f xt 2 prescaler selector stop 2 1 5.3 timer/event counter six timer/event counter channels are incorporated. 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel table 5-2. operations of timer/event counter 16-bit timer/event 8-bit timer/event watch timer watchdog timer counter 00, 01 counter 50, 51 operation interval timer 2 channels 2 channels 1 channel note 1 1 channel note 2 mode external event counter 2 channels 2 channels function timer output 2 outputs 2 outputs pwm output 2 outputs ppg output 2 outputs pulse width measurement 4 inputs square wave output 2 outputs 2 outputs interrupt source 4 2 2 1 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or the interval timer function.
data sheet u14259ej1v0ds 19 figure 5-2. block diagram of 16-bit timer/event counter 00 figure 5-3. block diagram of 16-bit timer/event counter 01 remark 16-bit timer/event counter 01 shares pins with the clock output (pcl) and buzzer output (buz) functions, in addition to the port function. internal bus ti010/p71 f x f x /2 2 f x /2 6 f x /2 3 ti000/to00/p70 16-bit timer capture/ compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator inttm000 to00/ti000/p70 inttm010 internal bus selector 16-bit timer capture/ compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ti011/pcl/p74 ti001/to01/ buz/p75 to01/ti001/ buz/p75 inttm011 f x /2 f x /2 3 f x /2 9 f x /2 3 inttm001 internal bus 16-bit timer capture/ compare register 001 (cr001) selector selector noise elimi- nator clear 16-bit timer counter 01 (tm01) match match 16-bit timer capture/ compare register 011 (cr011) internal bus selector noise elimi- nator noise elimi- nator selector output controller
data sheet u14259ej1v0ds 20 figure 5-4. block diagram of 8-bit timer/event counter 50 figure 5-5. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p72 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 level inversion 8-bit timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p72 selector 8-bit timer counter 50 (tm50) selector internal bus ti51/to51/p73 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 match mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 level inversion 8-bit timer mode control register 51 (tmc51) s r q r inv selector inttm51 to51/ti51/p73 selector selector selector 8-bit timer compare register 51 (cr51) 8-bit timer counter 51 (tm51) s
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 21 figure 5-6. block diagram of watch timer remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency figure 5-7. block diagram of watchdog timer f x /2 7 f xt selector selector f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm3 wtm0 watch timer operation mode register (wtm) internal bus selector oscillation stabilization time selection register (osts) clock input controller intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 internal bus division circuit divided clock selector output controller division mode selector run wdtm4 wdtm3 watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) run f x /2 8 f x
data sheet u14259ej1v0ds 22 5.4 clock output/buzzer output controller a clock output/buzzer output control circuit (cku) is incorporated. clocks with the following frequencies can be output as clock output. 65.5 khz/131 khz/262 khz/524 khz/1.05 mhz/2.10 mhz/4.19 mhz/8.38 mhz (at 8.38 mhz operation with main system clock) 32.768 khz (at 32.768 khz operation with subsystem clock) clocks with the following frequencies can be output as buzzer output. 1.02 khz/2.05 khz/4.10 khz/8.19 khz (at 8.38 mhz operation with main system clock) figure 5-8. block diagram of clock output/buzzer output controller remark the clock output/buzzer output controller shares pins with 16-bit timer/event counter 01, in addition to the port function. prescaler f x f xt 8 clock controller pcl/ti011/p74 buz/to01/ti001/p75 4 f x to f x /2 7 f x /2 10 to f x /2 13 selector bcs0, bcs1 bzoe cloe bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 internal bus clock output selection register (cks) selector
data sheet u14259ej1v0ds 23 5.5 a/d converter an a/d converter of 10-bit resolution 8 channels is incorporated. the following two a/d conversion operation start-up methods are available. hardware start software start figure 5-9. block diagram of a/d converter tap selector intad0 intp3 internal bus av ref (shared with analog power supply) a/d conversion result register 0 (adcr0) controller successive approximation register (sar) edge detector ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/adtrg/p03 selector sample & hold circuit voltage comparator series resistor string av ss edge detector
data sheet u14259ej1v0ds 24 5.6 serial interface three channels of the serial interface are incorporated (four channels for the pd780078y subseries). serial interface uart0 serial interface uart2/sio3 serial interface csi1 serial interface iic0 ( pd780078y subseries only) (1) serial interface uart0 the serial interface uart0 has two modes, asynchronous serial interface (uart) mode and infrared data transfer mode. asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit. the on-chip dedicated uart baud rate generator enables communication using a wide range of selectable baud rates. in addition, a baud rate can be also defined by dividing the clock input to the asck0 pin. the dedicated uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). infrared data transfer mode this mode enables pulse output and pulse reception in an irda specification data format note . this mode can be used for office equipment applications such as personal computers. note transfer rate differs with that of irda standard. figure 5-10. block diagram of serial interface uart0 internal bus receive buffer register 0 rxb0 rxd0/p23 txd0/p24 receive shift register 0 pe0 fe0 ove0 asynchronous serial interface status register 0 (asis0) txs0 intser0 intst0 baud rate generator f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 asynchronous serial interface mode register 0 (asim0) intsr0 receive control parity check transmit shift register 0 transmit control parity addition rx0 asck0/p25
data sheet u14259ej1v0ds 25 (2) serial interface uart2/sio3 the serial interface uart2/sio3 has two modes, asynchronous serial (uart) interface mode and 3-wire serial i/o mode. caution do not enable uart2 and sio3 at the same time. (a) serial interface uart2 the serial interface uart2 has three modes, asynchronous serial interface (uart) mode, multiprocessor transfer mode, and infrared data transfer mode. asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit. the on-chip dedicated uart baud rate generator enables communication using a wide range of selectable baud rates. in addition, a baud rate can be also defined by dividing the clock input to the asck2 pin. the dedicated uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). multiprocessor transfer mode this mode enables multiprocessor compatible data transmission/reception. infrared data transfer (irda) mode this mode enables pulse output and pulse reception in an irda specification data format. this mode can be used for office equipment applications such as personal computers. figure 5-11. block diagram of serial interface uart2 rxb2 rx2 rxd2/so3/p35 txd2/si3/p34 pe2 fe2 ove2 txs2 intser2 intst2 f x /2 to f x /2 7 txe2 rxe2 ps21 ps20 cl2 sl2 isem2 power2 intsr2 asck2/sck3/p36 txb2 mpr2 receive buffer register 2 receive shift register 2 receive control parity check asynchronous serial interface status register 2 (asis2) transmit shift register 2 transmit control parity addition baud rate generator transmit buffer register 2 asynchronous serial interface mode register 2 (asim2) internal bus
data sheet u14259ej1v0ds 26 (b) serial interface sio3 the serial interface sio3 has the 3-wire serial i/o mode. 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: serial clock line (sck3), serial output line (so3), and serial input line (si3). since simultaneous transmit and receive operations are available in the 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in 8-bit data in the serial transfer is fixed as msb. the 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. figure 5-12. block diagram of serial interface sio3 internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 3 (sio3) si3/txd2/p34 so3/rxd2/p35 sck3/asck2/p36 intcsi3 f x /2 3 f x /2 4 f x /2 5
data sheet u14259ej1v0ds 27 (3) serial interface csi1 the serial interface csi1 has the 3-wire serial i/o mode. 3-wire serial i/o mode (msb/lsb first selectable) this is an 8-bit data transfer mode using three lines: serial clock line (sck1), serial output line (so1), and serial input line (si1). since simultaneous transmit and receive operations are available in the 3-wire serial i/o mode, the processing time for data transfer is reduced. the serial transfer of 8-bit data can be switched between msb or lsb first, enabling the chip to be connected to devices using either mode. the 3-wire serial i/o mode is useful for connection to a peripheral i/o device that includes a clocked serial interface, a display controller, etc. figure 5-13. block diagram of serial interface csi1 8 8 so1/p21 intcsi1 si1/p20 output selector f x /2 to f x /2 7 sck1/p22 ss1/p80 internal bus serial i/o shift register 1 (sio1) transmit buffer register 1 (sotb1) output latch transmit controller clock start/stop controller & clock phase controller selector transmit data controller
data sheet u14259ej1v0ds 28 (4) serial interface iic0 ( the serial interface iic0 has the i 2 c (inter ic) bus mode (multimaster supported). i 2 c bus mode (multimaster supported) this is an 8-bit data transfer mode using two lines: serial clock line (scl0) and serial data bus line (sda0). this mode complies with the i 2 c bus format, and can output start condition , data , and stop condition during transmission via the serial data bus. these data are automatically detected by hardware during reception. since the scl0 and sda0 are open-drain outputs in iic0, pull-up resistors for the serial clock line and the serial data bus line are required. figure 5-14. block diagram of serial interface iic0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator noise eliminator matched signal iic shift register 0 (iic0) so0 latch iice0 d set clear cl00 sda0/p32 scl0/p33 n-ch open- drain output data hold time correction circuit acknowledge detector wake-up controller acknowledge detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic0 f x cld0 iic transfer clock selection register 0 (iiccl0) internal bus lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detector dad0 smc0 dfc0 cl00 n-ch open- drain output
data sheet u14259ej1v0ds 29 6. interrupt functions a total of 25 interrupt sources (26 sources for the pd780078y subseries) are provided, divided into the following three types. non-maskable: 1 maskable: 23 (24 for the pd780078y subseries) software: 1 table 6-1. interrupt source list (1/2) interrupt default interrupt source internal/ vector table type priority note 1 name trigger external address non- intwdt watchdog timer overflow (non-maskable internal 0004h (a) maskable interrupt selected) maskable 0 intwdt watchdog timer overflow (interval timer mode (b) selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 generation of serial interface uart0 reception error internal 000eh (b) 6 intsr0 end of serial interface uart0 reception 0010h 7 intst0 end of serial interface uart0 transmission 0012h 8 intcsi1 end of serial interface csi1 transfer 0014h 9 intcsi3 end of serial interface sio3 transfer 0016h 10 intiic0 note 3 end of serial interface iic0 transfer 0018h 11 intwti reference time interval signal from watch timer 001ah 12 inttm000 coincidence of tm00 and cr000 (when 001ch compare register is specified) or detection of valid edge of ti010 (when capture register is specified) 13 inttm010 coincidence of tm00 and cr010 (when 001eh compare register is specified) or detection of valid edge of ti000 (when capture register is specified) 14 inttm50 coincidence of tm50 and cr50 0020h 15 inttm51 coincidence of tm51 and cr51 0022h 16 intad0 end of conversion by a/d converter 0024h 17 intwt watch timer overflow 0026h 18 intkr falling edge detection of port 4 external 0028h (d) notes 1. the default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 23, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively. 3. pd780078y subseries only. remark as the watchdog timer interrupt source (intwdt), a non-maskable interrupt or maskable interrupt (internal) can be selected. basic configuration type note 2
data sheet u14259ej1v0ds 30 table 6-1. interrupt source list (2/2) interrupt default interrupt source internal/ vector table type priority note 1 name trigger external address maskable 19 intser2 generation of uart2 reception error internal 002ah (b) 20 intsr2 end of uart2 reception 002ch 21 intst2 end of uart2 transmission/data transfer note 3 002eh 22 inttm001 coincidence of tm01 and cr001 (when 0030h compare register specified) or detection of ti011 valid edge (when capture register specified) 23 inttm011 coincidence of tm01 and cr011 (when 0032h compare register specified) or detection of ti001 valid edge (when capture register specified) software brk brk instruction execution 003eh (e) notes 1. the default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 23, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively. 3. this source generates an interrupt request signal during data transfer from the transmit buffer register 2 (txb2) to the transmit shift register. interrupt sources can be selected by the transmit interrupt signal select flag (ismd). basic configuration type note 2
data sheet u14259ej1v0ds 31 figure 6-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp3) internal bus priority controller vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority controller vector table address generator standby release signal interrupt request mk ie pr isp if priority controller vector table address generator external interrupt edge enable register (egp, egn) edge detector internal bus standby release signal interrupt request
data sheet u14259ej1v0ds 32 figure 6-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mk ie pr isp if priority controller vector table address generator falling edge detector internal bus standby release signal interrupt request priority controller vector table address generator internal bus interrupt request
data sheet u14259ej1v0ds 33 7. external device expansion functions the external device expansion functions connect external devices to areas other than the internal rom, ram and sfr. ports 4 to 6 are used for external device connection. 8. standby function there are the following two standby functions to reduce the consumption current. halt mode: the cpu operating clock is stopped. the average consumption current can be reduced by intermittent operation in combination with the normal operating mode. stop mode: the main system clock oscillation is stopped. the whole operation by the main system clock is stopped, so that the system operates with ultra-low power consumption. this mode can be used only when the main system clock is operating (it cannot be used to stop the subsystem clock). figure 8-1. standby function note the current consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set bit 7 (mcc) of the processor clock control register (pcc) to stop the main system clock. the stop instruction cannot be used. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu halted, oscillation maintained) subsystem clock operation note halt mode note (clock supply to cpu halted, oscillation maintained) interrupt request interrupt request interrupt request halt instruction halt instruction stop instruction css = 1 css = 0
data sheet u14259ej1v0ds 34 9. reset function the following two reset methods are available. external reset by reset pin internal reset by watchdog timer inadvertent program loop time detection 10. mask option table 10-1. selection of pin mask options subseries pin mask option pd780078 subseries p30 to p33 an on-chip pull-up resistor can be specified in 1-bit pd780078y subseries p30, p31 units. p30 to p33 note on-chip pull-up resistor can be specified by mask option. the mask option can be specified in 1-bit units. note only p30 and p31 can be specified on the pd780078y subseries.
data sheet u14259ej1v0ds 35 11. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
data sheet u14259ej1v0ds 36 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 37 parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v av ref ?.3 to v dd + 0.3 note v av ss ?.3 to +0.3 note v input voltage v i1 p00 to p03, p10 to p17, p20 to p25, p34 to p36, ?.3 to v dd + 0.3 note v p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, x1, x2, xt1, xt2, reset v i2 p30 to p33 n-ch open-drain ?.3 to v dd + 0.3 note v output voltage v o ?.3 to v dd + 0.3 note v analog input v an p10 to p17 analog input pin av ss ?0.3 to av ref + 0.3 v voltage and ?.3 to v dd + 0.3 output current, i oh per pin ?0 ma high total for p00 to p03, p40 to p47, p50 to p57, p64 to p67, ?5 ma p70 to p75, p80 total for p20 to p25, p30 to p36 ?5 ma output current, low i ol per pin for p00 to p03, p20 to p25, p34 to p36, 20 ma p40 to p47, p64 to p67, p70 to p75, p80 per pin for p30 to p33, p50 to p57 30 ma total for p00 to p03, p40 to p47, p64 to p67, 50 ma p70 to p75, p80 total for p20 to p25 20 ma total for p30 to p36 100 ma total for p50 to p57 100 ma operating ambient t a ?0 to +85 c temperature storage t stg ?0 to +150 c temperature 12. electrical specifications absolute maximum ratings (t a = 25 c) note 6.5 v or below. caution product quality may suffer if the absolute maximum rating is exceeded for even single parameter or even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions ensuring that the absolute maximum ratings are not exceeded.
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 38 resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation v dd = 4.0 to 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.0 5.0 mhz oscillation after v dd reaches oscil- 4 ms stabilization time note 2 lation voltage range min. crystal oscillation v dd = 4.0 to 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.0 5.0 mhz oscillation v dd = 4.0 to 5.5 v 10 ms stabilization time note 2 30 ms external x1 input v dd = 4.0 to 5.5 v 1.0 8.38 mhz clock frequency (f x ) note 1 5.0 mhz x1 input v dd = 4.0 to 5.5 v 50 500 ns high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a line through which a high fluctuating current flows. always keep the ground point of the oscillator to the same potential as v ss1 . do not ground the capacitor to a ground pattern in which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. main system clock oscillator characteristics (t a = ?0 to 85 c, v dd = 1.8 to 5.5 v) x2 ic x1 c1 c2 x2 x1 pd74hcu04 c2 x1 x2 ic c1 capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75, p80 p30 to p33 20 pf remark unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics.
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 39 subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. 2. time required to stabilize oscillation after v dd reaches oscillation voltage min. cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a line through which a high fluctuating current flows. always keep the ground point of the oscillator to the same potential as v ss1 . do not ground the capacitor to a ground pattern in which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consump- tion current, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillation 32 32.768 35 khz resonator frequency (f xt ) note 1 oscillation v dd = 4.0 to 5.5 v 1.2 2 s stabilization time note 2 10 s external xt1 input frequency (f xt ) note 1 32 38.5 khz clock xt1 input high-/low- level width (t xth , t xtl )5 15 s c3 xt2 xt1 ic r c4 xt1 xt2 pd74hcu04
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 40 manufacturer part number frequency recommended circuit constant oscillation voltage range remarks (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. csb1000j 1.00 150 150 1.8 5.5 co., ltd. csbf1000j csa2.00mg040 2.00 100 100 cst2.00mg040 on-chip on-chip cstcc2.00mg0h6 2.0 5.5 csa3.58mg 3.58 30 30 1.8 5.5 cst3.58mgw on-chip on-chip cstcc3.58mg0h6 2.0 5.5 csa4.00mg 4.00 30 30 1.8 5.5 csts0400mh06 on-chip on-chip cstcc4.0mg0h6 2.0 5.5 csa4.19mg 4.19 30 30 1.8 5.5 csts0419mg06 on-chip on-chip cstcc4.19mg0h6 2.0 5.5 csa4.91mg 4.91 30 30 1.8 5.5 csts0491mg03 on-chip on-chip cstcc4.91mg0h6 2.0 5.5 csa5.00mg 5.00 30 30 1.8 5.5 csts0500mg03 on-chip on-chip cstcc5.00mg0h6 2.0 5.5 csa8.00mtz 8.00 30 30 4.0 5.5 csts0800mg03 on-chip on-chip cstcc8.00mg csa8.38mtz 8.38 30 30 csts0838mg03 on-chip on-chip cstcc8.38mg tdk ccr3.58mc3 3.58 on-chip on-chip 1.8 5.5 ccr4.0mc3 4.00 ccr4.19mc3 4.19 ccr5.0mc3 5.00 ccr6.0mc3 6.00 4.0 5.5 ccr8.0mc5 8.00 ccr8.38mc5 8.38 recommended oscillator constant main system clock: ceramic resonator (t a = ?5 to +85 c) caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details please contact directly the manufacturer of the resonator you will use.
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 41 main system clock: crystal resonator (t a = ?0 to +70 c) manufacturer part number frequency recommended circuit constant oscillation voltage range remarks (mhz) c1 (pf) c2 (pf) min. (v) max. (v) kinseki, ltd. hc-49/u-s note 4.19 18 18 1.9 5.5 r = 4.7 k ? 8.38 27 27 4.0 5.5 note a limiting resistor (r = 4.7 k ? ) is required when the hu-49/u-s manufactured by kinseki, ltd. is used as the ceramic resonator (see the figure below) at f x = 4.19 mhz. note a limiting resistor (r = 330 k ? ) is required when the c-002rx, mc-206, or mc-306 manufactured by seiko epson inc. is used as the ceramic resonator (see the figure below). manufacturer part number frequency recommended circuit constant oscillation voltage range remarks (mhz) c1 (pf) c2 (pf) min. (v) max. (v) seiko c-002rx note 32.768 15 15 1.8 5.5 r = 330 k ? epson inc. mc-206 note mc-306 note subsystem clock: crystal resonator (t a = ?0 to +85 c) caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details please contact directly the manufacturer of the resonator you will use. c3 xt2 c-002rx mc-206 mc-306 xt1 r c4 c2 x1 hc-49/u-s (4.19 mhz) x2 r c1
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 42 dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit output current, i oh per pin 1ma high all pins 15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75, p80 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, 20 ma p70 to p75, p80 total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, p40 to p47, v dd = 2.7 to 5.5 v 0.7v dd v dd v high p50 to p57, p64 to p67 0.8v dd v dd v v ih2 p00 to p03, p20, p22, p23, p25, v dd = 2.7 to 5.5 v 0.8v dd v dd v p34 to p36, p70 to p75, p80, 0.85v dd v dd v reset v ih3 p30 to p33 (n-ch open-drain) v dd = 2.7 to 5.5 v 0.7v dd v dd v 0.8v dd v dd v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd 0.5 v dd v v dd 0.2 v dd v v ih5 xt1, xt2 v dd = 4.0 to 5.5 v 0.8v dd v dd v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, p40 to p47, v dd = 2.7 to 5.5 v 0 0.3v dd v low p50 to p57, p64 to p67 0 0.2v dd v v il2 p00 to p03, p20, p22, p23, p25, v dd = 2.7 to 5.5 v 0 0.2v dd v p34 to p36, p70 to p75, p80, 0 0.15v dd v reset v il3 p30 to p33 (n-ch open-drain) 4.0 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v v il5 xt1, xt2 v dd = 4.0 to 5.5 v 0 0.2v dd v 0 0.1v dd v output voltage, v oh1 i oh = 1 ma v dd = 4.0 to 5.5 v v dd 1.0 v dd v high i oh = 100 av dd = 1.8 to 5.5 v v dd 0.5 v dd v output voltage, v ol1 p30 to p33 v dd = 4.0 to 5.5 v, 2.0 v low i ol = 15 ma v ol2 p50 to p57 v dd = 4.0 to 5.5 v, 0.4 2.0 v i ol = 15 ma v ol3 p00 to p03, p20 to p25, v dd = 4.0 to 5.5 v, 0.4 v p34 to p36, p40 to p47, i ol = 1.6 ma p64 to p67, p70 to p75, p80 v ol4 i ol = 400 a 0.5 v remark unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics.
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 43 parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, 3 a current, high p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, ? a current, low p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80, reset i lil2 x1, x2, xt1, xt2 ?0 a i lil3 p30 to p33 ? a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v ? a current, low mask option r 1 v in = 0 v, p30, p31, p32 note , p33 note 15 30 90 k ? pull-up resistor software pull-up r 2 v in = 0 v, p00 to p03, p20 to p25, p34 to p36, 15 30 90 k ? resistor p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) note pd780078 subseries only. remark unless specified otherwise, alternate-function pin characteristics are the same as port pin characteristics.
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 44 parameter symbol conditions min. typ. max. unit power i dd1 note 2 8.38 mhz crystal v dd = 5.0 v 10% note 3 when a/d converter stopped 5.5 11.0 ma supply oscillation operating when a/d converter is operating 6.5 13.0 ma current note 1 mode 5.0 mhz crystal v dd = 3.0 v 10% note 3 when a/d converter stopped 2.0 4.0 ma oscillation operating when a/d converter is operating 3.0 6.0 ma mode v dd = 2.0 v 10% note 4 when a/d converter stopped 0.4 1.5 ma when a/d converter is operating 1.4 4.2 ma i dd2 8.38 mhz crystal v dd = 5.0 v 10% note 3 when peripheral function stopped 1.1 2.2 ma oscillation halt mode when peripheral function is operating 4.7 ma 5.0 mhz crystal v dd = 3.0 v 10% note 3 when peripheral function stopped 0.35 0.7 ma oscillation halt when peripheral function is operating 1.7 ma mode v dd = 2.0 v 10% note 4 when peripheral function stopped 0.15 0.4 ma when peripheral function is operating 1.1 ma i dd3 32.768 khz crystal v dd = 5.0 v 10% 40 80 a oscillation operating v dd = 3.0 v 10% 20 40 a mode note 5 v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal v dd = 5.0 v 10% 30 60 a oscillation halt v dd = 3.0 v 10% 6 18 a mode note 5 v dd = 2.0 v 10% 2 10 a i dd5 stop mode v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a notes 1. total current flowing in the internal power supply (v dd0 , v dd1 ). 2. includes the peripheral operating current. however, the pull-up resistor on the port and the current flowing in the av ref pin are not included. 3. when the processor clock control register (pcc) is set to 00h. 4. when pcc is set to 02h. 5. when the main system clock has been stopped. dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v)
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 45 parameter symbol conditions min. typ. max. unit cycle time t cy operating with main 4.0 v v dd 5.5 v 0.24 16 s (min. instruction system clock 2.7 v v dd < 4.0 v 0.4 16 s execution time) 1.8 v v dd < 2.7 v 1.6 16 s operating with subsystem clock 103.9 note 1 122 125 s ti000, ti010, t tih0 3.5 v v dd 5.5 v 2/f sam + 0.1 note2 s ti001, ti011 input t til0 2.7 v v dd < 3.5 v 2/f sam + 0.2 note2 s high-/low-level width 1.8 v v dd < 2.7 v 2/f sam + 0.5 note2 s ti50, ti51 input f ti5 v dd = 2.7 to 5.5 v 0 4 mhz frequency 0 275 khz ti50, ti51 input t tih5 v dd = 2.7 to 5.5 v 100 ns high-/low-level width t til5 1.8 s interrupt request input t inth intp0 to intp3, v dd = 2.7 to 5.5 v 1 s high-/low-level width t intl p40 to p47 2 s reset t rsl v dd = 2.7 to 5.5 v 10 s low-level width 20 s ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) notes 1. value when using the external clock. when using a crystal resonator, the value becomes 114 s (min.). 2. selection of f sam = f x , f x /4, f x /64 is available with bits 0 and 1 (prm0n0, prm0n1) of prescaler mode register 0n (prm0n). however, if the ti00n valid edge is selected as the count clock, the value becomes f sam = f x /8 (n = 0, 1).
data sheet u14259ej1v0ds 46 t cy vs v dd (at main system clock operation) cycle time t cy [ s] 5.0 1.0 2.0 1.6 0.4 0.24 0.1 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 16.0 supply voltage v dd [v] operation guaranteed range
data sheet u14259ej1v0ds 47 (2) read/write operation (t a = 40 to + 85 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy 54 ns t add2 (3 + 2n)t cy 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy 87 ns t rdd2 (3 + 2n)t cy 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 33 ns t rdl2 (2.5 + 2n)t cy 33 ns wait input time from rd t rdwt1 t cy 43 ns t rdwt2 t cy 43 ns wait input time from wr t wrwt t cy 25 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy 15 ns rd delay time from astb t astrd 6ns wr delay time from astb t astwr 2t cy 15 ns astb delay time from t rdast 0.8t cy 15 1.2t cy ns rd in external fetch address hold time from t rdadh 0.8t cy 15 1.2t cy + 30 ns rd in external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy 15 1.2t cy + 30 ns rd delay time from wait t wtrd 0.8t cy 2.5t cy + 25 ns wr delay time from wait t wtwr 0.8t cy 2.5t cy + 25 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l is the load capacitance of ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins)
data sheet u14259ej1v0ds 48 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns data input time from address t add1 (2 + 2n)t cy 108 ns t add2 (3 + 2n)t cy 120 ns address output time from rd t rdad 0 200 ns data input time from rd t rdd1 (2 + 2n)t cy 148 ns t rdd2 (3 + 2n)t cy 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 40 ns t rdl2 (2.5 + 2n)t cy 40 ns wait input time from rd t rdwt1 t cy 75 ns t rdwt2 t cy 75 ns wait input time from wr t wrwt t cy 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy 30 ns rd delay time from astb t astrd 10 ns wr delay time from astb t astwr 2t cy 30 ns astb delay time from t rdast 0.8t cy 30 1.2t cy ns rd in external fetch address hold time from t rdadh 0.8t cy 30 1.2t cy + 60 ns rd in external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns address hold time from wr t wradh 0.8t cy 30 1.2t cy + 60 ns rd delay time from wait t wtrd 0.5t cy 2.5t cy + 50 ns wr delay time from wait t wtwr 0.5t cy 2.5t cy + 50 ns (2) read/write operation (t a = 40 to + 85 t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l is the load capacitance of ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins)
data sheet u14259ej1v0ds 49 (2) read/write operation (t a = 40 to + 85 parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns data input time from address t add1 (2 + 2n)t cy 233 ns t add2 (3 + 2n)t cy 240 ns address output time from rd t rdad 0 400 ns data input time from rd t rdd1 (2 + 2n)t cy 325 ns t rdd2 (3 + 2n)t cy 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 92 ns t rdl2 (2.5 + 2n)t cy 92 ns wait input time from rd t rdwt1 t cy 350 ns t rdwt2 t cy 350 ns wait input time from wr t wrwt t cy 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy 60 ns rd delay time from astb t astrd 20 ns wr delay time from astb t astwr 2t cy 60 ns astb delay time from t rdast 0.8t cy 60 1.2t cy ns rd in external fetch address hold time from t rdadh 0.8t cy 60 1.2t cy + 120 ns rd in external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 40 240 ns address hold time from wr t wradh 0.8t cy 60 1.2t cy + 120 ns rd delay time from wait t wtrd 0.5t cy 2.5t cy + 100 ns wr delay time from wait t wtwr 0.5t cy 2.5t cy + 100 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l is the load capacitance of ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins)
data sheet u14259ej1v0ds 50 (3) serial interface (t a = 40 to +85 parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy1 4.0 v v dd 5.5 v 954 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3 high-/low-level t kh1 v dd = 4.0 to 5.5 v t kcy1 /2 50 ns width t kl1 t kcy1 /2 100 ns si3 setup time t sik1 4.0 v v dd 5.5 v 100 ns (to sck3 ) 2.7 v v dd < 4.0 v 150 ns 1.8 v v dd < 2.7 v 300 ns si3 hold time t ksi1 400 ns (from sck3 ) delay time from sck3 t kso1 c = 100 pf note 300 ns to so3 output parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy2 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3 high-/low-level t kh2 4.0 v v dd 5.5 v 400 ns width t kl2 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns si3 setup time t sik2 100 ns (to sck3 ) si3 hold time t ksi2 400 ns (from sck3 ) delay time from sck3 t kso2 c = 100 pf note 300 ns to so3 output note c is the load capacitance of the so3 output line. note c is the load capacitance of the sck3 and so3 output lines. (b) sio3 3-wire serial i/o mode (sck3 ... external clock input)
data sheet u14259ej1v0ds 51 (c) csi1 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy3 4.0 v v dd 5.5 v 240 ns 2.7 v v dd < 4.0 v 500 ns 1.8 v v dd < 2.7 v 1 s sck1 high-/low-level t kh3 4.0 v v dd 5.5 v t kcy3 /2 5ns width t kl3 2.7 v v dd < 4.0 v t kcy3 /2 20 ns 1.8 v v dd < 2.7 v t kcy3 /2 30 ns si1 setup time t sik3 25 ns (to sck1 ) si1 hold time t ksi3 110 ns (to sck1 ) delay time from sck1 t kso3 c = 100 pf note 150 ns to so1 output note c is the load capacitance of the sck1 and so1 output lines. (d) csi1 3-wire serial i/o mode (sck1 ... external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy4 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 500 ns 1.8 v v dd < 2.7 v 1 s sck1 high-/low-level t kh4 4.0 v v dd 5.5 v 100 ns width t kl4 2.7 v v dd < 4.0 v 250 ns 1.8 v v dd < 2.7 v 500 ns si1 setup time t sik4 25 ns (to sck1 ) si1 hold time t ksi4 110 ns (to sck1 ) delay time from sck1 t kso4 c = 100 pf note 150 ns to so1 output note c is the load capacitance of the so1 output line. (e) uart0 mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps 2.7 v v dd < 4.0 v 78125 bps 1.8 v v dd < 2.7 v 39063 bps
data sheet u14259ej1v0ds 52 parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy5 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck0 high-/low-level t kh5 4.0 v v dd 5.5 v 400 ns width t kl5 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 1.8 v v dd < 2.7 v 9766 bps (f) uart0 mode (external clock input) (g) uart0 mode (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate v dd = 4.0 to 5.5 v 131031 bps bit rate allowable error v dd = 4.0 to 5.5 v 0.87 % output pulse width v dd = 4.0 to 5.5 v 1.2 0.24/fbr note s input pulse width v dd = 4.0 to 5.5 v 4/f x s note fbr: specified baud rate (h) uart2 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 262062 bps 2.7 v v dd < 4.0 v 156250 bps 1.8 v v dd < 2.7 v 62500 bps (i) uart2 (external clock input) parameter symbol conditions min. typ. max. unit asck2 cycle time t kcy6 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck2 high-/low-level t kh6 4.0 v v dd 5.5 v 400 ns width t kl6 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 78125 bps 2.7 v v dd < 4.0 v 39063 bps 1.8 v v dd < 2.7 v 19531 bps
data sheet u14259ej1v0ds 53 (k) i 2 c bus mode parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f scl 0 100 0 400 khz bus free time t buf 4.7 1.3 s (between stop and start condition) hold time note 1 t hd:sta 4.0 0.6 s scl0 clock low-level width t low 4.7 1.3 s scl0 clock high-level width t high 4.0 0.6 s start/restart condition setup time t su:sta 4.7 0.6 s data hold time cbus compatible master t hd:dat 5.0 s i 2 c bus 0 note 2 0 note 2 0.9 note 3 s data setup time t su:dat 250 100 note 4 ns sda0 and scl0 signal rise time t r 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto 4.0 0.6 s capacitive load per each bus line cb 400 400 pf spike pulse width controlled by input filter t sp 050ns notes 1. on start condition, the first clock pulse is generated after hold period. 2. to fulfill undefined area of the scl0 falling edge, it is necessary for the device to provide internally sda0 signal (on v ihmin. of scl0 signal) with at least 300 ns of hold time. 3. if the device does not extend the scl0 signal low hold time (t low ), only maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in the standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. if the device does not extend the scl0 signal low state hold time t su:dat 250 ns if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by standard mode i 2 c bus specification). 5. cb : total capacitance per one bus line (unit : pf) (j) uart2 (infrared data transfer mode) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 262062 bps bit rate allowable error 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate
data sheet u14259ej1v0ds 54 ac timing test points (excluding x1, xt1 inputs) clock timing ti timing 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input 1/f t5 t tih5 t til5 ti50, ti51 ti000, ti010, ti001, ti011 t til0 t tih0
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 55 read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd lower 8-bit address operation code a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address operation code t add1 hi-z t ads t asth t adh t rdd1 t rdad t rdadh t rdast t astrd t rdl1 t rdh
data sheet u14259ej1v0ds 56 external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 higher 8-bit address lower 8-bit address astb rd t add2 t ads t asth t adh t rdad t rdd2 t astrd wr t astwr hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z a8 to a15 ad0 to ad7 read data write data higher 8-bit address lower 8-bit address
data sheet u14259ej1v0ds 57 serial transfer timing 3-wire serial i/o mode: uart mode (external clock input): i 2 c bus mode: si1, si3 so1, so3 t kcyn t kln t khn t sikn t ksin input data t kson output data sck1, sck3 n = 1 to 4 t kcyn t khn t kln asck0, asck2 n = 5, 6 scl0 sda0 t hd:sta t buf t hd:dat t high t f t su:dat t su:sta t hd:sta t sp t su : sto t r stop condition start condition stop condition restart condition t low
data sheet u14259ej1v0ds 58 a/d converter characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 2.2 v av ref < 2.7 v 0.6 1.2 %fsr conversion time t conv 4.0 v av ref 5.5 v 14 100 s 2.7 v av ref < 4.0 v 19 100 s 2.2 v av ref < 2.7 v 28 100 s zero-scale error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 2.2 v av ref < 2.7 v 1.2 %fsr full-scale error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 2.2 v av ref < 2.7 v 1.2 %fsr integral linear error 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb 2.2 v av ref < 2.7 v 8.5 lsb differential linear error 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb 2.2 v av ref < 2.7 v 3.5 lsb analog input impedance during sampling 100 k ? other than during sampling 10 m ? analog input voltage v ian 0av ref v av ref resistance r airef during a/d conversion 20 40 k ? overall error excluding quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. remark fsr: full-scale range
data sheet u14259ej1v0ds 59 data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention i dddr subsystem clock is not used (xt1 = v dd ) 0.1 30 a power supply current and feed-back resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /fx ms wait time release by interrupt request note ms note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
data sheet u14259ej1v0ds 60 interrupt request input timing reset input timing intp0 to intp3 t intl t inth t rsl reset
data sheet u14259ej1v0ds 61 13. package drawings 48 49 32 64 1 17 16 33 64-pin plastic qfp (14x14) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.6 0.4 14.0 0.2 0.8 (t.p.) 1.0 j 17.6 0.4 k p64gc-80-ab8-5 c 14.0 0.2 i0.15 1.8 0.2 l 0.8 0.2 f 1.0 n p q 0.10 2.55 0.1 0.1 0.1 r s 5 5 2.85 max. h0.37 + 0.08 ? 0.07 m0.17 + 0.08 ? 0.07 s s n j detail of lead end c d a b r k m l p i s q g f m h remark the external dimensions and material of the es version are the same as those of the mass-produced version.
data sheet u14259ej1v0ds 62 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.0 0.2 c 12.0 0.2 d f 1.125 14.0 0.2 b 12.0 0.2 n 0.10 p q 0.1 0.05 1.0 s r 3 + 4 ? 3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 + 0.06 ? 0.10 i 0.13 j k 1.0 0.2 0.65 (t.p.) l 0.5 m 0.17 + 0.03 ? 0.07 p64gk-65-9et-3 t u 0.6 0.15 0.25 f m a b cd n t l u 1.1 0.1 remark the external dimensions and material of the es version are the same as those of the mass-produced version.
data sheet u14259ej1v0ds 63 14. recommended soldering conditions the pd780078, 780078y subseries should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 14-1. surface mounting type soldering conditions (1) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), ir35-00-2 count: two times or less vps package peak temperature: 215 c, time: 40 sec. max. (at 200 c or higher), vp15-00-2 count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 sec. max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) caution do not use different soldering methods together (except for partial heating).
data sheet u14259ej1v0ds 64 (2) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), ir35-107-2 count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 sec. max. (at 200 c or higher), vp15-107-2 count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max., time: 10 sec. max., count: once, ws60-107-1 preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
pd780076, 780078, 780076y, 780078y data sheet u14259ej1v0ds 65 appendix a. development tools the following development tools are available for system development using the pd780078, 780078y subseries. also refer to (6) cautions on using development tools. (1) software package sp78k0 software package common to 78k/0 series (2) language processing software ra78k0 assembler package common to 78k/0 series cc78k0 c compiler package common to 78k/0 series df780078 device file for pd780078, 780078y subseries cc78k0-l c compiler library source file common to 78k/0 series (3) flash memory writing tools flashpro iii (fl-pr3, flash programmer dedicated to on-chip flash memory microcontroller pg-fp3) fa-64gc adapter for flash memory writing fa-64gk-9et ? fa-64gc: for 64-pin plastic qfp (gc-ab8 type) ? fa-64gk-9et: for 64-pin plastic tqfp (gk-9et type) (4) debugging tool ?when using in-circuit emulator ie-78k0-ns(?) ie-78k0-ns(?) in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa performance board to enhance/expand functions of ie-78k0-ns ie-70000-98-if-c adapter when using pc-9800 series as host machine (excluding notebook pcs) (c bus compatible) ie-70000-cd-if-a pc card and interface cable when using notebook pc as host machine (pcmcia socket compatible) ie-70000-pc-if-c adapter when using ibm pc/at tm compatible as host machine (isa bus compatible) ie-70000-pci-if-a adapter necessary when using on-chip pci bus pc as host machine ie-780078-ns-em1 emulation board to emulate pd780078, 780078y subseries np-64gc emulation probe for 64-pin plastic qfp (gc-ab8 type) np-64gc-tq np-64gk emulation probe for 64-pin plastic tqfp (gk-9et type) ev-9200gc-64 conversion socket for connecting target system designed to mount a 64-pin plastic qfp (gc-ab8 type) and np-64gc tgc-064sap conversion adapter for connecting target system designed to mount a 64-pin plastic qfp (gc-ab8 type) and np-64gc-tq tgk-064sbp conversion adapter for connecting target system board designed to mount a 64-pin plastic tqfp (gk-9et type) and np-64gk id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df780078 device file common to pd780078, 780078y subseries
data sheet u14259ej1v0ds 66 when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs) (c bus compatible) ie-70000-pc-if-c interface adapter when using ibm pc/at compatible as host machine (isa bus compatible) ie-70000-pci-if-a adapter necessary when using on-chip pci bus pc as host machine ie-78000-r-sv3 interface adapter and cable when using ews as host machine ie-780078-ns-em1 emulation board to emulate pd780078, 780078y subseries ie-78k0-r-ex1 emulation probe conversion board necessary to use ie-780078-ns-em1 on ie-78001-r-a ep-78240gc-r emulation probe for 64-pin plastic qfp (gc-ab8 type) ep-78012gk-r emulation probe for 64-pin plastic tqfp (gk-9et type) ev-9200gc-64 socket to be mounted on target system board manufactured for 64-pin plastic qfp (gc-ab8 type) tgk-064sbp conversion adapter for connecting target system board designed to mount a 64-pin plastic tqfp (gk- 9et) and ep-78012gk-r. id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780078 device file common to pd780078, 780078y subseries (5) real-time os rx78k0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
data sheet u14259ej1v0ds 67 host machine pc ews [os] pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatible sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] ra78k0 cc78k0 id78k0-ns id78k0 sm78k0 rx78k0 mx78k0 dos-based software (6) cautions on using development tools the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780078. the cc78k0 and rx78k0 are used in combination with the ra78k0 and the df780078. the fl-pr3, fa-64gc, fa64gk, np-64gc, np-64gc-tq, and np-64gk-9et are products made by naito densei machida mfg. co., ltd. (+81-44-822-3813). the tgc-064sap and tgk-064sbp are products made by tokyo eletech corp. refer to: daimaru kogyo, ltd. electronics dept. (tel: tokyo +81-3-3820-7112) electronics 2nd dept. (tel: osaka +81-6-6244-6672) for third party development tools, see the single-chip microcontroller development tools selection guide (u11069e) . the host machines and oss supporting each software are as follows.
data sheet u14259ej1v0ds 68 appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780078, 780078y subseries user s manual u14260e pd780076, 780078, 780076y, 780078y data sheet this document pd78f0078, 78f0078y data sheet u14258e 78k/0 series user s manual instructions u12326e documents related to development tools (user s manuals) document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e ie-78k0-ns in-circuit emulator u13731e ie-78001-r-a in-circuit emulator u14142e ie-78k0-r-ex1 in-circuit emulator to be prepared ie-780078-ns-em1 emulation board to be prepared ep-78012gk-r emulation probe eeu-1538 ep-78240 emulation probe u10332e sm78k0s, sm78k0 system simulator ver. 2.10 or later operation u14611e windows based sm78k series system simulator ver. 2.10 or later external part user open u15006e interface specifications id78k0-ns integrated debugger ver. 2.00 or later windows based operation u14379e id78k0 integrated debugger ver. 2.00 or later ews based reference u11151e id78k0 integrated debugger ver. 2.00 or later windows based reference u11539e guide u11649e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u14259ej1v0ds 69 documents related to embedded software (user s manuals) document name document no. 78k/0 series real-time os fundamentals u11537e installation u11536e 78k/0 series os mx78k0 fundamental u12257e other documents document name document no. semiconductor selection guide - programs & packages - (cd-rom) x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
data sheet u14259ej1v0ds 70 purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip and iebus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc.
data sheet u14259ej1v0ds 71 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
pd780076, 780078, 780076y, 780078y the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00.4 the information in this document is current as of march, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a pa rticular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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