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am79q2241/42/43 data sheet publication# 080250 rev: g version:1.0 date: dec 20, 2001 intelligent access voice? solutions quad islac? quad intelligent subscriber line audio-processing circuit (quad islac?) am79q2241/2242/2243 device applications voice over ip/dsl ? integrated access devices (iad), smart residential gateways (srg), home gateway/ router cable telephony ? niu, set-top box, home side box, cable modem, cable pc fiber ? fiber in the loop (fitl), fiber to the home (ftth) wireless local loop, intelligent pbx dlc-mux co features high performance digital signal processor provides programmable control of all major linecard functions ? a-law/-law and linear codec ? transmit and receive gain ? two-wire ac impedance ? transhybrid balance ? equalization ? dc loop feeding ? smooth or abrupt polarity reversal ? loop supervision ? off-hook debounce circuit ? ground-key and ring-trip filters ? ringing generation and control ? adaptive hybrid balance ? line and circuit testing ? tone generation ? metering generation at 12 khz and 16 khz ? envelope shaping and level control selectable pcm/mpi or gci digital interfaces ? supports most available master clock frequencies from 512 khz to 8.192 mhz general purpose i/o pins +3.3 v dc operation exceeds lssgr and itu requirements supports external ringing with on-chip ring-trip circuit ? automatic or manual ring-trip modes ordering information device package am79q2241 vc 64-pin tqfp am79q2242 jc 68-pin plcc am79q2243 vc 80-pin tqfp description the quad islac? device, in combination with an islic? device, implements a four channel universal telephone line interface. this enables the design of a single, low cost, high performance, fully software programmable line interface for multiple country applications. all ac, dc, and signaling parameters are fully programmable via microprocessor or gci interfaces. additionally, the quad islac device has integrated self-test and line-test capabilities to resolve faults to the line or line circuit. the integrated test capability is crucial for remote applications where dedicated test hardware is not cost effective. related literature 080274 am79d2251 dual islac data sheet 080248 am79231 islic data sheet 080693 am79240 islic data sheet 080249 am79241 islic data sheet 080253 am79251 islic data sheet 080344 am79r2xx/am79q224x technical reference 080345 am79r240/am79d2251 technical reference block diagram bath dclk/s0 batl batp quad islac vcca dgnd 1 dgnd 2 i/o 1 - i/o 4 tsca/g tscb dra/dd drb dxb dxa/du pclk/fs mclk fs/dcl cs/rst dio/s1 int 4 vccd islic islic islic islic 4 7 7 rc networks and protection external ringing sense resistors rshb rslb rspb rref ld 4 p 1 -p 3 ld 3 adgnd 1 adgnd 2 ld 2 vref ld 1 a 1 b 1 a 2 b 2 a 3 b 3 a 4 b 4 5 5
intelligent access voice? solutions 2 am79q2241/42/43 data sheet table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 quad islac? device internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 features of the intelligent access? chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 environmental ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 electrical ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 intelligent access voice chipsets system target specifications . . . . . . . . .10 dc specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 transmission and signaling specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 transmit and receive paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 attenuation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 group delay distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 single frequency distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 intermodulation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 gain linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 total distortion including quantizing distortion . . . . . . . . . . . . . . . . . . . . . . . . .17 overload compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 discrimination against out-of-band input signals . . . . . . . . . . . . . . . . . . . . . . . . .18 spurious out-of-band signals at the analog output . . . . . . . . . . . . . . . . . . . . . .18 switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 pcm switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 microprocessor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 master clock: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 pcm switching waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 gci timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 gci waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 internal ringing linecard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 external ringing linecard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 linecard parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 68-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 64-pin thin quad flat pack (tqfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 80-pin thin quad flat pack (tqfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 revision a to revision b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 revision b to revisionc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 revision c to revision d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 revision d to revision e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 revision e to revision f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 revision f to g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
intelligent access voice? solutions am79q2241/42/43 data sheet 3 product description the intelligent access? voice chipsets integrate all functions of the subscriber line for four subscriber lines. one or more of two chip types are used to implement the linecard; an islic device and a quad islac device. these provide the following basic functions: 1. the islic device: a high voltage, bipolar ic that drives the subscriber line, maintains longitudinal balance and senses line conditions. 2. the quad islac device: a low voltage cmos ic that provides conversion and dsp functions for all 4 channels. complete schematics of linecards using the intelligent access voice chipsets for internal and external ringing are shown in ?application circuits? on page 26. the islic device uses reliable, bipolar technology to provide the power necessary to drive a wide variety of subscriber lines. it can be programmed by the islac device to operate in eight different modes that control power consumption and signaling modes. this enables it to have full control over the subscriber loop. the islic device is designed to be used exclusively with the islac device as part of a multiple-line chipset. the islic device requires only +5 v power and the battery supplies for its operation. the islic device implements a linear loop-current feeding method with the enhancement of intelligent thermal management in a controlled manner. this limits the amount of power dissipated on the islic chip by dissipating excess power in external resistors. each islac device contains high-performance codec circuits that provide a/d and d/a conversion for voice (codec), dc-feed and supervision signals for four subscriber channels. the islac device contains a dsp core that handles signaling, dc-feed, supervision and line diagnostics for all four channels. the dsp core selectively interfaces with three types of backplanes: ? standard pcm/mpi ? standard gci ? modified gci with a single analog line per gci channel the intelligent access voice chipset provides a complete software configurable solution to the borscht functions as well as complete programmable control over subscriber line dc-feed characteristics, such as current limit and feed resistance. in addition, these chipsets provide system level solutions for the loop supervisory functions and metering. in total, they provide a programmable solution that can satisfy worldwide linecard requirements by software configuration. software programmed filter coefficients, dc-feed data and supervision data are easily calculated with the winslac software. this pc software is provided free of charge. it allows the designer to enter a description of system requirements. winslac then computes the necessary coefficients and plots the predicted system results. the islic interface unit inside the islac device processes information regarding the line voltages, loop currents and battery voltage levels. these inputs allow the islac device to place several key islic performance parameters under software control. the main functions that can be observed and/or controlled through the islac backplane interface are: ? dc-feed characteristics ? ground-key detection ? off-hook detection ? metering signal ? longitudinal operating point ? subscriber line voltage and currents ? ring-trip detection ? abrupt and smooth battery reversal ? subscriber line matching ? ringing generation ? sophisticated line and circuit tests to accomplish these functions, the islic device collects the following information and feeds it, in analog form, to the islac device: ? the metallic (imt) and longitudinal (ilg) loop currents ? the ac (vtx) and dc (vsab) loop voltages ? the outputs supplied by the islac device to the islic device are then: ? a voltage (vhli) that provides control for the following high-level islic device outputs: ? dc loop current ? internal ringing signal ? 12 or 16 khz metering signal
intelligent access voice? solutions 4 am79q2241/42/43 data sheet ? a low-level voltage proportional to the voice signal (vouti) ? a voltage that controls longitudinal offset for test purposes (vlbi) the islac device performs the codec and filter functions associated with the four-wire section of the subscriber line circuitry in a digital switch. these functions involve converting an analog voice signal into digital pcm samples and converting digital pcm samples back into an analog signal. during conversion, digital filters are used to band-limit the voice signals. the user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment of the two-wire termination impedance and provide frequency attenuation adjustment (equalization) of the receive and transmit paths. adaptive transhybrid balancing is also included. all programmable digital filter coefficients can be calculated using winslac software. the pcm codes can be either 16-bit linear two?s-complement or 8-bit companded a-law or -law. besides the codec functions, the intelligent access voice chipset provides all the sensing, feedback, and clocking necessary to completely control islic device functions with programmable parameters. system-level parameters under programmable control include active loop current limits, feed resistance, and feed mode voltages. the islac device supplies complete mode control to the islic device using the control bus and (p1-p3) tri-level load signal (ldi). the intelligent access voice chipset provides extensive loop supervision capability including off-hook, ring-trip and ground-ke y detection. detection thresholds for these functions are programmable. a programmable debounce timer is available that eliminates false detection due to contact bounce. for subscriber line diagnostics, ac and dc line conditions can be monitored using built in test tools. measured parameters can be compared to programmed threshold levels to set a pass/fail bit. the user can choose to send the actual pcm measurement data directly to a higher level processor by way of the voice channel. both longitudinal and metallic resistance and capacitanc e can be measured, which allows leakage resistance, line capacitance, and telephones to be identified. quad islac? device internal block diagram ch 1 converter block vhl 1 clock and reference circuits pcm and gci interface and time slot assigner digital signal processor ch 2 (as ch 1) ch 3 (as ch 1) ch 4 (as ch 1) vlb 1 vout 1 vilg 1 vimt 1 vsab 1 vini 1 xsb 1 gci control logic and microprocessor interface islic control logic common external sense inputs mclk iref vref fs/dcl pclk/fs dxa/du dra/dd tsca/g dxb drb tscb dclk/s0 dio/s1 int cs/rst i/o 1 ld 1 i/o 4 i/o 3 i/o 2 ld 2 ld 3 ld 4 p 1 p 2 p 3 xsc shb slb spb
intelligent access voice? solutions am79q2241/42/43 data sheet 5 features of the intelligent access? chipset ? performs all battery feed, ringing, signaling, hybrid and test (borscht) functions ? two chip solution supports high density, multi-channel architecture ? single hardware design meets multiple country require- ments through software programming of: ? ringing waveform and frequency ? dc loop-feed characteristics and current-limit ? loop-supervision detection thresholds ? off-hook debounce circuit ? ground-key and ring-trip filters ? off-hook detect de-bounce interval ? two-wire ac impedance ? transhybrid balance ? transmit and receive gains ? equalization ? digital i/o pins ? a-law/-law and linear selection ? supports internal and external battery-backed ringing ? self-contained ringing generation and control ? supports external ringing generator and ring relay ? ring relay operation synchronized to zero crossings of ringing voltage and current ? integrated ring-trip filter and software enabled man- ual or automatic ring-trip mode ? supports metering generation with envelope shaping ? smooth or abrupt polarity reversal ? adaptive transhybrid balance ? continuous or adapt and freeze ? supports both loop-start and ground-start signaling ? exceeds lssgr and ccitt central office requirements ? selectable pcm or gci interface ? supports most available master clock frequencies from 512 khz to 8.192 mhz ? on-hook transmission ? power/service denial mode ? line-feed characteristics independent of battery voltage ? only 5 v, 3.3 v and battery supplies needed ? low idle-power per line ? linear power-feed with intelligent power-management feature ? compatible with inexpensive protection networks; accommodates low-tolerance fuse resistors while main- taining longitudinal balance ? monitors two-wire interface voltages and currents for subscriber line diagnostics ? built-in voice-path test modes ? power-cross, fault, and foreign voltage detection ? integrated line-test features ? leakage ? line and ringer capacitance ? loop resistance ? integrated self-test features ? echo gain, distortion, and noise ? small physical size ? up to three relay drivers per islic? device ? configurable as test load switches
intelligent access voice? solutions 6 am79q2241/42/43 data sheet connection diagrams figure 1. 68-pin plcc connection diagram figure 2. 64-pin tqfp connection diagram am79q2242 quad islac 68-pin plcc 98765432 16867 xsc vout 4 vin 4 vhl 4 vsab 4 vilg 4 vimt 4 vlb 4 xsb 4 xsb 3 vlb 3 66 65 64 63 62 61 vimt 3 vilg 3 vsab 3 vhl 3 vin 3 vout 3 60 59 58 57 56 55 54 53 52 51 50 vcca 3 iref vref xsb 1 agnd 2 vlb 1 vimt 1 vilg 1 vsab 1 vcca1 vhl 1 49 48 47 46 45 vin 1 vout 1 dgnd 2 i/o 3 i/o 1 ld 3 44 10 vcca 4 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 shb slb xsb 2 agnd 1 vlb 2 vimt 2 vilg 2 vsab 2 vcca 2 vhl 2 vin 2 vout 2 spb dgnd 1 i/o 4 i/o 2 27 ld2 ld4 p 3 p 2 p 1 mclk pclk/fs fs/dcl dra/dd dxa/du tsca/g vccd dio/s1 dclk/s0 ld 1 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 cs/rst int am79q2241 quad islac 64-pin tqfp 64 63 62 61 60 59 58 57 56 55 vout 4 vin 4 vhl 4 vsab 4 vilg 4 vimt 4 vlb 4 xsb 4 xsb 3 vlb 3 54 53 52 51 50 49 vimt 3 vilg 3 vsab 3 vhl 3 vin 3 vout 3 17 ld 2 ld 4 p 3 p 2 p 1 mclk pclk/fs fs/dcl dra/dd dxa/du tsca/g vccd dio/s1 dclk/s0 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 vcca 3 iref vref xsb1 agnd 2 vlb 1 vimt 1 vilg 1 vsab 1 vcca 1 vhl 1 37 36 35 34 33 vin 1 vout 1 dgnd 2 ld 1 ld 3 1 xsc 2 vcca 4 shb slb xsb 2 agnd 1 vlb 2 vimt 2 vilg 2 vsab 2 vcca 2 vhl 2 vin 2 vout 2 spb dgnd 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 int cs/rst
intelligent access voice? solutions am79q2241/42/43 data sheet 7 figure 3. 80-pin tqfp connection diagram am79q2243 quad islac 80-pin tqfp iref vref xsb 1 agnd 2 vlb 1 vimt 1 vilg 1 vsab 1 vcca 1 vhl 1 vin 1 vout 1 dgnd 2 i/o 1 i/o 3 n/c vcca 3 drb ld 3 ld 1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 ld 2 ld 4 p 3 p 2 p 1 int mclk pclk/fs fs/dcl 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 dra/dd dxa/du tsca/g vccd dio/s1 dclk/s0 cs/rst tscb n/c n/c n/c 37 38 39 40 80 vout 4 vin 4 vhl 4 vsab 4 vilg 4 vimt 4 vlb 4 xsb 4 xsb 3 vlb 3 vimt 3 vilg 3 vsab 3 vhl 3 vin 3 vout 3 xsc n/c n/c n/c 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vcca 4 shb slb xsb 2 agnd 1 vlb 2 vimt 2 vilg 2 vsab 2 vcca 2 vhl 2 vin 2 vout 2 spb dgnd 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o 4 i/o 2 dxb n/c n/c
intelligent access voice? solutions 8 am79q2241/42/43 data sheet pin descriptions pin pin name i/o description agnd 1 , agnd 2 analog ground analog circuitry ground returns dclk/s0 data clock/gci address strap 0 i provides data control for mpi interface control. for gci operation, this pin is device address bit 0.5 v tolerant. dgnd 1 , dgnd 2 digital ground digital ground returns dio/s1 data i/o/gci address strap 1 i/o for pcm backplane operation, control data is serially written into and read out of the islac device via the dio pin with the msb first. the data clock (dclk) determines the data rate. dio is high impedance except when data is being transmitted from the islac device under control of cs /rst . for gci operation, this pin is device address bit 1. 5 v tolerant. dra/dd, drb rx path a backplane data/ gci data downstream, receive path b backplane data i for the pcm highway, the receive pcm data is input serially through the dra or drb ports. the data input is received every 125 s and is shifted in, msb first, in 8-bit pcm or 16-bit linear bursts at the pclk rate. the receive port can receive information for direct control of the islic device. this mode is selected in device configuration register 2 (rtsen=1, rtsmd=1). when selected, this data is received in an independently programmable timeslot from the pcm data. for the gci mode, downstream receive and control data is accepted on this pin. the drb pin is available only on the 80-pin tqfp package. 5 v tolerant. dxa/du, dxb tx path a backplane data/ gci data upstream, tx path b backplane data o for the pcm highway, the transmit pcm data is transmitted serially through the dxa or dxb ports. the transmission data output is available every 125 s and is shifted out, msb first, in 8-bit pcm or 16-bit linear bursts at the pclk rate. dxa and dxb are high impedance between bursts and while the device is in the inactive mode. can also select a mode (rtsen= 1, rtsmd=1 or 0 in device configuration register 2) that transmits the signaling register msb contents first, in an independently programmable timeslot from the pcm data. this data is transmitted in all modes except disconnect. for the gci mode, upstream transmit and signaling data is transferred on this pin. the dxb pin is available only on the 80-pin tqfp package. 5 v tolerant. fs/dcl frame sync/gci downstream clock i for pcm operation, pin is frame sync. pcm operation is selected by the presence of an 8 khz frame sync signal on this pin in conjunction with the pclk on the pclk/fs pin (see below). this 8 khz pulse identifies the beginning of a frame. the islac device references individual timeslots with respect to this input, which must be synchronized to pclk. gci operation is selected by the presence of the downstream clock dcl, on this pin in conjunction with the presence of a fs on the pclk/fs pin. in gci mode, the data rate is 2 mhz and dcl must be either 2 or 4 mhz. 5 v tolerant. int interrupt o for pcm operation, when a subscriber line requires service, this pin goes to a logic 0 to interrupt a higher level processor. several registers work together to control operation of the interrupt: signaling and global interrupt registers with their associated mask registers, and the interrupt register. see the description at channel configuration register 6 (mask) for operation. logic drive is selectable between open drain and ttl-compatible outputs. i/o 1 ?i/o 4 control ports i/o general purpose, ttl-compatible, logic input/output connection for each of 4 channels. these control lines are ttl-compatible and each can be programmed as an input or output in the global i/o direction register. when programmed as outputs, they can control an external logic device. when programmed as inputs, they can monitor external, ttl-compatible logic circuits. data for these pins can be written or read individually (from the channel specific i/o register) or as a group (from the global i/o data register). not available on the 64-pin package. iref current reference i external resistor (rref) connected between this pin and analog ground generates an accurate, on-chip reference current for the a/d's and d/a's on the islac chip. ld 1 ?ld 4 register load o the ld pins output 3-level voltages. when ld n is a logic 0 ( < 0.4 v), the destination of the code on p 1 ?p 3 is the relay control latches in the islic control register. when ld n is a logic 1 ( > v cc ? 0.4 v), the destination of p 1 ?p 3 is the mode control latches. ld n is driven to vref when the contents of the islic control register must not change.
intelligent access voice? solutions am79q2241/42/43 data sheet 9 mclk master clock i for pcm backplane operation, the dsp master clock connects here. a signal is required only for pcm backplane operation when pclk is not used as the master clock. mclk can be a wide variety of frequencies. upon initialization the mclk input is disabled, and relevant circuitry is driven by a connection to pclk. 5 v tolerant. pclk/fs pcm clock/ frame sync i for pcm operation, this is pcm clock. pcm operation is selected by the presence of a pclk signal on this pin in conjunction with the fs on the fs/dcl pin (see below). for pcm backplane operation, connect a data clock, which determines the rate at which pcm data is serially shifted into or out of the pcm ports. pclk can be any multiple of the fs frequency. the minimum clock frequency for linear/ companded data plus signaling data is 256 khz. for gci operation, this pin is frame sync. the fs signal is an 8 khz pulse that identifies the beginning of a frame. the islac device references individual timeslots with respect to this input, which must be synchronized to dcl. 5 v tolerant. p 1 ?p 3 islic control o control the operating modes of the four islic devices connected to the quad islac device. cs /rst chip select/ reset i for pcm backplane operation, a logic low on this pin for 16 or more dclk cycles resets the sequential logic in the islac device into a known mode. a logic low placed on this pin for less than 15 dclk cycles is a chip select and enables serial data transmission into or out of the dio port. for gci operation, a logic low on this pin for 1 ms or longer resets the sequential logic into a known mode. see table 2-4 in the technical reference for details. 5 v tolerant. shb, slb, spb battery sense i resistors that sense the high, low and positive battery voltages connect here. if only one negative battery is used, connect both resistors at the supply. if the positive battery is not used, leave the pin unconnected. these pins are current inputs whose voltage is held at vref. tsca /g timeslot control a/gci mode o (pcm) i (gci) for pcm backplane operation, tsca or tscb is active low when pcm data is output on the dxa or dxb pins. the outputs are open-drain and are normally inactive (high impedance). pull-up loads should be connected to vccd. tscb is only available on the 80 pin tqfp package. when gci mode is selected, one of two gci modes may be selected by connecting tsca /g to dgnd or vccd. tscb time slot control b o vsab 1 ? vsab 4 loop voltage sense i connect to the vsab pins of four islic devices. vcca 1 ? vcca 4 power supply +3.3 vdc supplies to the analog sections in each of the four channels. vccd power supply +3.3 vdc supply to all digital sections. vref analog reference o this pin provides a 1.4 v, single-ended reference to the four islic devices to which the islac device is connected. vhl 1 ? vhl 4 high level d/a o high-level loop control voltages on these pins are used to control dc-feed, internal ringing, metering and polarity reversal for each islic device. vin 1 ? vin 4 tx analog i analog transmit signals (vtx) from each islic device connect to these pins. the islac device converts these signals to digital words and processes them. after processing, they are multiplexed into serial time slots and sent out of the dxa/du pin. vlb 1 ? vlb 4 longitudinal reference o normally connected to vcca internally. they supply longitudinal reference voltages to the islic devices during certain test procedures. these outputs are connected internally to vcca during islic active, standby, ringing, and disconnect modes. during test modes, it can be connected to the receive d/a. pin options package type 80 pin 68 pin 64 pin drb xx dxb xx tscb xx i/o 1 ?i/o 4 ? x pin pin name i/o description
intelligent access voice? solutions 10 am79q2241/42/43 data sheet electrical characteristics absolute maximum ratings stresses greater than those listed under absolute maximum ratings can cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods can affect device reliability operating ranges operating ranges define those limits between which device functionality is guaranteed. functionality of the device from 0 to 70 o c is guaranteed by production testing. performance from ?40 to 85oc is guaranteed by characterization and periodic sampling of production units. environmental ranges electrical ranges specifications the performance targets defined in this section are for the entire linecard comprised of both chips in the intelligent access v oice chipsets unless otherwise noted. specifications for the individual chips in the set will be published separately (see note 1). t a = 0 to 70o c unless otherwise noted. intelligent access voice chipsets system target specifications storage temperature ?60o c t a +125o c ambient temperature, under bias ?40o c t a +85o c ambient relative humidity (non condensing) 5 to 100% v cca with respect to dgnd ?0.4 to + 3.6 v v ccd with respect to dgnd ?0.4 to + 3.6 v v in with respect to dgnd ?0.4 to vcca + 0.4 v 5 v tolerant pins ?0.4 to vcc + 2.25 or 5.25 v, whichever is less agnd dgnd 0.4 v latch up immunity (any pin) 100 ma any other pin with respect to dgnd ?0.4 v to v cc ambient temperature ?40 to +85o c ambient relative humidity 15 to 85% analog supply v cca +3.3 v 5% digital supply v ccd +3.3 v 5% dgnd 0 v agnd dgnd 50 mv item condition min typ max unit note peak ringing voltage active ringing mode, rload =1500 ? , vbh = 80 v 70 v output impedance during internal ringing active ringing mode, quad islac generating internal ringing 200 ? sinusoidal ringing thd active ringing mode, rload =1500 ? , vbh = 80v, islac generating internal sinusoidal ringing 2% psrr (vbh, vbl) loop open, in anti-sat db 1, 2 f = 50 hz 2 f = 200 to 3400 hz 12
intelligent access voice? solutions am79q2241/42/43 data sheet 11 note: 1. not tested or partially-tested in production. 2. these numbers are only valid when an islic device operates with an islac device, because the islac generates the anti-sat fee d characteristic. when the intelligent access voice chipsets operate in the normal feed region, the performance is dominated by t he islic device. see appropriate islic data sheet for specific psrr. dc specifications no. item condition min typ max unit note 1 input low voltage, i/o 1 ?i/o 4 ?0.05 1.36 v v all other digital inputs ?0.50 0.80 v 2 input high voltage, i/o 1 ?i/o 4 2.36 vcc+0.4 all other digital inputs 2.0 5.25 4 input leakage current, i/o 1 ?i/o 4 0 to v cc ?10 +10 a all other digital inputs 0 to 5.25 v ?120 +180 5 input hysteresis (pclk/fs, fs/dcl, mclk, dio, dra, drb) .15 .225 .3 v 2 i/o1?i/o4 .16 .25 .34 6 ternary output voltages, ld 1 ?ld 4 high voltage iout = 1 ma vcc?.4 ? low voltage iout = 2 ma ? 0.4 medium voltage 10 a vref 7 output low voltage (dxa/du, dio, i/o 1 ?i/o 4 , int , tsca , tscb , dxb, p 1 -p 3 ) iol = 1 ma 0.4 v 8 output low voltage (i/o 1 ?i/o 4 , int , tsca , tscb ) iol = 10 ma 1.0 9 output high voltage (all digital outputs except int in open drain mode and tsca, tscb ) ioh = 400 a vcc?0.4 10 input leakage current (vin 1 ?vin 4 , vsab 1 ?vsab 4 , vilg 1 ?vilg 4 , vimt 1 ?vimt 4 ) ?1 0.2 1 a 12 input voltage (vin 1 ?vin 4 ) v -law 3.205 dbm0 vref vref a-law 3.14 dbm0 to insertion loss in adc ?1.02 +1.02 13 input voltage (vsab 1 ?vsab 4 or vimt 1 ?vimt 4 or vilg 1 ?vilg 4 ) |vov?vref| where vov is input overload voltage 0.99 1.02 1.05 14 offset voltage allowed on vin 1 ?vin 4 ?50 +50 mv 4 15 vout 1 ?vout 4 offset voltage disn off ?40 +40 disn on ?80 +80 16 vhl output offset voltage tbd 17 output voltage, vref load current = 0 to 10 ma 1.4 v source or sink 18 capacitance load on vref or vout 1 ?vout 4 200 pf 2 19 output drive current, vout 1 ?vout 4 or vlb 1 ?vlb 4 source or sink ?1 +1 ma 2 20 output leakage current vout 1 ?vout 4 or vlb 1 ?vlb 4 500 200 500 na
intelligent access voice? solutions 12 am79q2241/42/43 data sheet transmission and signaling specifications 21 maximum output voltage on vout |vout?vref| with peak digital input 0.99 1.02 1.05 v 8 22 vlb 1 ?vlb 4 operating voltage source current < 250a or vref vref sink current < 25 a. ?1.02 +1.02 23 maximum output voltage on vhl (krfb) |vhl?vref| with peak digital input 0.97 1.00 1.03 8 24 gain from vsab to vhl vfd = 1 4.9 5 5.1 v/v 25 gain from vsab to vhl vfd = 0 ?.0255 ? .025 ?.0245 v/v 26 % error of vlb voltage (for vlb equation, see am79r2xx/ am79q224x technical reference ) ?5 +5 % 27 capacitance load on vlb 1 ?vlb 4 120 pf 2 28 capacitance load on xsb 1 ?xsb 4 , xsc 400 2 29 quad islac power dissipation one channel active (islic state register set to active); three channels inactive (islic state register set to standby) 183 235 mw all channels active (islic state register set to active) 264 340 all channels inactive (islic state register set to standby) 143 188 table 1. 0 dbm0 voltage definitions with unity gain in x, r, gx, gr, ax, and ar signal at digital interface transmit receive unit a-law digital mw or equivalent (0 dbm0) 0.5026 0.5026 vrms -law digital mw or equivalent (0 dbm0) 0.4987 0.4987 5,800 peak linear coded sine wave 0.5026 0.5025 no. item condition min typ max unit note 1 insertion loss a-d input: 1014hz, ?10dbm0 ar = ax = gr = gx = 0 db, disn, r, x, b and z disabled ?0.25 0 +0.25 db 3, 8 d-a a-d + d-a temperature = 70 c ?0.15 0 +0.15 a-d ? d-a variation over temperature ?0.1 0 +0.1 2 level set error (error between setting and actual value) a-d ax + gx d-a ar + gr ?0.1 0.1 3 dr to dx gain in full digital loopback mode dr input: 1014 hz, ?10 dbm0 ar=ax=gr=gx=0 db, disn, r, x, b and z filters default ?0.3 +0.3 4 idle channel noise, psophometric weighted (a-law) a-d (pcm output) ?69 dbm0p 5 d-a (v out ) ?78 5 idle channel noise, c message weighted (-law) a-d (pcm output) +19 dbrnc0 d-a (v out +12 6 coder offset decision value, xn a-d, input signal = 0 v ?7 +7 bits 2 no. item condition min typ max unit note
intelligent access voice? solutions am79q2241/42/43 data sheet 13 1. not tested or partially tested in production. this parameter is guaranteed by characterization or correlation to other tests. 2. guaranteed by design. 3. overall 1.014 khz insertion loss error of the intelligent access voice chipset is guaranteed to be 0.34 db 4. these voltages are referred to vref. 5. when relative levels (dbm0) are used, the specification holds for any setting of (ax + gx) gain from 0 to 12 db or (ar + gr) from 0 to ?12 db. 6. group delay spec valid only when channels 1?4 occupy consecutive slots in the frame. programming channels in non-consecutive timeslots can add up to 1 frame delay in the group delay measurements. 7. the group delay specification is defined as the sum of the minimum values of the group delays for transmit and the receive pa ths when the b, x, r, and z filters are disabled with null coefficients. see figure 8 for group delay distortion. 8. requires that the calibration command (7ch) must be performed to achieve this performance. transmit and receive paths in this section, the transmit path is defined as the analog input to the islac device (vin n ) to the pcm voice output of the islac a-law/-law speech compressor. the receive path is defined as the pcm voice input to the islac speech expander to the analog output of the islac device (vout n ). all limits defined in this section are tested with b = 0, z = 0 and x = r = gr = 1. when ar is enabled, a nominal gain of ?6.02 db is added to the analog section of the receive path. when ax is enabled, a nominal gain of +6.02 db is added to the analog section of the transmit path. when relative levels (dbm0) are used in any of the following transmission characteristics, the specification holds for any sett ing of (ax + gx) gain from 0 to 12 db or (ar + gr) from 0 to ?12 db. these transmission characteristics are valid for 0 to 70 o c. 7 psrr (vcc) a-d input: 4.8 to 7.8 khz, 200 mv p-p 37 db 1 image frequency d-a measure 8000 hz-input frequency 8 disn gain accuracy gdisn = ?0.9375 to 0.9375 ?0.25 +0.25 db vin = 0 dbm0 9 end-to-end group delay 1014hz; ?10dbm0 525 s 2, 6, 7 b = z = 0; x = r = 1 10 crosstalk tx to rx 0 dbm0 300 hz to 3400 hz ?75 dbm0 2 same channel rx to tx 0 dbm0 300 hz to 3400 hz 11 crosstalk tx or rx to tx 0 dbm0 1014 hz ?76 dbm0 2 crosstalk tx or rx to rx 0 dbm0 1014 hz ?78 no. item condition min typ max unit note
intelligent access voice? solutions 14 am79q2241/42/43 data sheet attenuation distortion the attenuation of the signal in either path is nominally independent of the frequency. the deviations from nominal attenuation will stay within the limits shown in figure 4 and figure 5. the reference frequency is 1014 hz and the signal level is ?10 dbm0 . the minimum transmit attenuation at 60 hz is 24 db. figure 4. transmit path attenuation vs. frequency figure 5. receive path attenuation vs. frequency 3000 3400 acceptable region 0.65 600 300 200 3200 0.80 0.2 frequency (hz) 0 2 0.6 0 -0.125 0.125 attenuation (db) 1 3000 3400 2 0.6 acceptable region 0.65 600 300 200 0 3200 0.80 0.2 attenuation (db) 1 frequency (hz) 0 -0.125 0.125
intelligent access voice? solutions am79q2241/42/43 data sheet 15 group delay distortion for either transmission path, the group delay distortion is within the limits shown in figure 6. the minimum value of the group delay is taken as the reference. the signal level is ?10 dbm0. figure 6. group delay distortion single frequency distortion the output signal level, at any single frequency in the range of 300 to 3400 hz, other than that due to an applied 0 dbm0 sine wave signal with frequency f in the same frequency range, is less than ?46 dbm0. with f swept between 0 to 300 hz and 3.4 to 12 khz, any generated output signals other than f are less than ?28 dbm0. this specification is valid for either transmission p ath. intermodulation distortion tbd 0 500 600 1000 2600 2800 90 150 420 delay (s) acceptable region frequency (hz)
intelligent access voice? solutions 16 am79q2241/42/43 data sheet gain linearity the gain deviation relative to the gain at ?10 dbm0 is within the limits shown in figure 7 (a-law) and figure 8 (-law) for eit her transmission path when the input is a sine wave signal of 1014 hz. figure 7. a-law gain linearity with tone input (both paths) figure 8. -law gain linearity with tone input (both paths) 0.55 0.25 0 -0.25 -0.55 -1.5 -55 -50 -40 -10 1.5 gain (db) 0 acceptable region input level (dbm0) +3 0.45 0.25 0 -0.25 -0.45 -1.4 -55 -50 -37 -10 1.4 gain (db) 0 acceptable region +3 input level (dbm0)
intelligent access voice? solutions am79q2241/42/43 data sheet 17 total distortion including quantizing distortion the signal to total distortion ratio will exceed the limits shown in figure 9 for either path when the input signal is a sine w ave signal of frequency 1014 hz. figure 9. total distortion with tone input, both paths overload compression figure 10 shows the acceptable region of operation for input signal levels above the reference input power (0 dbm0). the conditions for this figure are: (1) 1 db < gx +12 db; (2) ?12 db gr < ?1 db; (3) digital voice output connected to digital voice input; and (4) measurement analog to analog. figure 10. a/a overload compression input level (dbm0) signal-to-total distortion (db) acceptable region 0 -30 -40 -45 a a-law -law a 35.5db 35.5db b 35.5db 35.5db c 30db 31db d 25db 27db b c d fundamental output power (dbm0) fundamental input power (dbm0) 1 2 3 4 5 6 7 8 9 123456 789 2.6 region acceptable
intelligent access voice? solutions 18 am79q2241/42/43 data sheet discrimination against out-of-band input signals when an out-of-band sine wave signal with frequency and level a is applied to the analog input, there may be frequency components below 4 khz at the digital output which are caused by the out-of-band signal. these components are at least the specified db level below the level of a signal at the same output originating from a 1014 hz sine wave signal with a level of a dbm0 also applied to the analog input. the minimum specifications are shown in the following table figure 11. discrimination against out-of-band signals note: the attenuation of the waveform below amplitude a between 3400 hz and 4600 hz is given by the formula: spurious out-of-band signals at the analog output with pcm code words representing a sine wave signal in the range of 300 hz to 3400 hz at a level of 0 dbm0 applied to the digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below. with code words representing any sine wave signal in the range 3.4 khz to 4.0 khz at a level of 0 dbm0 applied to the digital input, the level of the signals at the analog output are below the limits in figure 12. the amplitude of the spurious out-of-ba nd signals between 3400 hz and 4600 hz is given by the formula: table 2. minimum specifications for out-of-band input signals frequency of out-of-band signal amplitude of out-of-band signal level below a 16.6 hz < f < 45 hz ?25 dbm0 < a 0 dbm0 18 db 45 hz < f < 65 hz ?25 dbm0 < a 0 dbm0 25 db 65 hz < f < 100 hz ?25 dbm0 < a 0 dbm0 10 db 3400 hz < f < 4600 hz ?25 dbm0 < a 0 dbm0 see figure 11 4600 hz < f < 100 khz ?25 dbm0 < a 0 dbm0 32 db table 3. limits for spurious out-of-band signals frequency level 4.6 khz to 40 khz ?32 dbm0 40 khz to 240 khz ?46 dbm0 240 khz to 1 mhz ?36 dbm0 0 -10 -20 -30 -40 level (db) -50 3.4 4.0 4.6 frequency (khz) -28 dbm -32 db, -25 dbm0 < input , 0 dbm0 attenuation (db) 14 14 4000 f ? () 1200 ----------------------------- sin ? = a14 ? 14 f4000 ? () 1200 ----------------------------- dbm0 sin ? =
intelligent access voice? solutions am79q2241/42/43 data sheet 19 figure 12. spurious out-of-band signals switching characteristics pcm switching characteristics figure 13. pcm switching characteristics vcc = 3.3 v + 5%, agnd = dgnd = 0 v. 0 -10 -20 -30 -40 level (db) -50 3.4 4.0 4.6 frequency (khz) -32 db -28 dbm 2.0 v 0.8 v test points 2.4 v 0.4 v 2.0 v 0.8 v
intelligent access voice? solutions 20 am79q2241/42/43 data sheet microprocessor interface min and max values are valid for all digital outputs with a 100 pf load, except dio,dxa, int , tsca, tscb and dxb which are valid with 150 pf loads. pcm interface no. symbol parameter min typ max unit note 1 t dcy data clock period 122 ns 2 t dch data clock high pulse width 48 1 3 t dcl data clock low pulse width 48 1 4 t dcr rise time of clock 15 5 t dcf fall time of clock 15 6 t icss chip select setup time, input mode 30 t dcy ?10 7 t icsh chip select hold time, input mode 0 t dch ?20 8 t icsl chip select pulse width, input mode 7.5t dcy 7 9 t icso chip select off time, input mode 1,6 10 t ids input data setup time 25 5 11 t idh input data hold time 30 13 t ocss chip select setup time, output mode 30 t dcy ?10 ns 14 t ocsh chip select hold time, output mode t dch ?20 15 t ocsl chip select pulse width, output mode 8t dcy 16 t ocso chip select off time, output mode 2000 1,6 17 t odd output data turn on delay 50 18 t odh output data hold time 3 19 t odof output data turn off delay 50 20 t odc output data valid 0 50 no. symbol parameter min. typ max unit note 22 t pcy pcm clock period 0.122 7.8125 s 2 23 t pch pcm clock high pulse width 48 ns 24 t pcl pcm clock low pulse width 48 25 t pcf fall time of clock 15 26 t pcr rise time of clock 15 27 t fss fs setup time 30 t pcy ?30 28 t fsh fs hold time 50 29 t tsd delay to tscx valid 5 80 3 30 t tso delay to tscx off 5 4 31 t dxd pcm data output delay 5 70 32 t dxh pcm data output hold time 5 70 33 t dxz pcm data output delay to high-z 10 70 4 34 t drs pcm data input setup time 25 35 t drh pcm data input hold time 5 36 t fst pcm or frame sync jitter time ?97 97
intelligent access voice? solutions am79q2241/42/43 data sheet 21 master clock : for a 2.048 mhz 100 ppm, 4.096 mhz 100 ppm, or 8.192 100 ppm operation: note: 1. dclk may be stopped in the high or low state indefinitely without loss of information. when cs makes a transition to the high state, the last byte received will be interpreted by the microprocessor interface logic. 2. the pcm clock (pclk) frequency must be an integer multiple of the frame sync (fs) frequency and synchronous to the mclk frequ ency. the actual pclk rate is dependent on the number of channels allocated within a frame. a pclk of 1.544 mhz can be used for stand ard us transmission systems. the minimum clock frequency is 128 khz. 3. tsca is delayed from fs by a typical value of n ? t pcy , where n is the value stored in the time/clock slot register. 4. t tso is defined as the delay time the output driver turns off after the pclk transaction. the actual delay time is dependent on the load circuitry. the maximum load capacitance on tscx is 150 pf and the minimum pull-up resistance is 360 ? . 5. the first data bit is enabled on the falling edge of cs or on the falling edge of dclk, whichever occurs last. 6. if the mpi is being accessed while the mclk (or pclk if combined with mclk) input is not active, a chip select off time of 20 s is required when accessing coefficient ram. 7. if chip select is held low for 16 or more dclk cycles, the part will reset. 8. mclk?s frequency can range from 128 khz to 8.192 mhz and can be set with: write/read device configuration register 1, and if necessary write/read master clock correction register. no. symbol parameter min typ max unit no 37 t mcy period 122 7812 ns 2,8 38 t mcr rise time of clock 15 39 t mcf fall time of clock 15 40 t mch mclk high pulse width 48 41 t mcl mclk low pulse width 48
intelligent access voice? solutions 22 am79q2241/42/43 data sheet pcm switching waveforms figure 14. master clock timing figure 15. microprocessor interface (input mode) 38 41 40 39 37 v ih v il data valid 1 5 v il dclk 9 4 cs data valid 11 dio 2 3 6 8 10 7 data valid v ih v il v ih
intelligent access voice? solutions am79q2241/42/43 data sheet 23 figure 16. microprocessor interface (output mode) figure 17. pcm highway timing for xe = 0 (transmit on negative pclk edge) 16 15 dclk cs d out three-state three-state 13 14 19 20 18 17 data valid data valid data valid v oh v ol v il v ih time slot zero, clock slot zero 33 30 first bit pclk fs dxa first bit second bit v ol v oh tsca v ih v il v ih v il see note 4 26 24 23 28 29 31 32 27 22 25 34 35 dra
intelligent access voice? solutions 24 am79q2241/42/43 data sheet figure 18. pcm highway timing for xe = 1 (transmit on positive pclk edge) gci timing specifications note: 1. the data clock (dcl) can be stopped in the high or low state without loss of information. 2. a temporary stoppage of dcl must not put the islac into a state in which it does not respond to a software reset command. 3. all frequency-dependent specifications are guaranteed for clock frequencies within 100 ppm from nominal. symbol signal parameter min typ max unit t r , t f dcl rise/fall time 60 ns t dcl dcl period, f dcl = 2048 khz f dcl = 4096 khz 478 239 498 249 t wh , t wl dcl pulse width 90 t r , t f fs rise/fall time 60 t sf fs setup time 70 t dcl ?50 t hf fs hold time 50 t wfh fs high pulse width 130 t ddc du delay from dcl edge 100 t ddf du delay from fs edge 150 t sd dd data setup twh+20 t hd dd data hold 50 t rst rst reset pulse width 1.1 ms pclk fs first bit second bit v ih v il v ih v il 26 24 23 27 22 25 28 34 35 dra 33 30 first bit dxa v ol v oh tsca see note 4 31 32 29 time slot zero, clock slot zero
intelligent access voice? solutions am79q2241/42/43 data sheet 25 gci waveforms detail a t r dcl fs dcl* * fs du dd bit 7 bit 6 dd, du ** timing diagram valid for f dcl = 2048 or 4096 khz t f t wh t dcl t wl t sf t hf t ddf t wfh t ddc t hd t sd
intelligent access voice? solutions 26 am79q2241/42/43 data sheet application circuits internal ringing linecard schematic r fai r fbi r sai r sbi a b dhi bath batl u1 am79r251 p 1 p 2 p 3 ld sa sb ad bd vbh vbl tmp tmn rsn vlb imt ilg vtx vref vsab gnd +5v vcc dli tms bgnd r2 rye r3 r1 hpa hpb c hpi c ssi r rxi r mti vref r lgi vref u2 islac vref vilg i vimt i vlb i vsabi vin i vout i back plane ld i p 1 p 2 p 3 dgnd vcca vccd shb slb bath batl iref agnd r shb r slb r ref cref 3.3v c adi c bdi rsvd rt i c s u3 bath u4 spb cbatli cbathi dt2 i *** r hlai vhl i r hlb i r hlc i r hldi vref c hldi c hlb i r test dt1 i d1 d2 rsvd vcc +3.3vdc r mgpi r mgli *css required for > 2.2 vms metering **connections shown for one channel ***dt2 i diode is optional; should be connected if there is a chance that this chip may be replaced by the le79r251 device. otherwise, it creates a short.
intelligent access voice? solutions am79q2241/42/43 data sheet 27 external ringing linecard schematic cbatli cbathi rsvd 2 r fai r fbi r sai r sbi r rxi a b dhi bath batl u1 am79r251 p 1 p 2 p 3 ld sa sb ad bd vbh vbl tmp tmn rsn vlb imt ilg vtx vref vsab gnd +5 v vcc r mgli r mgpi tms r mti vref r lgi bgnd r2h rye r3h r1 vref hpa hpb r srbi r src ring bus kr i kr i (a) c adi c bdi c hpi c ssi u2 islac vref vilg i vimt i vlb i vsab i vin i vout i back plane ld i p 1 p 2 p 3 dgnd agnd vcca vccd r shb r slb shb slb bath batl iref xsb i xsc vcc +3.3 vdc +5v kr i spb rsvd cref 3.3 v r ti dt2 i *** r hlai vhl i r hlbi r hlci r hldi vref c hldi c hlbi r ref u5 r test dt1 i r gfdli *css required for > 2.2 vms metering **connections shown for one channel ***dt2i diode is optional; should be connected if there is a chance that this chip may be replaced by the le79r251 device. (b) 18 c s bath 2 6 7 r testli dli
intelligent access voice? solutions 28 am79q2241/42/43 data sheet linecard parts list the following list defines the parts and part values required to meet target specification limits for channel i of the linecard (i = 1, 2, 3, 4).. note: 1. value can be adjusted to suit application. 2. can be less stringent for relaxed ring-trip requirements. 3. required for metering > 2.2 vrms, otherwise must be omitted. 4. dt2 i is optional - should be put if there is a chance that this chip may be replaced by am79r251. item type value tol. rating comments u1 am79r241 islic device u2 am79x22xx islac device u3, u4 b1100cc 100 v teccor battrax protector u5 tisp61089a transient voltage suppressor, power innovations d1, d2 diode 1 a 100 v dh i , dl i , dt1 i , dt2 i 4 diode 100 ma 100 v 50 ns r fai , r fbi resistor 50 ? 2% 2 w fusible ptc protection resistors r sai , r sbi resistor 200 k ? 2% 1/4 w sense resistors r ti resistor 80.6 k ? 1% 1/10 w r rxi resistor 100 k ? 1% 1/10 w r ref resistor 69.8 k ? 1% 1/10 w current reference r mgli , r mgpi resistor 1 k ? 5% 1 w thermal management resistors r shb , r slb resistor 750 k ? 1% 1/8 w r hlai resistor 40.2 k ? 1% 1/10 w r hlbi resistor 4.32 k ? 1% 1/10 w r hlci resistor 2.87 k ? 1% 1/10 w r hldi resistor 2.87 k ? 1% 1/10 w c hlbi capacitor 3.3 nf 10 % 10 v not polarized c hldi capacitor 0.82 mf 10 % 10 v ceramic r mti resistor 3.01 k ? 1% 1/8 w r lgi resistor 6.04 k ? 1% 1/8 w r test resistor 2 k ? 1% 1 w test board c adi , c bdi 1 capacitor 22 nf 10% 100 v ceramic, not voltage sensitive c bathi , c batli capacitor 100 nf 20% 100 v ceramic c hpi capacitor 22 nf 20% 100 v ceramic c si 1 capacitor 100 nf 20% 100 v protector speed up capacitor c ssi 3 capacitor 56 pf 5% 100 v ceramic components for external ringing r gfdi resistor 510 ? 2% 2 w 1.2 w typ r srbi , r src resistor 750 k ? 2% 1/4 w matched to within 0.2% for initial tolerance and 0 to 70 c ambient temperature range. 2 17 mw typ k ri relay 5 v coil dpdt
intelligent access voice? solutions am79q2241/42/43 data sheet 29 physical dimensions 68-pin plcc dwg rev. an; 8/00 pl 068
intelligent access voice? solutions 30 am79q2241/42/43 data sheet 64-pin thin quad flat pack (tqfp) dwg rev. as; 08/00 pqt 064
intelligent access voice? solutions am79q2241/42/43 data sheet 31 80-pin thin quad flat pack (tqfp) dwg rev. as; 08/00 pqt 080
intelligent access voice? solutions 32 am79q2241/42/43 data sheet revision summary revision a to revision b ? revision a was a condensed version of the datasheet while revision b contains the full version. revision b to revisionc ? page 14, linecard parts list, rows chlbi and chldi: switched the numbers in the ?values? column. revision c to revision d ? page 12, figure 5, dt1i was added and the last note was modified. ? page 14, linecard parts list, item u3, u4 type information was changed. revision d to revision e ? updated document to new format. ? in pin descriptions table, changed i/o status of tscb to "o" ? in dc specifications table, the following changes were made: ? changed information for "quad islac power dissipation". ? updated "min", "max", and "typ" values for input leakage current (vin1-4, vsab1-4, vilg1-4, vimt1-4, vsab1-4) ? updated "min", "max", and "typ" values for output leakage current (vout1-4 or vlb1-4) ? made the following changes to the transmission and signaling specifications table: ? reformatted table ? for insertion loss, changed one of the "a-d + d-a" items to "a-d ? d-a" ? for psrr, added "a-d" to item; added min value of 37 ? for image frequency, added "d-a" to item; added min value of 37 ? for disn gain accuracy, changed conditions to: gdisn = ? 0.9375 to 0.9375; vin = 0 dbm0 ? for crosstalk tx or rx to tx; tx or rx to rx, added 0dbm0 to conditions ? divided transmit and receive path attenuation vs. frequency graphic into two separate graphics ? in the "intermodulation distortion" section, changed text to "tbd" ? updated pcm switching characteristics graphic. ? in "master clock" section, added information for t mcy ; added note 8 ? updated external ringing linecard schematic. ? added a linecard parts list. ? updated all "physical dimensions" graphics. revision e to revision f ? in pin descriptions table, pins ld1-ld4, changed description for logic 0 to < 0.4 v; changed description for logic 1 to (v cc ? 0.4 v) ? in dc specifications table, item 6, removed "output current" row; inserted "medium voltage" row. ? subscripted channel numbers throughout document. revision f to g ? corrected physical dimensions for 64-pin tqfp.
intelligent access voice? solutions am79q2241/42/43 data sheet 33 the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descri ptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this pub lication. except as set forth in legerity's standard terms and conditions of sale, legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellect ual property right. legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 2001 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, and qislac?, islac?, and islic? are trademarks of legerity, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies.
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