hy512260 128kx16 , cmos dram with /2cas this family is a 2m bit dynamic ram organized 131,072 x 16-bit configuration with cmos drams . the circuit and process design allow this device to achieve high performance and low power dissipation. independent read and write of upper and lower byte is controlled by 2 separate cas inputs. optional features are access time(50, 60 or 70ns) and power onsumption (normal or low power with self refresh). hyundai ? s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability . description features ? fast page mode operation ? read-modify-write capability ? 2/cas inputs for upper and lower byte control ? ttl compatible inputs and outputs ? /cas-before-/ras, /ras-only, hidden and self refresh capability ? max. active power dissipation speed 50 power 605 mw ? fast access time and cycle time speed 50 60 trac 50 ns 60 ns tcac 15 ns 15 ns tpc 35 ns 40 ns ? refresh cycle part number hy512260 refresh 512 normal 8 ms sl-part 128 ms this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licences are implied rev.10 / jan.97 ordering information part name hy512260jc refresh 512 power package 40 pin soj hy512260ljc 512 l-part 40 pin soj 60 550 mw hyundai semiconductor ? jedec standard pinout ? 40-pin plastic soj (400mil) ? single power supply of 5v 10% ? early write or output enable controlled write 1 * sl : low power with self refresh 70 495 mw 70 70 ns 20 ns 45 ns hy512260sljc 512 sl-part 40 pin soj
hy512260 functional block diagram we lcas ucas oe data input buffer dq0~7 dq8~15 data output buffer dq0~7 dq8~15 cas clock generator cloumn predecoder (8) column controller refresh counter (9) cas clock generator sense amp i/o gate memory array 131,077 x 16 row decoder row predecoder (9) ras clock generator substrate bias generator v cc v ss address buffer ras dq0 ~ dq15 8 9 8 8 8 8 8 8 8 8 a0 a1 a2 2 a3 a4 a5 a6 a7 a8 16 128 kx16,fp dram rev.10 / jan.97
hy512260 pin configuration (marking side) pin description / ras / cas row address strobe column address strobe / we write enable / oe output enable a0~a8 address input dq0~dq15 data in/out vcc power (5v) vss ground pin name parameter 3 128 kx16 ,fp dram rev.10 / jan.97 40 pin plastic soj (400mil) v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 n.c n.c we ras n.c a0 a1 a2 a3 vcc 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 v ss dq15 dq14 ucas a8 a7 a6 a5 a4 vss dq13 dq12 v ss dq11 dq10 dq9 dq8 n.c lcas oe
hy512260 absolute maximum rating symbol t a parameter ambient temperature rating 0 to 70 unit c t stg storage temperature -55 to 150 c v in, v out voltage on any pin relative to v ss -1.0 to 7.0 v v cc voltage on v cc relative to v ss -1.0 to 7.0 v i os short circuit output current 50 ma p d power dissipation 1 w t solder soldering temperature ? time 260 ? 10 c ? sec note : operation at or above absolute maximum ratings can adversely affect device reliability symbol i li parameter input leakage current (any input) unit m a min -10 max 10 test condition v ss v in v cc + 1.0 all other pins not under test = v ss dc operating characteristic i lo output leakage current (any input) m a -10 10 v ss v out v cc /ras & /cas at v ih v ol output low voltage v - 0.4 i ol = 4.2 ma v oh output high voltage v 2.4 - i oh = -5.0 ma 4 recommended dc operating conditions symbol v cc parameter power supply voltage unit v max 5.5 typ 5.0 min 4.5 v ih input high voltage v v cc+ 1.0 - 2.4 v il input low voltage v 0.8 - -1.0 note : all voltages are referenced to v ss . ( t a = 0 c to 70 c ) 128 kx16 ,fp dram rev.10 / jan.97
hy512260 dc characteristics symbol i cc1 parameter operating current speed 50 60 70 unit ma ( t a = 0 c to 70 c , v cc = 5v 10% , v ss = 0v, unless otherwise noted.) note 110 100 90 test condition / ras, /cas cycling t rc = t rc (min.) max. i cc2 ttl standby current ma 2 / ras, /cas 3 v ih(min) other inputs 3 v ss i cc3 / ras-only refresh current 50 60 70 ma 110 100 90 / ras cycling,/cas = v ih t rc = t rc (min.) i cc4 fast page mode current 50 60 70 ma 80 70 60 / cas cycling, /ras = v il t pc = t pc (min.) i cc5 cmos standby current l -part ma m a 1 200 / ras = /cas 3 v cc - 0.2v i cc6 / cas-before-/ras refresh current 50 60 70 ma 100 100 90 / ras & /cas = 0.2v t rc = t rc (min.) i cc7 battery back-up current (sl-part) m a trc =125 s /cas = cbr cycling or 0.2v /oe & /we = v cc - 0.2v address = vcc -0.2v or 0.2v dq0~dq15 = vcc -0.2, 0.2v or open i cc8 self refresh current (sl-part) m a 400 / ras & /cas = 0.2v other pins are same as i cc7 1. i cc1 , i cc3 , i cc4 and i cc6 depend on output loading and cycle rates( t rc and t pc ). 2. specified values are obtained with output unloaded. 3. i cc is specified as an average current. in i cc1 , i cc3 , i cc6 , address can be changed only once while /ras=v il . in i cc4 , address can be changed maximum once while /cas=v ih within one fast page mode cycle time t pc . 4. only tras (max) = 1 s is applied to refresh of battery backup but tras (max) = 10 s is to applied to normal functional operation. 5. icc5(max.), icc7 and icc8 are applied to l -part only. 6. operating condition for 50ns part is vcc =5v ?? 5%, cout 30pf . 5 128 kx16 ,fp dram rev.10 / jan.97 tras 1 s 400
t rc random read or write cycle time 110 ns symbol parameter min max min max unit note 60 ns 70 ns ac characteristics ( t a = 0 c to 70 c , v cc = 5 v 10% , v ss = 0v, unless otherwise noted.) hy512260 read-modify-write cycle time 155 fast page mode cycle time 40 fast page mode read-modify-write cycle time 80 access time from /ras - access time from /cas - access time from column address - access time from /cas precharge - / cas to output low impedance transition time(rise and fall) / ras precharge time / ras pulse width / ras pulse width(fast page mode) / ras hold time / cas hold time / cas pulse width / ras to /cas delay time / ras to column address delay time / cas to /ras precharge time / cas precharge time row address set-up time row address hold time column address set-up time column address hold time column address to /ras lead time read command set-up time read command hold time referenced to /cas t rwc t pc t prwc t rac t cac t aa t cpa t clz t t t rp t ras t rasp t rsh t csh t cas t rcd t rad t crp t cp t asr t rah t asc t cah t ral t rcs t rch 0 3 40 60 60 15 60 15 20 15 5 10 0 10 0 15 30 0 0 - - - - 60 15 30 35 - 50 - 10 k 100 k - - 10 k 45 30 - - - - - - - - - 130 185 45 95 - - - - 0 3 50 70 70 20 70 20 20 15 5 10 0 10 0 15 35 0 0 - - - - 70 20 35 40 - 50 - 10 k 100 k - - 10 k 50 35 - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 4,9,10 4,9 4,10 4,15 4 3 9 10 14 6 128 kx16 ,fp dram rev.10 / jan.97 read command hold time referenced to /ras t rrh 0 - 0 - ns 6 write command hold time write command pulse width t wch t wp 10 10 - - 15 15 - - ns ns 50 ns 90 min max 130 35 75 - - - - 0 3 30 50 50 15 50 15 15 10 5 10 0 8 0 15 25 0 0 - - - - 50 15 25 30 - 50 - 10 k 100 k - - 10 k 35 25 - - - - - - - - - 0 - 10 10 - - write command hold time from /ras t wcr 45 - 55 - ns 40 - column address hold time from /cas t ar 50 - 55 - ns 40 - write command to /ras lead time t rwl 15 - 20 - ns 15 -
symbol parameter min max min max unit note 60 ns 70 ns ac characteristics continued hy512260 data-in set-up time data-in hold time refresh period(512 cycles) refresh period(sl-part) write command set-up time / cas to /we delay time / ras to /we delay time column address to /we delay time / cas set-up time(cbr cycle) / cas hold time(cbr cycle) / ras to /cas precharge time / cas precharge time(cbr counter test) / ras hold time referenced to /oe / oe access time / oe to data delay output buffer turn-off delay time from /oe / oe command hold time / we delay time from /cas precharge / ras hold time from /cas precharge / ras pulse width(self refresh) t ds t dh t ref t wcs t cwd t rwd t awd t csr t chr t rpc t cpt t roh t oea t oed t oez t oeh t cpwd t rhcp t rass 0 15 - - 0 40 85 55 5 10 5 20 0 - 15 0 15 55 35 100 - - 8 128 - - - - - - - - - 15 - 15 - - - - 0 15 - - 0 50 100 65 5 10 5 25 0 - 20 0 20 65 40 100 - - 8 128 - - - - - - - - - 20 - 20 - - - - ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 7 7 11 11 8 8 8 8 5 8 128 kx16 ,fp dram rev.10 / jan.97 t rps t chs 130 -50 - - 150 -50 - - ns ns / ras precharge time (self refresh) / cas hold time (self refresh) min max 0 15 - - 0 35 70 45 5 10 5 20 0 - 15 0 15 50 35 100 - - 8 128 - - - - - - - - - 15 - 15 - - - - 120 -50 - - 50 ns data-in hold time referenced to /ras t dhr 50 - 55 - ns 40 - t cwl write command to /cas lead time ns 15 - 20 - 15 -
hy512260 note 1. an initial pause of 200 m s is required after power-up followed by 8 /ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cbr refresh cycles instead of 8 /ras-only refresh cycles are required. 2. if /ras= vss during power-up,the hy512264 could begin an active cycle. this condition results in higher current than necessary current which is demanded from the power supply during power-up. it is recommended that /ras and /cas track with vcc during power-up or be held at a valid vih in other to minimize the power-up current. 3. vih(min.) and vil(max.) are reference levels for measuring timing of input signals. transition times are measured between vih(min.) and vil(max.),and are assumed to be 2ns for all inputs. 4. measured at v oh =2.0v and v ol =0.8v with a load equivalent to 2ttl loads and 30pf . 5. tcez(max.) and toez define the time at which the output achieves the open circuit conditions and is not referenced to output voltage levels. 6. either trcd or trrh must be satisfied for a read cycle. 7 these parameters are referenced to /lcas or /ucas leading edge in early write cycles and to /we leading edge in read-modify-write cycles 8. t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs(min.) , the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if t rwd 3 t rwd(min.) , t cwd 3 t cwd(min.) , t awd 3 t awd(min) , and t cpwd 3 t cpwd(min.) , the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. operation within the t rcd(max.) limit ensures that t rac(max.) can be met. t rcd(max.) is specified as a reference point only. if t rcd is greater than the specified t rcd(max.) limit, then access time is controlled by t cac . 10.operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11. t ref( max.)=128ms is aren;t to l-parts and sl-parts. 12.a burst of 512 cbr refresh cycles must be executed within 8ms (128ms for sl-part) after exiting self refresh. 13.when both /lcas and /ucas go low at the same time, all 16-bits data are written into the device. /lcas and /ucas must be transited simultaneously withen a same read or write cycle. 14.these parameters are determined by the earlier falling edge of /lcas and /ucas. 15.these parameters are determined by the later rising edge of /lcas or /ucas. 16.tcwl must be satisfied by both /lcas and /ucas for 16-bits access cycles. 17.tcp and tcpt are measured when both /lcas and /ucas are high state. 18.operating condition for 50ns part is vcc =5v ?? 5%, cout =30pf . 8 128 kx16 ,fp dram rev.10 / jan.97 capacitance symbol c in1 parameter input capacitance (a0~a8) max 5 unit pf c in2 input capacitance (/ras, /lcas,/ucas, /we, /oe) 7 pf c dq data input / output capacitance (dq0~dq15) 7 pf ( t a = 25 c, v cc = 5v 10%, v ss = 0v and f=1mhz, unless otherwise noted.) typ . - - -
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