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1 opa689 ? 1997 burr-brown corporation pds-1409d printed in u.s.a. january, 2000 opa689 wideband, high gain voltage limiting amplifier features l high linearity near limiting l fast recovery from overdrive: 2.4ns l limiting voltage accuracy: 15mv l C3db bandwidth (g = +6): 280mhz l stable for g 3 +4 l slew rate: 1600v/ m s l 5v and +5v supply operation l low gain version: opa688 opa689 opa689 applications l transimpedance with fast overdrive recovery l fast limiting adc input driver l low prop delay comparator l non-linear analog signal processing l difference amplifier l if limiting amplifier l am signal generation description the opa689 is a wideband, voltage feedback op amp that offers bipolar output voltage limiting, and is stable for gains 3 +4. two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. this new output limiting architecture holds the limiter offset error to 15mv. the op amp operates linearly to within 30mv of the limits. the combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within 100mv of the desired linear output range. a fast 2.4ns recovery from limiting ensures that overdrive signals will be transparent to the signal channel. implementing the limiting function at the output, as opposed to the input, gives the specified limiting accuracy for any gain, and allows the opa689 to be used in all standard op amp applications. non-linear analog signal processing circuits will benefit from the opa689s sharp transition from linear operation to output limiting. the quick recovery time supports high speed applications. the opa689 is available in an industry-standard pinout in pdip-8 and so-8 packages. for lower gain applica- tions requiring output limiting with fast recovery, con- sider the opa688. 2.5 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 ?.5 limited output response v in v o time (200ns/div) input and output voltage (v) g = +6 v h = 2.0v v l = ?.0v 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 detail of limited output voltage time (50ns/div) v o input and output voltage (v) international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 for most current data sheet and other product information, visit www.burr-brown.com sbos076
2 opa689 ac performance (see fig. 1) small signal bandwidth v o < 0.5vp-p g = +6 280 220 210 200 mhz min b g = +12 90 mhz typ c g = C6 220 mhz typ c gain bandwidth product (g 3 +20) v o < 0.5vp-p 720 490 460 430 mhz min b gain peaking v o < 0.5vp-p, g = +4 8 db typ c 0.1db gain flatness bandwidth v o < 0.5vp-p 110 mhz typ c large signal bandwidth v o = 2vp-p 290 185 175 170 mhz min b step response slew rate 2v step 1600 1300 1250 950 v/ m s min b rise/fall time 0.5v step 1.2 1.8 1.9 2.4 ns max b settling time: 0.05% 2v step 7 nstypc spurious free dynamic range f = 5mhz, v o = 2vp-p 61 57 53 48 db min b differential gain ntsc, pal, r l = 500 w 0.02 % typ c differential phase ntsc, pal, r l = 500 w 0.01 typ c input noise density voltage noise f 3 1mhz 4.6 5.3 6.0 6.1 nv/ ? hz max b current noise f 3 1mhz 2.0 2.5 2.9 3.6 pa/ ? hz max b dc performance (v cm = 0v) open-loop voltage gain (a ol )v o = 0.5v 56 50 48 47 db min a input offset voltage 1 5 6 7 mv max a average drift 14 14 m v/ c max b input bias current (3) +8 12 13 20 m a max a average drift C60 C90 na/ c max b input offset current 0.3 2 3 4 m a max a average drift 10 10 na/ c max b input common-mode rejection ratio input referred, v cm = 0.5v 60 53 52 50 db min a common-mode input range (4) 3.3 3.2 3.2 3.1 v min a input impedance differential-mode 0.4 || 1 m w || pf typ c common-mode 1 || 1 m w || pf typ c output v h = Cv l = 4.3v output voltage range r l 3 500 w 4.1 3.9 3.9 3.8 v min a current output, sourcing 105 90 85 80 ma min a sinking C85 C70 C65 C60 ma min a closed-loop output impedance g = +4, f < 100khz 0.8 w typ c power supply operating voltage, specified 5 vtypc maximum 6 6 6 v max a quiescent current, maximum 15.8 17 19 20 ma max a minimum 15.8 14 12.8 11 ma min a power supply rejection ratio +v s = 4.5v to 5.5v +psr (input referred) 65 58 57 55 db min a output voltage limiters default limit voltage limiter pins open 3.3 3.0 3.0 2.9 v min a minimum limiter separation (v h C v l ) 200 200 200 200 mv min b maximum limit voltage 4.3 4.3 4.3 v max b limiter input bias current magnitude (5) v o = 0 maximum 54 65 68 70 m a max a minimum 54 35 34 31 m a min a average drift 40 45 na/ c max b limiter input impedance 2 || 1 m w || pf typ c limiter feedthrough (6) f = 5mhz C60 db typ c dc performance in limit mode v in = 0.7v limiter offset voltage (v o C v h ) or (v o C v l ) 15 35 40 40 mv max a op amp input bias current shift (3) 3 m a typ c opa689u, p typ guaranteed (1) 0 c to C40 c to min/ test parameter conditions +25 c +25 c +70 c +85 c units max level (2) specifications v s = 5v g = +6, r l = 500 w , r f = 750 w, v h = Cv l = 2v, (figure 1 for ac performance only), unless otherwise noted.
3 opa689 output voltage limiters (cont) ac performance in limit mode limiter small signal bandwidth v in = 0.7v, v o < 0.02vp-p 450 mhz typ c limiter slew rate (7) 100 v/ m s typ c limited step response overshoot v in = 0 to 0.7v step 250 mv typ c recovery time v in = 0.7v to 0 step 2.4 2.8 3.0 3.2 ns max b linearity guardband (8) f = 5mhz, v o = 2vp-p 30 mv typ c thermal characteristics temperature range specification: p, u C40 to +85 c typ c thermal resistance p 8-pin dip 100 c/w typ c u 8-pin so-8 125 c/w typ c notes: (1) junction temperature = ambient temperature for low temperature limit and 25 c guaranteed specifications. junction temperature = ambient temperature + 23 c at high temperature limit guaranteed specifications. (2) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value for information only. (3) current is considered positive o ut of node. (4) cmir tested as < 3db degradation from minimum cmrr at specified limits. (5) i vh (v h bias current) is positive, and i vl (v l bias current) is negative, under these conditions. see note 3 and figures 1 and 7. (6) limiter feedthrough is the ratio of the output magnitude to the sinewave added to v h (or v l ) when v in = 0. (7) v h slew rate conditions are: v in = +0.7v, g = +6, v l = C2v, v h = step between 2v and 0v. v l slew rate conditions are similar. (8) linearity guardband is defined for an output sinusoid (f = 1mhz, v o = 2vpp) centered between the limiter levels (v h and v l ). it is the difference between the limiter level and the peak output voltage where sfdr decreases by 3db (see figure 8). opa689u, p typ guaranteed (1) 0 c to C40 c to min/ test parameter conditions +25 c +25 c +70 c +85 c units max level (2) specifications v s = 5v (cont.) g = +6, r l = 500 w , r f = 750 w, v h = Cv l = 2v, (figure 1 for ac performance only), unless otherwise noted. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems.
4 opa689 ac performance (see fig. 2) small signal bandwidth v o < 0.5vp-p g = +6 210 180 160 150 mhz min b g = +12 70 mhz typ c g = C6 180 mhz typ c gain bandwidth product (g 3 +20) v o < 0.5vp-p 440 330 310 300 mhz min b gain peaking v o < 0.5vp-p, g = +4 4 db typ b 0.1db gain flatness bandwidth v o < 0.5vp-p 35 mhz typ c large signal bandwidth v o = 2vp-p 175 150 140 125 mhz min b step response slew rate 2v step 1600 1300 1250 950 v/ m s min b rise/fall time 0.5v step 1.9 2.1 2.2 2.6 ns max b settling time: 0.05% 2v step 7 nstypc spurious free dynamic range f = 5mhz, v o = 2vp-p 59 55 51 46 db min b input noise voltage noise density f 3 1mhz 4.6 5.3 6.0 6.1 nv/ ? hz max b current noise density f 3 1mhz 2.0 2.5 2.9 3.6 pa/ ? hz max b dc performance open-loop voltage gain (a ol )v o = 0.5v 56 50 48 47 db min a input offset voltage 1 5 6 8 mv max a average drift 14 14 m v/ c max b input bias current (3) +8 12 13 20 m a max a average drift C60 C90 na/ c max b input offset current 0.3 2 3 4 m a max a average drift 10 10 na/ c max b input common-mode rejection ratio input referred, v cm 0.5v 58 51 50 48 db min a common-mode input range (4) v cm 0.8 v cm 0.7 v cm 0.7 v cm 0.6 v min a input impedance differential-mode 0.4 || 1 m w || pf typ c common-mode 1 || 1 m w || pf typ c output v h = v cm + 1.8v, v l = v cm C 1.8v output voltage range r l 3 500 w v cm 1.6 v cm 1.4 v cm 1.4 v cm 1.3 v min a current output, sourcing 70 60 55 50 ma min a sinking C60 C50 C45 C40 ma min a closed-loop output impedance g = +4, f < 100khz 0.8 w typ c power supply operating voltage, specified 5 v typ c maximum 12 12 12 v max a quiescent current, maximum 13 15 15 16 ma max a minimum 13 11 10 9 ma min a power supply rejection ratio v s = 4.5v to 5.5v +psr (input referred) 65 db typ c output voltage limiters default limiter voltage limiter pins open v cm 0.9 v cm 0.6 v cm 0.6 v cm 0.6 v min a minimum limiter separation (v h C v l ) 200 200 200 200 mv min b maximum limit voltage v cm 1.8 v cm 1.8 v cm 1.8 v max b limiter input bias current magnitude (5) v o = 2.5v maximum 35 65 75 85 m a max a minimum 35 0 00 m a min a average drift 30 50 na/ c max b limiter input impedance 2 || 1 m w || pf typ c limiter isolation (6) f = 5mhz C60 db typ c dc performance in limit mode v in = v cm 0.4v limiter voltage accuracy (v o C v h ) or (v o C v l ) 15 35 40 40 mv max a op amp bias current shift (3) 5 m a typ c ac performance in limit mode limiter small signal bandwidth v in = 0.4v, v o < 0.02vp-p 300 mhz typ c limiter slew rate (7) 20v/ m s typ c limited step response overshoot v in = v cm to v cm 0.4v step 55 mv typ c recovery time v in = v cm 0.4v to v cm step 15 nstypc linearity guardband (8) f = 5mhz, v o = 2vp-p 30 mv typ c opa689u, p typ guaranteed (1) 0 c to C40 c to min/ test parameter conditions +25 c +25 c +70 c +85 c units max level (2) specifications v s = +5v g = +6, r f = 750 w, r l = 500 w tied to v cm = 2.5v, v l = v cm C1.2v, v h = v cm +1.2v, (figure 2 for ac performance only), unless otherwise noted.
5 opa689 thermal characteristics temperature range specification: p, u C40 to +85 c typ c thermal resistance p 8-pin dip 100 c/w typ c u 8-pin so-8 125 c/w typ c notes: (1) junction temperature = ambient temperature for low temperature limit and 25 c guaranteed specifications. junction temperature = ambient temperature + 23 c at high temperature limit guaranteed specifications. (2) test levels: (a) 100% tested at 25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value for information only. (3) current is considered positive o ut of node. (4) cmir tested as < 3db degradation from minimum cmrr at specified limits. (5) i vh (v h bias current) is negative, and i vl (v l bias current) is positive, under these conditions. see note 3 and figures 2 and 7. (6) limiter feedthrough is the ratio of the output magnitude to the sinewave added to v h (or v l ) when v in = 0. (7) v h slew rate conditions are: v in = v cm +0.4v, g = +6, v l = v cm C1.2v, v h = step between v cm +1.2v and v cm . v l slew rate conditions are similar. (8) linearity guardband is defined for an output sinusoid (f = 5mhz, v o = v cm 1vp-p) centered between the limiter levels (v h and v l ). it is the difference between the limiter level and the peak output voltage where sfdr decreases by 3db (see figure 8). opa689u, p typ guaranteed (1) 0 c to C40 c to min/ test parameter conditions +25 c +25 c +70 c +85 c units max level (2) specifications v s = +5v (cont.) g = +6, r f = 750 w, r l = 500 w tied to v cm = 2.5v, v l = v cm C1.2v, v h = v cm +1.2v, (figure 2 for ac performance only), unless otherwise noted. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. supply voltage ................................................................................. 6.5v internal power dissipation ........................... see thermal characteristics input voltage range ............................................................................ v s differential input voltage ..................................................................... v s limiter voltage range ........................................................... (v s C 0.7v) storage temperature range: p, u ................................ C40 c to +125 c lead temperature (dip, soldering, 10s) ...................................... +300 c (so-8, soldering, 3s) ...................................... +260 c junction temperature .................................................................... +175 c absolute maximum ratings absolute maximum ratings top view dip-8, so-8 1 2 3 4 8 7 6 5 nc inverting input non-inverting input ? s v h +v s output v l package/ordering information package specified drawing temperature package ordering transport product package number range marking number (1) media opa689p dip-8 006 C40 c to +85 c opa689p opa689p rails opa689u so-8 surface mount 182 C40 c to +85 c opa689u opa689u rails """"" opa689u/2k5 tape and reel notes: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2k5 indicates 2500 d evices per reel). ordering 2500 pieces of opa689u/2k5 will get a single 2500-piece tape and reel.
6 opa689 typical performance curves v s = 5v g = +6, r l = 500 w , r f = 750 w, v h = Cv l = 2v, (figure 1 for ac performance only), unless otherwise noted. 9 6 3 0 ? ? ? ?2 ?5 ?8 ?1 non-inverting small-signal frequency response frequency (hz) normalized gain (db) 1m 10m 100m 1g v o = 0.5vp-p g = +12 g = +20 g = +4 g = +6 6 3 0 ? ? ? ?2 ?5 ?8 ?1 ?4 inverting small-signal frequency response frequency (hz) normalized gain (db) 1m 10m 100m 1g v o = 0.5vp-p g = ? g = ?2 g = ? small-signal pulse response time (5ns/div) output voltage (v) v o = 0.5vp-p 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 large-signal pulse response time (5ns/div) v o = 2vp-p output voltage (v) 2.5 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 ?.5 v h ?imited pulse response v o 2.5 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 ?.5 time (20ns/div) input and output voltages (v) v in v h = +2v g = +6 v l ?imited pulse response 2.5 2.0 1.5 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 ?.5 time (20ns/div) input and output voltages (v) v o v in v l = ?v g = +6
7 opa689 typical performance curves v s = 5v (cont.) g = +6, r l = 500 w , r f = 750 w, v h = Cv l = 2v, (figure 1 for ac performance only), unless otherwise noted. ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 2nd harmonic distortion vs output swing output swing (vp-p) 2nd harmonic distortion (dbc) 0.1 1.0 5.0 r l = 500 w f 1 = 20mhz f 1 = 10mhz f 1 = 1mhz f 1 = 5mhz f 1 = 2mhz ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 3rd harmonic distortion vs output swing output swing (vp-p) 3rd harmonic distortion (dbc) 0.1 1.0 5.0 r l = 500 w f 1 = 20mhz f 1 = 10mhz f 1 = 5mhz f 1 = 2mhz f 1 = 1mhz harmonic distortion vs frequency ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 2nd and 3rd harmonic distortion (dbc) hd2 hd3 v o = 2vp-p r l = 500 w frequency (hz) 1m 10m 20m ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 harmonic distortion vs load resistance load resistance ( w ) 2nd and 3rd harmonic distortion (dbc) 50 100 1000 v o = 2vp-p f 1 = 5mhz hd2 hd3 21.6 18.6 15.6 12.6 9.6 6.6 3.6 0.6 ?.4 ?.4 ?.4 large signal frequency response frequency (hz) 0.1 10m 100m 1g gain (db) g = +6 0.5vp-p 2vp-p harmonic distortion near limit voltages ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?limit voltage (v) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2nd and 3rd harmonic distortion (dbc) v o = 0v dc ?vp f 1 = 5mhz r l = 500 w hd2 hd3
8 opa689 typical performance curves v s = 5v (cont.) g = +6, r l = 500 w , r f = 750 w, v h = Cv l = 2v, (figure 1 for ac performance only), unless otherwise noted. 100 10 1 input noise density frequency (hz) 100 1k 10k 100k 1m 10m input voltage noise density (nv/ ? hz) input current noise density (pa/ ? hz) voltage noise 4.6nv/ ? hz current noise 2.0pa/ ? hz 60 50 40 30 20 10 0 ?0 ?0 open-loop frequency response frequency (hz) 10k 100k 1m 10m 100m 1g open-loop gain (db) 0 ?0 ?0 ?0 ?20 ?50 ?80 ?10 ?40 open-loop phase (deg) gain phase v o = 0.5vp-p 6 3 0 ? ? ? ?2 ?5 ?8 ?1 ?4 limiter small-signal frequency response frequency (hz) 1m 10m 100m 1g limiter gain (db) v o = 0.02vp-p 750 w 125 w 150 w v o 8 v h = 0.02vp-p + 2.0v dc 0.7v dc ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 limiter feedthrough frequency (hz) feedthrough (db) 1m 10m 50m 750 w 125 w 150 w v o 8 v h = 0.02vp-p + 2v dc 21.6 18.6 15.6 12.6 9.6 6.6 3.6 0.6 ?.4 ?.4 ?.4 frequency response vs capacitive load frequency (hz) 0.1 10m 100m 1g gain to capacitive load (db) v o = 0.5vp-p c l = 100pf c l = 0 c l = 1000pf c l = 10pf opa689 r s 125 w v in v o c l 1k w 1k w is optional 750 w 150 w 50 45 40 35 30 25 20 15 10 5 0 r s vs capacitive load capacitive load (pf) 1 10 100 1000 r s ( w )
9 opa689 typical performance curves v s = 5v (cont.) g = +6, r l = 500 w , r f = 750 w, v h = Cv l = 2v, (figure 1 for ac performance only), unless otherwise noted. 100 10 1 0.1 closed-loop output impedance frequency (hz) 100k 1g 1m 10m 100m output impedance ( w ) g = +4 v o = 0.5vp-p 20 18 16 14 12 10 supply and output currents vs temperature ambient temperature (?) ?0 ?5 0 25 50 75 100 supply current (ma) 200 180 160 140 120 100 output current (ma) output current, sourcing supply current | output current, sinking | 100 95 90 85 80 75 70 65 60 55 50 psr and cmr vs temperature ambient temperature (?) ?0 ?5 0 25 50 75 100 psr and cmr, input referred (db) psr psrr psr+ cmrr 5.0 4.5 4.0 3.5 3.0 voltage ranges vs temperature ambient temperature (?) ?0 ?5 0 25 50 75 100 ?voltage range (v) output voltage range v h = ? l = 4.3v common-mode input range 100 75 50 25 0 ?5 ?0 ?5 ?00 limiter input bias current vs bias voltage limiter headroom (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 limter input bias current ( a) maximum over temperature minimum over temperature limiter headroom = +v s ?v h current = i vh or ? vl = v l ?(? s )
10 opa689 typical performance curves v s = +5v g = +6, r f = 402 w , r l = 500 w tied to v cm = 2.5v , v l = v cm C1.2v , v h = v cm +1.2v, (figure 2 for ac performance only), unless otherwise noted. 9 6 3 0 ? ? ? ?2 ?5 ?8 ?1 non-inverting small-signal frequency response frequency (hz) normalized gain (db) 1m 10m 100m 1g v o = 0.5vp-p g = +12 g = +20 g = +4 g = +6 6 3 0 ? ? ? ?2 ?5 ?8 ?1 ?4 inverting small-signal frequency response frequency (hz) normalized gain (db) 1m 10m 100m 1g v o = 0.5vp-p g = ? g = ?2 g = ? 21.6 18.6 15.6 12.6 9.6 6.6 3.6 0.6 ?.4 ?.4 ?.4 large-signal frequency response frequency (hz) 0.1 10m 100m 1g gain (db) 0.5vp-p 2vp-p ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 harmonic distortion vs frequency frequency (hz) 1m 10m 20m 2nd and 3rd harmonic distortion (dbc) v o = 2vp-p r l = 500 w hd2 hd3 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 harmonic distortion near limit voltages | limit voltages ?2.5v dc | 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2nd and 3rd harmonic distortion (dbc) v o = 2.5v dc ?vp f 1 = 5mhz r l = 500 w hd2 hd3 v h and v h ?imited pulse response 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 time (20ns/div) input and output voltages (v) v h = v cm +1.2v v l = v cm ?.2v v o v o v in v in v cm = 2.5v
11 opa689 typical applications dual supply, non-inverting amplifier figure 1 shows a non-inverting gain amplifier for dual supply operation. this circuit was used for ac characteriza- tion of the opa689, with a 50 w source, which it matches, and a 500 w load. the power supply bypass capacitors are shown explicitly in figures 1 and 2, but will be assumed in the other figures. the limiter voltages (v h and v l ) and their bias currents (i vh and i vl ) have the polarities shown. single supply, non-inverting amplifier figure 2 shows an ac coupled, non-inverting gain amplifier for single supply operation. this circuit was used for ac characterization of the opa689, with a 50 w source, which it matches, and a 500 w load. the power supply bypass capacitors are shown explicitly in figures 1 and 2, but will be assumed in the other figures. the limiter voltages (v h and v l ) and their bias currents (i vh and i vl ) have the polarities shown. notice that the single supply circuit can use 3 resistors to set v h and v l , where the dual supply circuit usually uses 4 to reference the limit voltages to ground. low distortion, adc input driver the circuit in figure 3 shows an inverting, low distortion adc driver that operates on single supply. the converters internal references bias the op amp input. the 4.0pf and 18pf capacitors form a compensation network that allows figure 3. low distortion, limiting adc input driver. figure 1. dc-coupled, dual supply amplifier. figure 2. ac-coupled, single supply amplifier. opa689 49.9 w 6 i vh v o v in i vl ? s = ?v 3 2 4 7 8 5 r f 750 w r g 150 w 500 w 0.1? 0.1? 0.1? 100 w 3.01k w 1.91k w 3.01k w 1.91k w 0.1? v h = +2v v l = ?v + 2.2? + 2.2? +v s = +5v opa689 53.6 w 6 i vh v h = 3.7v v o v l = 1.3v v in i vl 1.50k w 3 2 4 7 8 5 1.50k w 523 w 976 w 523 w r g 150 w r f 750 w 500 w 0.1? 0.1? 0.1? + 2.2? 0.1? v s = +5v 0.1? 0.1? opa689 v s = +5v v s = +5v 4 3 2 7 5 8 6 v s = +5v v in 4.0pf 750 w 0.1 f refb reft in int/ext rsel +v s gnd 0.1 f 18pf 100pf v h = +3.6v v l = +1.4v +2.5v 374 w 1.40k w 24.9 w 1.40k w 0.1 f 0.1 f 787 w 100 w 100 w 787 w ads822 10-bit 40msps 10-bit data +1.5v +3.5v
12 opa689 the opa689 to have a flat frequency response at a gain of C 2. this increases the loop gain of the op amp feedback network, which reduces the distortion products below their specified values. precision half wave rectifier figure 4 shows a half wave rectifier with outstanding preci- sion and speed. v h will default to a voltage between 3.1 and 3.8v if left open, while the negative limit is set to ground. opa689 6 v o ? s = ?v +v s = +5v v in 2 3 4 7 8 5 750 w 150 w 124 w nc figure 4. precision half wave rectifier. very high speed comparator figure 5 shows a very high speed comparator with hysterisis. the output level are precisely defined, and the recovery time is exceptional. the output voltage swings between 0.5v and 3.5v to provide a logic level output that switches as v in crosses v ref . opa689 6 v o ? s = ?v 3 2 4 7 8 5 0.1? 0.1? 2.00k w 1.21k w 200k w 604 w +v s = +5v 100 w v in 95.3 w figure 5. very high speed comparator. figure 6. transimpedance amplifier. design-in tools applications support the burr-brown applications department is available for design assistance at phone number 1-800-548-6132 (us/canada only). the burr-brown internet web page (http://www.burr-brown.com) has the latest data sheets and other design aids. demonstration boards two pc boards are available to assist in the initial evaluation of circuit performance of the opa689 in both package styles. these will be available as an unpopulated pcb with descriptive documentation. see the board literature for more information. the summary information for these boards is shown below: board literature part request product package number number opa689p 8-pin dip dem-opa68xp mkt-350 opa689u 8-pin so-8 dem-opa68xu mkt-351 contact the burr-brown applications department for avail- ability of these boards. spice models computer simulation of circuit performance using spice is often useful when analyzing analog circuit or system perfor- mance. this is particularly true for high speed amplifier circuits where parasitic capacitance and inductance can have a major effect on frequency response. spice models are available through the burr-brown web site (www.burr-brown.com). these models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. they do not do as well in predicting the harmonic distortion, temperature ef- fects, or different gain and phase characteristics. these models do not distinquish between the ac performance of different package types. opa689 +v s = +5v nc nc ? s = ?v 4 2 3 7 5 8 6 v o 4.32k w 4.32k w c f 1.0pf c d 5.0pf l 0.1 f ? b i d transimpedance amplifier figure 6 shows a transimpedance amplifier that has excep- tional overdrive characteristics. the feedback capacitor (c f ) stabilizes the circuit for the assumed diode capacitance (c d ).
13 opa689 operating information theory of operation the opa689 is a voltage feedback op amp that is stable for gains 3 +4. the output voltage is limited to a range set by the limiter pins (5 and 8). when the input tries to overdrive the output, the limiters take control of the output buffer. this avoids saturating any parts in the signal path, gives quick overdrive recovery, and gives consistent limiter accuracy for any gain. this part is de-compensated (stable for gains 3 +4). this gives greater bandwidth, higher slew rate, and lower noise than the unity gain stable companion part opa688. the limiters have a very sharp transition from the linear region of operation to output limiting. this allows the limiter voltages to be set very near (<100 mv) the desired signal range. the distortion performance is also very good near the limiter voltages. circuit layout achieving optimum performance with the high frequency opa689 requires careful attention to layout design and component selection. recommended pcb layout techniques and component selection criteria are: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. open a window in the ground and power planes around the signal i/o pins, and leave the ground and power planes unbroken elsewhere. b) provide a high quality power supply. use linear regu- lators, ground plane, and power planes, to provide power. place high frequency 0.1 m f decoupling capacitors < 0.2" away from each power supply pin. use wide, short traces to connect to these capacitors to the ground and power planes. also use larger (2.2 m f to 6.8 m f) high frequency decoupling capacitors to bypass lower frequencies. they may be some- what further from the device, and be shared among several adjacent devices. c) place external components close to the opa689. this minimizes inductance, ground loops, transmission line ef- fects and propagation delay problems. be extra careful with the feedback (r f ), input and output resistors. d) use high frequency components to minimize parasitic elements. resistors should be a very low reactance type. surface mount resistors work best and allow a tighter layout. metal film or carbon composition axially-leaded resistors can also provide good performance when their leads are as short as possible. never use wire-wound resistors for high frequency applications. remember that most potentiometers have large parasitic capacitances and inductances. multilayer ceramic chip capacitors work best and take up little space. monolithic ceramic capacitors also work very well. use rf type capacitors with low esr and esl. the large power pin bypass capacitors (2.2 m f to 6.8 m f) should be tantalum for better high frequency and pulse perfor- mance. e) choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel capacitance. good metal film or surface mount resistors have approximately 0.2pf parasitic parallel capacitance. for resistors > 1.5k w , this adds a pole and/or zero below 500mhz. make sure that the output loading is not too heavy. the recommended 750 w feedback resistor is a good starting point in your design. f) use short direct traces to other wideband devices on the board. short traces act as a lumped capacitive load. wide traces (50 to 100 mils) should be used. estimate the total capacitive load at the output, and use the series isolation resistor recommended in the r s vs capacitive load plot. parasitic loads < 2pf may not need the isolation resistor. g) when long traces are necessary, use transmission line design techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 w transmis- sion line is not required on boarda higher characteristic impedance will help reduce output loading. use a matching series resistor at the output of the op amp to drive a transmission line, and a matched load resistor at the other end to make the line appear as a resistor. if the 6db of attenuation that the matched load produces is not acceptable, and the line is not too long, use the series resistor at the source only. this will isolate the op amp output from the reactive load presented by the line, but the frequency re- sponse will be degraded. multiple destination devices are best handled as separate transmission lines, each with its own series source and shunt load terminations. any parasitic impedances acting on the terminating resistors will alter the transmission line match, and can cause unwanted signal reflections and reactive loading. h) do not use sockets for high speed parts like the opa689. the additional lead length and pin-to-pin capacitance intro- duced by the socket creates an extremely troublesome para- sitic network. best results are obtained by soldering the part onto the board. if socketing for dip prototypes is desired, high frequency flush mount pins (e.g., mckenzie technol- ogy #710c) can give good results. power supplies the opa689 is nominally specified for operation using either 5v supplies or a single +5v supply. the maximum specified total supply voltage of 13v allows reasonable tolerances on the supplies. higher supply voltages can break down internal junctions, possibly leading to catastrophic failure. single supply operation is possible as long as com- mon mode voltage constraints are observed. the common mode input and output voltage specifications can be inter- preted as a required headroom to the supply voltage. observ- ing this input and output headroom requirement will allow design of non-standard or single supply operation circuits. figure 2 shows one approach to single-supply operation.
14 opa689 esd protection esd damage is known to damage mosfet devices, but any semiconductor device is vulnerable to esd damage. this is particularly true for very high speed, fine geometry processes. esd damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. in precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. therefore, esd handling precautions are required when handling the opa689. output limiters the output voltage is linearly dependent on the input(s) when it is between the limiter voltages v h (pin 8) and v l (pin 5). when the output tries to exceed v h or v l , the corresponding limiter buffer takes control of the output voltage and holds it at v h or v l . because the limiters act on the output, their accuracy does not change with gain. the transition from the linear region of operation to output limiting is sharpthe desired output signal can safely come to within 30mv of v h or v l . distortion performance is also good over the same range. the limiter voltages can be set to within 0.7v of the supplies (v l 3 Cv s + 0.7v, v h +v s C 0.7v). they must also be at least 200mv apart (v h C v l 3 0.2v). when pins 5 and 8 are left open, v h and v l go to the default voltage limit; the minimum values are in the spec table. looking at figure 7 for the zero bias current case will show the expected range of (v s C default limit voltages) = head- room). when the limiter voltages are more than 2.1v from the supplies (v l 3 Cv s + 2.1v or v h +v s C 2.1v), you can use simple resistor dividers to set v h and v l (see figure 1). make sure you include the limiter input bias currents (figure 7) in the calculations (i.e., i vl ? C50 m a out of pin 5, and i vh ? +50 m a out of pin 8). for good limiter voltage accuracy, run at least 1ma quiescent bias current through these resistors. when the limiter voltages need to be within 2.1v of the supplies (v l Cv s + 2.1v or v h 3 +v s C 2.1v), use low impedance voltage sources to set v h and v l to minimize errors due to bias current uncertainty. this will typically be the case for single supply operation (v s = +5v). figure 2 runs 2.5ma through the resistive divider that sets v h and v l . this keeps errors due to i vh and i vl < 1% of the target limit voltages. the limiters dc accuracy depends on attention to detail. the two dominant error sources can be improved as follows: ? power supplies, when used to drive resistive dividers that set v h and v l , can contribute large errors (e.g., (5%). using a more accurate source, or bypassing pins 5 and 8 with good capacitors, will improve limiter psrr. ? the resistor tolerances in the resistive divider can also dominate. use 1% resistors. other error sources also contribute, but should have little impact on the limiters dc accuracy: ? reduce offsets caused by the limiter input bias currents. select the resistors in the resistive divider(s) as described above. ? consider the signal path dc errors as contributing to the uncertainty in the useable output range. ? the limiter offset voltage only slightly degrades the limiter accuracy. figure 8 shows how the limiters affect distortion perfor- mance. virtually no degradation in linearity is observed for output voltages swinging right up to the limiter voltages. figure 8. linearity guardband. figure 7. limiter bias current vs limiter voltage. harmonic distortion near limit voltages ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?limit voltage (v) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2nd and 3rd harmonic distortion (dbc) v o = 0v dc ?vp f 1 = 5mhz r l = 500 w hd2 hd3 100 75 50 25 0 ?5 ?0 ?5 ?00 limiter input bias current vs bias voltage limiter headroom (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 limter input bias current ( a) maximum over temperature minimum over temperature limiter headroom = +v s ?v h current = i vh or ? vl = v l ?(? s )
15 opa689 opa689 c l r l r iso r l is optional v o offset voltage adjustment the circuit in figure 9 allows offset adjustment without degrading offset drift with temperature. use this circuit with caution since power supply noise can inadvertently couple into the op amp. remember that additional offset errors can be created by the amplifiers input bias currents. whenever possible, match the resistance seen by both dc input bias currents by using r 3 . this minimizes the output offset voltage caused by the input bias currents. figure 9. offset voltage trim. output drive the opa689 has been optimized to drive 500 w loads, such as a/d converters. it still performs very well driving 100 w loads. this makes the opa689 an ideal choice for a wide range of high frequency applications. many high speed applications, such as driving a/d convert- ers, require op amps with low output impedance. as shown in the output impedance vs frequency performance curve, the opa689 maintains very low closed-loop output imped- ance over frequency. closed-loop output impedance in- creases with frequency since loop gain decreases with fre- quency. thermal considerations the opa689 will not require heat-sinking under most oper- ating conditions. maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. in no case should the maximum junction temperature be allowed to exceed 175 c. the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and the additional power dissipated in the output stage (p dl ) while delivering load power. p dq is simply the specified no-load supply current times the total supply voltage across the part. p dl depends on the required output signals and loads. for a grounded resistive load, and equal bipolar supplies, it is at a maximum when the output is at 1/2 either supply voltage. in this condition, p dl = v s 2 /(4r l ) where r l includes the feedback network loading. note that it is the power in the output stage, and not in the load, that determines internal power dissipation. the operating junction temperature is: t j = t a + p d q ja , where t a is the ambient temperature. for example, the maximum t j for a opa689u with g = +6, r fb = 750 w , r l = 100 w , and v s = 5v at the maximum t a = +85 c is calculated this way: p dq =10 v 20 ma () = 200 mw p dl = 5 v () 2 4 100w || 850w () p d = 200 mw +70 mw = 270 mw t j =85 c + 270 mw 125 c/w = 119 c capacitive loads capacitive loads, such as flash a/d converters, will decrease the amplifiers phase margin, which may cause peaking or oscillations. capacitive loads 3 1pf should be isolated by connecting a small resistor in series with the output as shown in figure 10. increasing the gain from +6 will improve the capacitive drive capabilities due to increased phase margin. figure 10. driving capacitive loads. in general, capacitive loads should be minimized for opti- mum high frequency performance. the capacitance of coax cable (29pf/foot for rg-58) will not load the amplifier when the coaxial cable, or transmission line, is terminated in its characteristic impedance. r 2 opa689 r 3 = r 1 || r 2 r 1 r trim 47k w +v s v o ? s v in or ground 0.1? notes: (1) r 3 is optional and minimizes output offset due to input bias currents. (2) set r 1 << r trim .
16 opa689 frequency response compensation the opa689 is internally compensated to be stable at a gain of +4, and has a nominal phase margin of 60 at a gain of +6. phase margin and peaking improve at higher gains. recall that an inverting gain of C5 is equivalent to a gain of +6 for bandwidth purposes (i.e., noise gain = 6). standard external compensation techniques work with this device. for example, in the inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series rc network to ground on the inverting node. this has the effect of increasing the noise gain at high frequencies, which limits the bandwidth. to maintain a large bandwidth at high gains, cascade several op amps. in applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the parasitic capacitance from the inverting input to ground causes peak- ing or oscillations. to compensate for this effect, connect a small capacitor in parallel with the feedback resistor. the bandwidth will be limited by the pole that the feedback resistor and this capacitor create. in other high gain applica- tions, use a three resistor tee network to reduce the rc time constants set by the parasitic capacitances. be careful to not increase the noise generated by this feedback network too much. pulse settling time the opa689 is capable of an extremely fast settling time in response to a pulse input. frequency response flatness and phase linearity are needed to obtain the best settling times. for capacitive loads, such as an a/d converter, use the recommended r s in the r s vs capacitive load plot. ex- tremely fine scale settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors. the pulse settling characteristics when recovering from overdrive are very good. distortion the opa689s distortion performance is specified for a 500 w load, such as an a/d converter. driving loads with smaller resistance will increase the distortion as illustrated in figure 11. remember to include the feedback network in the load resistance calculations. figure 11. 5mhz harmonic distortion vs load resistance. ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 harmonic distortion vs load resistance load resistance ( w ) 2nd and 3rd harmonic distortion (dbc) 50 100 1000 v o = 2vp-p f 1 = 5mhz hd2 hd3
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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