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description the puma 68fv32006 is a high density 32mbit cmos 3.3v only flash memory organised as 1m x 32 in a jedec 68 pin surface mount plcc, with read access times of 90, 120, and 150ns. the plastic device is screened to ensure high reliability. the output width is user configurable as 8 , 16 or 32 bits using four chip selects (cs1~4) for optimum application flexibility. the device incorporates embedded algorithms for program and erase with sector architecture (64k sector) and supports full chip erase. the puma 68fv32006 also features hardware sector protection, which disables both program and erase operations in any of the 32 sectors on the device. features ? fast access times of 90/120/150 ns. output configurable as 32 / 16 / 8 bit wide. operating power 660/330/165 mw (max). low power standby 1.1ma (max). industrial and military (restricted) grade parts. automatic write/erase by embedded algorithm - end of write/erase indicated by data polling and toggle bit. flexible sector erase architecture - 64k byte sector size, with hardware protection of any number of sectors. 3.3v operation, 3.3v program. single byte program time of 9 s (typ). sector program time of 1sec (typ). erase/write cycle endurance 100,000 (min). 1m x 32 flash memory puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 pin functions a0-a19 address input d0-d31 data inputs/outputs cs1-4 chip enables we write enable oe output enable vcc power (+3.3v) gnd ground 44 nc a0 a1 a2 a3 a4 a5 cs3 gnd cs4 we a6 a7 a8 a9 a10 vcc d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 view from above vcc a11 a12 a13 a14 a15 a16 cs1 oe cs2 nc nc gnd a19 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 a17 nc a18 puma 68fv32006 d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 oe a0~a19 we 1m x 8 flash 1m x 8 flash 1m x 8 flash 1m x 8 flash block diagram (see page 20 for 'a' version) pin definition (see page 20 for 'a' version) elm road, west chirton, north shields, tyne & wear ne29 8se, england tel. +44 (0191) 2930500 fax. +44 (0191) 2590997
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 2 parameter symbol test condition min typ max unit i/p leakage currentaddress, oe, we i li1 v cc =v cc max, v in =0v or v cc --4a a9 input leakage current i li2 v cc =v cc max, a9=12.5v - - 140 a other pins i li3 v cc =v cc max, v in =0v or v cc --4a output leakage current i lo v cc =v cc max, v out =0v or v cc --4a v cc read current 32 bit i cco32 cs=v il (1) , oe=v ih , i out =0ma, f =5mhz --64ma 16 bit i cco16 as above --32ma 8 bit i cco8 as above --16ma v cc write current 32 bit i ccp32 programming in progress - - 120 ma 16 bit i ccp16 as above --60ma 8 bit i ccp8 as above --30ma standby supply current i sb1 v cc =v cc max, cs (1) ,reset=v cc + 0.3v --40a autoselect / sector unprotect voltage v id v cc = 3.3v 11.5 - 12.5 v output low voltage v ol i ol =4ma. v cc = v cc min. - - 0.45 v output high voltage v oh1 i oh =-2.0ma. v cc = v cc min. 0.85vcc - - v low v cc lock-out voltage v lko 2.3 - 2.5 v notes (1) cs above are accessed through cs1-4. these inputs must be operated simultaneously for 32 bit operation, in pairs in 16 bit mode and singly for 8 bit mode. recommended operating conditions parameter min typ max unit supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 0.7v cc -v cc +0.3 v input low voltage v il -0.5 - 0.8 v operating temperature t a 0- 70 c t ai -40 - 85 o c (-i suffix) t am -55 - 115 o c (-m suffix) absolute maximum ratings (1) range unit voltage on any pin w.r.t. gnd -0.5 to +vcc+0.5 v supply voltage (2) -0.5 to +4.0 v voltage on a9, oe, reset w.r.t. gnd (3) -0.5 to +12.5 v storage temperature -65 to +150 c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functiona l operationof the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. (2) minimum dc voltage on any input or i/o pin is -0.5v. maximum dc voltage on output and i/o pins is vcc+0.5v during transitions voltage may overshoot to vcc +1.0v for periods of 10ns (3) minimum dc input voltage on a9,oe, reset is -0.5v during voltage transitions, a9,oe, reset may overshoot vss to -1v for periods of up to 10ns, maximum dc input voltage on a9 is 12.5v which may overshoot to 14.0v for periods up to 10ns. dc electrical characteristic (t a =-55 o c to +115 o c, vcc=3.3v + 10%)
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 3 capacitance (t a =25 c,f=1mhz) parameter symbol test condition typ max unit input capacitanceaddress, oe, we c in1 v in =0v - 35 pf other pins c in2 v in =0v - 10 pf output capacitance 8 bit c out8 v out =0v - 52 pf note: these parameters are calculated, not measured. 166 30pf i/o pin 1.76v ? * input pulse levels : 0.0v to 3.0v * input rise and fall times : 5 ns * input and output timing reference levels : 1.5v * vcc = 3.3v +/- 10% * module tested in 32 bit mode ac test conditions
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 4 parameter symbol 90 120 150 min typ max min typ max min typ max unit write cycle time (4) t wc 90 - - 120 - - 150 - - ns address setup time t as 0- - 0- - 0- -ns address hold time t ah 50 - - 55 - - 65 - - ns data setup time t ds 50 - - 55 - - 65 - - ns data hold time t dh 0- - 0- - 0- -ns output enable setup time t oes 0- - 0- - 0- -ns read recover before write t ghwl 0- - 0- - 0- -ns cs setup time t ce 0- - 0- - 0- -ns cs hold time t ch 0- - 0- - 0- -ns we pulse width t wp 50 - - 55 - - 65 - - ns we pulse width high t wph 30 - - 30 - - 35 - - ns programming operation t whwh1 -9- -9- -9-s sector erase operation (1) t whwh2 - 1 - - 1 - - 1 - sec v cc setup time (4) t vcs 50 - - 50 - - 50 - - s notes: (1) this does not include the preprogramming time. (2) not 100% tested.under development. ac operating conditions under development. read cycle write/erase/program parameter 90 120 150 min typ max min typ max min typ max unit read cycle time t rc 90 - - 120 - - 150 - - ns address to output delay t acc - - 90 - - 120 - - 150 ns chip enable to output t ce - - 90 - - 120 - - 150 ns output enable to output t oe - - 40 - - 50 - - 55 ns output enable to output high z t df - - 30 - - 35 - - 40 ns output hold time from address t oh 0- - 0 - - 0 - -ns cs or oe whichever occurs first
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 5 90 120 150 parameter symbol min typ max min typ max min typ max unit write cycle time (2) t wc 90 - - 120 - - 150 - - ns address setup time t as 0- - 0- - 0- -ns address hold time t ah 50 - - 55 - - 65 - - ns data setup time t ds 50 - - 55 - - 65 - - ns data hold time t dh 0- - 0- - 0- -ns output enable setup time t oes 0- - 0- - 0- -ns read recover before write t ghel 0- - 0- - 0- -ns we setup time t ws 0- - 0- - 0- -ns we hold time t wh 0- - 0- - 0- -ns cs pulse width t cp 50 - - 55 - - 65 - - ns cs pulse width high t cph 30 - - 30 - - 35 - - ns programming operation t whwh1 -9- -9- -9-us sector erase operation (1) t whwh2 - 1 - - 1 - - 1 - sec note: (1) does not include pre-programming time. (2) not 100% tested. under development. write/erase/program alternate cs controlled writes
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 6 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the out put of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. notes: output valid oe t oe t acc t df t oh t ce addresses addresses stable rc ce outputs we high z high z t address v cc oe data ce ce 5555h pa pa t a0h pd out dq7 ah as t wc t t ghwl wp t t whwh1 rc t t cs ds t dh whp t t oh t oe t data pollin g d df t oe t ac waveforms for read operation ac waveforms program
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 7 notes : 1. pa is address of memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. oe ce we ch oeh oe df ce whwh 1 or 2 dq7= valid data dq7 high z oh dq0-dq6 high z oe dq0-dq6 = invalid dq0-dq7= vaild data dq7 * t t t t t t t t address v cc oe data we ce 555 pa pa t a0 pd d out d out dq7 ah as t wc t t ghel cp t t whwh1 or 2 rc t t ws ds t dh chp t t oh t oe t data pollin g a.c waveforms - alternate cs controlled program operation timings ac waveforms for data polling during embedded algorithm operations
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 8 * dq6 stops toggling ( the device has completed the embedded operations) oe ce we t data (dq0-dq7) * dq 6=to gg le dq 6=to gg le dq6= stop to gg lin g dq 0-dq7 valid oeh oh t t oe notes: 1. sa is the address for sector erase. addresses = don't care for chip erase. address oe we data vcc tghwl twp twph tdh tcs tvcs tas tah tds 5555h 2aaah 5555h 5555h 2aaah sa address ce aah 55h 80h aah 55h 30h tghwl twp twph tdh tcs tvcs tas tah tds ac waveforms for toggle bit during embedded algorithm operations ac waveforms chip / sector erase
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 9 data poll device write program command sequence (see below) last address ? programming completed increment address no yes start start write erase command sequence see below data poll or to gg le bit successfully completed erasure completed embedded programming algorithm embedded erase algorithm
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 10 notes: 1. dq6 is rechecked even if dq5 = 1 because dq6 may stop toggling at the same time as dq5 changing to "1". 2 read toggle bit twice to determin wether or not it is toggling. note: 1. dq7 is rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 2. va = byte address for programming. = any of the sector addresses within the sector being erased during sector erase operation = xxxxxh during chip erase start fail dq7 = data ? dq5 = 1 ? read byte (dq0-dq7) addr =va read byte (dq0-dq7) addr =va dq7 = data ? pass no yes yes no no yes start read byte (dq0-dq7) dq6=to gg le ? pass fail dq5 = 1 ? read byte (dq0-dq7) twice dq6=to gg le ? no yes yes no yes no note (1,2) data polling algorithm toggle bit algorithm
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 11 reset ce we ry/by program or erase command sequence t rsp t vidr t vidr 12 v 0 or 3 v 0 or 3 v temporary sector unprotect waveform
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 12 the device has two control functions which must be satisfied in order to obtain data at the outputs cs1-4 is the power control and should be used for device selection oe is the output control and should be used to gate data to the output pins if the device is selected. two standby modes are available : cmos standby : cs1-4 held at vcc +/- 0.3v ttl standby : cs1-4 held at v ih in the standby mode the outputs are in a high impedance state independent of the oe input. if the device is deselected during erasure or programming the device will draw active current until the operation is completed. with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. the following description deals with the device operating in 8 bit mode accessed through cs1, however status flag definitions shown apply equally to the corresponding flag for each device in the module. device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the register is a latch used to store the commands along with the address and data information required to execute the command. the command register is written by bringing we/we1-4 to v il while cs1-4 is at v il and oe is at v ih .addresses are latched on the falling edge of we/we1-4 while data is latched on the rising edge. the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7 - dq0. this mode is primarily intended for programing equipment to automaticly match a device to be programed with its corresponding programing algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5v to 12.5v) on address pin a9. address pins a6, a1 and a0 must be as shown in the table below. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. the table below shows the remaining address bits have been set as required, the programming equipment may then read the correspond- ing identifier code on dq7 - dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in command definitions table. this method does not require v id . description ce oe we a19 to a13 a12 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 sector protection verification l lh sa x v id x lx h l 01h (protected) 00h (unprotected) l = logic low = v il, h = logic high = vih, sa = sector address, x = don't care device operation read mode standby mode output disable autoselect write
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 13 notes: 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. all address bits are don't cares for unlock and command cycles, except when sa or pa required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while device is providing status data. 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. 9. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 10. the erase resume command is valid only during the erase suspend mode. the read or reset operation is initiated by writing the read/reset command sequence into the command regis- ter. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of memory content occurs during the power transition. refer to the ac read characteristics and waveforms for specific timing parameters. sectors which have previously been protected from being programmed or erased may be unprotected using the sector unprotect algorithm. all sectors must be placed in the protection mode using the protection algorithm before unprotection can proceed. a special high voltage for unprotection v sp is defined to be 12v+/-0.5v. the unprotection mode is entered by setting oe to v id or v sp , we to v sp , a5 to v ih and a0=a9 to v il . unprotect is invoked by applying to negative pulses on cs for a period of t wpp2 . command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle read (note 5) reset autoselect (note 7) program chip erase sector erase sector erase suspend (note 9) sector erase resume (note 10) 1 1 4 4 6 6 addr data addr addr addr addr addr data data data data data ra xxx rd fo 80 xxx xxx xxx aa aa aa 55 55 55 xxx xxx xxx xxx a0 pa xxx pd aa xxx 55 xxx sa 10 30 erase can be suspended during sector erase with addr (don't care) data (b0) erase can be resumed after suspend with addr (don't care), data (30) 1 1 sector protect verify (note 8) 90 xxx xxx xxx xxx xxx (sa) x02 00 01 80 xxx aa 55 xxx xxx xxx aa xxx 55 bus cycles (notes 2-4) command definitions read / reset command sector unprotect
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 14 a19 a18 a17 a16 address ran g e sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 0000 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 11 111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 00000h-0ffffh 10000h-1ffffh 20000h-2ffffh 30000h-3ffffh 40000h-4ffffh 50000h-5ffffh 60000h-6ffffh 70000h-7ffffh 80000h-8ffffh 90000h9ffffh a0000h-affffh b0000h-bffffh c0000h-cffffh d0000h-dffffh e0000h-effffh f0000h-fffffh the device features hardware sector protection. this feature will disable both program and erase operations in any sector. the sector protect feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe, and cs=v ih. the sector adresses (a19, a18, a17 and a16) should be set to the sector to be protected. program- ming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. to verify programming of the protection equipment circuitry, the programming equipment must force v id on address pin a9 with ce and oe at v il and we at v ih . reading the device at a particular sector address (a16, a17, a18 and a19) while (a6,a1,a0) = (0,1,0) will produce 01h at data output d0 for a protected sector. otherwise the device will read 00h for unprotected sector. in this mode, the lower order addresses, except for a0, a 1 and a6 , are don't care. address with a1=v il are reserved for autoselect codes. it is also possible to determine if a sector is protected in the system by writing the autoselect command. performing a read operation at xx02h , where the higher order addresses (a16, a17, a18 and a19) are sector addresses,(other addresses are a don't care) will produce 01h data if those sectors are protected. otherwise the devidce will read 00h for an unprotected sector. sector address table sector protection
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 15 the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. see command definitions table. this method is an alternative to that shown in the autoselect codes table, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle containing a sector address (sa) and the address 02h in it, returns 01h if that sector is protected, or 00h if it is unprotected. refer to sector address table for valid sector address. the system must write the reset command to exit the autoselect mode and return to reading array data. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are writen next, which in turn initiate the embeded program algorithm. the system is not required to provide further controls or timings. the device automaticlly provides internally generated program pulses and verify the programmed cell margin. command definitions table shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. see "write operation status" for information on these status bits. any commands writen to the device during the embedded program algorithm are ignored. note that a hard- ware reset immediatly terminates the programming opperation. the program command sequence should be reinitiated once the device has reset to reading data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot from a "0" back to a "1". attempting to do so may halt the opperation and set dq5 to "1", or cause the data polling algorithm to indicate the opperation was sucessful. however, a succeeding read will show that the data is still "0". only erase operations can convert a "0" to a "1". chip erase is a six bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command. two more "unlock" write cycles are then followed by the chip erase command. chip erase doesn't require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. the systems is not required to provide any controls or timings during these operations. any commands written to the chip during the embeded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command se- quence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase operation by using dq7, dq6 or dq2. see "write operation status" for information on these status bits. when the embeded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. autoselect command byte programming chip erase
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 16 sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the addresses and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embeded erase algorithm automaticlly programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50ms begins. during the time-out period, additional sector addresses and sector erase commands may be writen. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50ms, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that the processor interrupts be disabled during this time to ensure all commands are accepted. the interupts can be re-enabled after the last sector erase command is writen. if the time between additional sector erase commands can be assumed to be less than 50ms, the system need not monitor dq3. any command other than sector erase suspend during the time-out period resets the device to reading array data . the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. the time-out begins from the rising edge of the final we pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embeded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6 or dq2. erase suspend the erase suspend command allows the system to interupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embeded program algorithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. addresses are "don't-cares" when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maxi- mum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device "erase suspends" all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq7-dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase suspended. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation. sector erase
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 17 operation standard mode erase suspend mode embedded program algorithm embedded erase algorithm reading within erase suspended sector reading within non-erase suspended sector erase suspend program dq7 (2) dq6 dq5 (1) dq3 dq2 (2) 0 0 0 0 0 to gg le to gg le to gg le to gg le to gg le no toggle no toggle data data data data data n/a n/a n/a n/a 1 1 dq7 dq7 notes: 1. dq5 switches to '1' when an embedded pro g ram or embedded erase operation has exceeded the maximum timin g limits. 2. dq7 and dq2 require a valid address when readin g status information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. the system must write the erase resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be writen after the device has resumed erasing. the device features data polling as a method to indicate to the host system that the embedded algorithms are in progress or completed. during the embedded programming algorithm, an attempt to read the device will produce complement data of the data last written to d7. upon completion of the embedded programming algorithm an attempt to read the device will produce the true data last written to d7. data polling is valid after the rising edge of the forth we pulse in the four write pulse sequence. during the embedded erase algorithm, d7 will be "0" until the erase operation is completed. upon completion the data at d7 is "1". for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, data polling is valid after the last rising edge of the sector erase we pulse. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or sector erase time-out. write operations status d7 data polling
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 18 dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a "1." this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." only an erase operation can change a "0" back to a "1" . under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a "1." under both these conditions, the system must issue the reset command to return the device to reading array data. d 6 toggle bit the device also features the "toggle bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read data from the device will result in d6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, d6 will stop toggling and valid data will be read on successive attempts. during programming, the toggle bit is valid after the rising edge of the forth we pulse in the four write command pulse sequence. for chip erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. the toggle bit is active during the sector time-out. after the completion of the initial sector erase command sequence the sector erase time-out will begin. d3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, d3 may be used to determine if the sector erase timer window is still open. if d3 is high the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase opera- tion is completed as indicated by data polling or toggle bit. if d3 is low , the device will accept additional sector erase commands. to insure the command has been accepted, the software should check the status of d3 prior to and following each subsequent sector erase command. if d3 were high on the second status check, the command may not have been accepted. d 5 exceeding time limits d 3 sector erase timer
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 19 parameter limits unit comments min typ (1) max (2) sector erase time byte pro g rammin g time chip pro g rammin g time erase/pro g ram time chip erase time 1 15 9 300 9 27 100,000 1,000,000 16 sec us sec sec cycles excludes 00h pro g rammin g prior to erasure excludes system level overhead excludes system level overhead 10,000 min. notes : (1) 25 o c, 3v v cc , 100,000 cycles. (2) under work conditions 0f 90 o c , v cc 2.7v, 100,000 cycles the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the internal state machine in the read mode. also, with its controls register architecture , alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power up and power down transitions or system noise. noise pulses of less than 5ns (typical) on oe, cs, we will not initiate a write cycle writing is inhibited by holding any one of oe=v il , cs=v ih or we=v ih . to initiate a write cycle cs and we must be logical zero while oe is a logical one. power-up of the device with we=cs=v il and oe=v ih will not accept commands on the rising edge of we. the internal state machine is automatically reset to the read mode on power-up. sectors of the device may be hardware protected at the users factory. the protection circuitry will disable both program and erase functions for the protected sector(s). requests to program or erase a protected sector will be ignored by the device. when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power- up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored untill vcc is greater than v lko. the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than v lko . data protection low v cc write inhibit write pulse "glitch" protection logical inhibit power up write inhibit sector protect erase and programming performance
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 20 44 nc a0 a1 a2 a3 a4 a5 cs3 gnd cs4 we1 a6 a7 a8 a9 a10 vcc d0 d1 d2 d3 d4 d5 d6 d7 gnd d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 gnd d24 d25 d26 d27 d28 d29 d30 d31 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 view from above vcc a11 a12 a13 a14 a15 a16 cs1 oe cs2 we3 we4 gnd a19 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 a17 we2 a18 puma 68fv32006a d16~23 d0~7 d8~15 d24~31 cs1 cs2 cs3 cs4 oe a0~a19 we1 1m x 8 flash 1m x 8 flash 1m x 8 flash 1m x 8 flash we2 we3 we4 version 'a' pin definition version 'a' block diagram
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 21 1.02 (0.040) typ. 5.08 (0.200) max. 23.11 (0.910) 24.13 (0.950) 25.40 (1.000) 24.89 (0.980) 1.27 (0.050) typ. 0.43 (0.017) typ. note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. our products are subject to a constant process of development. data may be changed without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director. package details 68 'j' leaded surface mount hi-rel plastic package ordering information puma 68fv32006am-90 speed 90 = 90 ns 12 = 120 ns 15 = 150 ns temp. range/screening blank = commercial temperature i = industrial temperature m = military temperature (restricted) we option blank = single we a = we1~we4 organisation 32006 = 1m x 32, user confiurable as 2m x 16 and 4m x 8 technology fv = flash memory (3.3v operation) package type puma 68= 68 pin "j" leaded plcc
puma 68fv32006/a - 90/12/15 issue 1.4 : may 2001 22 visual inspection standard all devices inspected to ansi/j-std-001b class 2 standard moisture sensitivity devices are moisture sensitive. shelf life in sealed bag 12 months at <40 o c and <90% relative humidity (rh). after this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220 o c) must be : a : mounted within 72 hours at factory conditions of <30 o c/60% rh or b : stored at <20% rh if these conditions are not met or indicator card is >20% when read at 23 o c +/-5% devices require baking as specified below. if baking is required, devices may be baked for :- a : 24 hours at 125 o c +/-5% for high temperature device containers or b : 192 hours at 40 o c +5 o c/-0 o c and <5% rh for low temperature device containers . packaging standard devices packaged in dry nitrogen, jed-std-020. packaged in trays as standard. tape and reel available for shipment quantities exceeding 200pcs upon request. soldering recomendations ir/convection - ramp rate 6 o c/sec max. temp. exceeding 183 o c 150 secs. max. peak temperature 225 o c time within 5 o c of peak 20 secs max. ramp down 6 o c/sec max. vapour phase - ramp up rate 6 o c/sec max. peak temperature 215 - 219 o c time within 5 o c of peak 60 secs max. ramp down 6 o c/sec max. the above conditions must not be exceeded. note : the above recommendations are based on standard industry practice. failure to comply with the above recommendations invalidates product warranty.

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