sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 1 of 11 product features supports pentium ? & pentium ? ii using the 440lx chipset. . 5 cpu / agp clocks up to 16 sdram clocks for 4 dimms. 7 pci synchronous clocks. optional common or mixed supply mode: (vdd = vddp = vddc = 3.3v) or (vdd = vddp = 3.3v, vddc = 2.5v) supports power management < 250ps skew cpu and sdram clocks. < 250ps skew among pci clocks. i 2 c 2-wire serial interface programmable registers featuring: - enable/disable each output pin - mode as tri-state, test, or normal 3 ioapic clocks for multiprocessor support. 56-pin ssop package block diagram frequency table sel cpu pci 0 60.0 30.0 1 66.6 33.3 connection diagram ps# : pci_stop# cs# : cpu_stop# pd# : pwr_dwn# sel pll clock gen. b cpuclk(1:5) vddc 5 b pciclk(1:6) 6 dly ref xin xout ref ioapic(1:3) vddc pciclk_f sdata sclock b sdram(1:16) 16 ps# cs# pd# mode vdd 1 ioapic3 2 ref 3 vss 4 vss 17 sdram12 18 sdram11 19 vddp 20 xin 5 xout 6 vddp 7 pciclk_f 8 pciclk1 9 vss 10 pciclk2 11 pciclk3 12 pciclk4 13 pciclk5 14 vddp 15 pciclk6 16 sdram10 21 sdram9 22 vss 23 sdram16 24 vddc 56 ioapic1 55 ioapic2 54 vss 53 cpuclk1 52 cpuclk2 51 vddc 50 cpuclk3 49 cpuclk4 48 vss 47 cpuclk5 46 sdram1 45 sdram2 44 vddp 43 sdram3 42 sdram4 41 vss 40 sdram5 39 sdram6/ pd# 38 vddp 37 sdram7 / cs# 36 sdram8 / ps# 35 vss 34 sdram13 33 sdram15 25 vddp 26 sdata 27 sdclk 28 sdram14 32 vss 31 sel 30 mode 29 b sdram(1:5, 9:16)
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 2 of 11 pin description pin no. pin name pwr i/o type description 5 xin vdd i osc1 on-chip reference oscillator input pin. requires either an external crystal (nominally 14.318 mhz) or externally generated reference signal 6 xout vdd o osc1 o-chip reference oscillator output pin. drives an external crystal when an externally generated reference signal is used, is left unconnected 30 sel - i padi4 pu frequency select input pin. see frequency select table on page 1. 52, 51, 49, 48, 46 cpuclk(1:5) vddc o buf1 clock outputs. cpu frequency table specified on page 1. 55, 54, 2 ioapic(1:2) vddc o buf2 ioapic clock for multi processor support. fixed frequency at 14.31818 mhz. (2.5 or 3.3 supply = vddi) 9, 11, 12, 13, 14, 16 pciclk(1:6) vddp o buf4 pci bus clocks. see frequency select table on page 1. 8 pci_f vddp o buf4 pci clock that ceases only when pd (pin 29) is ascerted. see frequency select table on page 1. 29 mode - i pad input output mode control pin for pins 35, 36 and 38 27 sdata - i/o pad serial i2c control interface data pin. 28 sclk - i pad serial i2c control interface clock pin. 4, 10, 17, 23, 31, 34, 40, 47, 53 vss - p - ground pins for the device. 3 ref vddp o buf 4 buffered copy of the 14.31818 mhz reference oscillator. 7, 15, 20, 26, 37, 43 vddp - p - 3.3 volt power supply pin for sdram, pci and pci_f clock output buffers. 56, 50 vddc - p - 3.3 or 2.5 v power supply for cpu and ioapic clock buffers. 1 vdd - p power supply pins for analog circuits and core logic 45, 44, 42, 41, 39, 22, 21, 19, 18, 33, 32, 25, 24 sdram(1:5), (8:16) vddp o buf 4 high drive sdram output clocks. 35 sdram7 vddp o buf 4 bidirectional pin. when mode is high, acts as a sdram ps# - i pad pu clock. when mode is low and sel is high, acts as an input and when driven low, will synchronously stop all pci clocks (except pci_f) at a logic low level. 36 sdram6 vddp o buf 4 bidirectional pin. when mode is high (logic 1) this pin acts as a sdram clock. when mode is low (logic 0) and sel is high this pin acts as an input and when driven to a logic cs# - i pad pu low level, will synchronously stop all cpu clocks at a logic low level. 38 sdram5 vddp o buf 4 bi-directional pin. when mode is high (logic 1) this pin acts as a sdram clock. when mode is low (logic 0) and sel is high this pin acts as an input and when driven to a logic pd# - i pad pu low level the ic will enter shutdown mode and all internal circuitry is turned off.
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 3 of 11 power management functions all clocks can be individually enabled or stopped via the 2-wire control interface. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. on power up, the vcos will stabilize to the correct pulse widths within about 0.2 ms. the cpu, and pci clocks transition between running and stopped by waiting for one positive edge on pciclk_f followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. when mode=0, pins 26 and 27 are inputs pci_stop# and cpu_stop# respectively (when mode=1, these functions are not available). a particular output is enabled only when both the serial interface and these pins indicate that it should be enabled. the devices clocks may be disabled according to the following table in order to reduce power consumption. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stopped. on low to high transitions of pwr_dwn#, external circuitry should allow 0.2 ms for the vcos to stabilize prior to assuming the clock periods are correct. the cpu and pci clocks transition between running and stopped by waiting for one positive edge on pciclk_f followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. cpu_stop# pci_stop# pwr_dwn# cpuclk pciclk other clks xtal & vcos x x 0 low low low off 0 0 1 low low running running 0 1 1 low running running running 1 0 1 running low running running 1 1 1 running running running running power management timing pciclk_f pci_stop# pciclk(0:5) cpu_stop# cpuclk(0:3)
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 4 of 11 2-wire i 2 c control interface the 2-wire control interface implements a write only slave interface. the imisc674 cannot be read back. sub- addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. the 2- wire control interface allows each clock output to be individually enabled or disabled. during normal data transfer, the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high. there are two exceptions to this. a high to low transition on sdata while sdclk is high is used to indicate the start of a data transfer cycle. a low to high transition on sdata while sdclk is high indicates the end of a data transfer cycle. data is always sent as complete 8-bit bytes, after which an acknowledge is generated. the first byte of a transfer cycle is a 7-bit address with a read/write bit as the lsb. data is transferred msb first. the imisc674 will respond to writes to 10 bytes (max) of data to address d2 by generating the acknowledge (low) signal on the sdata wire following reception of each byte. the imisc674 will not respond to any other control interface conditions. previously set control registers are retained. serial control registers note: the pin# column lists the affected pin number where applicable. the @pup column gives the state at true power up. bytes are set to the values shown only on true power up, and not when the pwr_dwn# pin is activated. following the acknowledge of the address byte (d2), two additional bytes must be sent: 1) ? command code ? byte, and 2) ? byte count ? byte. although the data (bits) in these two bytes are considered ?don?t care?, they must be sent and will be acknowledged. byte 0 : function select register ( 1 = enable, 0 = stopped) bit @pup pin# description 7 0 * reserved, don?t set 6 0 * reserved, don?t set 5 0 * reserved, don?t set 4 0 * reserved, don?t set 3 1 23 48/24 mhz 2 1 22 48/24 mhz 1 0 0 0 bit1 bit0 1 1 tri-state 1 0 reserved 0 1 test mode 0 0 normal important note reserved bits are intended for possible future functions. it is important that they be left at their power up logic at all times. otherwise data sheet specifications cannot be guaranteed.
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 5 of 11 serial control registers (continued) function table function outputs description cpu pci sdram ref ioapic tri-state hi-z hi-z hi-z hi-z hi-z test mode tclk/2 tclk/4 tclk/2 tclk tclk normal sel=1 66 cpu/2 cpu 14.318 14.318 normal sel=0 60 cpu/2 cpu 14.318 14.318 notes: 1. tclk is a test clock over driven on the xin input during test mode. byte 1 : cpu clock register ( 1 = enable, 0 = stopped) bit @pup pin# description 7 x - reserved 6 x - reserved 5 x - reserved 4 1 46 cpuclk5 enable/stopped 3 1 48 cpuclk4 enable/stopped 2 1 49 cpuclk3 enable/stopped 1 1 51 cpuclk2 enable/stopped 0 1 52 cpuclk1 enable/stopped byte 2 : pci clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 x - reserved 6 1 8 pciclk_f enable/stopped 5 1 16 pciclk6 enable/stopped 4 1 14 pciclk5 enable/stopped 3 1 13 pciclk4 enable/stopped 2 1 12 pciclk3 enable/stopped 1 1 11 pciclk2 enable/stopped 0 1 9 pciclk1 enable/stopped
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 6 of 11 serial control registers(continued) byte 3 : sdram clock register ( 1 = enable, 0 = stopped ) bit @pup pin# description 7 1 35 sdram8 enable/stopped 6 1 36 sdram7 enable/stopped 5 1 38 sdram6 enable/stopped 4 1 39 sdram5 enable/stopped 3 1 41 sdram4 enable/stopped 2 1 42 sdram3 enable/stopped 1 1 44 sdram2 enable/stopped 0 1 45 sdram1 enable/stopped byte 4 : additional sdram clock register (1 = enable, 0 = stopped) bit @pup pin# description 7 1 24 sdram16 enable/stopped 6 1 25 sdram15 enable/stopped 5 1 32 sdram14 enable/stopped 4 1 33 sdram13 enable/stopped 3 1 18 sdram12 enable/stopped 2 1 19 sdram11 enable/stopped 1 1 21 sdram10 enable/stopped 0 1 22 sdram9 enable/stopped byte 5 : peripheral control (1 = enable, 0 = stopped) bit @pup pin# description 7 x - reserved 6 1 2 ioapic3 enable/stopped 5 1 54 ioapic2 enable/stopped 4 1 55 ioapic1 enable/stopped 3 x - reserved 2 x - reserved 1 x - reserved 0 1 3 ref enable/stopped
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 7 of 11 serial control registers(continued) byte 6 : reserved register bit @pup pin# description 7 x - reserved 6 x - reserved 5 x - reserved 4 x - reserved 3 x - reserved 2 x - reserved 1 x - reserved 0 x - reserved maximum ratings voltage relative to vss: -0.3v voltage relative to vdd: 0.3v storage temperature: -65oc to + 150oc ambient temperature: -55oc to +125oc maximum power supply: 7v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 8 of 11 switching characteristics characteristic symbol min typ max units conditions output duty cycle - 45 50 55 % measured at 1.5v cpu to pci offset toff 1 - 4 ns 15 pf load measured at 1.5v skew (cpu-cpu,sdram- sdram,pci-pci) tskew1 - - 350 ps 15 pf load measured at 1.5v skew (cpu-sdram) tskew2 - 200* 300** 500* 600** ps 20 pf cpu, 30 pf sdram load * @ vddc = 3.3v 5% ** @ = vddc = 2.5v 5%, d period adjacent cycles d p - - + 250 ps - jitter spectrum 20 db bandwidth from center bw j 500 khz vdd = vddp =3.3v 5 %, vddc = 2.5v 5 %,, ta = 0oc to +70oc note 1: ring back must not enter this range. type 1 buffer characteristics for cpuclk(1:4) characteristic symbol min typ max units conditions pull-up current min ioh min -27 - - ma vout = 1.0 v pull-up current max ioh max - - -27 ma vout = 2.6 v pull-down current min iol min -27 - - ma vout = 1.2 v pull-down current max iol max - - 27 ma vout = 0.3 v rise/fall time min between 0.4 v and 2.0 v trf min 0.4 - - ns 10 pf load rise/fall time max between 0.4 v and 2.0 v trf max - - 2.0 ns 20 pf load vdd = vddp =3.3v 5 %, vddc = 2.5v 5 %,, ta = 0oc to +70oc
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 9 of 11 type 2 buffer characteristics for ioapic(1:2) characteristic symbol min typ max units conditions pull-up current min ioh min -28 - - ma vout = 1.4 v pull-up current max ioh max - - -28 ma vout = 2.7 v pull-down current min iol min -28 - - ma vout = 1.0 v pull-down current max iol max - - 28 ma vout = 0.2 v rise/fall time min between 0.4 v and 2.0 v trf min 0.4 - - ns 10 pf load rise/fall time max between 0.4 v and 2.0 v trf max - - 2.0 ns 20 pf load vdd = vddp =3.3v 5 %, vddc = 2.5v 5 %,, ta = 0oc to +70oc type 4 buffer characteristics for ref and sdram(1:16) characteristic symbol min typ max units conditions pull-up current min ioh min -46 - - ma vout = 1.65 v pull-up current max ioh max - - 46 ma vout = 3.135 v pull-down current min iol min -53 - - ma vout = 1.65 v pull-down current max iol max - - 53 ma vout = 0.4 v rise/fall time min between 0.4 v and 2.4 v trf min 0.5 - - ns 20 pf load rise/fall time max between 0.4 v and 2.4 v trf max - - 2.0 ns 30 pf load vdd = vddp =3.3v 5 %, vddc = 2.5v 5 %,, ta = 0oc to +70oc type 5 buffer characteristics for pciclk(1:6, f) characteristic symbol min typ max units conditions pull-up current min ioh min -33 - - ma vout = 1.0 v pull-up current max ioh max - - -33 ma vout = 3.135 v pull-down current min iol min 30 - - ma vout = 1.95 v pull-down current max iol max - - 38 ma vout = 0.4 v rise/fall time min between 0.4 v and 2.4 v trf min 0.5 - - ns 15 pf load rise/fall time max between 0.4 v and 2.4 v trf max - - 2.0 ns 30 pf load vdd = vddp =3.3v 5 %, vddc = 2.5v 5 %,, ta = 0oc to +70oc
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 10 of 11 crystal and reference oscillator parameters characteristic symbol min typ max units conditions frequency f o 12.00 14.31818 16.00 mhz tolerance tc - - +/-100 ppm calibration note 1 ts - - +/- 100 ppm stability (ta -10 to +60c) note 1 ta - - 5 ppm aging (first year @ 25c) note 1 mode om - - - parallel resonant pin capacitance cp 6 pf capacitance of xin and xout pins to ground (each) dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v startup time ts - - 30 m s load capacitance cl - 20 - pf the crystals rated load. note 1 effective series resonant resistance r1 - - 40 ohms power dissipation dl - - 0.10 mw note 1 shunt capacitance co - -- 8 pf crystals internal package capacitance (total) for maximum accuracy, the total circuit loading capacitance should be equal to cl. this loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (cp) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. budgeting calculations typical trace capacitance, (< half inch) is 4 pf, load to the crystal is therefore 2.0 pf clock generator internal pin capacitance of 36 pf, load to the crystal is therefore 3.0 pf external crystal loading capacitors (connected to ground) (3o pf each) 15.0 pf the total parasitic capacitance would therefore be = 20.0.0 pf. note 1: it is recommended but not mandatory that a crystal meets these specifications.
sc674 i 2 c clock generator for pentium ? ? and pentium ? ? ii with 440lx chipset and 4 dimms approved product international microcircuits, inc. 525 los coches st. rev. 1.7 4/23/97 milpitas, ca 95035. tel: 408-263-6300. fax 408-263-6571 page 11 of 11 package drawing and dimensions 56 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.20 0.31 0.41 a2 0.088 0.090 0.092 2.24 2.29 2.34 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 - 0.010 0.127 - 0.254 d .720 .725 .730 18.29 18.42 18.54 e 0.292 0.296 0.299 7.42 7.52 7.59 e 0.025 bsc 0.635 bsc h 0.400 0.406 0.410 10.16 10.31 10.41 a 0.10 0.013 0.016 0.25 0.33 0.41 l 0.024 0.032 0.040 0.61 0.81 1.02 a 0o 5o 8o 0o 5o 8o x 0.085 0.093 0.100 2.16 2.36 2.54 ordering information part number package type production flow IMISC674BYB 56 pin ssop commercial, 0oc to +70oc note : th e ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking : example: imi sc674byb date code, lot # IMISC674BYB flow b = commercial, 0oc to + 70oc package y = ssop revision imi device number purchase of i 2 c components of international microcircuits, inc. or one of its sublicensed associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. b e a a 1 a 2 e h a l c d
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