View STEL-1172BMG_2273517.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

r

stel-1172b 2 features n 32 bit frequency resolution n parallel sine and cosine outputs n 50 mhz clock frequency (0 to 70c) n 8-bit internal sine and cosine amplitude resolution n 10-bit internal sine and cosine phase resolution n 12-bit phase output available n military and commercial temperature ranges available n microprocessor bus compatible n pin compatible with st-1172a n cascadable for ultra high resolution n low power cmos applications n frequency synthesizers n hi-speed frequency hopped sources n single sideband converters n baseband receivers n digital signal processors circuit description the stel-1172b numerically controlled oscillator (nco) generates digital sine and cosine signals of very precise frequency to be used directly in digital signal processing applications or in conjunction with a d/a converter in analog frequency generation applications. the device, implemented with low power cmos, can operate with clock frequencies as high as 50 mhz. (40?mhz over the military temperature range, ?55 c to +125 c). the nco is designed to interface with an eight bit microprocessor bus. the nco maintains a record of phase which is accurate to 32 bits of resolution. at each clock cycle, the number stored in the 32 bit d -phase register is added to the previous value of the phase accumulator. the number in the phase accumulator represents the current phase of the synthesized sine and cosine functions. the number in the d -phase register represents the change of phase for each cycle of the clock. this number is directly related to the output frequency by the following: f c x d d d d d -phase f o = 2 32 where: f o is the frequency of the output signal and: f c is the clock frequency. block diagram 8 data 7-0 ldstb 2 addr 1-0 reset clock -phase register block buffer register block addr. select logic block wrn carry in select a,b 2 32 32-bit phase accumulator block 32 carry out sync 10 cosine lookup table block 8 8 10 sine lookup table block phase 11-4 8 mux block 2 phase 3-2 cosine 7-0 (phase 1-0) sine 7-0 (phase 11-4) tcp 54836.c
3 stel-1172b functional description the sine and cosine signals are generated from the 10 most significant bits of the phase accumulator. the frequency of the nco is determined by the number stored in the phase register which may be programmed by an eight-bit microprocessor. the stel-1172b nco generates digitized sampled sine and cosine signals where the sampling function is the clock. if the output frequency is very low with respect to the clock ( stel-1172b 4 input signals reset the reset input is synchronous with the clock input. when reset goes to a logic high level all registers except the 32 bit input buffer and d -phase register are cleared within 20 nsecs. of the next rising edge of the clock . the output data and phase accumulator are cleared to zero. after the reset returns to a logic zero the chip requires 37 rising clock edges to resume normal operation. for the first two of these cycles the output data will be 00 h and then 80 h , respectively. for the remaining 35 clock cycles the sin and cos outputs remain at the value corresponding to zero phase, i.e. 129, or 81 h . normal operation will then commence, starting at zero phase clock all synchronous functions performed within the nco are referenced to the rising edge of the clock input. the clock signal should be nominally a square wave at a maximum frequency of 50 mhz. a non-repetitive clock waveform is permissible as long as the minimum duration positive or negative pulse on the waveform is always greater than 8 nanoseconds. at each rising edge of the clock signal the contents of the phase accumulator are added to the number stored in the d -phase register, and the result is placed in the phase accumulator. wrn the information on the 8-bit data bus is transferred to the buffer register selected by addr 1 and addr 0 on the falling edge of the wrn input. ldstb on the rising edge of the clock following the rising edge of the ldstb input the information in the four buffer registers is transferred to the d -phase register. the frequency at the nco output will change 34 clock cycles after the ldstb command due to pipelining delays. addr 1 and addr 0 the addr 1 and addr 0 signals control the use of the data 7-0 bus according to the table: addr 0 addr 1 d d d d d -phase register field 1 1 bits 0 (lsb) through 7 0 1 bits 8 through 15 1 0 bits 16 through 23 0 0 bits 24 through 31 (msb) function block description address select logic block this block controls the writing of data into the device via the data 7-0 inputs. the data is written into the device on the falling edge of the wrn input, and the register into which the data is written is selected by the addr 1-0 inputs. buffer register block the buffer register is used to temporarily store the d - phase data written into the device. this allows the data to be written asynchronously as four bytes per 32-bit d - phase word. the data is transferred from this register into the d - phase register after a rising edge on the ldstb input. d d d d d - phase register block this block controls the updating of the d - phase word used in the accumulator. the frequency data from the mux block is loaded into this block after a rising edge on the ldstb input. the sync output, which indicates the instant of frequency change at the output at the end of the pipeline delay, is generated in this block. phase accumulator block this block forms the core of the nco function. it is a high-speed, pipelined, 32-bit parallel accumulator, generating a new sum in every clock cycle. a carry input (the carry in input) allows the resolution of the accumulator to be expanded by means of an auxiliary nco or phase accumulator. the overflow signal is discarded (and is available at the carry out pin), since the required output is the modulo (2 32 ) sum only. this represents the modulo (2 p ) phase angle. sine and cosine lookup table blocks these blocks are the sine and cosine memories. the 10 most significant bits from the phase accumulator are used to address this memory to generate the 8-bit s i n 7-0 and cos 7-0 outputs. mux block the twelve most significant bits from the phase accumulator block are available at the output via the mux blocks as alternatives to the sin 7-0 and cos 7-0 outputs. the mux blocks are controlled by the select a and select b inputs.
5 stel-1172b output signals carry out each time the contents of the phase accumulator exceeds the maximum value that can be represented by a 32 bit number the carry out signal goes high for one clock cycle. when two ncos are cascaded to obtain 64 bit frequency resolution the carry out of the lower order nco must be connected to the carry in of the higher order nco. sin 7-0 and cos 7-0 the sine and cosine functions which are presented on the sin 7-0 and cos 7-0 buses are derived from the 10 most significant bits of the phase accumulator. the 8-bit sine and cosine functions are presented in offset binary format with a minimum value of 00 h and a maximum value of ff h . sin 7 /cos 7 are the msbs. when the phase accumulator is zero, the decimal value of the sin output is 81 h . the nominal phase (in degrees) of the sine and cosine outputs may be determined by multiplying the decimal equivalent of the ten most significant bits of the phase accumulator by (360/1024) and adding (360/2048). the average amplitude over a full cycle is 127.5 decimal. see the description of select a/b and phase for the alternate use of the sin 7- 0 and cos 7-0 buses. phase 11-0 the twelve most significant bits of the 32 bit phase accumulator are available as outputs of the nco. phase 11 is the most significant bit of the 32 bit phase accumulator. the eight most significant phase bits are multiplexed on the sin bus (see description of select a input). the next two significant bits ( phase 2 and phase 3 ) are available continuously on pins 18 and 19 respectively. the two least significant bits ( phase 1 and phase 0 ) are multiplexed on the cos bus (see description of select b input). sync the normally high sync output goes low for one clock cycle 35 rising clock edges after a reset and 34 rising clock edges after a ldstb command. if two ncos are cascaded for higher frequency resolution the sync output of the lower order nco must be connected to the ldstb input of the higher order nco to insure a phase continuous frequency transition. the least significant bit of the input data bus always maps into the least significant bit of the d -phase register field. data 7 through data 0 the eight bit data 7-0 bus is used to program the 32 bit d -phase register. data 0 is the least significant bit of the bus. to change all 32 bits of the d -phase register, the data 7-0 bus must be sequentially used four times in conjunction with the wrn , addr 0 and addr 1 signals. select a when select a is a logic 0, the sine function appears on the sin 7-0 bus. when select a is a logic 1, the eight most significant bits of the phase accumulator appear on this bus. the twelve most significant bits of the 32 bit phase accumulator are available externally. the eight most significant bits appear on the sin bus and are labeled phase 11 (msb) through phase 4 . output pin function: function: pin name select a =0 select a =1 14 sin 7 sin 7 (msb) phase 4 22 sin 6 sin 6 phase 5 13 sin 5 sin 5 phase 6 12 sin 4 sin 4 phase 7 11 sin 3 sin 3 phase 8 10 sin 2 sin 2 phase 9 9 sin 1 sin 1 phase 10 21 sin 0 sin 0 (lsb) phase 11 (msb) select b when select b is a logic 1 the two most significant bits of the cosine function appear on output pins 3 and 15. when select b is a logic 0 pin 15 provides the signal phase 1 and pin 3 provides the signal phase 0 . phase 1 and phase 0 are the eleventh and twelfth most significant bits of the phase accumulator, with phase 0 being the least significant accessible bit. carry in normal operation of the nco requires that the carry in be set at a logic 0. when carry in is a logic 1 the effective value of the d -phase register is increased by one. if two ncos are cascaded together to obtain 64 bits of frequency resolution the carry out of the lower order nco is connected to the carry in of the higher order nco.
stel-1172b 6 electrical characteristics absolute maximum ratings warning : stresses greater than those shown below may cause permanent damage to the device. exposure of the device to these conditions for extended periods may also affect device reliability. all voltages are referenced to v ss . symbol parameter r ange units t stg storage temperature ?40 to +125 c (plastic package) ?65 to +150 c (ceramic package) v ddmax supply voltage on v dd ?0.3 to + 7 volts v i(max) input voltage ?0.3 to v dd + 0.3 volts i i dc input current 10 ma recommended operating conditions symbol p arameter r ange units v dd supply voltage +5 5% volts (commercial) +5 10% volts (military) t a operating temperature (ambient) 0 to +70 c (commercial) ?55 to +125 c (military) d.c. characteristics (operating conditions: v dd = 5.0 v 5%, v ss = 0 v, t a = 0 to 70 c, commercial v dd = 5.0 v 10%, v ss = 0 v, ta = ?55 to 125 c, military) symbol parameter min. typ. max. units conditions i dd(q) supply current, quiescent 1.0 ma static, no clock i dd supply current, operational 3.0 ma/mhz v ih(min) high level input voltage standard operating conditions 2.0 volts logic '1' extended operating conditions 2.25 volts logic '1' v il(max) low level input voltage 0.8 volts logic '0' i ih(min) high level input current 10 a v in = v dd i il(max) low level input current ?15 ?45 ?130 a v in = v ss v oh(min) high level output voltage 2.4 4.5 volts i o = ?4.0 ma v ol(max) low level output voltage 0.2 0.4 volts i o = +4.0 ma i os output short circuit current 20 65 130 ma v out = v dd , v dd = max ?10 ?45 ?130 ma v out = v ss , v dd = max c in input capacitance 2 pf all inputs c out output capacitance 4 pf all outputs { { {
7 stel-1172b (commercial) (military) symbol parameter min. max. min. max. units conditions t rs reset pulse width 30 35 nsec. t sr reset to clock setup 10 10 nsec. t su data or addr 5 6 nsec. to wrn setup, and ldstb to clock setup t hd data or addr 5 6 nsec. to wrn hold, and ldstb to clock hold t ch clock high 8 10 nsec. f clk = max. t cl clock low 8 10 nsec. f clk = max. t w wrn or frld pulse width 20 25 nsec. t cd clock to output delay 5 10 3 13 nsec. load = 15 pf t sd sel a/b to sin/cos delay 20 25 nsec. load = 15 pf nco reset sequence 00 h reset clock sync sin 7-0 35 clock edges 81 h valid 1 234 33 34 35 32 80 h 36 37 t rs t sr 00 h cos 7-0 ff h valid 80 h a.c. characteristics (operating conditions: v dd = 5.0 v 5%, vss = 0 v, t a = 0 to 70 c, commercial v dd = 5.0 v 10%, vss = 0 v, ta = ?55 to 125 c, military)
stel-1172b 8 nco frequency change 1 34 23 35 sin/cos phase new frequency old frequency 35 clock edges don't care don't care select a select b sin 7-0, cos 7-0 ldstb sync clock data 7-0 addr 1-0 wrn 36 37 don't care don't care t su t hd t wr t ch t cl t so t cd t ls
9 stel-1172b spectral purity in many applications the nco is used with a digital to analog converter (dac) to generate an analog waveform which approximates an ideal sinewave. the spectral purity of this synthesized waveform is a function of many variables including the phase and amplitude quantization, the ratio of the clock frequency to output frequency, and the dynamic characteristics of the dac. the sine and cosine signals generated by the stel-1172b have eight bits of amplitude resolution and ten bits of phase resolution which results in spurious levels which are theoretically about -60 dbc. the highest output frequency the nco can generate is half the clock frequency (f c /2), and the spurious components at frequencies greater than f c /2 can be removed by filtering. as the output frequency f o of the nco approaches f c /2 the "image" spur at f c ? f o also approaches f c/ 2 from above. if the programmed output frequency is very close to f c/ 2 it will be virtually impossible to remove this "image" spur by filtering. for this reason, the maximum practical output frequency of the nco should be limited to about 40% of the clock frequency. if the stel-1172b is combined with a high-speed 8-bit video dac, signals with spectral purity of better than ?55 dbc can be generated up to 10 mhz. in this way a signal can be generated in the 66 to 74 mhz band after filtering and upconversion. because of the phase continuous frequency switching characteristics of the stel-1172b this architecture is suitable for frequency hopping spread spectrum applications. typical application high-speed hopping 66-74 mhz synthesizer stel-1172b nco clk 8 data 7-0 2 addr 1-0 ldstb reset clock 8 sine d/a clk bpf 2-10 mhz 64 mhz oscillator bpf 66-74 mhz 66-74 mhz
stel-1172b 10 the higher the resolution of the nco outputs the greater the spectral purity. each additional bit used in quantizing the phase and amplitude of the sine func- tion (assuming equal resolution for each) provides 6 db improvement in spectral purity. for this reason, 12 bits of phase information are brought to the stel- 1172b outputs. it is possible to use these signals with an external sine rom to generate sine waves which have spurious levels as low as -72 dbc. in some applications the nco is used with two dacs to generate analog sine and cosine signals to drive a single sideband mixer. if the sine and cosine functions were ideal a typical single sideband mixer would provide 20 to 30 db of lo and image suppression. this performance can be significantly degraded if an nco is used to generate these signals near the maximum nco frequency. it is recommended that care be taken when designing the stel-1172b into such systems when the output frequency is a significant fraction of the clock frequency. a spectral plot of the nco output after conversion with a dac (ad9703) is shown below. in this case the clock frequency is 50 mhz and the output frequency is programmed to 5.6789 mhz. the maximum spur level observed over the entire useful output frequency range in this case is ?55 dbc. under other conditions the spurious levels may be greater than this due to dac limitations or clock feedthrough problems relating to grounding on the pc board. at higher output frequencies the waveform produced by the dac will have large output changes from sample to sample. for this reason the settling time of the dac should be short in comparison to the clock period . as a general rule the dac used should have the lowest possible glitch energy as well as the shortest possible settling time. typical spectrum output frequency: 5.6789 mhz clock frequency: 50.0 mhz frequency span: 0 to 20 mhz reference level: 0 dbm resolution bandwidth: 1 khz video bandwidth: 3 khz scale: log, 10 db/div

!

"

#

!

!

!

$

!

!"
#$%
&'"()"* + $#%#
$%
&'"()"* + ,-&'"()"* (((

▲Up To Search▲

Price & Availability of STEL-1172BMG

	To Download STEL-1172BMG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .