philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet description quick reference data monolithic temperature and symbol parameter max. unit overload protected logic level power mosfet in a 3 pin plastic surface v ds continuous drain source voltage 50 v mount envelope, intended as a i d continuous drain current 13.5 a general purpose switch for p d total power dissipation 40 w automotive systems and other t j continuous junction temperature 150 ?c applications. r ds(on) drain-source on-state resistance 125 m w applications i isl input supply current v is = 5 v 650 m a general controller for driving lamps motors solenoids heaters features functional block diagram vertical power dmos output stage low on-state resistance overload protection against over temperature overload protection against short circuit load latched overload protection reset by input 5 v logic compatible input level control of power mosfet and supply of overload protection circuits derived from input lower operating input current permits direct drive by micro-controller esd protection on input pin overvoltage clamping for turn off of inductive loads fig.1. elements of the topfet. pinning - sot404 pin configuration symbol pin description 1 input 2 drain 3 source mb drain power mosfet drain source input o/v clamp logic and protection rig 13 mb 2 p d s i topfet june 1996 1 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet limiting values limiting values in accordance with the absolute maximum rating system (iec 134) symbol parameter conditions min. max. unit v ds continuous drain source voltage 1 - - 50 v v is continuous input voltage - 0 6 v i d continuous drain current t mb 25 ?c; v is = 5 v - 13.5 a i d continuous drain current t mb 100 ?c; v is = 5 v - 8.5 a i drm repetitive peak on-state drain current t mb 25 ?c; v is = 5 v - 54 a p d total power dissipation t mb 25 ?c - 40 w t stg storage temperature - -55 150 ?c t j continuous junction temperature 2 normal operation - 150 ?c t sold lead temperature during soldering - 250 ?c overload protection limiting values with the protection supply provided via the input pin, topfet can protect itself from two types of overload. symbol parameter conditions min. max. unit v isp protection supply voltage 3 for valid protection 4 - v over temperature protection v ddp(t) protected drain source supply voltage v is = 5 v - 50 v short circuit load protection 4 v ddp(p) protected drain source supply v is = 5 v - 24 v voltage 5 p dsm instantaneous overload dissipation t mb = 25 ?c - 0.6 kw overvoltage clamping limiting values at a drain source voltage above 50 v the power mosfet is actively turned on to clamp overvoltage transients. symbol parameter conditions min. max. unit i drom repetitive peak clamping current v is = 0 v - 15 a e dsm non-repetitive clamping energy t mb 25 ?c; i dm = 15 a; - 200 mj v dd 20 v; inductive load e drm repetitive clamping energy t mb 95 ?c; i dm = 8 a; - 20 mj v dd 20 v; f = 250 hz esd limiting value symbol parameter conditions min. max. unit v c electrostatic discharge capacitor human body model; - 2 kv voltage c = 250 pf; r = 1.5 k w 1 prior to the onset of overvoltage clamping. for voltages above this value, safe operation is limited by the overvoltage clampi ng energy. 2 a higher t j is allowed as an overload condition but at the threshold t j(to) the over temperature trip operates to protect the switch. 3 the input voltage for which the overload protection circuits are functional. 4 for further information, refer to overload protection characteristics. 5 the short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for p dsm , which is always the case when v ds is less than v ddp(p) maximum. june 1996 2 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet thermal characteristics symbol parameter conditions min. typ. max. unit thermal resistance r th j-mb junction to mounting base - - 2.5 3.1 k/w r th j-a junction to ambient minimum footprint fr4 pcb - 50 - k/w (see fig. 23) static characteristics t mb = 25 ?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (cl)dss drain-source clamping voltage v is = 0 v; i d = 10 ma 50 - - v v (cl)dss drain-source clamping voltage v is = 0 v; i dm = 1 a; t p 300 m s; - - 70 v d 0.01 i dss zero input voltage drain current v ds = 12 v; v is = 0 v - 0.5 10 m a i dss zero input voltage drain current v ds = 50 v; v is = 0 v - 1 20 m a i dss zero input voltage drain current v ds = 40 v; v is = 0 v; t j = 125 ?c - 10 100 m a r ds(on) drain-source on-state v is = 5 v; i dm = 7.5 a; t p 300 m s; - 85 125 m w resistance 1 d 0.01 overload protection characteristics topfet switches off when one of the overload thresholds is reached. it remains latched off until reset by the input. symbol parameter conditions min. typ. max. unit short circuit load protection 2 t mb = 25 ?c; l 10 m h; r l = 10 m w e ds(to) overload threshold energy v dd = 13 v; v is = 5 v - 0.2 - j t d sc response time v dd = 13 v; v is = 5 v - 0.8 - ms i d(sc) drain current 3 v dd = 13 v; v is = 5 v - 25 - a i dm(sc) peak drain current 4 v is = 5 v; v dd = 13 v - 60 - a over temperature protection t j(to) threshold junction temperature v is = 5 v; from i d 3 0.5 a 5 150 - - ?c transfer characteristic t mb = 25 ?c symbol parameter conditions min. typ. max. unit g fs forward transconductance v ds = 10 v; i dm = 7.5 a t p 300 m s; 5 9 - s d 0.01 1 continuous input voltage. the specified pulse width is for the drain current. 2 refer to overload protection limiting values. 3 continuous drain-source supply voltage. pulsed input voltage. 4 continuous input voltage. momentary short circuit load connection. (the higher peak current is due to the effect of capacitan ce cgd). 5 the over temperature protection feature requires a minimum on-state drain source voltage for correct operation. the specified minimum i d ensures this condition. june 1996 3 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet input characteristics t mb = 25 ?c unless otherwise specified. the supply for the logic and overload protection is taken from the input. symbol parameter conditions min. typ. max. unit v is(to) input threshold voltage v ds = 5 v; i d = 1 ma 1.0 1.5 2.0 v i is input supply current normal operation; v is = 5 v 100 200 350 m a v is = 4 v - 160 270 m a v isr protection reset voltage 1 t j = 25 ?c 2.0 2.6 3.5 v t j = 150 ?c 1.0 - - i isl input supply current protection latched; v is = 5 v - 330 650 m a v is = 3.5 v - 240 430 m a v (br)is input breakdown voltage i i = 10 ma 6 - - v r ig input series resistance t j = 25 ?c - 33 - k w to gate of power mosfet t j = 150 ?c - 50 - k w switching characteristics t mb = 25 ?c. r i = 50 w . refer to waveform figure and test circuit. symbol parameter conditions min. typ. max. unit t d on turn-on delay time v dd = 13 v; v is = 5 v - 8 - m s t r rise time resistive load r l = 4 w -40- m s t d off turn-off delay time v dd = 13 v; v is = 0 v - 40 - m s t f fall time resistive load r l = 4 w -35- m s reverse diode limiting value symbol parameter conditions min. max. unit i s continuous forward current t mb 25 ?c; v is = 0 v - 15 a reverse diode characteristics t mb = 25 ?c symbol parameter conditions min. typ. max. unit v sdo forward voltage i s = 15 a; v is = 0 v; t p = 300 m s - 1.0 1.5 v t rr reverse recovery time not applicable 2 ---- envelope characteristics symbol parameter conditions min. typ. max. unit l d internal drain inductance measured from upper edge of tab - 2.5 - nh to centre of die l s internal source inductance measured from source lead - 7.5 - nh soldering point to source bond pad 1 the input voltage below which the overload protection circuits will be reset. 2 the reverse diode of this type is not intended for applications requiring fast reverse recovery. june 1996 4 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet fig.2. normalised limiting power dissipation. p d % = 100 p d /p d (25 ?c) = f(t mb ) fig.3. normalised continuous drain current. i d % = 100 i d /i d (25 ?c) = f(t mb ); conditions: v is = 5 v fig.4. safe operating area. t mb = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.5. transient thermal impedance. z th j-mb = f(t); parameter d = t p /t fig.6. typical on-state characteristics, t j = 25 ?c. id = f(v ds ); parameter v is ; t p = 2 ms fig.7. typical on-state resistance, t j = 25 ?c. r ds(on) = f(i d ); parameter v is ; t p = 2 ms 0 20 40 60 80 100 120 140 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 1e-07 1e-05 1e-03 1e-01 1e+01 t / s zth / (k/w) 10 1 0.1 0.01 0 0.5 0.2 0.1 0.05 0.02 d = t p t p t t p t d d = BUK108-50DL 0 20 40 60 80 100 120 140 tmb / c id% normalised current derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0 2 4 vds / v id / a BUK108-50DL 30 20 10 0 vis / v = 4.5 5 5.5 6 4 3.5 3 1 100 vds / v 100 10 1 0.1 BUK108-50DL 10 id & idm / a overload protection characteristics not shown dc rds(on) = vds/id 100 us 1 ms 10 ms 100 ms tp = 0 20 id / a rds(on) / ohm BUK108-50DL 0.20 0.15 0.10 0.05 0 10 30 vis / v = 5.5 6 5 4.5 4 3.5 june 1996 5 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet fig.8. normalised drain-source on-state resistance. a = r ds(on) /r ds(on) 25 ?c = f(t j ); i d = 7.5 a; v is = 5 v fig.9. typical overload protection characteristics. t d sc = f(p ds ); conditions: v is 3 4 v; t j = 25 ?c. fig.10. normalised limiting overload dissipation. p dsm % =100 p dsm /p dsm (25 ?c) = f(t mb ) fig.11. typical overload protection characteristics. conditions: v dd = 13 v; v is = 5 v; sc load = 30 m w fig.12. typical clamping characteristics, 25 ?c. i d = f(v ds ); conditions: v is = 0 v; t p 50 m s fig.13. input threshold voltage. v is(to) = f(t j ); conditions: i d = 1 ma; v ds = 5 v -60 -40 -20 0 20 40 60 80 100 120 140 tj / c a normalised rds(on) = f(tj) 1.5 1.0 0.5 0 -60 -20 20 60 100 140 180 220 tmb / c energy & time BUK108-50DL 1 0.5 0 energy / j time / ms tj(to) 0.01 1 pds / kw td sc / ms BUK108-50DL 100 10 1 0.1 0.1 pdsm 50 60 70 BUK108-50DL vds / v id / a 20 15 10 5 0 typ. -60 -40 -20 0 20 40 60 80 100 120 140 tmb / c pdsm% 120 100 80 60 40 20 0 -60 -40 -20 0 20 40 60 80 100 120 140 tj / c vis(to) / v 2 1 0 max. typ. min. june 1996 6 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet fig.14. typical dc input characteristics, t j = 25 ?c. i isl & i is = f(v is ); protection latched & normal operation fig.15. typical reverse diode current, t j = 25 ?c. i s = f(v sds ); conditions: v is = 0 v; t p = 250 m s fig.16. test circuit for resistive load switching times. fig.17. typical switching waveforms, resistive load. v dd = 13 v; r l = 4 w ; r i = 50 w , t j = 25 ?c. fig.18. normalised limiting clamping energy. e dsm % = f(t mb ); conditions: i d = 15 a; v is = 5 v fig.19. clamping energy test circuit, r is = 50 w . 0 2 4 6 vis / v iisl & iis / ua BUK108-50DL 600 500 400 300 200 100 0 reset protection latched normal iisl iis 0 100 200 300 400 time / us vis / v & vds / v BUK108-50DL 10 5 0 vis vds 0 20 40 60 80 100 120 140 tmb / c edsm% 120 110 100 90 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 BUK108-50DL vsd / v is / a 60 50 40 30 20 10 0 l d.u.t. vdd ris r 01 vds -id/100 + - shunt vis 0 p d s i topfet id 0 vds 0 vdd v(cl)dss schottky vdd d.u.t. r 0v 0r1 i vis id measure d s i topfet p rl e dsm = 0.5 li d 2 v ( cl ) dss /( v ( cl ) dss - v dd ) june 1996 7 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet fig.20. typical off-state leakage current. i dss = f(t j ); conditions: v ds = 40 v; i is = 0 v. fig.21. normalised input currents (normal & latched). i iso /i iso 25?c & i isl /i isl 25?c = f(t j ); v is = 5 v 0 20 40 60 80 100 120 140 tj / c idss 1 ma 100 ua 10 ua 1 ua 100 na typ. -60 -20 20 60 100 140 180 tj / c iiso & iisl normalised to 25 c 1.5 1 0.5 june 1996 8 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet mechanical data dimensions in mm net mass: 1.4 g fig.22. sot404 : centre pin connected to mounting base. notes 1. epoxy meets ul94 v0 at 1/8". mounting instructions dimensions in mm fig.23. sot404 : minimum pad sizes for surface mounting . notes 1. plastic meets ul94 v0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 june 1996 9 rev 1.000
philips semiconductors product specification powermos transistor BUK108-50DL logic level topfet definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. june 1996 10 rev 1.000
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