1 errata ? releasing reset condition without clock reset during eeprom write serial programming at voltages below 2.9 volts 3. releasing reset condition without clock if an external reset or a watchdog reset occurs while the clock is stopped and the reset is released before the clock is restarted, the internal reset will time out after the start-up delay, which is independent of the external clock. if no external clock pulses are present in the period when internal reset is active, the reset does cor- rectly cause tri-stating of the i/o while the reset is held. however, if the internal reset is relesed before the clock starts running, the part does not clear its i/o reg- isters, nor set pc to 0x00. here, stopping the clock refers to gating the external clock input. power-down mode does not have this issue. problem fix/workaround make sure the clock is running whenever an external reset can be expected. if the watchdog is used, never stop an external clock. 2. reset during eeprom write if reset is activated during eeprom write, the result is not what should be expected. the eeprom write cycle completes as normal, but the address regis- ters are reset to 0. the result is that both the address written and address 0 in the eeprom can be corrupted. problem fix/workaround avoid using address 0 for storage, unless you can guarantee that you will not get a reset during eeprom write. 1. serial programming at voltages below 2.9 volts at voltages below 2.9 volts, serial programming might fail. problem fix/workaround keep v cc at 2.9 volts or higher during in-system programming. 8-bit microcontroller with 1k byte in-system programmable flash at90s1200/a rev. f errata sheet rev. 1190d?09/01
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