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| hitachi single-chip microcomputer h8s/2128 series h8s/2124 series h8s/2128 f-ztat ? h8s/2128 hd6432128w, hd6432128, hd64f2128, hd64f2128v h8s/2127 hd6432127rw, hd6432127r h8s/2126 hd6432126rw, hd6432126r h8s/2124 hd6432124 h8s/2123 hd6432123 h8s/2122 hd6432122 h8s/2120 hd6432120 hardware manual ade-602-114a rev. 2.0 3/12/99 hitachi, ltd. 1997
notice when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. i contents contents ..... .....................................................................................................i preface ....... .....................................................................................................1 section 1 overview ........................................................................................3 1.1 overview ......................................................................................................................... 3 1.2 internal block diagram.................................................................................................... 8 1.3 pin arrangement and functions ....................................................................................... 10 1.3.1 pin arrangement................................................................................................. 10 1.3.2 pin functions in each operating mode ............................................................... 16 1.3.3 pin functions ...................................................................................................... 23 section 2 cpu................................................................................................29 2.1 overview ......................................................................................................................... 29 2.1.1 features .............................................................................................................. 29 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu ................................... 30 2.1.3 differences from h8/300 cpu ............................................................................ 31 2.1.4 differences from h8/300h cpu ......................................................................... 31 2.2 cpu operating modes ..................................................................................................... 32 2.3 address space.................................................................................................................. 37 2.4 register configuration ..................................................................................................... 38 2.4.1 overview ............................................................................................................ 38 2.4.2 general registers................................................................................................ 39 2.4.3 control registers ................................................................................................ 40 2.4.4 initial register values ........................................................................................ 41 2.5 data formats.................................................................................................................... 42 2.5.1 general register data formats ........................................................................... 42 2.5.2 memory data formats ........................................................................................ 44 2.6 instruction set.................................................................................................................. 45 2.6.1 overview ............................................................................................................ 45 2.6.2 instructions and addressing modes..................................................................... 46 2.6.3 table of instructions classified by function ....................................................... 48 2.6.4 basic instruction formats ................................................................................... 57 2.6.5 notes on use of bit-manipulation instructions.................................................... 58 2.7 addressing modes and effective address calculation...................................................... 59 2.7.1 addressing mode................................................................................................ 59 2.7.2 effective address calculation............................................................................. 62 ii 2.8 processing states.............................................................................................................. 65 2.8.1 overview ............................................................................................................ 65 2.8.2 reset state.......................................................................................................... 66 2.8.3 exception-handling state ................................................................................... 67 2.8.4 program execution state..................................................................................... 68 2.8.5 bus-released state ............................................................................................. 68 2.8.6 power-down state .............................................................................................. 68 2.9 basic timing ................................................................................................................... 69 2.9.1 overview ............................................................................................................ 69 2.9.2 on-chip memory (rom, ram)......................................................................... 70 2.9.3 on-chip supporting module access timing....................................................... 71 2.9.4 external address space access timing .............................................................. 72 section 3 mcu operating modes .................................................................. 73 3.1 overview ......................................................................................................................... 73 3.1.1 operating mode selection .................................................................................. 73 3.1.2 register configuration........................................................................................ 74 3.2 register descriptions ....................................................................................................... 74 3.2.1 mode control register (mdcr)......................................................................... 74 3.2.2 system control register (syscr)...................................................................... 75 3.2.3 bus control register (bcr) ............................................................................... 77 3.2.4 serial timer control register (stcr) ................................................................ 78 3.3 operating mode descriptions........................................................................................... 79 3.3.1 mode 1 ............................................................................................................... 79 3.3.2 mode 2 ............................................................................................................... 79 3.3.3 mode 3 ............................................................................................................... 80 3.4 pin functions in each operating mode ............................................................................ 80 3.5 memory map in each operating mode ............................................................................ 81 section 4 exception handling........................................................................ 91 4.1 overview ......................................................................................................................... 91 4.1.1 exception handling types and priority............................................................... 91 4.1.2 exception handling operation............................................................................ 92 4.1.3 exception sources and vector table................................................................... 92 4.2 reset................................................................................................................................ 94 4.2.1 overview ............................................................................................................ 94 4.2.2 reset sequence................................................................................................... 94 4.2.3 interrupts after reset........................................................................................... 96 4.3 interrupts ......................................................................................................................... 97 4.4 trap instruction ............................................................................................................... 98 4.5 stack status after exception handling ............................................................................. 99 4.6 notes on use of the stack ................................................................................................ 100 iii section 5 interrupt controller.........................................................................101 5.1 overview ......................................................................................................................... 101 5.1.1 features .............................................................................................................. 101 5.1.2 block diagram.................................................................................................... 102 5.1.3 pin configuration................................................................................................ 102 5.1.4 register configuration........................................................................................ 103 5.2 register descriptions ....................................................................................................... 104 5.2.1 system control register (syscr)...................................................................... 104 5.2.2 interrupt control registers a to c (icra to icrc)............................................ 105 5.2.3 irq enable register (ier) ................................................................................. 106 5.2.4 irq sense control registers h and l (iscrh, iscrl)...................................... 107 5.2.5 irq status register (isr) ................................................................................... 108 5.2.6 address break control register (abrkcr)....................................................... 109 5.2.7 break address registers a, b, c (bara, barb, barc).................................. 110 5.3 interrupt sources.............................................................................................................. 111 5.3.1 external interrupts .............................................................................................. 111 5.3.2 internal interrupts ............................................................................................... 112 5.3.3 interrupt exception vector table........................................................................ 113 5.4 address breaks ................................................................................................................ 115 5.4.1 features .............................................................................................................. 115 5.4.2 block diagram.................................................................................................... 115 5.4.3 operation............................................................................................................ 116 5.4.4 usage notes........................................................................................................ 116 5.5 interrupt operation........................................................................................................... 118 5.5.1 interrupt control modes and interrupt operation ................................................ 118 5.5.2 interrupt control mode 0 .................................................................................... 121 5.5.3 interrupt control mode 1 .................................................................................... 123 5.5.4 interrupt exception handling sequence .............................................................. 126 5.5.5 interrupt response times ................................................................................... 127 5.6 usage notes..................................................................................................................... 128 5.6.1 contention between interrupt generation and disabling ..................................... 128 5.6.2 instructions that disable interrupts...................................................................... 129 5.6.3 interrupts during execution of eepmov instruction .......................................... 129 5.7 dtc activation by interrupt ............................................................................................ 130 5.7.1 overview ............................................................................................................ 130 5.7.2 block diagram.................................................................................................... 130 5.7.3 operation............................................................................................................ 131 section 6 bus controller ................................................................................133 6.1 overview ......................................................................................................................... 133 6.1.1 features .............................................................................................................. 133 6.1.2 block diagram.................................................................................................... 134 6.1.3 pin configuration................................................................................................ 135 iv 6.1.4 register configuration........................................................................................ 135 6.2 register descriptions ....................................................................................................... 136 6.2.1 bus control register (bcr) ............................................................................... 136 6.2.2 wait state control register (wscr).................................................................. 137 6.3 overview of bus control ................................................................................................. 139 6.3.1 bus specifications .............................................................................................. 139 6.3.2 advanced mode.................................................................................................. 140 6.3.3 normal mode ..................................................................................................... 140 6.3.4 i/o select signal................................................................................................. 140 6.4 basic bus interface .......................................................................................................... 141 6.4.1 overview ............................................................................................................ 141 6.4.2 data size and data alignment............................................................................ 141 6.4.3 valid strobes ...................................................................................................... 143 6.4.4 basic timing ...................................................................................................... 144 6.4.5 wait control....................................................................................................... 146 6.5 burst rom interface........................................................................................................ 148 6.5.1 overview ............................................................................................................ 148 6.5.2 basic timing ...................................................................................................... 148 6.5.3 wait control....................................................................................................... 150 6.6 idle cycle ........................................................................................................................ 150 6.6.1 operation............................................................................................................ 150 6.6.2 pin states in idle cycle....................................................................................... 151 6.7 bus arbitration ................................................................................................................ 151 6.7.1 overview ............................................................................................................ 151 6.7.2 operation............................................................................................................ 151 6.7.3 bus transfer timing........................................................................................... 152 section 7 data transfer controller [h8s/2128 series] ................................... 153 7.1 overview ......................................................................................................................... 153 7.1.1 features .............................................................................................................. 153 7.1.2 block diagram ................................................................................................... 154 7.1.3 register configuration........................................................................................ 155 7.2 register descriptions ....................................................................................................... 156 7.2.1 dtc mode register a (mra)............................................................................ 156 7.2.2 dtc mode register b (mrb) ............................................................................ 158 7.2.3 dtc source address register (sar).................................................................. 159 7.2.4 dtc destination address register (dar).......................................................... 160 7.2.5 dtc transfer count register a (cra) .............................................................. 161 7.2.6 dtc transfer count register b (crb)............................................................... 162 7.2.7 dtc enable registers (dtcer) ........................................................................ 163 7.2.8 dtc vector register (dtvecr) ....................................................................... 164 7.2.9 module stop control register (mstpcr) .......................................................... 165 v 7.3 operation ......................................................................................................................... 166 7.3.1 overview ............................................................................................................ 166 7.3.2 activation sources.............................................................................................. 168 7.3.3 dtc vector table .............................................................................................. 169 7.3.4 location of register information in address space ............................................ 171 7.3.5 normal mode...................................................................................................... 172 7.3.6 repeat mode....................................................................................................... 173 7.3.7 block transfer mode .......................................................................................... 174 7.3.8 chain transfer .................................................................................................... 176 7.3.9 operation timing ............................................................................................... 177 7.3.10 number of dtc execution states ..................................................................... 178 7.3.11 procedures for using the dtc .......................................................................... 179 7.3.12 examples of use of the dtc ............................................................................ 180 7.4 interrupts ......................................................................................................................... 181 7.5 usage notes..................................................................................................................... 181 section 8 i/o ports .........................................................................................183 8.1 overview ......................................................................................................................... 183 8.2 port 1 ............................................................................................................................... 189 8.2.1 overview ............................................................................................................ 189 8.2.2 register configuration........................................................................................ 190 8.2.3 pin functions in each mode ............................................................................... 192 8.2.4 mos input pull-up function .............................................................................. 194 8.3 port 2 ............................................................................................................................... 195 8.3.1 overview ............................................................................................................ 195 8.3.2 register configuration........................................................................................ 196 8.3.3 pin functions in each mode ............................................................................... 198 8.3.4 mos input pull-up function .............................................................................. 199 8.4 port 3 ............................................................................................................................... 200 8.4.1 overview ............................................................................................................ 200 8.4.2 register configuration........................................................................................ 201 8.4.3 pin functions in each mode ............................................................................... 203 8.4.4 mos input pull-up function .............................................................................. 204 8.5 port 4 ............................................................................................................................... 205 8.5.1 overview ............................................................................................................ 205 8.5.2 register configuration........................................................................................ 206 8.5.3 pin functions ...................................................................................................... 207 8.6 port 5 ............................................................................................................................... 210 8.6.1 overview ............................................................................................................ 210 8.6.2 register configuration........................................................................................ 210 8.6.3 pin functions ...................................................................................................... 212 vi 8.7 port 6 ............................................................................................................................... 213 8.7.1 overview ............................................................................................................ 213 8.7.2 register configuration........................................................................................ 213 8.7.3 pin functions...................................................................................................... 215 8.8 port 7 ............................................................................................................................... 218 8.8.1 overview ............................................................................................................ 218 8.8.2 register configuration........................................................................................ 219 8.8.3 pin functions...................................................................................................... 219 section 9 8-bit pwm timers [h8s/2128 series] ........................................... 221 9.1 overview ......................................................................................................................... 221 9.1.1 features .............................................................................................................. 221 9.1.2 block diagram ................................................................................................... 222 9.1.3 pin configuration ............................................................................................... 223 9.1.4 register configuration........................................................................................ 223 9.2 register descriptions ....................................................................................................... 224 9.2.1 pwm register select (pwsl) ............................................................................ 224 9.2.2 pwm data registers (pwdr0 to pwdr15) ...................................................... 226 9.2.3 pwm data polarity registers a and b (pwdpra and pwdprb)..................... 227 9.2.4 pwm output enable registers a and b (pwoera and pwoerb) .................. 228 9.2.5 peripheral clock select register (pcsr) ............................................................ 229 9.2.6 port 1 data direction register (p1ddr)............................................................. 230 9.2.7 port 2 data direction register (p2ddr)............................................................. 231 9.2.8 port 1 data register (p1dr)............................................................................... 232 9.2.9 port 2 data register (p2dr)............................................................................... 233 9.2.10 module stop control register (mstpcr) ........................................................ 234 9.3 operation......................................................................................................................... 235 9.3.1 correspondence between pwm data register contents...................................... 235 section 10 14-bit pwm d/a ......................................................................... 237 10.1 overview ....................................................................................................................... 237 10.1.1 features ............................................................................................................ 237 10.1.2 block diagram.................................................................................................. 238 10.1.3 pin configuration.............................................................................................. 238 10.1.4 register configuration...................................................................................... 239 10.2 register descriptions ..................................................................................................... 240 10.2.1 pwm d/a counter (dacnt)........................................................................... 240 10.2.2 d/a data registers a and b (dadra and dadrb) ....................................... 241 10.2.3 pwm d/a control register (dacr)................................................................ 243 10.2.4 module stop control register (mstpcr) ........................................................ 245 10.3 bus master interface ...................................................................................................... 246 10.4 operation ....................................................................................................................... 249 vii section 11 16-bit free-running timer...........................................................253 11.1 overview ....................................................................................................................... 253 11.1.1 features ............................................................................................................ 253 11.1.2 block diagram.................................................................................................. 254 11.1.3 input and output pins ....................................................................................... 255 11.1.4 register configuration...................................................................................... 256 11.2 register descriptions ..................................................................................................... 257 11.2.1 free-running counter (frc)............................................................................ 257 11.2.2 output compare registers a and b (ocra, ocrb) ........................................ 257 11.2.3 input capture registers a to d (icra to icrd)............................................... 258 11.2.4 output compare registers ar and af (ocrar, ocraf) .............................. 259 11.2.5 output compare register dm (ocrdm) ......................................................... 260 11.2.6 timer interrupt enable register (tier)............................................................ 260 11.2.7 timer control/status register (tcsr).............................................................. 262 11.2.8 timer control register (tcr) .......................................................................... 266 11.2.9 timer output compare control register (tocr)............................................. 268 11.2.10 module stop control register (mstpcr) ...................................................... 270 11.3 operation ....................................................................................................................... 271 11.3.1 frc increment timing ..................................................................................... 271 11.3.2 output compare output timing........................................................................ 272 11.3.3 frc clear timing ............................................................................................ 273 11.3.4 input capture input timing............................................................................... 273 11.3.5 timing of input capture flag (icf) setting ...................................................... 276 11.3.6 setting of output compare flags a and b (ocfa, ocfb)............................... 277 11.3.7 setting of frc overflow flag (ovf) ............................................................... 278 11.3.8 automatic addition of ocra and ocrar/ocraf ........................................ 278 11.3.9 icrd and ocrdm mask signal generation .................................................... 279 11.4 interrupts........................................................................................................................ 280 11.5 sample application........................................................................................................ 280 11.6 usage notes ................................................................................................................... 281 section 12 8-bit timers .................................................................................287 12.1 overview ....................................................................................................................... 287 12.1.1 features ............................................................................................................ 287 12.1.2 block diagram.................................................................................................. 288 12.1.3 pin configuration.............................................................................................. 289 12.1.4 register configuration...................................................................................... 290 12.2 register descriptions ..................................................................................................... 291 12.2.1 timer counter (tcnt)..................................................................................... 291 12.2.2 time constant register a (tcora) ................................................................ 292 12.2.3 time constant register b (tcorb)................................................................. 293 12.2.4 timer control register (tcr) .......................................................................... 294 12.2.5 timer control/status register (tcsr).............................................................. 298 viii 12.2.6 serial/timer control register (stcr) .............................................................. 302 12.2.7 system control register (syscr).................................................................... 303 12.2.8 timer connection register s (tconrs).......................................................... 304 12.2.9 input capture register (ticr) [tmrx additional function] ........................... 305 12.2.10 time constant register c (tcorc) [tmrx additional function] ................ 305 12.2.11 input capture registers r and f (ticrr, ticrf).......................................... 305 12.2.12 timer input select register (tisr) [tmry additional function] .................. 306 12.2.13 module stop control register (mstpcr) ...................................................... 306 12.3 operation ....................................................................................................................... 308 12.3.1 tcnt incrementation timing .......................................................................... 308 12.3.2 compare-match timing.................................................................................... 309 12.3.3 tcnt external reset timing ........................................................................... 311 12.3.4 timing of overflow flag (ovf) setting ........................................................... 311 12.3.5 operation with cascaded connection................................................................ 312 12.4 interrupt sources............................................................................................................ 313 12.5 8-bit timer application example .................................................................................. 314 12.6 usage notes................................................................................................................... 315 12.6.1 contention between tcnt write and clear...................................................... 315 12.6.2 contention between tcnt write and increment .............................................. 316 12.6.3 contention between tcor write and compare-match..................................... 317 12.6.4 contention between compare-matches a and b ............................................... 318 12.6.5 switching of internal clocks and tcnt operation........................................... 319 section 13 timer connection [h8s/2128 series] ........................................... 321 13.1 overview ....................................................................................................................... 321 13.1.1 features ............................................................................................................ 321 13.1.2 block diagram.................................................................................................. 322 13.1.3 input and output pins ....................................................................................... 323 13.1.4 register configuration...................................................................................... 324 13.2 register descriptions ..................................................................................................... 324 13.2.1 timer connection register i (tconri) ........................................................... 324 13.2.2 timer connection register o (tconro) ........................................................ 327 13.2.3 timer connection register s (tconrs).......................................................... 329 13.2.4 edge sense register (sedgr).......................................................................... 331 13.2.5 module stop control register (mstpcr) ........................................................ 334 13.3 operation ....................................................................................................................... 335 13.3.1 pwm decoding (pdc signal generation) ........................................................ 335 13.3.2 clamp waveform generation (cl1/cl2/cl3 signal generation) .................... 336 13.3.3 measurement of 8-bit timer divided waveform period................................... 338 13.3.4 ihi signal and 2fh modification....................................................................... 339 13.3.5 ivi signal fall modification and ihi synchronization ...................................... 341 13.3.6 internal synchronization signal generation ...................................................... 342 13.3.7 hsynco output .............................................................................................. 345 ix 13.3.8 vsynco output .............................................................................................. 346 13.3.9 cblank output .............................................................................................. 347 section 14 watchdog timer (wdt)...............................................................349 14.1 overview ....................................................................................................................... 349 14.1.1 features ............................................................................................................ 349 14.1.2 block diagram.................................................................................................. 350 14.1.3 pin configuration.............................................................................................. 351 14.1.4 register configuration...................................................................................... 352 14.2 register descriptions ..................................................................................................... 352 14.2.1 timer counter (tcnt)..................................................................................... 352 14.2.2 timer control/status register (tcsr).............................................................. 353 14.2.3 system control register (syscr).................................................................... 357 14.2.4 notes on register access.................................................................................. 358 14.3 operation ....................................................................................................................... 358 14.3.1 watchdog timer operation............................................................................... 358 14.3.2 interval timer operation .................................................................................. 360 14.3.3 timing of setting of overflow flag (ovf) ....................................................... 361 14.4 interrupts........................................................................................................................ 361 14.5 usage notes ................................................................................................................... 362 14.5.1 contention between timer counter (tcnt) write and increment .................... 362 14.5.2 changing value of cks2 to cks0 ................................................................... 362 14.5.3 switching between watchdog timer mode and interval timer mode............... 362 14.5.4 counter value in transitions between high-speed mode, ................................ 363 section 15 serial communication interface (sci) ..........................................365 15.1 overview ....................................................................................................................... 365 15.1.1 features ............................................................................................................ 365 15.1.2 block diagram.................................................................................................. 367 15.1.3 pin configuration.............................................................................................. 367 15.1.4 register configuration...................................................................................... 368 15.2 register descriptions ..................................................................................................... 369 15.2.1 receive shift register (rsr)............................................................................ 369 15.2.2 receive data register (rdr) ........................................................................... 369 15.2.3 transmit shift register (tsr)........................................................................... 370 15.2.4 transmit data register (tdr) .......................................................................... 370 15.2.5 serial mode register (smr) ............................................................................. 371 15.2.6 serial control register (scr) ........................................................................... 374 15.2.7 serial status register (ssr).............................................................................. 378 15.2.8 bit rate register (brr) ................................................................................... 382 15.2.9 serial interface mode register (scmr)............................................................ 390 15.2.10 module stop control register (mstpcr) ...................................................... 391 x 15.3 operation ....................................................................................................................... 392 15.3.1 overview .......................................................................................................... 392 15.3.2 operation in asynchronous mode..................................................................... 395 15.3.3 multiprocessor communication function.......................................................... 406 15.3.4 operation in synchronous mode ....................................................................... 413 15.4 sci interrupts................................................................................................................. 421 15.5 usage notes................................................................................................................... 422 section 16 i 2 c bus interface (iic) [h8s/2128 series option] ........................ 425 16.1 overview ....................................................................................................................... 425 16.1.1 features ............................................................................................................ 425 16.1.2 block diagram.................................................................................................. 427 16.1.3 input/output pins.............................................................................................. 428 16.1.4 register configuration...................................................................................... 429 16.2 register descriptions ..................................................................................................... 430 16.2.1 i 2 c bus data register (icdr)........................................................................... 430 16.2.2 slave address register (sar) .......................................................................... 433 16.2.3 second slave address register (sarx) ........................................................... 435 16.2.4 i 2 c bus mode register (icmr) ........................................................................ 436 16.2.5 i 2 c bus control register (iccr) ...................................................................... 440 16.2.6 i 2 c bus status register (icsr) ......................................................................... 446 16.2.7 serial/timer control register (stcr) .............................................................. 450 16.2.8 ddc switch register (ddcswr).................................................................... 451 16.2.9 module stop control register (mstpcr) ........................................................ 454 16.3 operation ....................................................................................................................... 455 16.3.1 i 2 c bus data format ......................................................................................... 455 16.3.2 master transmit operation ............................................................................... 457 16.3.3 master receive operation................................................................................. 459 16.3.4 slave receive operation................................................................................... 461 16.3.5 slave transmit operation ................................................................................. 463 16.3.6 iric setting timing and scl control .............................................................. 465 16.3.7 automatic switching from formatless mode to i 2 c bus format ....................... 466 16.3.8 operation using the dtc ................................................................................. 467 16.3.9 noise canceler.................................................................................................. 468 16.3.10 sample flowcharts.......................................................................................... 469 16.3.11 initialization of internal state.......................................................................... 473 16.4 usage notes................................................................................................................... 474 section 17 a/d converter.............................................................................. 481 17.1 overview ....................................................................................................................... 481 17.1.1 features ............................................................................................................ 481 17.1.2 block diagram.................................................................................................. 482 17.1.3 pin configuration.............................................................................................. 483 xi 17.1.4 register configuration...................................................................................... 484 17.2 register descriptions ..................................................................................................... 485 17.2.1 a/d data registers a to d (addra to addrd) ............................................ 485 17.2.2 a/d control/status register (adcsr).............................................................. 486 17.2.3 a/d control register (adcr) .......................................................................... 489 17.2.4 keyboard comparator control register (kbcomp)......................................... 490 17.2.5 module stop control register (mstpcr) ........................................................ 491 17.3 interface to bus master .................................................................................................. 492 17.4 operation ....................................................................................................................... 493 17.4.1 single mode (scan = 0).................................................................................. 493 17.4.2 scan mode (scan = 1) .................................................................................... 495 17.4.3 input sampling and a/d conversion time........................................................ 497 17.4.4 external trigger input timing .......................................................................... 498 17.5 interrupts........................................................................................................................ 498 17.6 usage notes ................................................................................................................... 499 section 18 ram.............................................................................................505 18.1 overview ....................................................................................................................... 505 18.1.1 block diagram.................................................................................................. 505 18.1.2 register configuration...................................................................................... 506 18.2 system control register (syscr) ................................................................................. 506 18.3 operation ....................................................................................................................... 507 18.3.1 expanded mode (modes 1, 2, and 3 (expe = 1)).............................................. 507 18.3.2 single-chip mode (modes 2 and 3 (expe = 0)) ............................................... 507 section 19 rom.............................................................................................509 19.1 overview ....................................................................................................................... 509 19.1.1 block diagram.................................................................................................. 509 19.1.2 register configuration...................................................................................... 510 19.2 register descriptions ..................................................................................................... 510 19.2.1 mode control register (mdcr) ....................................................................... 510 19.3 operation ....................................................................................................................... 511 19.4 overview of flash memory............................................................................................ 512 19.4.1 features ............................................................................................................ 512 19.4.2 block diagram.................................................................................................. 513 19.4.3 flash memory operating modes ....................................................................... 514 19.4.4 pin configuration.............................................................................................. 518 19.4.5 register configuration...................................................................................... 518 19.5 register descriptions ..................................................................................................... 519 19.5.1 flash memory control register 1 (flmcr1) ................................................... 519 19.5.2 flash memory control register 2 (flmcr2) ................................................... 522 19.5.3 erase block registers 1 and 2 (ebr1, ebr2)................................................... 524 19.5.4 serial/timer control register (stcr) .............................................................. 525 xii 19.6 on-board programming modes...................................................................................... 526 19.6.1 boot mode........................................................................................................ 527 19.6.2 user program mode.......................................................................................... 532 19.7 programming/erasing flash memory ............................................................................. 533 19.7.1 program mode .................................................................................................. 533 19.7.2 program-verify mode....................................................................................... 534 19.7.3 erase mode....................................................................................................... 536 19.7.4 erase-verify mode ........................................................................................... 536 19.8 flash memory protection ............................................................................................... 538 19.8.1 hardware protection ......................................................................................... 538 19.8.2 software protection........................................................................................... 539 19.8.3 error protection ................................................................................................ 539 19.9 interrupt handling when programming/erasing flash memory ...................................... 541 19.10 flash memory writer mode ......................................................................................... 542 19.10.1 prom mode setting....................................................................................... 542 19.10.2 socket adapters and memory map ................................................................. 543 19.10.3 writer mode operation................................................................................... 543 19.10.4 memory read mode ....................................................................................... 545 19.10.5 auto-program mode ....................................................................................... 548 19.10.6 auto-erase mode............................................................................................ 549 19.10.7 status read mode ........................................................................................... 551 19.10.8 status polling.................................................................................................. 552 19.10.9 writer mode transition time ......................................................................... 553 19.10.10 notes on memory programming................................................................... 554 19.11 flash memory programming and erasing precautions.................................................. 555 section 20 clock pulse generator .................................................................. 557 20.1 overview ....................................................................................................................... 557 20.1.1 block diagram.................................................................................................. 557 20.1.2 register configuration...................................................................................... 558 20.2 register descriptions ..................................................................................................... 558 20.2.1 standby control register (sbycr) .................................................................. 558 20.2.2 low-power control register (lpwrcr) ......................................................... 559 20.3 oscillator ....................................................................................................................... 560 20.3.1 connecting a crystal resonator ........................................................................ 560 20.3.2 external clock input......................................................................................... 562 20.4 duty adjustment circuit ................................................................................................ 565 20.5 medium-speed clock divider........................................................................................ 565 20.6 bus master clock selection circuit................................................................................ 565 20.7 subclock input circuit ................................................................................................... 566 20.8 subclock waveform shaping circuit ............................................................................. 566 xiii section 21 power-down state ........................................................................567 21.1 overview ....................................................................................................................... 567 21.1.1 register configuration...................................................................................... 571 21.2 register descriptions ..................................................................................................... 571 21.2.1 standby control register (sbycr) .................................................................. 571 21.2.2 low-power control register (lpwrcr) ......................................................... 573 21.2.3 timer control/status register (tcsr).............................................................. 575 21.2.4 module stop control register (mstpcr) ........................................................ 577 21.3 medium-speed mode..................................................................................................... 578 21.4 sleep mode .................................................................................................................... 579 21.4.1 sleep mode....................................................................................................... 579 21.4.2 clearing sleep mode......................................................................................... 579 21.5 module stop mode......................................................................................................... 579 21.5.1 module stop mode ........................................................................................... 579 21.5.2 usage note ....................................................................................................... 580 21.6 software standby mode ................................................................................................. 581 21.6.1 software standby mode .................................................................................... 581 21.6.2 clearing software standby mode...................................................................... 581 21.6.3 setting oscillation settling time after clearing software standby mode.......... 582 21.6.4 software standby mode application example .................................................. 583 21.6.5 usage note ....................................................................................................... 584 21.7 hardware standby mode................................................................................................ 584 21.7.1 hardware standby mode................................................................................... 584 21.7.2 hardware standby mode timing ...................................................................... 585 21.8 watch mode .................................................................................................................. 585 21.8.1 watch mode ..................................................................................................... 585 21.8.2 clearing watch mode ....................................................................................... 585 21.9 subsleep mode............................................................................................................... 586 21.9.1 subsleep mode.................................................................................................. 586 21.9.2 clearing subsleep mode ................................................................................... 586 21.10 subactive mode ........................................................................................................... 587 21.10.1 subactive mode .............................................................................................. 587 21.10.2 clearing subactive mode ................................................................................ 587 21.11 direct transition .......................................................................................................... 588 21.11.1 overview of direct transition......................................................................... 588 section 22 electrical characteristics.................................................................589 22.1 absolute maximum ratings........................................................................................... 589 22.2 dc characteristics ......................................................................................................... 590 22.3 ac characteristics ......................................................................................................... 598 22.3.1 clock timing.................................................................................................... 599 22.3.2 control signal timing ...................................................................................... 601 xiv 22.3.3 bus timing....................................................................................................... 603 22.3.4 timing of on-chip supporting modules........................................................... 610 22.4 a/d conversion characteristics ..................................................................................... 618 22.5 flash memory characteristics ........................................................................................ 620 22.6 usage note .................................................................................................................... 622 appendix a instruction set............................................................................ 623 a.1 instruction....................................................................................................................... 623 a.2 instruction codes ............................................................................................................ 641 a.3 operation code map ....................................................................................................... 655 a.4 number of states required for execution ....................................................................... 659 a.5 bus states during instruction execution ......................................................................... 672 appendix b internal i/o registers ................................................................. 689 b.1 addresses ........................................................................................................................ 689 b.2 register selection conditions.......................................................................................... 694 b.3 functions......................................................................................................................... 700 appendix c i/o port block diagrams............................................................ 769 c.1 port 1 block diagram...................................................................................................... 769 c.2 port 2 block diagrams .................................................................................................... 771 c.3 port 3 block diagram...................................................................................................... 777 c.4 port 4 block diagrams .................................................................................................... 778 c.5 port 5 block diagrams .................................................................................................... 783 c.6 port 6 block diagrams .................................................................................................... 786 c.7 port 7 block diagrams .................................................................................................... 791 appendix d pin states ................................................................................... 793 d.1 port states in each processing state................................................................................ 793 appendix e timing of transition to and recovery from hardware standby mode ......... ..................................................................................................... 795 e.1 timing of transition to hardware standby mode............................................................ 795 e.2 timing of recovery from hardware standby mode......................................................... 795 appendix f product code lineup .................................................................. 797 appendix g package dimensions .................................................................. 799 1 preface the h8s/2128 series and h8s/2124 series comprise high-performance microcomputers with a 32-bit h8s/2000 cpu core, and a set of on-chip supporting functions required for system configuration. the h8s/2000 cpu can execute basic instructions in one state, and is provided with sixteen internal 16-bit general registers with a 32-bit configuration, and a concise and optimized instruction set. the cpu can handle a 16-mbyte linear address space (architecturally 4 gbytes). programs based on the high-level language c can also be run efficiently. single-power-supply flash memory (f-ztat?*) and mask rom versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. on-chip peripheral functions include a 16-bit free-running timer module (frt), 8-bit timer module (tmr), watchdog timer module (wdt), two pwm timers (pwm and pwmx), a serial communication interface (sci), a/d converter (adc), and i/o ports. an i 2 c bus interface (iic) can also be incorporated as an option. an on-chip data transfer controller (dtc) is also provided, enabling high-speed data transfer without cpu intervention. the h8s/2128 series has all the above on-chip supporting functions, and can also be provided with an iic module as an options. the h8s/2124 series comprises reduced-function versions, with fewer tmr, and no pwm, iic, or dtc modules. use of the h8s/2128 or h8s/2124 series enables compact, high-performance systems to be implemented easily. the various timer functions and their interconnectability (timer connection), plus the interlinked operation of the i 2 c bus interface and data transfer controller (dtc), in particular, make these devices ideal for use in pc monitors. in addition, the combination of f-ztat tm and reduced-function versions is ideal for system applications in which on-chip program memory is essential to meet performance requirements, product start-up times are short, and program modifications may be necessary after end-product assembly. this manual describes the hardware of the h8s/2128 series and h8s/2124 series. refer to the h8s/2600 series and h8s/2000 series programming manual for a detailed description of the instruction set. note: * f-ztat tm (flexible-ztat) is a trademark of hitachi, ltd. 2 on-chip supporting modules series h8s/2128 series h8s/2124 series product names h8s/2128, 2127 h8s/2124, 2123, 2122, 2120 bus controller (bsc) available (8 bits) available (8 bits) data transfer controller (dtc) available 8-bit pwm timer (pwm) 16 14-bit pwm timer (pwmx) 2 16-bit free-running timer (frt) 1 1 8-bit timer (tmr) 4 3 timer connection available watchdog timer (wdt) 2 2 serial communication interface (sci) 2 2 i 2 c bus interface (iic) 2 (option) a/d converter 8 (analog inputs) 8 (expansion a/d inputs) 8 (analog inputs) 8 (expansion a/d inputs) 3 section 1 overview 1.1 overview the h8s/2128 series and h8s/2124 series comprise microcomputers (mcus) built around the h8s/2000 cpu, employing hitachis proprietary architecture, and equipped with supporting modules on-chip. the h8s/2000 cpu has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-mbyte linear address space. the instruction set is upward-compatible with h8/300 and h8/300h cpu instructions at the object-code level, facilitating migration from the h8/300, h8/300l, or h8/300h series. on-chip supporting modules required for system configuration include a data transfer controller (dtc) bus master, rom and ram memory, a16-bit free-running timer module (frt), 8-bit timer module (tmr), watchdog timer module (wdt), two pwm timers (pwm and pwmx), serial communication interface (sci), a/d converter (adc), and i/o ports. an i 2 c bus interface (iic) can also be incorporated as an option. the on-chip rom is either flash memory (f-ztat?*) or mask rom, with a capacity of 128, 96, or 64 kbytes. rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching has been speeded up, and processing speed increased. three operating modes, modes 1 to 3, are provided, and there is a choice of address space and single-chip mode or externally expanded modes. the features of the h8s/2128 series and h8s/2124 series are shown in table 1.1. note: * f-ztat tm is a trademark of hitachi, ltd. 4 table 1.1 overview item specifications cpu general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) high-speed operation suitable for real-time control ? maximum operating frequency: 20 mhz/5 v, 10 mhz/3 v ? high-speed arithmetic and logic operations 8/16/32-bit register-register add/subtract: 50 ns (20 mhz operation) 16 16-bit register-register multiply: 1000 ns (20 mhz operation) 32 16-bit register-register divide: 1000 ns (20 mhz operation) instruction set suitable for high-speed operation ? sixty-five basic instructions ? 8/16/32-bit transfer/arithmetic and logic instructions ? unsigned/signed multiply and divide instructions ? powerful bit-manipulation instructions two cpu operating modes ? normal mode: 64-kbyte address space ? advanced mode: 16-mbyte address space operating modes three mcu operating modes external data bus mode cpu operating mode description on-chip rom initial value maximum value 1 normal expanded mode with on-chip rom disabled disabled 8 bits 8 bits 2 advanced expanded mode with on-chip rom enabled enabled 8 bits 8 bits single-chip mode none 3 normal expanded mode with on-chip rom enabled enabled 8 bits 8 bits single-chip mode none bus controller 2-state or 3-state access space can be designated for external expansion areas number of program wait states can be set for external expansion areas 5 table 1.1 overview (cont) item specifications data transfer controller (dtc) (h8s/2128 series) can be activated by internal interrupt or software multiple transfers or multiple types of transfer possible for one activation source transfer possible in repeat mode, block transfer mode, etc. request can be sent to cpu for interrupt that activated dtc 16-bit free-running timer module (frt: 1 channel) one 16-bit free-running counter (also usable for external event counting) two output compare outputs four input capture inputs (with buffer operation capability) 8-bit timer module (2 channels: tmr0, tmr1) each channel has: one 8-bit up-counter (also usable for external event counting) two timer constant registers the two channels can be connected timer connection and 8-bit timer module (2 channels: tmrx, tmry) (timer connection and tmrx provided in h8s/2128 series) input/output and frt, tmr1, tmrx, tmry can be interconnected measurement of input signal or frequency-divided waveform pulse width and cycle (frt, tmr1) output of waveform obtained by modification of input signal edge (frt, tmr1) determination of input signal duty cycle (tmrx) output of waveform synchronized with input signal (frt, tmrx, tmry) automatic generation of cyclical waveform (frt, tmry) watchdog timer module (wdt: 2 channels) watchdog timer or interval timer function selectable subclock operation capability (channel 1 only) 8-bit pwm timer module (pwm) (h8s/2128 series) up to 16 outputs pulse duty cycle settable from 0 to 100% resolution: 1/256 1.25 mhz maximum carrier frequency (20 mhz operation) 14-bit pwm timer module (pwmx) (h8s/2128 series) up to 2 outputs resolution: 1/16384 312.5 khz maximum carrier frequency (20 mhz operation) serial communication interface (sci: 2 channels, sci0, sci1) asynchronous mode or synchronous mode selectable multiprocessor communication function 6 table 1.1 overview (cont) item specifications a/d converter resolution: 10 bits input: 8 channels (dedicated analog input pins) 8 channels (expansion a/d input pins) high-speed conversion: 6.7 s minimum conversion time (20 mhz operation) single or scan mode selectable sample-and-hold function a/d conversion can be activated by external trigger or timer trigger i/o ports 43 input/output pins (including 24 with led drive capability) 8 input-only pins memory flash memory or mask rom high-speed static ram product name rom ram h8s/2124, h8s/2128 128 kbytes 4 kbytes h8s/2123 96 kbytes 4 kbytes h8s/2122, h8s/2127 64 kbytes 2 kbytes h8s/2120, h8s/2126 32 kbytes 2 kbytes interrupt controller four external interrupt pins (nmi, ,54 to ,54 ) 33 internal interrupt sources three priority levels settable power-down state medium-speed mode sleep mode module stop mode software standby mode hardware standby mode subclock operation clock pulse generator built-in duty correction circuit packages 64-pin plastic dlp (dp-64s) 64-pin plastic qfp (fp-64a) 80-pin plastic tqfp (tfp-80c) i 2 c bus interface (iic: 2 channels) (option in h8s/2128 series) conforms to philips i 2 c bus interface standard single master mode/slave mode arbitration lost condition can be identified supports two slave addresses 7 table 1.1 overview (cont) item specifications product lineup product code (preliminary) series mask rom versions f-ztat? versions rom/ram (bytes) packages h8s/2128 hd6432128 hd6432128w * hd6432127r hd6432127rw * hd64f2128 128 k/4 k 64 k/2 k dp-64s, fp-64a, tfp-80c hd6432126r hd6432126rw * 32 k/2 k h8s/2124 hd6432124 128 k/4 k hd6432123 96 k/4 k hd6432122 64 k/2 k hd6432120 32 k/2 k note: * w indicates the i 2 c bus option. 8 1.2 internal block diagram an internal block diagram of the h8s/2128 series is shown in figure 1.1, and an internal block diagram of the h8s/2124 series in figure 1.2. peripheral address bus p37/ d7 p36/ d6 p35/ d5 p34/ d4 p33/ d3 p32/ d2 p31/ d1 p30/ d0 p27/ a15/ pw15 /sck1/ cblank p26/ a14/ pw14/rxd1 p25/ a13/ pw13/txd1 p24/ a12/ pw12/ scl1 p23/ a11/ pw11/ sda1 p22/ a10/ pw10 p21/ a9/ pw9 p20/ a8/ pw8 p17/ a7/ pw7 p16/ a6/ pw6 p15/ a5/ pw5 p14/ a4/ pw4 p13/ a3/ pw3 p12/ a2/ pw2 p11/ a1/ pw1/ pwx1 p10/ a0/ pw0/ pwx0 p52/ sck0/ scl0 p51/ rxd0 p50/ txd0 avcc avss p77/ an7 p76/ an6 p75/ an5 p74/ an4 p73/ an3 p72/ an2 p71/ an1 p70/ an0 p47/ wait /sda0 p46/ ?excl p45/ as / ios p44/ wr p43/ rd p42/ irq0 p41/ irq1 p40/ irq2 / adtrg p67/ tmox/tmo1/cin7/hsynco p66/ ftob/tmri1/cin6/csynci p65/ ftid/tmci1/cin5/hsynci p64/ ftic/tmo0/cin4/clampo p63/ ftib/tmri0/cin3/vfbacki p62/ ftia /cin2/ vsynci/tmiy p61/ ftoa/cin1/vsynco p60/ ftci/tmci0/cin0/hfbacki/tmix rom ram wdt0, wdt1 8-bit timer 4ch timer connection (tmr0, tmr1, tmrx, tmry) 8-bit pwm 14-bit pwm sci 2ch iic 2ch (option) 10-bit a/d 16-bit frt vcc1 vcc2 vss vss md1 md0 extal xtal stby res nmi h8s/2000 cpu dtc interrupt controller internal address bus internal data bus peripheral data bus port 4 bus controller clock pulse generator port 6 port 7 port 5 port 1 port 2 port 3 figure 1.1 internal block diagram of h8s/2128 series 9 p37/ d7 p36/ d6 p35/ d5 p34/ d4 p33/ d3 p32/ d2 p31/ d1 p30/ d0 p27/ a15/sck1 p26/ a14/rxd1 p25/ a13/txd1 p24/ a12 p23/ a11 p22/ a10 p21/ a9 p20/ a8 p17/ a7 p16/ a6 p15/ a5 p14/ a4 p13/ a3 p12/ a2 p11/ a1 p10/ a0 p52/ sck0 p51/ rxd0 p50/ txd0 avcc avss p77/ an7 p76/ an6 p75/ an5 p74/ an4 p73/ an3 p72/ an2 p71/ an1 p70/ an0 p47/ wait p46/ ?excl p45/ as / ios p44/ wr p43/ rd p42/ irq0 p41/ irq1 p40/ irq2 / adtrg p67/tmo1/cin7 p66/ ftob/tmri1/cin6 p65/ ftid/tmci1/cin5 p64/ ftic/tmo0/cin4 p63/ ftib/tmri0/cin3 p62/ ftia /cin2 /tmiy p61/ ftoa/cin1 p60/ ftci/tmci0/cin0 rom ram vcc1 vcc2 vss vss md1 md0 extal xtal stby res nmi h8s/2000 cpu clock pulse generator interrupt controller port 4 port 6 port 7 8-bit timer 3ch (tmr0, tmr1, tmry) 16-bit frt wdt0, wdt1 sci 2ch 10-bit a/d peripheral address bus internal address bus internal data bus peripheral data bus bus controller port 5 port 1 port 2 port 3 figure 1.2 internal block diagram of h8s/2124 series 10 1.3 pin arrangement and functions 1.3.1 pin arrangement the pin arrangement of the h8s/2128 series is shown in figures 1.3 to 1.5, and the pin arrangement of the h8s/2124 series in figures 1.6 to 1.8. adtrg / irq2 /p40 p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 p10/a0/pw0/pwx0 p11/a1/pw1/pwx1 p12/a2/pw2 p13/a3/pw3 p14/a4/pw4 p15/a5/pw5 p16/a6/pw6 p17/a7/pw7 vss p20/a8/pw8 p21/a9/pw9 p22/a10/pw10 p23/a11/pw11/sda1 p24/a12/pw12/scl1 p25/a13/pw13/txd1 p26/a14/pw14/rxd1 p27/a15/pw15/sck1/cblank vcc1 p66/ftob/tmri1/cin6/csynci p65/ftid/tmci1/cin5/hsynci p64/ftic/tmo0/cin4/clampo p63/ftib/tmri0/cin3/vfbacki p62/ftia/cin2/vsynci/tmiy p67/tmox/tmo1/cin7/hsynco irq1 /p41 irq0 /p42 rd /p43 wr /p44 ios / as /p45 excl/?p46 sda0/ wait /p47 txd0/p50 rxd0/p51 scl0/sck0/p52 res nmi vcc2 stby vss xtal extal md1 md0 avss an0/p70 an1/p71 an2/p72 an3/p73 an4/p74 an5/p75 an6/p76 an7/p77 avcc tmix/hfbacki/cin0/tmci0/ftci/p60 vsynco/cin1/ftoa/p61 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 1.3 pin arrangement of h8s/2128 series (dp-64s: top view) 11 an3/p73 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 cblank/sck1/pw15/a15/p27 p10/a0/pw0/pwx0 p11/a1/pw1/pwx1 p12/a2/pw2 p13/a3/pw3 p14/a4/pw4 p15/a5/pw5 p16/a6/pw6 p17/a7/pw7 vss p20/a8/pw8 p21/a9/pw9 p22/a10/pw10 p23/a11/pw11/sda1 p24/a12/pw12/scl1 p25/a13/pw13/txd1 p26/a14/pw14/rxd1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 txd0/p50 rxd0/p51 scl0/sck0/p52 res nmi vcc2 stby vss xtal extal md1 md0 avss an0/p70 an1/p71 an2/p72 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p47/ wait /sda0 p46/?excl p45/ as / ios p44/ wr p43/ rd p42/ irq0 p41/ irq1 p40/ irq2 / adtrg p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 tmix/hfbacki/cin0/tmci0/ftci/p60 vsynco/cin1/ftoa/p61 tmiy/vsynci/cin2/ftia/p62 vfbacki /cin3/tmri0/ftib/p63 clampo/cin4/tmo0/ftic/p64 hsynci/cin5/tmci1/ftid/p65 csynci/cin6/tmri1/ftob/p66 hsynco/cin7/tmo1/tmox/p67 vcc1 an4/p74 an5/p75 an6/p76 an7/p77 avcc figure 1.4 pin arrangement of h8s/2128 series (fp-64a: top view) 12 an3/p73 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 cblank/sck1/pw15/a15/p27 p10/a0/pw0/pwx0 p11/a1/pw1/pwx1 p12/a2/pw2 p13/a3/pw3 p14/a4/pw4 p15/a5/pw5 p16/a6/pw6 p17/a7/pw7 vss vss vss vss vss p20/a8/pw8 p21/a9/pw9 p22/a10/pw10 p23/a11/pw11/sda1 p24/a12/pw12/scl1 p25/a13/pw13/txd1 p26/a14/pw14/rxd1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 txd0/p50 rxd0/p51 scl0/sck0/p52 res nmi vcc2 stby vss vss vss vss xtal extal md1 vss md0 avss an1/p71 an0/p70 an2/p72 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 44 43 42 41 p47/ wait /sda0 p46/?excl p45/ as / ios p44/ wr vss vss vss vss p43/ rd p42/ irq0 p41/ irq1 p40/ irq2 / adtrg p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 tmix/hfbacki/cin0/tmci0/ftci/p60 vsynco/cin1/ftoa/p61 tmiy/vsynci/cin2/ftia/p62 vfbacki /cin3/tmri0/ftib/p63 clampo/cin4/tmo0/ftic/p64 hsynci/cin5/tmci1/ftid/p65 csynci/cin6/tmri1/ftob/p66 hsynco/cin7/tmo1/tmox/p67 vcc1 vss vss vss vss an4/p74 an5/p75 an6/p76 an7/p77 avcc figure 1.5 pin arrangement of h8s/2128 series (tfp-80c: top view) 13 adtrg / irq2 /p40 p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 p10/a0 p11/a1 p12/a2 p13/a3 p14/a4 p15/a5 p16/a6 p17/a7 vss p20/a8 p21/a9 p22/a10 p23/a11 p24/a12 p25/a13/txd1 p26/a14/rxd1 p27/a15/sck1 vcc1 p66/ftob/tmri1/cin6 p65/ftid/tmci1/cin5 p64/ftic/tmo0/cin4 p63/ftib/tmri0/cin3 p62/ftia/cin2/tmiy p67/tmo1/cin7 irq1 /p41 irq0 /p42 rd /p43 wr /p44 ios / as /p45 excl/?p46 wait /p47 txd0/p50 rxd0/p51 sck0/p52 res nmi vcc2 stby vss xtal extal md1 md0 avss an0/p70 an1/p71 an2/p72 an3/p73 an4/p74 an5/p75 an6/p76 an7/p77 avcc cin0/tmci0/ftci/p60 cin1/ftoa/p61 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 1.6 pin arrangement of h8s/2124 series (dp-64s: top view) 14 an3/p73 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 a15/p27/sck1 p10/a0 p11/a1 p12/a2 p13/a3 p14/a4 p15/a5 p16/a6 p17/a7 vss p20/a8 p21/a9 p22/a10 p23/a11 p24/a12 p25/a13/txd1 p26/a14/rxd1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 txd0/p50 rxd0/p51 sck0/p52 res nmi vcc2 stby vss xtal extal md1 md0 avss an0/p70 an1/p71 an2/p72 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p47/ wait p46/?excl p45/ as / ios p44/ wr p43/ rd p42/ irq0 p41/ irq1 p40/ irq2 / adtrg p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 cin0/tmci0/ftci/p60 cin1/ftoa/p61 tmiy/cin2/ftia/p62 cin3/tmri0/ftib/p63 cin4/tmo0/ftic/p64 cin5/tmci1/ftid/p65 cin6/tmri1/ftob/p66 cin7/tmo1/p67 vcc1 an4/p74 an5/p75 an6/p76 an7/p77 avcc figure 1.7 pin arrangement of h8s/2124 series (fp-64a: top view) 15 an3/p73 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 a15/p27/sck1 p10/a0 p11/a1 p12/a2 p13/a3 p14/a4 p15/a5 p16/a6 p17/a7 vss vss vss vss vss p20/a8 p21/a9 p22/a10 p23/a11 p24/a12 p25/a13/txd1 p26/a14/rxd1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 txd0/p50 rxd0/p51 sck0/p52 res nmi vcc2 stby vss vss vss vss xtal extal md1 vss md0 avss an1/p71 an0/p70 an2/p72 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 44 43 42 41 p47/ wait p46/?excl p45/ as / ios p44/ wr vss vss vss vss p43/ rd p42/ irq0 p41/ irq1 p40/ irq2 / adtrg p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 cin0/tmci0/ftci/p60 cin1/ftoa/p61 tmiy/cin2/ftia/p62 cin3/tmri0/ftib/p63 cin4/tmo0/ftic/p64 cin5/tmci1/ftid/p65 cin6/tmri1/ftob/p66 cin7/tmo1/p67 vcc1 vss vss vss vss an4/p74 an5/p75 an6/p76 an7/p77 avcc figure 1.8 pin arrangement of h8s/2124 series (tfp-80c: top view) 16 1.3.2 pin functions in each operating mode tables 1.2 and 1.3 show the pin functions of the h8s/2128 series and h8s/2124 series in each of the operating modes. table 1.2 h8s/2128 series pin functions in each operating mode pin name pin no. dp-64s fp-64a tfp-80c expanded modes mode 2 (expe = 1) mode 1 mode 3 (expe = 1) single-chip modes mode 2 (expe = 0) mode 3 (expe = 0) flash memory writer mode 1 57 71 p40/ ,54 / $'75* p40/ ,54 / $'75* p40/ ,54 / $'75* vcc 2 58 72 p41/ ,54 p41/ ,54 p41/ ,54 vcc 73 vss vss vss vss 3 59 74 p42/ ,54 p42/ ,54 p42/ ,54 vss 46075 5' 5' p43 :( 76 vss vss vss vss 56177 :5 :5 p44 fa15 66278 $6 / ,26 $6 / ,26 p45 fa16 7 63 79 ?/p46/excl p46/?/excl p46/?/excl nc 8 64 80 p47/ :$,7 /sda0 p47/ :$,7 /sda0 p47/sda0 vcc 9 1 1 p50/txd0 p50/txd0 p50/txd0 nc 10 2 2 p51/rxd0 p51/rxd0 p51/rxd0 fa17 11 3 3 p52/sck0/scl0 p52/sck0/scl0 p52/sck0/scl0 nc 12 4 4 5(6 5(6 5(6 5(6 13 5 5 nmi nmi nmi fa9 14 6 6 vcc2 vcc2 vcc2 vcc 15 7 7 67%< 67%< 67%< vcc 16 8 8 vss vss vss vss 9 vss vss vss vss 10 vss vss vss vss 17 9 11 xtal xtal xtal xtal 12 vss vss vss vss 18 10 13 extal extal extal extal 19 11 14 md1 md1 md1 vss 17 table 1.2 h8s/2128 series pin functions in each operating mode (cont) pin name pin no. dp-64s fp-64a tfp-80c expanded modes mode 2 (expe = 1) mode 1 mode 3 (expe = 1) single-chip modes mode 2 (expe = 0) mode 3 (expe = 0) flash memory writer mode 15 vss vss vss vss 20 12 16 md0 md0 md0 vss 21 13 17 avss avss avss vss 22 14 18 p70/an0 p70/an0 p70/an0 nc 23 15 19 p71/an1 p71/an1 p71/an1 nc 24 16 20 p72/an2 p72/an2 p72/an2 nc 25 17 21 p73/an3 p73/an3 p73/an3 nc 26 18 22 p74/an4 p74/an4 p74/an4 nc 27 19 23 p75/an5 p75/an5 p75/an5 nc 24 vss vss vss vss 28 20 25 p76/an6 p76/an6 p76/an6 nc 29 21 26 p77/an7 p77/an7 p77/an7 nc 30 22 27 avcc avcc avcc vcc 31 23 28 p60/ftci/tmci0/ cin0/hfbacki/ tmix p60/ftci/tmci0/ cin0/hfbacki/ tmix p60/ftci/tmci0/ cin0/hfbacki/ tmix nc 29 vss vss vss vss 32 24 30 p61/ftoa/cin1/ vsynco p61/ftoa/cin1/ vsynco p61/ftoa/cin1/ vsynco nc 31 vss vss vss vss 33 25 32 p62/ftia/cin2/ vsynci/tmiy p62/ftia/cin2/ vsynci/tmiy p62/ftia/cin2/ vsynci/tmiy nc 34 26 33 p63/ftib/tmri0/ cin3/vfbacki p63/ftib/tmri0/ cin3/vfbacki p63/ftib/tmri0/ cin3/vfbacki nc 34 vss vss vss vss 35 27 35 p64/ftic/tmo0/ cin4/clampo p64/ftic/tmo0/ cin4/clampo p64/ftic/tmo0/ cin4/clampo nc 36 28 36 p65/ftid/tmci1/ cin5/hsynci p65/ftid/tmci1/ cin5/hsynci p65/ftid/tmci1/ cin5/hsynci nc 37 29 37 p66/ftob/tmri1/ cin6/csynci p66/ftob/tmri1/ cin6/csynci p66/ftob/tmri1/ cin6/csynci nc 18 table 1.2 h8s/2128 series pin functions in each operating mode (cont) pin name pin no. dp-64s fp-64a tfp-80c expanded modes mode 2 (expe = 1) mode 1 mode 3 (expe = 1) single-chip modes mode 2 (expe = 0) mode 3 (expe = 0) flash memory writer mode 38 30 38 p67/tmox/ tmo1/cin7/ hsynco p67/tmox/tmo1/ cin7/hsynco p67/tmo1/tmox/ cin7/hsynco vss 39 31 39 vcc1 vcc1 vcc1 vcc 40 32 40 a15 a15/p27/pw15/ sck1/cblank p27/pw15/ sck1/cblank &( 41 33 41 a14 a14/p26/pw14/ rxd1 p26/pw14/ rxd1 fa14 42 34 42 a13 a13/p25/pw13/ txd1 p25/pw13/ txd1 fa13 43 35 43 a12 a12/p24/pw12/ scl1 p24/pw12/scl1 fa12 44 36 44 a11 a11/p23/pw11/ sda1 p23/pw11/sda1 fa11 45 vss vss vss vss 45 37 46 a10 a10/p22/pw10 p22 /pw10 fa10 46 38 47 a9 a9 /p21/pw9 p21/pw9 2( 47 39 48 a8 a8 /p20 /pw8 p20/pw8 fa8 49 vss vss vss vss 48 40 50 vss vss vss vss 51 vss vss vss vss 49 41 52 a7 a7/p17/pw7 p17/pw7 fa7 50 42 53 a6 a6/p16/pw6 p16/pw6 fa6 51 43 54 a5 a5/p15/pw5 p15/pw5 fa5 55 vss vss vss vss 52 44 56 a4 a4/p14/pw4 p14/pw4 fa4 53 45 57 a3 a3/p13/pw3 p13/pw3 fa3 54 46 58 a2 a2/p12/pw2 p12/pw2 fa2 55 47 59 a1 a1/p11/pw1/pwx 1 p11/pw1/pwx1 fa1 56 48 60 a0 a0/p10/pw0/pwx 0 p10/pw0/pwx0 fa0 19 table 1.2 h8s/2128 series pin functions in each operating mode (cont) pin name pin no. dp-64s fp-64a tfp-80c expanded modes mode 2 (expe = 1) mode 1 mode 3 (expe = 1) single-chip modes mode 2 (expe = 0) mode 3 (expe = 0) flash memory writer mode 57 49 61 d0 d0 p30 fo0 58 50 62 d1 d1 p31 fo1 59 51 63 d2 d2 p32 fo2 60 52 64 d3 d3 p33 fo3 61 53 65 d4 d4 p34 fo4 66 vss vss vss vss 62 54 67 d5 d5 p35 fo5 63 55 68 d6 d6 p36 fo6 64 56 69 d7 d7 p37 fo7 70 vss vss vss vss 20 table 1.3 h8s/2124 series pin functions in each operating mode pin name pin no. dp-64s fp-64a tfp-80c expanded modes mode 2 (expe = 1) mode 1 mode 3 (expe = 1) single-chip modes mode 2 (expe = 0) mode 3 (expe = 0) flash memory writer mode 1 57 71 p40/ ,54 / $'75* p40/ ,54 / $'75* p40/ ,54 / $'75* vcc 2 58 72 p41/ ,54 p41/ ,54 p41/ ,54 vcc 73 vss vss vss vss 3 59 74 p42/ ,54 p42/ ,54 p42/ ,54 vss 46075 5' 5' p43 :( 76 vss vss vss vss 56177 :5 :5 p44 fa15 66278 $6 / ,26 $6 / ,26 p45 fa16 7 63 79 p46/?/excl p46/?/excl p46/?/excl nc 8 64 80 p47/ :$,7 p47/ :$,7 p47 vcc 9 1 1 p50/txd0 p50/txd0 p50/txd0 nc 10 2 2 p51/rxd0 p51/rxd0 p51/rxd0 fa17 11 3 3 p52/sck0 p52/sck0 p52/sck0 nc 12 4 4 5(6 5(6 5(6 5(6 13 5 5 nmi nmi nmi fa9 14 6 6 vcc2 vcc2 vcc2 vcc 15 7 7 67%< 67%< 67%< vcc 16 8 8 vss vss vss vss 9 vss vss vss vss 10 vss vss vss vss 17 9 11 xtal xtal xtal xtal 12 vss vss vss vss 18 10 13 extal extal extal extal 19 11 14 md1 md1 md1 vss 15 vss vss vss vss 20 12 16 md0 md0 md0 vss 21 13 17 avss avss avss vss 22 14 18 p70/an0 p70/an0 p70/an0 nc 21 table 1.3 h8s/2124 series pin functions in each operating mode (cont) pin name pin no. dp-64s fp-64a tfp-80c expanded modes mode 2 (expe = 1) mode 1 mode 3 (expe = 1) single-chip modes mode 2 (expe = 0) mode 3 (expe = 0) flash memory writer mode 23 15 19 p71/an1 p71/an1 p71/an1 nc 24 16 20 p72/an2 p72/an2 p72/an2 nc 25 17 21 p73/an3 p73/an3 p73/an3 nc 26 18 22 p74/an4 p74/an4 p74/an4 nc 27 19 23 p75/an5 p75/an5 p75/an5 nc 24 vss vss vss vss 28 20 25 p76/an6 p76/an6 p76/an6 nc 29 21 26 p77/an7 p77/an7 p77/an7 nc 30 22 27 avcc avcc avcc vcc 31 23 28 p60/ftci/tmci0/ cin0 p60/ftci/tmci0/ cin0 p60/ftci/tmci0/ cin0 nc 29 vss vss vss vss 32 24 30 p61/ftoa/cin1 p61/ftoa/cin1 p61/ftoa/cin1 nc 31 vss vss vss vss 33 25 32 p62/ftia/cin2/ tmiy p62/ftia/cin2/ tmiy p62/ftia/cin2/ tmiy nc 34 26 33 p63/ftib/tmri0/ cin3 p63/ftib/tmri0/ cin3 p63/ftib/tmri0/ cin3 nc 34 vss vss vss vss 35 27 35 p64/ftic/tmo0/ cin4 p64/ftic/tmo0/ cin4 p64/ftic/tmo0/ cin4 nc 36 28 36 p65/ftid/tmci1/ cin5 p65/ftid/tmci1/ cin5 p65/ftid/tmci1/ cin5 nc 37 29 37 p66/ftob/tmri1/ cin6 p66/ftob/tmri1/ cin6 p66/ftob/tmri1/ cin6 nc 38 30 38 p67/tmo1/cin7 p67/tmo1/cin7 p67/tmo1/cin7 vss 39 31 39 vcc1 vcc1 vcc1 vcc 40 32 40 a15 a15/p27/sck1 p27/sck1 &( 41 33 41 a14 a14/p26/rxd1 p26/rxd1 fa14 22 table 1.3 h8s/2124 series pin functions in each operating mode (cont) pin name pin no. dp-64s fp-64a tfp-80c expanded modes mode 2 (expe = 1) mode 1 mode 3 (expe = 1) single-chip modes mode 2 (expe = 0) mode 3 (expe = 0) flash memory writer mode 42 34 42 a13 a13/p25/txd1 p25/txd1 fa13 43 35 43 a12 a12/p24 p24 fa12 44 36 44 a11 a11/p23 p23 fa11 45 vss vss vss vss 45 37 46 a10 a10/p22 p22 fa10 46 38 47 a9 a9 /p21 p21 2( 47 39 48 a8 a8 /p20 p20 fa8 49 vss vss vss vss 48 40 50 vss vss vss vss 51 vss vss vss vss 49 41 52 a7 a7/p17 p17 fa7 50 42 53 a6 a6/p16 p16 fa6 51 43 54 a5 a5/p15 p15 fa5 55 vss vss vss vss 52 44 56 a4 a4/p14 p14 fa4 53 45 57 a3 a3/p13 p13 fa3 54 46 58 a2 a2/p12 p12 fa2 55 47 59 a1 a1/p11 p11 fa1 56 48 60 a0 a0/p10 p10 fa0 57 49 61 d0 d0 p30 fo0 58 50 62 d1 d1 p31 fo1 59 51 63 d2 d2 p32 fo2 60 52 64 d3 d3 p33 fo3 61 53 65 d4 d4 p34 fo4 66 vss vss vss vss 62 54 67 d5 d5 p35 fo5 63 55 68 d6 d6 p36 fo6 64 56 69 d7 d7 p37 fo7 70 vss vss vss vss 23 1.3.3 pin functions table 1.4 summarizes the functions of the h8s/2128 series and h8s/2124 series pins. table 1.4 pin functions pin no. type symbol dp-64s fp-64a tfp-80c i/o name and function power supply vcc1, vcc2 14, 39 6, 31 6, 39 input power supply: for connection to the power supply. all vcc1 and vcc2 pins should be connected to the system power supply. vss 16, 48 8, 40 8, 9, 10, 12, 15, 24, 29, 31, 34, 45, 49, 50, 51, 55, 66, 70, 73, 76 input ground: for connection to the power supply (0 v). all vss pins should be connected to the system power supply (0 v). clock xtal 17 9 11 input connected to a crystal oscillator. see section 21, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. extal 18 10 13 input connected to a crystal oscillator. the extal pin can also input an external clock. see section 21, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. ? 7 63 79 output system clock: supplies the system clock to external devices. excl 7 63 79 input external subclock input: input a 32.768 khz external subclock. 24 table 1.4 pin functions (cont) pin no. type symbol dp-64s fp-64a tfp-80c i/o name and function operating mode control md1 md0 19 20 11 12 14 16 input mode pins: these pins set the operating mode. the relation between the settings of pins md1 and md0 and the operating mode is shown below. these pins should not be changed while the mcu is operating. md1 md0 operating mode description 0 1 mode 1 normal expanded mode with on-chip rom disabled 1 0 mode 2 advanced expanded mode with on-chip rom enabled single-chip mode 1 1 mode 3 normal expanded mode with on-chip rom enabled single-chip mode system control 5(6 12 4 4 input reset input: when this pin is driven low, the chip is reset. 67%< 15 7 7 input standby: when this pin is driven low, a transition is made to hardware standby mode. address bus a15 to a0 40 to 47, 49 to 56 32 to 39, 41 to 48 40 to 44, 46 to 48, 52 to 54, 56 to 60 output address bus: these pins output an address. data bus d7 to d0 64 to 57 56 to 49 69 to 67, 65 to 61 input/ output data bus: these pins constitute a bidirectional data bus. 25 table 1.4 pin functions (cont) pin no. type symbol dp-64s fp-64a tfp-80c i/o name and function bus control :$,7 8 64 80 input wait: requests insertion of a wait state in the bus cycle when accessing external 3-state address space. 5' 4 60 75 output read: when this pin is low, it indicates that the external address space is being read. :5 5 61 77 output write: when this pin is low, it indicates that the external address space is being written to. $6 / ,26 6 62 78 output address strobe: when this pin is low, it indicates that address output on the address bus is valid. interrupt signals nmi 13 5 5 input nonmaskable interrupt: requests a nonmaskable interrupt. ,54 to ,54 1 to 3 57 to 59 71, 72, 74 input interrupt request 0 to 2: these pins request a maskable interrupt 16-bit free- running timer (frt) ftci 31 23 28 input frt counter clock input: input pin for an external clock signal for the free-running counter (frc). ftoa 32 24 30 output frt output compare a output: the output compare a output pin. ftob 37 29 37 output frt output compare b output: the output compare b output pin. ftia 33 25 32 input frt input capture a input: the input capture a input pin. ftib 34 26 33 input frt input capture b input: the input capture b input pin. ftic 25 27 35 input frt input capture c input: the input capture c input pin. ftid 36 28 36 input frt input capture d input: the input capture d input pin. 26 table 1.4 pin functions (cont) pin no. type symbol dp-64s fp-64a tfp-80c i/o name and function 8-bit timer (tmr0, tmr1, tmrx, tmry) tmo0 tmo1 tmox tmci0 tmci1 35 38 38 31 36 27 30 30 23 28 35 38 38 28 36 output input compare-match output: tmr0, tmr1, and tmrx compare-match output pins. counter external clock input: tmr0 and tmr1 input pins for the external clock input to the counter. tmri0 tmri1 34 37 26 29 33 37 input counter external reset input: tmr0 and tmr1 counter reset input pins. tmix tmiy 31 33 23 25 28 32 input counter external clock input and reset input: tmrx and tmry counter clock input pins and reset input pins. serial com- munication interface (sci0, sci1) txd0 txd1 rxd0 rxd1 9 42 10 41 1 34 2 33 1 42 2 41 output input transmit data: data output pins. receive data: data input pins. sck0 sck1 11 40 3 32 3 40 input/ output serial clock: clock input/output pins. the sck0 output type is nmos push-pull. (h8s/2128 series only) a/d converter an7 to an0 29 to 22 21 to 14 26, 25, 23 to 18 input analog 7 to 0: analog input pins. cin0 to cin7 31 to 38 23 to 30 28, 30, 32 to 33, 35 to 38 input expansion a/d input: expansion a/d input pins can be connected to the a/d converter, but as they are also used as digital i/o pins, precision falls to the equivalent of 6-bit resolution. $'75* 1 57 71 input a/d conversion external trigger input: pin for input of an external trigger to start a/d conversion. 27 table 1.4 pin functions (cont) pin no. type symbol dp-64s fp-64a tfp-80c i/o name and function a/d converter avcc 30 22 27 input analog power supply: the reference power supply pin for the a/d converter. when the a/d converter is not used, this pin should be connected to the system power supply (+5 v or +3 v). avss 21 13 17 input analog ground: the ground pin for the a/d converter. this pin should be connected to the system power supply (0 v). pwm timer (pwm) pw15 to pw0 40 to 47, 49 to 56 32 to 39, 41 to 48 40 to 44, 46 to 48, 52 to 54, 56 to 60 output pwm timer output: pwm timer pulse output pins. 14-bit pwm timer (pwmx) pwx0 pwx1 56 55 48 47 60 59 output pwmx timer output: pwm d/a pulse output pins. timer connection vsynci hsynci csynci vfbacki hfbacki 33 36 37 34 31 25 28 29 26 23 32 36 37 33 28 input timer connection input: timer connection synchronous signal input pins. vsynco hsynco clampo cblank 32 38 35 40 24 30 27 32 30 38 35 40 output timer connection output: timer connection synchronous signal output pins. i 2 c bus interface (iic) (option) scl0 scl1 11 43 3 35 3 43 input/ output i 2 c clock input/output (channels 0 and 1): i 2 c clock i/o pins. these pins have a bus drive function. the scl0 output form is nmos open-drain. sda0 sda1 8 44 64 36 80 44 input/ output i 2 c clock input/output (channels 0 and 1): i 2 c clock i/o pins. these pins have a bus drive function. the sda0 output form is nmos open-drain. 28 table 1.4 pin functions (cont) pin no. type symbol dp-64s fp-64a tfp-80c i/o name and function i/o ports p17 to p10 49 to 56 41 to 48 52 to 54, 56 to 60 input/ output port 1: eight input/output pins. the data direction of each pin can be selected in the port 1 data direction register (p1ddr). these pins have built-in mos input pull-ups, and also have led drive capability. p27 to p20 40 to 47 32 to 39 40 to 44, 46 to 48 input/ output port 2: eight input/output pins. the data direction of each pin can be selected in the port 2 data direction register (p2ddr). these pins have built-in mos input pull-ups, and also have led drive capability. p37 to p30 64 to 57 56 to 49 69 to 67, 65 to 61 input/ output port 3: eight input/output pins. the data direction of each pin can be selected in the port 3 data direction register (p3ddr). these pins have built-in mos input pull-ups, and also have led drive capability. p47 to p40 8 to 1 64 to 57 80 to 77, 75, 74, 72, 71 input/ output port 4: eight input/output pins. the data direction of each pin can be selected in the port 4 data direction register (p4ddr). (except p46) p47 is an nmos push-pull output. (h8s/2128 series only) p52 to p50 11 to 9 3 to 1 3 to 1 input/ output port 5: three input/output pins. the data direction of each pin can be selected in the port 5 data direction register (p5ddr). p52 is an nmos push-pull output. (h8s/2128 series only) p67 to p60 38 to 31 30 to 23 38 to 35, 33, 32, 30, 28 input/ output port 6: eight input/output pins. the data direction of each pin can be selected in the port 6 data direction register (p6ddr). p77 to p70 29 to 22 21 to 14 26, 25, 23 to 18 input port 7: eight input pins. 29 section 2 cpu 2.1 overview the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte (architecturally 4-gbyte) linear address space, and is ideal for realtime control. 2.1.1 features the h8s/2000 cpu has the following features. upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h object programs general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) sixty-five basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @Cern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes (4 gbytes architecturally) 30 high-speed operation ? all frequently-used instructions execute in one or two states ? maximum clock rate: 20 mhz ? 8/16/32-bit register-register add/subtract: 50 ns ? 8 8-bit register-register multiply: 600 ns ? 16 8-bit register-register divide: 600 ns ? 16 16-bit register-register multiply: 1000 ns ? 32 16-bit register-register divide: 1000 ns two cpu operating modes ? normal mode ? advanced mode power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are shown below. register configuration the mac register is supported only by the h8s/2600 cpu. basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. number of execution states the number of execution states of the mulxu and mulxs instructions differ as follows. number of execution states instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21 there are also differences in the address space, exr register functions, power-down state, etc., depending on the product. 31 2.1.3 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements. more general registers and control registers ? eight 16-bit extended registers, and one 8-bit control register, have been added. expanded address space ? normal mode supports the same 64-kbyte address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast. 2.1.4 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2000 cpu has the following enhancements. additional control register ? one 8-bit control register has been added. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast. 32 2.2 cpu operating modes the h8s/2000 cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space (architecturally the maximum total address space is 4 gbytes, with a maximum of 16 mbytes for the program area and a maximum of 4 gbytes for the data area). the mode is selected by the mode pins of the microcontroller. cpu operating modes normal mode advanced mode maximum 64 kbytes for program and data areas combined maximum 16 mbytes for program and data areas combined figure 2.1 cpu operating modes (1) normal mode the exception vector table and stack have the same structure as in the h8/300 cpu. address space: a maximum address space of 64 kbytes can be accessed. extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre- decrement (@Crn) or post-increment (@rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (en) will be affected. instruction set: all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. 33 exception vector table and memory indirect branch addresses: in normal mode the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits. the configuration of the exception vector table in normal mode is shown in figure 2.2. for details of the exception vector table, see section 4, exception handling. h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b reset exception vector exception vector 1 exception vector 2 exception vector table (reserved for system use) figure 2.2 exception vector table (normal mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16- bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table. 34 stack structure: when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc and condition-code register (ccr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. the extended control register (exr) is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (16 bits) ccr ccr * pc (16 bits) sp note: * ignored when returning. sp figure 2.3 stack structure in normal mode (2) advanced mode address space: linear access is provided to a 16-mbyte maximum address space (architecturally a maximum 16-mbyte program area and a maximum 4-gbyte data area, with a maximum of 4 gbytes for program and data areas combined). extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. instruction set: all instructions and addressing modes can be used. 35 exception vector table and memory indirect branch addresses: in advanced mode the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). for details of the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c exception vector table reserved reset exception vector (reserved for system use) reserved exception vector 1 reserved h'00000010 h'00000008 h'00000007 figure 2.4 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table. 36 stack structure: in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc and condition-code register (ccr) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. the extended control register (exr) is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (24 bits) ccr pc (24 bits) sp sp reserved figure 2.5 stack structure in advanced mode 37 2.3 address space figure 2.6 shows a memory map of the h8s/2000 cpu. the h8s/2000 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in advanced mode. (b) advanced mode h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff (a) normal mode data area program area cannot be used by the h8s/2128 series or h8s/2124 series figure 2.6 memory map 38 2.4 register configuration 2.4.1 overview the cpu has the internal registers shown in figure 2.7. there are two types of registers: general registers and control registers. t i2 i1 i0 exr * 76543210 pc 23 0 15 07 07 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend: stack pointer program counter extended control register trace bit interrupt mask bits condition-code register interrupt mask bit user bit or interrupt mask bit sp: pc: exr: t: i2 to i0: ccr: i: ui: note: * does not affect operation in the h8s/2128 series and h8s/2124 series. er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 76543210 half-carry flag user bit negative flag zero flag overflow flag carry flag h: u: n: z: v: c: figure 2.7 cpu registers 39 2.4.2 general registers the cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. figure 2.8 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.8 usage of general registers general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.9 shows the stack. 40 free area stack area sp (er7) figure 2.9 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), and 8-bit condition-code register (ccr). (1) program counter (pc): this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) (2) extended control register (exr): an 8-bit register. in the h8s/2128 series and h8s/2124 series, this register does not affect operation. bit 7trace bit (t): this bit is reserved. in the h8s/2128 series and h8s/2124 series, this bit does not affect operation. bits 6 to 3reserved: these bits are reserved. they are always read as 1. bits 2 to 0interrupt mask bits (i2 to i0): these bits are reserved. in the h8s/2128 series and h8s/2124 series, these bits do not affect operation. (3) condition-code register (ccr): this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7interrupt mask bit (i): masks interrupts other than nmi when set to 1. (nmi is accepted regardless of the i bit setting.) the i bit is set to 1 by hardware at the start of an exception-handling sequence. for details, refer to section 5, interrupt controller. 41 bit 6user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details, refer to section 5, interrupt controller. bit 5half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3negative flag (n): stores the value of the most significant bit (sign bit) of data. bit 2zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. bit 0carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to store the carry the carry flag is also used as a bit accumulator by bit-manipulation instructions. some instructions leave some or all of the flag bits unchanged. for the action of each instruction on the flag bits, refer to appendix a.1, list of instructions. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. 2.4.4 initial register values reset exception handling loads the cpus program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets the interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset. 42 2.5 data formats the cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, , 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4- bit bcd data. 2.5.1 general register data formats figure 2.10 shows the data formats in general registers. 76543210 don? care 70 don? care 76543210 43 70 70 don? care upper digit lower digit lsb msb lsb data type general register data format 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data rnh rnl rnh rnl rnh rnl msb don? care upper digit lower digit 43 70 don? care 70 don? care 70 figure 2.10 general register data formats 43 0 msb lsb 15 word data word data rn en 0 lsb 15 16 msb 31 en rn general register er general register e general register r general register rh general register rl most significant bit least significant bit legend: ern: en: rn: rnh: rnl: msb: lsb: 0 msb lsb 15 longword data ern data type general register data format figure 2.10 general register data formats (cont) 44 2.5.2 memory data formats figure 2.11 shows the data formats in memory. the cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2.11 memory data formats when er7 (sp) is used as an address register to access the stack, the operand size should be word size or longword size. 45 2.6 instruction set 2.6.1 overview the h8s/2000 cpu has 65 types of instructions. the instructions are classified by function in table 2.1. table 2.1 instruction classification function instructions size types data transfer mov bwl 5 pop * 1 , push * 1 wl ldm, stm l movfpe * 3 , movtpe * 3 b arithmetic add, sub, cmp, eg bwl 19 operations addx, subx, daa, das b inc, dec bwl adds, subs l mulxu, divxu, mulxs, divxs bw extu, exts wl tas b logic operations and, or, xor, not bwl 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr bwl 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 total: 65 types notes: b: byte size; w: word size; l: longword size. 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @-sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. bcc is the general name for conditional branch instructions. 3. cannot be used in the h8s/2128 series or h8s/2124 series. 46 2.6.2 instructions and addressing modes table 2.2 indicates the combinations of instructions and addressing modes that the h8s/2000 cpu can use. table 2.2 combinations of instructions and addressing modes addressing modes function instruction #xx rn @ern @(d:16,ern) @(d:32,ern) @?rn/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 data mov bwl bwl bwl bwl bwl bwl b bwl bwl transfer pop, push wl ldm, stm l movfpe * , movtpe * b arithmetic add, cmp bwl bwl operations sub wlbwl addx, subx b b adds, subs l inc, dec bwl daa, das b mulxu, divxu bw mulxs, divxs bw neg bwl extu, exts wl tas b logic operations and, or, xor bwl bwl not bwl shift bwl bit manipulation b b b b b branch bcc, bsr jmp, jsr rts note: * cannot be used in the h8s/2128 series or h8s/2124 series. 47 table 2.2 combinations of instructions and addressing modes (cont) addressing modes function instruction #xx rn @ern @(d:16,ern) @(d:32,ern) @?rn/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 system trapa control rte sleep ldc b b wwwwww stc b wwwwww andc, orc, xorc b nop block data transfer bw legend: b: byte w: word l: longword 48 2.6.3 table of instructions classified by function table 2.3 summarizes the instructions in each functional category. the notation used in table 2.3 is defined below. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication division logical and logical or ? logical exclusive or ? move ? not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). 49 table 2.3 instructions classified by function type instruction size * function data transfer mov b/w/l (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in the h8s/2128 series or h8s/2124 series. movtpe b cannot be used in the h8s/2128 series or h8s/2124 series. pop w/l @sp+ ? rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn ? @Csp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @Csp. push.l ern is identical to mov.l ern, @Csp. ldm l @sp+ ? rn (register list) pops two or more general registers from the stack. stm l rn (register list) ? @Csp pushes two or more general registers onto the stack. 50 table 2.3 instructions classified by function (cont) type instruction size * function arithmetic operations add sub b/w/l rd rs ? rd, rd #imm ? rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 ? rd, rd 2 ? rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 ? rd, rd 2 ? rd, rd 4 ? rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust ? rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs ? rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. mulxs b/w rd rs ? rd performs signed multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. divxu b/w rd rs ? rd performs unsigned division on data in two general registers: either 16 bits 8 bits ? 8-bit quotient and 8- bit remainder or 32 bits 16 bits ? 16-bit quotient and 16-bit remainder. 51 table 2.3 instructions classified by function (cont) type instruction size * function arithmetic operations divxs b/w rd rs ? rd performs signed division on data in two general registers: either 16 bits 8 bits ? 8-bit quotient and 8- bit remainder or 32 bits 16 bits ? 16-bit quotient and 16-bit remainder. cmp b/w/l rd C rs, rd C #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 C rd ? rd takes the two's complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas b @erd C 0, 1 ? ( 52 table 2.3 instructions classified by function (cont) type instruction size * function logic operations and b/w/l rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) ? (rd) takes the one's complement (logical complement) of general register contents. shift operations shal shar b/w/l rd (shift) ? rd performs an arithmetic shift on general register contents. a 1-bit or 2-bit shift is possible. shll shlr b/w/l rd (shift) ? rd performs a logical shift on general register contents. a 1-bit or 2-bit shift is possible. rotl rotr b/w/l rd (rotate) ? rd rotates general register contents. 1-bit or 2-bit rotation is possible. rotxl rotxr b/w/l rd (rotate) ? rd rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. 53 table 2.3 instructions classified by function (cont) type instruction size * function bit- manipulation instructions bset b 1 ? ( 54 table 2.3 instructions classified by function (cont) type instruction size * function bit- manipulation instructions bxor b c ? ( 55 table 2.3 instructions classified by function (cont) type instruction size * function branch instructions bcc branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address. bsr branches to a subroutine at a specified address. jsr branches to a subroutine at a specified address. rts returns from a subroutine 56 table 2.3 instructions classified by function (cont) type instruction size * function system control trapa starts trap-instruction exception handling. instructions rte returns from an exception-handling routine. sleep causes a transition to a power-down state. ldc b/w (eas) ? ccr, (eas) ? exr moves contents of a general register or memory or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr ? (ead), exr ? (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ? ccr, exr #imm ? exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ? ccr, exr #imm ? exr logically ors the ccr or exr contents with immediate data. xorc b ccr ? #imm ? ccr, exr ? #imm ? exr logically exclusive-ors the ccr or exr contents with immediate data. nop pc + 2 ? pc only increments the program counter. 57 table 2.3 instructions classified by function (cont) type instruction size * function block data transfer instructions eepmov.b eepmov.w if r4l _ 0 then repeat @er5+ ? @er6+ r4lC1 ? r4l until r4l = 0 else next; if r4 _ 0 then repeat @er5+ ? @er6+ r4C1 ? r4 until r4 = 0 else next; block transfer instruction. transfers the number of data bytes specified by r4l or r4 from locations starting at the address indicated by er5 to locations starting at the address indicated by er6. after the transfer, the next instruction is executed. note: * size refers to the operand size. b: byte w: word l: longword 2.6.4 basic instruction formats the cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. register field: specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. 58 condition field: specifies the branching condition of bcc instructions. figure 2.12 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc figure 2.12 instruction formats (examples) 2.6.5 notes on use of bit-manipulation instructions the bset, bclr, bnot, bst, and bist instructions read a byte of data, carry out bit manipulation, then write back the byte of data. caution is therefore required when using these instructions on a register containing write-only bits, or a port. the bclr instruction can be used to clear internal i/o register flags to 0. in this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. 59 2.7 addressing modes and effective address calculation 2.7.1 addressing mode the cpu supports the eight addressing modes listed in table 2.4. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program- counter relative and memory indirect. bit-manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.4 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @-ern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 register directrn: the register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. register indirect@ern: the register field of the instruction code specifies an address register (ern) which contains the address of the operand in memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). register indirect with displacement@(d:16, ern) or @(d:32, ern): a 16-bit or 32-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. 60 register indirect with post-increment or pre-decrement@ern+ or @-ern: register indirect with post-increment@ern+ the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. register indirect with pre-decrement@-ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. absolute address@aa:8, @aa:16, @aa:24, or @aa:32: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2.5 indicates the accessible absolute address ranges. table 2.5 absolute address access ranges absolute address normal mode advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) 61 immediate#xx:8, #xx:16, or #xx:32: the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. program-counter relative@(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is C126 to +128 bytes (C63 to +64 words) or C32766 to +32768 bytes (C16383 to +16384 words) from the branch instruction. the resulting value should be an even number. memory indirect@@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'000000 to h'0000ff in advanced mode). in normal mode the memory operand is a word operand and the branch address is 16 bits long. in advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (h'00). note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling. (a) normal mode (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address figure 2.13 branch address specification in memory indirect mode if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (for further information, see section 2.5.2, memory data formats.) 62 2.7.2 effective address calculation table 2.6 indicates how effective addresses are calculated in each addressing mode. in normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. table 2.6 effective address calculation no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents. 2 register indirect (@ern) general register contents 31 0 31 0 r op 24 23 don? care 3 register indirect with displacement @(d:16, ern) or @(d:32, ern) general register contents sign extension disp 31 0 31 0 31 0 op r disp don? care 24 23 4 register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ general register contents 1, 2, or 4 31 0 31 0 r op don? care 24 23 register indirect with pre-decrement @-ern general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 op r don? care 24 23 63 table 2.6 effective address calculation (cont) no. addressing mode and instruction format effective address calculation effective address (ea) 5 absolute address @aa:8 @aa:16 @aa:32 31 0 8 7 @aa:24 31 0 16 15 31 0 31 0 op abs op abs abs op op abs h'ffff 24 23 don? care don? care don? care don? care 24 23 24 23 24 23 sign exten- sion 6 immediate #xx:8/#xx:16/#xx:32 op imm operand is immediate data. 7 program-counter relative @(d:8, pc)/@(d:16, pc) 0 0 23 23 disp 31 0 24 23 op disp pc contents don? care sign exten- sion 64 table 2.6 effective address calculation (cont) no. addressing mode and instruction format effective address calculation effective address (ea) 8 memory indirect @@aa:8 normal mode 0 0 31 8 7 0 15 h'000000 31 0 16 15 op abs abs memory contents h'00 24 23 don? care advanced mode 31 0 31 8 7 0 abs h'000000 31 0 24 23 op abs memory contents don? care 65 2.8 processing states 2.8.1 overview the cpu has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and power-down state. figure 2.14 shows a diagram of the processing states. figure 2.15 indicates the state transitions. reset state the cpu and all on-chip supporting modules have been initialized and are stopped. exception-handling state a transient state in which the cpu changes the normal processing flow in response to a reset, interrupt, or trap instruction. program execution state the cpu executes program instructions in sequence. bus-released state the external bus has been released in response to a bus request signal from a bus master other than the cpu. power-down state cpu operation is stopped to conserve power. * sleep mode software standby mode hardware standby mode processing states note: * the power-down state also includes a medium-speed mode, module stop mode, sub-active mode, sub-sleep mode, and watch mode. figure 2.14 processing states 66 end of bus request bus request program execution state bus-released state sleep mode exception-handling state external interrupt software standby mode res = high reset state stby = high, res = low hardware standby mode * 2 power-down state * 3 * 1 notes: 1. 2. 3. from any state except hardware standby mode, a transition to the reset state occurs whenever res goes low. a transition can also be made to the reset state when the watchdog timer overflows. from any state, a transition to hardware standby mode occurs when stby goes low. the power-down state also includes a watch mode, subactive mode, subsleep mode, etc. for details, refer to section 21, power-down state. sleep instruction with lson = 0, ssby = 0 interrupt request end of bus request bus request request for exception handling end of exception handling sleep instruction with lson = 0, pss = 0, ssby = 1 figure 2.15 state transitions 2.8.2 reset state when the 5(6 input goes low all current processing stops and the cpu enters the reset state. all interrupts are disabled in the reset state. reset exception handling starts when the 5(6 signal changes from low to high. the reset state can also be entered by a watchdog timer overflow. for details, refer to section 14, watchdog timer. 67 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to a reset, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. types of exception handling and their priority: exception handling is performed for resets, interrupts, and trap instructions. table 2.7 indicates the types of exception handling and their priority. trap instruction exception handling is always accepted in the program execution state. exception handling and the stack structure depend on the interrupt control mode set in syscr. table 2.7 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately after a low-to-high transition at the 5(6 pin, or when the watchdog timer overflows. interrupt end of instruction execution or end of exception-handling sequence * 1 when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence. low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed. * 2 notes: 1. interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. 2. trap instruction exception handling is always accepted in the program execution state. reset exception handling: after the 5(6 pin has gone low and the reset state has been entered, when 5(6 goes high again, reset exception handling starts. when reset exception handling starts the cpu fetches a start address (vector) from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during reset exception handling and after it ends. interrupt exception handling and trap instruction exception handling: when interrupt or trap-instruction exception handling begins, the cpu references the stack pointer (er7) and pushes the program counter and other control registers onto the stack. next, the cpu alters the settings of the interrupt mask bits in the control registers. then the cpu fetches a start address (vector) from the exception vector table and program execution starts from that start address. 68 figure 2.16 shows the stack after exception handling ends. note: * ignored when returning. ccr pc (24 bits) sp ccr ccr * pc (16 bits) sp normal mode advanced mode figure 2.16 stack structure after exception handling (examples) 2.8.4 program execution state in this state the cpu executes program instructions in sequence. 2.8.5 bus-released state this is a state in which the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts except for internal operations. there is one other bus master in addition to the cpu: the data transfer controller (dtc). for further details, refer to section 6, bus controller. 2.8.6 power-down state the power-down state includes both modes in which the cpu stops operating and modes in which the cpu does not stop. there are five modes in which the cpu stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. there are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. in medium-speed mode, the cpu and other bus masters operate on a medium-speed clock. module stop mode permits halting of the operation of individual modules, other than the cpu. subactive mode, subsleep mode, and watch mode are power-down modes that use subclock input. for details, refer to section 21, power-down state. 69 sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the software standby bit (ssby) in the standby control register (sbycr) and the lson bit in the low-power control register (lpwrcr) are both cleared to 0. in sleep mode, cpu operations stop immediately after execution of the sleep instruction. the contents of cpu registers are retained. software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit in sbycr is set to 1 and the lson bit in lpwrcr and the pss bit in the wdt1 timer control/status register (tcsr) are both cleared to 0. in software standby mode, the cpu and clock halt and all mcu operations stop. as long as a specified voltage is supplied, the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. hardware standby mode: a transition to hardware standby mode is made when the 67%< pin goes low. in hardware standby mode, the cpu and clock halt and all mcu operations stop. the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained. 2.9 basic timing 2.9.1 overview the cpu is driven by a system clock, denoted by the symbol ?. the period from one rising edge of ? to the next is referred to as a state. the memory cycle or bus cycle consists of one, two, or three states. different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 70 2.9.2 on-chip memory (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 2.17 shows the on-chip memory access cycle. figure 2.18 shows the pin states. internal address bus internal read signal internal data bus internal write signal internal data bus bus cycle t1 address read data write data read access write access figure 2.17 on-chip memory access cycle bus cycle t1 unchanged address bus as rd wr data bus high high high high impedance figure 2.18 pin states during on-chip memory access 71 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. figure 2.19 shows the access timing for the on-chip supporting modules. figure 2.20 shows the pin states. bus cycle t1 t2 address read data write data internal read signal internal data bus internal write signal internal data bus read access write access internal address bus figure 2.19 on-chip supporting module access cycle 72 bus cycle t1 t2 unchanged address bus as rd wr data bus high high high high impedance figure 2.20 pin states during on-chip supporting module access 2.9.4 external address space access timing the external address space is accessed with an 8-bit data bus width in a two-state or three-state bus cycle. in three-state access, wait states can be inserted. for further details, refer to section 6, bus controller. 73 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8s/2128 series and h8s/2124 series have three operating modes (modes 1 to 3). these modes enable selection of the cpu operating mode and enabling/disabling of on-chip rom, by setting the mode pins (md1 and md0). table 3.1 lists the mcu operating modes. table 3.1 mcu operating mode selection mcu operating mode md1 md0 cpu operating mode description on-chip rom 0 00 1 1 normal expanded mode with on-chip rom disabled disabled 2 1 0 advanced expanded mode with on-chip rom enabled single-chip mode enabled 3 1 normal expanded mode with on-chip rom enabled single-chip mode the cpus architecture allows for 4 gbytes of address space, but the h8s/2128 series and h8s/2124 series actually access a maximum of 16 mbytes. however, as there are 16 external address output pins, advanced mode is enabled only in single-chip mode or in expanded mode with on-chip rom enabled when a specific area in the external address space is accessed using ,26 . the external data bus width is 8 bits. mode 1 is an externally expanded mode that allows access to external memory and peripheral devices. with modes 2 and 3, operation begins in single-chip mode after reset release, but a transition can be made to external expansion mode by setting the expe bit in mdcr. the h8s/2128 series and h8s/2124 series can only be used in modes 1 to 3. these means that the mode pins must select one of these modes. do not changes the inputs at the mode pins during operation. 74 3.1.2 register configuration the h8s/2128 series and h8s/2124 series have a mode control register (mdcr) that indicates the inputs at the mode pins (md1 and md0), a system control register (syscr) and bus control register (bcr) that control the operation of the mcu, and a serial/timer control register (stcr) that controls the operation of the supporting modules. table 3.2 summarizes these registers. table 3.2 mcu registers name abbreviation r/w initial value address * mode control register mdcr r/w undetermined h'ffc5 system control register syscr r/w h'09 h'ffc4 bus control register bcr r/w h'd7 h'ffc6 serial/timer control register stcr r/w h'00 h'ffc3 note: * lower 16 bits of the address. 3.2 register descriptions 3.2.1 mode control register (mdcr) bit initial value read/write 7 expe * r/w * 6 ? 0 5 ? 0 4 ? 0 3 ? 0 0 mds0 * r 2 ? 0 1 mds1 * r note: * determined by the md1 and md0 pins. mdcr is an 8-bit read-only register that indicates the operating mode setting and the current operating mode of the mcu. the expe bit is initialized in coordination with the mode pin states by a reset and in hardware standby mode. 75 bit 7expanded mode enable (expe): sets expanded mode. in mode 1, this bit is fixed at 1 and cannot be modified. in modes 2 and 3, this bit has an initial value of 0, and can be read and written. bit 7 expe description 0 single chip mode is selected 1 expanded mode is selected bits 6 to 2reserved: these bits cannot be modified and are always read as 0. bits 1 and 0mode select 1 and 0 (mds1, mds0): these bits indicate the input levels at pins md1 and md0 (the current operating mode). bits mds1 and mds0 correspond to md1 and md0. mds1 and mds0 are read-only bitsthey cannot be written to. the mode pin (md1 and md0) input levels are latched into these bits when mdcr is read. 3.2.2 system control register (syscr) 7 cs2e 0 r/w 6 iose 0 r/w 5 intm1 0 r 4 intm0 0 r/w 3 xrst 1 r 0 rame 1 r/w 2 nmieg 0 r/w 1 hie 0 r/w bit initial value read/write syscr is an 8-bit readable/writable register that performs selection of system pin functions, reset source monitoring, interrupt control mode selection, nmi detected edge selection, supporting module register access control, and ram address space control. only bits 7, 6, 3, 1, and 0 are described here. for a detailed description of these bits, refer also to the description of the relevant modules (bus controller, watchdog timer, ram, etc.). for information on bits 5, 4, and 2, see section 5.2.1, system control register (syscr). syscr is initialized to h'09 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7chip select 2 enable (cs2e): specifies the location of the host interface control pin. as these series do not include an on-chip host interface, this bit should not be set to 1. 76 bit 6ios enable (iose): controls the function of the $6 / ,26 pin in expanded mode. bit 6 iose description 0 the $6 / ,26 pin functions as the address strobe pin (low output when accessing an external area) (initial value) 1 the $6 / ,26 pin functions as the i/o strobe pin (low output when accessing a specified address from h'(ff)f000 to h'(ff)fe4f) bit 3external reset (xrst): indicates the reset source. when the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. xrst is a read-only bit. it is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. bit 3 xrst description 0 a reset is generated by watchdog timer overflow 1 a reset is generated by an external reset (initial value) bit 1host interface enable (hie): enables or disables cpu access to on-chip supporting function registers. this bit controls cpu access to the 8-bit timer (channel x and y) data registers and control registers (tcrx/tcry, tcsrx/tcsry, ticrr/tcoray, ticrf/tcorby, tcntx/tcnty, tcorc/tisr, tcorax, and tcorbx), and the timer connection control registers (tconri, tconro, tconrs, and sedgr). bit 1 hie description 0 in areas h'(ff)fff0 to h'(ff)fff7 and h'(ff)fffc to h'(ff)ffff, cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers, is permitted (initial value) 1 in areas h'(ff)fff0 to h'(ff)fff7 and h'(ff)fffc to h'(ff)ffff, cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers, is not permitted 77 bit 0ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 3.2.3 bus control register (bcr) 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 ios0 1 r/w 2 ? 1 r/w 1 ios1 1 r/w bit initial value read/write bcr is an 8-bit readable/writable register that specifies the external memory space access mode, and the i/o area range when the $6 pin is designated for use as the i/o strobe. for details on bits 7 to 2, see section 6.2.1, bus control register (bcr). bcr is initialized to h'd7 by a reset and in hardware standby mode. bits 1 and 0ios select 1 and 0 (ios1, ios0): these bits specify the addresses for which the $6 / ,26 pin output goes low when iose = 1. bcr bit 1 bit 0 ios1 ios0 description 0 0 the $6 / ,26 pin output goes low in accesses to addresses h'(ff)f000 to h'(ff)f03f 1 the $6 / ,26 pin output goes low in accesses to addresses h'(ff)f000 to h'(ff)f0ff 1 0 the $6 / ,26 pin output goes low in accesses to addresses h'(ff)f000 to h'(ff)f3ff 1 the $6 / ,26 pin output goes low in accesses to addresses h'(ff)f000 to h'(ff)fe4f (initial value) 78 3.2.4 serial timer control register (stcr) bit initial value read/write 7 ? 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 flshe 0 r/w 0 icks0 0 r/w 2 ? 0 r/w 1 icks1 0 r/w stcr is an 8-bit readable/writable register that controls register access, the iic operating mode (when the on-chip iic option is included), an on-chip flash memory (in f-ztat versions), and also selects the tcnt input clock. for details of functions other than register access control, see the descriptions of the relevant modules. if a module controlled by stcr is not used, do not write 1 to the corresponding bit. stcr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 5i 2 c control (iics, iicx1, iicx0): these bits control the operation of the i 2 c bus interface when the on-chip iic option is included. for details, see section 16, i 2 c bus interface. bit 4i 2 c master enable (iice): controls cpu access to the i 2 c bus interface data registers and control registers (iccr, icsr, icdr/sarx, and icmr/sar), the pwmx data registers and control registers (dadrah/dacr, dadral, dadrbh/dacnth, and dadrbl/dacntl), and the sci control registers (smr, brr, and scmr). bit 4 iice description 0 addresses h'(ff)ff88 and h'(ff)89, and h'(ff)ff8e and h'(ff)ff8f, are used for sci1 control register access addresses h'(ff)ffd8 and h'(ff)ffd9, and h'(ff)ffde and h'(ff)ffdf, are used for sci0 control register access (initial value) 1 addresses h'(ff)ff88 and h'(ff)ff89, and h'(ff)ff8e and h'(ff)ff8f, are used for iic1 data register and control register access addresses h'(ff)ffa0 and h'(ff)ffa1, and h'(ff)ffa6 and h'(ff)ffa7, are used for pwmx data register and control register access addresses h'(ff)ffd8 and h'(ff)ffd9, and h'(ff)ffde and h'(ff)ffdf, are used for iic0 data register and control register access 79 bit 3flash memory control register enable (flshe): controls cpu access to the flash memory control registers (flmcr1, flmcr2, ebr1, and ebr2), the power-down mode control registers (sbycr, lpwrcr, mstpcrh, and mstpcrl), and the supporting module control register (pcsr). bit 3 flshe description 0 addresses h'(ff)f80 to h'(ff)f87 are used for power-down mode control register and supporting module control register access (initial value) 1 addresses h'(ff)ff80 to h'(ff)ff87 are used for flash memory control register access bit 2reserved: do not write 1 to this bit. bits 1 and 0internal clock source select 1 and 0 (icks1, icks0): these bits, together with bits cks2 to cks0 in tcr, select the clock to be input to tcnt. for details, see section 12, 8-bit timers. 3.3 operating mode descriptions 3.3.1 mode 1 the cpu can access a 64-kbyte address space in normal mode. the on-chip rom is disabled. ports 1 and 2 function as an address bus, port 3 function as a data bus, and part of port 4 carries bus control signals. 3.3.2 mode 2 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. after a reset, single-chip mode is set, and the expe bit in mdcr must be set to 1 in order to use external addresses. however, as these series have a maximum of 16 address outputs, an external address can be specified correctly only when the i/o strobe function of the $6 / ,26 pin is used. when the expe bit in mdcr is set to 1, ports 1 and 2 function as input ports after a reset. they can be set to output addresses by setting the corresponding bits in the data direction register (ddr) to 1. port 3 function as a data bus, and part of port 4 carries bus control signals. 80 3.3.3 mode 3 the cpu can access a 64-kbyte address space in normal mode. the on-chip rom is enabled. after a reset, single-chip mode is set, and the expe bit in mdcr must be set to 1 in order to use external addresses. when the expe bit in mdcr is set to 1, ports 1 and 2 function as input ports after a reset. they can be set to output addresses by setting the corresponding bits in the data direction register (ddr) to 1. port 3 function as a data bus, and part of port 4 carries bus control signals. in products with an on-chip rom capacity of 64 kbytes or more, the amount of on-chip rom that can be used is limited to 56 kbytes. 3.4 pin functions in each operating mode the pin functions of ports 1 to 4 vary depending on the operating mode. table 3.3 shows their functions in each operating mode. table 3.3 pin functions in each mode port mode 1 mode 2 mode 3 port 1 a p * /a p * /a port 2 a p * /a p * /a port 3 d p * /d p * /d port 4 p47 p * /c p * /c p * /c p46 c * /p p * /c p * /c p45 to p43 c p * /c p * /c p42 to p40 p p p legend: p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : after reset 81 3.5 memory map in each operating mode figures 3.1 to 3.4 show memory maps for each of the operating modes. the address space is 64 kbytes in modes 1 and 3 (normal modes), and 16 mbytes in mode 2 (advanced mode). the on-chip rom capacity is 32 kbytes (h8s/2126 and h8s/2120), 64 kbytes (h8s/2127 and h8s/2122), 96 kbytes (h8s/2123), or 128 kbytes (h8s/2128 and h8s/2124), but for products with an on-chip rom capacity of 64 kbytes or more, the amount of on-chip rom that can be used is limited to 56 kbytes in mode 3 (normal mode). for details, see section 6, bus controller. 82 mode 3/expe = 0 (normal single-chip mode) h'0000 h'dfff h'0000 h'dfff h'0000 external address space on-chip rom external address space on-chip rom mode 3/expe = 1 (normal expanded mode with on-chip rom enabled) mode 1 (normal expanded mode with on-chip rom disabled) h'efff h'e080 h'efff h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 internal i/o registers 2 on-chip ram * internal i/o registers 1 h'efff on-chip ram * on-chip ram h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) * external address space internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 3.1 h8s/2128 and h8s/2124 memory map in each operating mode 83 h'01ffff h'020000 h'000000 h'01ffff h'000000 h'ffefff h'ffe080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffefff h'ffe080 h'fffeff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffffff mode 2/expe = 0 (advanced single-chip mode) on-chip rom external address * 2 space on-chip rom mode 2/expe = 1 (advanced expanded mode with on-chip rom enabled) internal i/o registers 2 on-chip ram * 1 internal i/o registers 1 on-chip ram (128 bytes) * 1 external address * 2 space internal i/o registers 2 on-chip ram internal i/o registers 1 on-chip ram (128 bytes) notes: 1. 2. external addresses can be accessed by clearing the rame bit in syscr to 0. for these models, the maximum number of external address pins is 16. an external address can only be specified correctly for an area that uses the i/o strobe function. figure 3.1 h8s/2128 and h8s/2124 memory map in each operating mode (cont) 84 mode 3/expe = 0 (normal single-chip mode) h'0000 h'dfff h'0000 h'dfff h'0000 external address space on-chip rom external address space on-chip rom mode 3/expe = 1 (normal expanded mode with on-chip rom enabled) mode 1 (normal expanded mode with on-chip rom disabled) h'efff h'e080 h'efff h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 internal i/o registers 2 on-chip ram * internal i/o registers 1 h'efff on-chip ram * on-chip ram h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) * external address space internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 3.2 h8s/2123 memory map in each operating mode 85 h'01ffff h'020000 h'000000 h'017fff h'01ffff h'000000 h'ffefff h'ffe080 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffefff h'ffe080 h'fffeff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffffff mode 2/expe = 0 (advanced single-chip mode) on-chip rom reserved area external address space * 2 mode 2/expe = 1 (advanced expanded mode with on-chip rom enabled) internal i/o registers 2 on-chip ram * 1 internal i/o registers 1 on-chip ram (128 bytes) * 1 external address space * 2 on-chip ram h'017fff on-chip rom reserved area internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) notes: 1. 2. external addresses can be accessed by clearing the rame bit in syscr to 0. for these models, the maximum number of external address pins is 16. an external address can only be specified correctly for an area that uses the i/o strobe function. figure 3.2 h8s/2123 memory map in each operating mode (cont) 86 mode 3/expe = 0 (normal single-chip mode) h'0000 h'dfff h'0000 h'dfff h'0000 external address space on-chip rom external address space mode 3/expe = 1 (normal expanded mode with on-chip rom enabled) mode 1 (normal expanded mode with on-chip rom disabled) h'efff h'e080 h'efff h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 internal i/o registers 2 on-chip ram * reserved area * internal i/o registers 1 h'efff h'e880 on-chip ram * reserved area * h'e880 on-chip ram reserved area h'e880 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) * external address space on-chip rom internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 3.3 h8s/2127 and h8s/2122 memory map in each operating mode 87 h'01ffff h'020000 h'000000 h'00ffff h'01ffff h'000000 h'ffefff h'ffe080 h'ffe880 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffefff h'ffe080 h'fffeff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffffff mode 2/expe = 0 (advanced single-chip mode) on-chip rom reserved area external address space * 2 mode 2/expe = 1 (advanced expanded mode with on-chip rom enabled) internal i/o registers 2 on-chip ram * 1 reserved area * 1 internal i/o registers 1 on-chip ram (128 bytes) * 1 external address space * 2 h'ffe880 on-chip ram reserved area h'00ffff on-chip rom reserved area internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) notes: 1. 2. external addresses can be accessed by clearing the rame bit in syscr to 0. for these models, the maximum number of external address pins is 16. an external address can only be specified correctly for an area that uses the i/o strobe function. figure 3.3 h8s/2127 and h8s/2122 memory map in each operating mode (cont) 88 mode 3/expe = 0 (normal single-chip mode) h'0000 h'dfff h'0000 h'dfff h'7fff h'7fff h'0000 external address space on-chip rom external address space reserved area mode 3/expe = 1 (normal expanded mode with on-chip rom enabled) mode 1 (normal expanded mode with on-chip rom disabled) h'efff h'e080 h'efff h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 internal i/o registers 2 on-chip ram * reserved area * internal i/o registers 1 h'efff h'e880 on-chip ram * reserved area * h'e880 on-chip ram reserved area reserved area h'e880 h'e080 h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 on-chip ram (128 bytes) * external address space internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) * external address space on-chip rom internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) h'feff h'ffff h'fe50 h'ff7f h'ff80 h'ff00 note: * external addresses can be accessed by clearing the rame bit in syscr to 0. figure 3.4 h8s/2126 and h8s/2120 memory map in each operating mode 89 h'01ffff h'020000 h'000000 h'007fff h'01ffff h'000000 h'ffefff h'ffe080 h'ffe880 h'fffeff h'ffffff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffefff h'ffe080 h'fffeff h'fffe50 h'ffff7f h'ffff80 h'ffff00 h'ffffff mode 2/expe = 0 (advanced single-chip mode) on-chip rom reserved area external address space * 2 mode 2/expe = 1 (advanced expanded mode with on-chip rom enabled) internal i/o registers 2 on-chip ram * 1 reserved area * 1 internal i/o registers 1 on-chip ram (128 bytes) * 1 external address space * 2 h'ffe880 on-chip ram reserved area h'007fff on-chip rom reserved area internal i/o registers 2 internal i/o registers 1 on-chip ram (128 bytes) notes: 1. 2. external addresses can be accessed by clearing the rame bit in syscr to 0. for these models, the maximum number of external address pins is 16. an external address can only be specified correctly for an area that uses the i/o strobe function. figure 3.4 h8s/2126 and h8s/2120 memory map in each operating mode (cont) 90 91 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. exception handling is prioritized as shown in table 4.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exceptions are accepted at all times in the program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits in syscr. table 4.1 exception types and priority priority exception type start of exception handling high reset starts immediately after a low-to-high transition at the 5(6 pin, or when the watchdog timer overflows. trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1. interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued. * 2 direct transition started by a direct transition resulting from execution of a sleep instruction. low trap instruction (trapa) * 3 started by execution of a trap instruction (trapa). notes: 1. traces are enabled only in interrupt control modes 2 and 3. (they cannot be used in the h8s/2128 series or h8s/2124 series.) trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in the program execution state. 92 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows: 1. the program counter (pc) and condition-code register (ccr) are pushed onto the stack. 2. the interrupt mask bits are updated. the t bit is cleared to 0. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out. 4.1.3 exception sources and vector table the exception sources are classified as shown in figure 4.1. different vector addresses are assigned to different exception sources. table 4.2 lists the exception sources and their vector addresses. exception sources reset trace interrupts direct transition trap instruction (cannot be used in the h8s/2128 series or h8s/2124 series) external interrupts: nmi, irq2 to irq0 internal interrupts: interrupt sources in on-chip supporting modules figure 4.1 exception sources 93 table 4.2 exception vector table vector address * 1 exception source vector number normal mode advanced mode reset 0 h'0000 to h'0001 h'0000 to h'0003 reserved for system use 1 h'0002 to h'0003 h'0004 to h'0007 2 h'0004 to h'0005 h'0008 to h'000b 3 h'0006 to h'0007 h'000c to h'000f 4 h'0008 to h'0009 h'0010 to h'0013 5 h'000a to h'000b h'0014 to h'0017 direct transition 6 h'000c to h'000d h'0018 to h'001b external interrupt nmi 7 h'000e to h'000f h'001c to h'001f trap instruction (4 sources) 8 h'0010 to h'0011 h'0020 to h'0023 9 h'0012 to h'0013 h'0024 to h'0027 10 h'0014 to h'0015 h'0028 to h'002b 11 h'0016 to h'0017 h'002c to h'002f reserved for system use 12 h'0018 to h'0019 h'0030 to h'0033 13 h'001a to h'001b h'0034 to h'0037 14 h'001c to h'001d h'0038 to h'003b 15 h'001e to h'001f h'003c to h'003f external interrupt irq0 16 h'0020 to h'0021 h'0040 to h'0043 irq1 17 h'0022 to h'0023 h'0044 to h'0047 irq2 18 h'0024 to h'0025 h'0048 to h'004b reserved 19 h'0026 to h'0027 h'004c to h'004f 20 h'0028 to h'0029 h'0050 to h'0053 21 h'002a to h'002b h'0054 to h'0057 22 h'002c to h'002d h'0058 to h'005b 23 h'002e to h'002f h'005c to h'005f internal interrupt * 2 24 ? 103 h'0030 to h'0031 ? h'00ce to h'00cf h'0060 to h'0063 ? h'019c to h'019f notes: 1. lower 16 bits of the address. 2. for details on internal interrupt vectors, see section 5.3.3, interrupt exception vector table. 94 4.2 reset 4.2.1 overview a reset has the highest exception priority. when the 5(6 pin goes low, all processing halts and the mcu enters the reset state. a reset initializes the internal state of the cpu and the registers of on-chip supporting modules. immediately after a reset, interrupt control mode 0 is set. reset exception handling begins when the 5(6 pin changes from low to high. h8s/2128 series and h8s/2124 series mcus can also be reset by overflow of the watchdog timer. for details, see section 14, watchdog timer. 4.2.2 reset sequence the mcu enters the reset state when the 5(6 pin goes low. to ensure that the chip is reset, hold the 5(6 pin low for at least 20 ms when powering on. to reset the chip during operation, hold the 5(6 pin low for at least 20 states. for pin states in a reset, see appendix d.1, port states in each processing state. when the 5(6 pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: [1] the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit is set to 1 in ccr. [2] the reset exception vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figures 4.2 and 4.3 show examples of the reset sequence. 95 internal address bus internal read signal internal write signal internal data bus (1) (3) vector fetch internal processing fetch of first program instruction high (1) reset exception vector address ((1) = h'0000) (2) start address (contents of reset exception vector address) (3) start address ((3) = (2)) (4) first program instruction (2) (4) res figure 4.2 reset sequence (mode 3) 96 address bus vector fetch internal processing fetch of first program instruction (1) (3) reset exception vector address ((1) = h'0000, (3) = h'0001) (2) (4) start address (contents of reset exception vector address) (5) start address ((5) = (2) (4)) (6) first program instruction res (1) (5) high (2) (4) (3) (6) rd wr d7 to d0 * note: * 3 program wait states are inserted. ** figure 4.3 reset sequence (mode 1) 4.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx:32, sp). 97 4.3 interrupts interrupt exception handling can be requested by four external sources (nmi and irq2 to irq0), and internal sources in the on-chip supporting modules. figure 4.4 shows the interrupt sources and the number of interrupts of each type. the on-chip supporting modules that can request interrupts include the watchdog timer (wdt), 16-bit free-running timer (frt), 8-bit timer (tmr), serial communication interface (sci), data transfer controller (dtc), a/d converter (adc), i 2 c bus interface (option). each interrupt source has a separate vector address. nmi is the highest-priority interrupt. interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to either three priority/mask levels to enable multiplexed interrupt control. for details on interrupts, see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq2 to irq0 (3) wdt * (2) frt (7) tmr (10) sci (8) dtc (1) adc (1) iic (3) (option) other (1) numbers in parentheses are the numbers of interrupt sources. * when the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. note: figure 4.4 interrupt sources and number of interrupts 98 4.4 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4.3 shows the status of ccr and exr after execution of trap instruction exception handling. table 4.3 status of ccr and exr after trap instruction exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 1 1 11 legend: 1: set to 1 0: cleared to 0 : retains value prior to execution. 99 4.5 stack status after exception handling figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. sp ccr ccr * pc (16 bits) interrupt control modes 0 and 1 note: * ignored on return. figure 4.5 (1) stack status after exception handling (normal mode) sp ccr pc (24bits) interrupt control modes 0 and 1 note: * ignored on return. figure 4.5 (2) stack status after exception handling (advanced mode) 100 4.6 notes on use of the stack when accessing word data or longword data, the h8s/2128 series or h8s/2124 series chip assumes that the lowest address bit is 0. the stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (sp: er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4.6 shows an example of what happens when the sp value is odd. sp legend: ccr: condition-code register pc: program counter r1l: general register r1l sp: stack pointer note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. sp sp ccr pc r1l pc h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff mov.b r1l, @?r7 sp set to h'fffeff trapa instruction executed data saved above sp contents of ccr lost figure 4.6 operation when sp value is odd 101 section 5 interrupt controller 5.1 overview 5.1.1 features h8s/2128 series and h8s/2124 series mcus control interrupts by means of an interrupt controller. the interrupt controller has the following features: two interrupt control modes ? either of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). priorities settable with icr ? an interrupt control register (icr) is provided for setting interrupt priorities. three priority levels can be set for each module for all interrupts except nmi. independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. four external interrupt pins ? nmi is the highest-priority interrupt, and is accepted at all times. a rising or falling edge at the nmi pin can be selected for the nmi interrupt. ? falling edge, rising edge, or both edge detection, or level sensing, at pins ,54 to ,54 can be selected for interrupts irq2 to irq0. dtc control ? dtc activation is controlled by means of interrupts. 102 5.1.2 block diagram a block diagram of the interrupt controller is shown in figure 5.1. syscr nmi input irq input internal interrupt requests wovi to iici1 intm1 intm0 nmieg nmi input unit irq input unit isr iscr ier icr interrupt controller priority determination interrupt request vector number i, ui ccr cpu irq sense control register irq enable register irq status register interrupt control register system control register legend: iscr: ier: isr: icr: syscr: figure 5.1 block diagram of interrupt controller 5.1.3 pin configuration table 5.1 summarizes the pins of the interrupt controller. table 5.1 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 2 to 0 ,54 to ,54 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 103 5.1.4 register configuration table 5.2 summarizes the registers of the interrupt controller. table 5.2 interrupt controller registers name abbreviation r/w initial value address * 1 system control register syscr r/w h'09 h'ffc4 irq sense control register h iscrh r/w h'00 h'feec irq sense control register l iscrl r/w h'00 h'feed irq enable register ier r/w h'f8 h'ffc2 irq status register isr r/(w) * 2 h'00 h'feeb interrupt control register a icra r/w h'00 h'fee8 interrupt control register b icrb r/w h'00 h'fee9 interrupt control register c icrc r/w h'00 h'feea address break control register abrkcr r/w h'00 h'fef4 break address register a bara r/w h'00 h'fef5 break address register b barb r/w h'00 h'fef6 break address register c barc r/w h'00 h'fef7 notes: 1. lower 16 bits of the address. 2. only 0 can be written, for flag clearing. 104 5.2 register descriptions 5.2.1 system control register (syscr) 7 cs2e 0 r/w 6 iose 0 r/w 5 intm1 0 r 4 intm0 0 r/w 3 xrst 1 r 0 rame 1 r/w 2 nmieg 0 r/w 1 hie 0 r/w bit initial value read/write syscr is an 8-bit readable/writable register of which bits 5, 4, and 2 select the interrupt control mode and the detected edge for nmi. only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, system control register (syscr). syscr is initialized to h'09 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 5 and 4interrupt control mode 1 and 0 (intm1, intm0): these bits select one of four interrupt control modes for the interrupt controller. the intm1 bit must not be set to 1. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 interrupts are controlled by i bit (initial value) 1 1 interrupts are controlled by i and ui bits and icr 1 0 2 cannot be used in the h8s/2128 series or h8s/2124 series 1 3 cannot be used in the h8s/2128 series or h8s/2124 series bit 2nmi edge select (nmieg): selects the input edge for the nmi pin. bit 2 nmieg description 0 interrupt request generated at falling edge of nmi input (initial value) 1 interrupt request generated at rising edge of nmi input 105 5.2.2 interrupt control registers a to c (icra to icrc) 7 icr7 0 r/w 6 icr6 0 r/w 5 icr5 0 r/w 4 icr4 0 r/w 3 icr3 0 r/w 0 icr0 0 r/w 2 icr2 0 r/w 1 icr1 0 r/w bit initial value read/write the icr registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other than nmi. the correspondence between icr settings and interrupt sources is shown in table 5.3. the icr registers are initialized to h'00 by a reset and in hardware standby mode. bit ninterrupt control level (icrn): sets the control level for the corresponding interrupt source. bit n icrn description 0 corresponding interrupt source is control level 0 (non-priority) (initial value) 1 corresponding interrupt source is control level 1 (priority) (n = 7 to 0) table 5.3 correspondence between interrupt sources and icr settings bits register 7 6 5 4 3 2 1 0 icra irq0 irq1 irq2 dtc watchdog timer 0 watchdog timer 1 icrb a/d converter free- running timer 8-bit timer channel 0 8-bit timer channel 1 8-bit timer channels x, y icrc sci channel 0 sci channel 1 iic channel 0 (option) iic channel 1 (option) 106 5.2.3 irq enable register (ier) bit 76543210 irq2e irq1e irq0e initial value 11111000 read/write rrrrrr/wr/wr/w ier is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests irq2 to irq0. ier is initialized to h'f8 by a reset and in hardware standby mode. bits 7 to 3reserved: these bits cannot be modified and are always read as 0. bits 2 to 0irq2 to irq0 enable (irq2e to irq0e): these bits select whether irq2 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupt disabled (initial value) 1 irqn interrupt enabled (n = 2 to 0) 107 5.2.4 irq sense control registers h and l (iscrh, iscrl) iscrh bit 15 14 13 12 11 10 9 8 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w iscrl bit 76543210 irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w iscrh and iscrl are 8-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins ,54 to ,54 . each of the iscr registers is initialized to h'00 by a reset and in hardware standby mode. iscrh bits 7 to 0, iscrl bits 7 and 6reserved: do not write 1 to this bit. iscrl bits 5 to 0irq2 sense control a and b (irq2sca, irq2scb) to irq0 sense control a and b (irq0sca, irq0scb) iscrl bits 5 to 0 irq2scb to irq0scb irq2sca to irq0sca description 0 0 interrupt request generated at ,54 to ,54 input low level (initial value) 1 interrupt request generated at falling edge of ,54 to ,54 input 1 0 interrupt request generated at rising edge of ,54 to ,54 input 1 interrupt request generated at both falling and rising edges of ,54 to ,54 input 108 5.2.5 irq status register (isr) bit 76543210 irq2f irq1f irq0f initial value 00000000 read/write rrrrr r/(w) * r/(w) * r/(w) * note: * only 0 can be written, to clear the flag. isr is an 8-bit readable/writable register that indicates the status of irq2 to irq0 interrupt requests. isr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 3reserved bits 2 to 0irq2 to irq0 flags (irq2f to irq0f): these bits indicate the status of irq2 to irq0 interrupt requests. bit n irqnf description 0 [clearing conditions] (initial value) cleared by reading irqnf when set to 1, then writing 0 in irqnf when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and ,54q input is high when irqn interrupt exception handling is executed when falling, rising, or both- edge detection is set (irqnscb = 1 or irqnsca = 1) 1 [setting conditions] when ,54q input goes low when low-level detection is set (irqnscb = irqnsca = 0) when a falling edge occurs in ,54q input when falling edge detection is set (irqnscb = 0, irqnsca = 1) when a rising edge occurs in ,54q input when rising edge detection is set (irqnscb = 1, irqnsca = 0) when a falling or rising edge occurs in ,54q input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 2 to 0) 109 5.2.6 address break control register (abrkcr) 7 cmf 0 r 6 ? 0 5 ? 0 4 ? 0 3 0 0 bie 0 r/w 2 0 1 0 bit initial value read/write abrkcr is an 8-bit readable/writable register that performs address break control. abrkcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7condition match flag (cmf): this is the address break source flag, used to indicate that the address set by bar has been prefetched. when the cmf flag and bie flag are both set to 1, an address break is requested. bit 7 cmf description 0 [clearing condition] when address break interrupt exception handling is executed (initial value) 1 [setting condition] when address set by bara to barc is prefetched while bie = 1 bits 6 to 1reserved: these bits cannot be modified and are always read as 0. bit 0break interrupt enable (bie): selects address break enabling or disabling. bit 0 bie description 0 address break disabled (initial value) 1 address break enabled 110 5.2.7 break address registers a, b, c (bara, barb, barc) 7 a23 0 r/w 6 a22 0 r/w 5 a21 0 r/w 4 a20 0 r/w 3 a19 0 r/w 0 a16 0 r/w 2 a18 0 r/w 1 a17 0 r/w bit bara initial value read/write 7 a15 0 r/w 6 a14 0 r/w 5 a13 0 r/w 4 a12 0 r/w 3 a11 0 r/w 0 a8 0 r/w 2 a10 0 r/w 1 a9 0 r/w bit barb initial value read/write 7 a7 0 r/w 6 a6 0 r/w 5 a5 0 r/w 4 a4 0 r/w 3 a3 0 r/w 0 ? 0 2 a2 0 r/w 1 a1 0 r/w bit barc initial value read/write bar consists of three 8-bit readable/writable registers (bara, barb, and barc), and is used to specify the address at which an address break is to be executed. each of the bar registers is initialized to h'00 by a reset and in hardware standby mode. they are not initialized in software standby mode. bara bits 7 to 0address 23 to 16 (a23 to a16) barb bits 7 to 0address 15 to 8 (a15 to a8) barc bits 7 to 1address 7 to 1 (a7 to a1) these bits specify the address at which an address break is to be executed. bar bits a23 to a1 are compared with internal address bus lines a23 to a1, respectively. the address at which the first instruction byte is located should be specified as the break address. occurrence of the address break condition may not be recognized for other addresses. in normal mode, no comparison is made with address lines a23 to a16. barc bit 0reserved: this bit cannot be modified and is always read as 0. 111 5.3 interrupt sources interrupt sources comprise external interrupts (nmi and irq2 to irq0) and internal interrupts. 5.3.1 external interrupts there are four external interrupt sources: nmi, and ,54 to ,54 . nmi, and irq2 to irq0 can be used to restore the h8s/2128 series or h8s/2124 series chip from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode and the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 7. irq2 to irq0 interrupts: interrupts irq2 to irq0 are requested by an input signal at pins ,54 to ,54 . interrupts irq2 to irq0 have the following features: using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins ,54 to ,54 . enabling or disabling of interrupt requests irq2 to irq0 can be selected with ier. the interrupt control level can be set with icr. the status of interrupt requests irq2 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. a block diagram of interrupts irq2 to irq0 is shown in figure 5.2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: n: 2 to 0 figure 5.2 block diagram of interrupts irq2 to irq0 112 figure 5.3 shows the timing of irqnf setting. irqn input pin irqnf figure 5.3 timing of irqnf setting the vector numbers for irq2 to irq0 interrupt exception handling are 18 to 16. detection of irq2 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. therefore, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr bit to 0 and use the pin as an i/o pin for another function. as interrupt request flags irq2f to irq0f are set when the setting condition is met, regardless of the ier setting, only the necessary flags should be referenced. 5.3.2 internal interrupts there are 32 sources for internal interrupts from on-chip supporting modules, plus one software interrupt source (pc break). for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if any one of these is set to 1, an interrupt request is issued to the interrupt controller. the interrupt control level can be set by means of icr. the dtc can be activated by an frt, tmr, sci, or other interrupt request. when the dtc is activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect. 113 5.3.3 interrupt exception vector table table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by means of icr. the situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5.4. table 5.4 interrupt sources, vector addresses, and interrupt priorities origin of vector address interrupt source interrupt source vector number normal mode advanced mode icr priority nmi external 7 h'000e h'00001c high irq0 pin 16 h'0020 h'000040 icra7 irq1 17 h'0022 h'000044 icra6 irq2 18 h'0024 h'000048 icra5 reserved 19 to 23 h'0026 to h'002e h'00004c to h'00005c swdtend (software activation interrupt end) dtc 24 h'0030 h'000060 icra2 wovi0 (interval timer) watchdog timer 0 25 h'0032 h'000064 icra1 wovi1 (interval timer) watchdog timer 1 26 h'0034 h'000068 icra0 pc break 27 h'0036 h'00006c adi (a/d conversion end) a/d 28 h'0038 h'000070 icrb7 reserved 29 to 47 h'003a to h'005e h'000074 to h'0000bc icia (input capture a) icib (input capture b) icic (input capture c) icid (input capture d) ocia (output compare a) ocib (output compare b) fovi (overflow) reserved free-running timer 48 49 50 51 52 53 54 55 h'0060 h'0062 h'0064 h'0066 h'0068 h'006a h'006c h'006e h'0000c0 h'0000c4 h'0000c8 h'0000cc h'0000d0 h'0000d4 h'0000d8 h'0000dc icrb6 reserved 56 to 63 h'0070 to h'007e h'0000e0 to h'0000fc low 114 table 5.4 interrupt sources, vector addresses, and interrupt priorities (cont) origin of vector address interrupt source interrupt source vector number normal mode advanced mode icr priority cmia0 (compare-match a) cmib0 (compare-match b) ovi0 (overflow) reserved 8-bit timer channel 0 64 65 66 67 h'0080 h'0082 h'0084 h'0086 h'000100 h'000104 h'000108 h'00010c icrb3 high cmia1 (compare-match a) cmib1 (compare-match b) ovi1 (overflow) reserved 8-bit timer channel 1 68 69 70 71 h'0088 h'008a h'008c h'008e h'000110 h'000114 h'000118 h'00011c icrb2 cmiay (compare-match a) cmiby (compare-match b) oviy (overflow) icix (input capture x) 8-bit timer channels y, x 72 73 74 75 h'0090 h'0092 h'0094 h'0096 h'000120 h'000124 h'000128 h'00012c icrb1 reserved 76 to 79 h'0098 to h'009e h'000130 to h'00013c eri0 (receive error 0) rxi0 (reception completed 0) txi0 (transmit data empty 0) tei0 (transmission end 0) sci channel 0 80 81 82 83 h'00a0 h'00a2 h'00a4 h'00a6 h'000140 h'000144 h'000148 h'00014c icrc7 eri1 (receive error 1) rxi1 (reception completed 1) txi1 (transmit data empty 1) tei1 (transmission end 1) sci channel 1 84 85 86 87 h'00a8 h'00aa h'00ac h'00ae h'000150 h'000154 h'000158 h'00015c icrc6 reserved 84 to 91 h'00b0 to h'00b6 h'000160 to h'00016c iici0 (1-byte transmission/ reception completed) ddcswi (format switch) iic channel 0 (option) 92 93 h'00b8 h'00ba h'000170 h'000174 icrc4 iici1 (1-byte transmission/ reception completed) reserved iic channel 1 (option) 94 95 h'00bc h'00be h'000178 h'00017c icrc3 reserved 96 to 103 h'00c0 to h'00ce h'000180 to h'00019c low 115 5.4 address breaks 5.4.1 features with the h8s/2128 series and h8s/2124 series, it is possible to identify the prefetch of a specific address by the cpu and generate an address break interrupt, using the abrkcr and bar registers. when an address break interrupt is generated, address break interrupt exception handling is executed. this function can be used to detect the beginning of execution of a bug location in the program, and branch to a correction routine. 5.4.2 block diagram a block diagram of the address break function is shown in figure 5.4. bar abrkcr comparator match signal control logic address break interrupt request internal address prefetch signal (internal signal) figure 5.4 block diagram of address break function 116 5.4.3 operation abrkcr and bar settings can be made so that an address break interrupt is generated when the cpu prefetches the address set in bar. this address break function issues an interrupt request to the interrupt controller when the address is prefetched, and the interrupt controller determines the interrupt priority. when the interrupt is accepted, interrupt exception handling is started on completion of the currently executing instruction. with an address break interrupt, interrupt mask control by the i and ui bits in the cpus ccr is ineffective. the register settings when the address break function is used are as follows. 1. set the break address in bits a23 to a1 in bar. 2. set the bie bit in abrkcr to 1 to enable address breaks. an address break will not be requested if the bie bit is cleared to 0. when the setting condition occurs, the cmf flag in abrkcr is set to 1 and an interrupt is requested. if necessary, the source should be identified in the interrupt handling routine. 5.4.4 usage notes with the address break function, the address at which the first instruction byte is located should be specified as the break address. occurrence of the address break condition may not be recognized for other addresses. in normal mode, no comparison is made with address lines a23 to a16. if a branch instruction (bcc, bsr), jump instruction (jmp, jsr), rts instruction, or rte instruction is located immediately before the address set in bar, execution of this instruction will output a prefetch signal for that address, and an address break may be requested. this can be prevented by not making a break address setting for an address immediately following one of these instructions, or by determining within the interrupt handling routine whether interrupt handling was initiated by a genuine condition occurrence. as an address break interrupt is generated by a combination of the internal prefetch signal and address, the timing of the start of interrupt exception handling depends on the content and execution cycle of the instruction at the set address and the preceding instruction. figure 5.5 shows some address timing examples. 117 address bus break request signal breakpoint nop instruction is executed at breakpoint address h'0312 and next address, h'0314; fetch from address h'0316 starts after end of exception handling. instruction fetch internal operation internal operation vector fetch stack save instruction fetch h'0310 nop execution h'0310 nop h'0312 nop h'0314 nop h'0316 nop nop execution nop execution interrupt exception handling h'0312 h'0314 h'0316 h'0318 h'0036 sp-2 sp-4 ? program area in on-chip memory, 1-state execution instruction at specified break address instruction fetch address bus break request signal breakpoint mov instruction is executed at breakpoint address h'0312, nop instruction at next address, h'0316, is not executed; fetch from address h'0316 starts after end of exception handling. internal operation internal operation vector fetch stack save instruction fetch h'0310 nop execution h'0310 nop h'0312 mov.w #xx:16,rd h'0316 nop h'0318 nop mov.w execution interrupt exception handling h'0312 h'0314 h'0316 h'0318 h'0036 sp-2 sp-4 ? program area in on-chip memory, 2-state execution instruction at specified break address address bus break request signal breakpoint nop instruction at breakpoint address h'0312 is not executed; fetch from address h'0312 starts after end of exception handling. instruction fetch internal operation internal operation vector fetch stack save h'0310 nop execution h'0310 nop h'0312 nop h'0314 nop h'0316 nop interrupt exception handling h'0312 h'0314 h'0036 sp-2 sp-4 ? program area in external memory (2-state access, 16-bit-bus access), 1-state execution instruction at specified break address instruction fetch instruction fetch instruction fetch instruction fetch instruction fetch instruction fetch instruction fetch instruction fetch instruction fetch instruction fetch figure 5.5 examples of address break timing 118 5.5 interrupt operation 5.5.1 interrupt control modes and interrupt operation interrupt operations in the h8s/2128 series and h8s/2124 series differ depending on the interrupt control mode. nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 5.5 shows the interrupt control modes. the interrupt controller performs interrupt control according to the interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in icr, and the masking state indicated by the i and ui bits in the cpus ccr. table 5.5 interrupt control modes interrupt syscr priority setting interrupt control mode intm1 intm0 register mask bits description 0 0 0 icr i interrupt mask control is performed by the i bit priority can be set with icr 1 1 icr i, ui 3-level interrupt mask control is performed by the i and ui bits priority can be set with icr 119 figure 5.6 shows a block diagram of the priority decision circuit. icr ui i default priority determination vector number interrupt acceptance control and 3-level mask control interrupt source interrupt control modes 0 and 1 figure 5.6 block diagram of interrupt control operation interrupt acceptance control and 3-level control: in interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the i and ui bits in ccr, and icr (control level). table 5.6 shows the interrupts selected in each interrupt control mode. table 5.6 interrupts selected in each interrupt control mode interrupt mask bits interrupt control mode i ui selected interrupts 00 * all interrupts (control level 1 has priority) 1 * nmi interrupts 10 * all interrupts (control level 1 has priority) 1 0 nmi and control level 1 interrupts 1 nmi interrupts legend: * : dont care 120 default priority determination: the priority is determined for the selected interrupt, and a vector number is generated. if the same value is set for icr, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accepted interrupt source are held pending. table 5.7 shows operations and control signal functions in each interrupt control mode. table 5.7 operations and control signal functions in each interrupt control mode interrupt setting interrupt acceptance control 3-level control default priority control mode intm1 intm0 i ui icr determination t (trace) 000 o im pr o 11 o im im pr o legend: o: interrupt operation control performed im: used as interrupt mask bit pr: sets priority : not used 121 5.5.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in the cpus ccr, and icr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. control level 1 interrupt sources have higher priority. figure 5.7 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. when interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in icr, has priority for selection, and other interrupt requests are held pending. if a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. 3. the i bit is then referenced. if the i bit is cleared to 0, the interrupt request is accepted. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. 4. when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. next, the i bit in ccr is set to 1. this disables all interrupts except nmi. 7. a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 122 program execution state interrupt generated? nmi? control level 1 interrupt? irq0? irq1? iici1 irq0? irq1? iici1 i = 0? save pc and ccr i ? 1 read vector address branch to interrupt handling routine yes no yes yes yes no no yes no yes no yes yes no no yes yes no hold pending figure 5.7 flowchart of procedure up to interrupt acceptance in interrupt control mode 0 123 5.5.3 interrupt control mode 1 three-level masking is implemented for irq interrupts and on-chip supporting module interrupts by means of the i and ui bits in the cpus ccr, and icr. control level 0 interrupt requests are enabled when the i bit is cleared to 0, and disabled when set to 1. control level 1 interrupt requests are enabled when the i bit or ui bit is cleared to 0, and disabled when both the i bit and the ui bit are set to 1. for example, if the interrupt enable bit for an interrupt request is set to 1, and h'20, h'00, and h'00 are set in icra, icrb, and icrc, respectively, (i.e. irq2 interrupts are set to control level 1 and other interrupts to control level 0), the situation is as follows: when i = 0, all interrupts are enabled (priority order: nmi > irq2 > irq0 > irq1 ...) when i = 1 and ui = 0, only nmi, and irq2 interrupts are enabled when i = 1 and ui = 1, only nmi interrupts are enabled figure 5.8 shows the state transitions in these cases. only nmi interrupts enabled all interrupts enabled exception handling execution or i ? 1, ui ? 1 i ? 0 i ? 1, ui ? 0 i ? 0ui ? 0 exception handling execution or ui ? 1 only nmi, and irq2 interrupts enabled figure 5.8 example of state transitions in interrupt control mode 1 124 figure 5.9 shows a flowchart of the interrupt acceptance operation in this case. 1. if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. when interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in icr, has priority for selection, and other interrupt requests are held pending. if a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.4 is selected. 3. the i bit is then referenced. if the i bit is cleared to 0, the ui bit has no effect. an interrupt request set to interrupt control level 0 is accepted when the i bit is cleared to 0. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. an interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0, and is accepted if the i bit is cleared to 0, or if the i bit is set to 1 and the ui bit is cleared to 0. when both the i bit and the ui bit are set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. 4. when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. 5. the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. next, the i and ui bits in ccr are set to 1. this disables all interrupts except nmi. 7. a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 125 program execution state interrupt generated? nmi? control level 1 interrupt? irq0? irq1? iici1 irq0? irq1? iici1 ui = 0? save pc and ccr i ? 1, ui ? 1 read vector address branch to interrupt handling routine yes no yes yes yes no no yes no yes no yes yes no no yes yes no hold pending i = 0? i = 0? yes yes no no figure 5.9 flowchart of procedure up to interrupt acceptance in interrupt control mode 1 126 5.5.4 interrupt exception handling sequence figure 5.10 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. (14) (12) (10) (8) (6) (4) (2) (1) (5) (7) (9) (11) (13) interrupt handling routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data bus (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp-2 sp-4 saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10) (12)) first instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) figure 5.10 interrupt exception handling 127 5.5.5 interrupt response times the h8s/2128 series and h8s/2124 series are capable of fast word access to on-chip memory, and high-speed processing can be achieved by providing the program area in on-chip rom and the stack area in on-chip ram. table 5.8 shows interrupt response timesthe interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the symbols used in table 5.8 are explained in table 5.9. table 5.8 interrupt response times number of states no. item normal mode advanced mode 1 interrupt priority determination * 1 33 2 number of wait states until executing instruction ends * 2 1 to 19+2s i 1 to 19+2s i 3 pc, ccr stack save 2s k 2s k 4 vector fetch s i 2s i 5 instruction fetch * 3 2s i 2s i 6 internal processing * 4 22 total (using on-chip memory) 11 to 31 12 to 32 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. table 5.9 number of states in interrupt handling routine execution object of access external device 8-bit bus symbol internal memory 2-state access 3-state access instruction fetch s i 1 4 6+2m branch address read s j stack manipulation s k legend: m: number of wait states in an external device access 128 5.6 usage notes 5.6.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 5.11 shows an example in which the cmiea bit in 8-bit timer register tcr is cleared to 0. internal address bus internal write signal cmiea cmfa cmia interrupt signal tcr write cycle by cpu cmia exception handling tcr address figure 5.11 contention between interrupt generation and disabling the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 129 5.6.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts, including nmi, are disabled and the next instruction is always executed. when the i bit or ui bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.6.3 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 130 5.7 dtc activation by interrupt 5.7.1 overview the dtc can be activated by an interrupt. in this case, the following options are available: interrupt request to cpu activation request to dtc both of the above for details of interrupt requests that can be used to activate the dtc, see section 7, data transfer controller. 5.7.2 block diagram figure 5.12 shows a block diagram of the dtc and interrupt controller. selection circuit dtcer dtvecr control logic determination of priority cpu dtc dtc activation request vector number clear signal cpu interrupt request vector number select signal interrupt request interrupt source clear signal irq interrupt on-chip supporting module clear signal interrupt controller i, ui swdte clear signal figure 5.12 interrupt control for dtc 131 5.7.3 operation the interrupt controller has three main functions in dtc control. selection of interrupt source: it is possible to select dtc activation request or cpu interrupt request with the dtce bit of dtcera to dtcere in the dtc. after a dtc data transfer, the dtce bit can be cleared to 0 and an interrupt request sent to the cpu in accordance with the specification of the disel bit of mrb in the dtc. when the dtc performs the specified number of data transfers and the transfer counter reaches 0, following the dtc data transfer the dtce bit is cleared to 0 and an interrupt request is sent to the cpu. determination of priority: the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. see section 7.3.3, dtc vector table, for the respective priorities. operation order: if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. table 5.10 summarizes interrupt source selection and interrupt source clearance control according to the settings of the dtce bit of dtcera to dtcere in the dtc and the disel bit of mrb in the dtc. table 5.10 interrupt source selection and clearing control settings dtc interrupt source selection/clearing control dtce disel dtc cpu 0 * ( 10 ( 1 ( legend ( : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt handling routine.) : the relevant interrupt is used. the interrupt source is not cleared. : the relevant bit cannot be used. * : dont care usage note: sci, iic, and a/d converter interrupt sources are cleared when the dtc reads or writes to the prescribed register, and are not dependent upon the disel bit. 132 133 section 6 bus controller 6.1 overview the h8s/2128 series and h8s/2124 series have a built-in bus controller (bsc) that allows external address space bus specifications, such as bus width and number of access states, to be set. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu and data transfer controller (dtc). 6.1.1 features the features of the bus controller are listed below. basic bus interface ? 2-state access or 3-state access can be selected ? program wait states can be inserted burst rom interface ? external space can be designated as rom interface space ? 1-state or 2-state burst access can be selected idle cycle insertion ? an idle cycle can be inserted when an external write cycle immediately follows an external read cycle bus arbitration function ? includes a bus arbiter that arbitrates bus mastership between the cpu and dtc 134 6.1.2 block diagram figure 6.1 shows a block diagram of the bus controller. bus controller bcr wscr wait controller bus arbiter internal control signals bus mode signal internal data bus cpu bus request signal dtc bus request signal cpu bus acknowledge signal dtc bus acknowledge signal external bus control signals wait figure 6.1 block diagram of bus controller 135 6.1.3 pin configuration table 6.1 summarizes the pins of the bus controller. table 6.1 bus controller pins name symbol i/o function address strobe $6 output strobe signal indicating that address output on address bus is enabled (when iose bit is 0) i/o select ,26 output i/o select signal (when iose bit is 1) read 5' output strobe signal indicating that external space is being read write :5 output strobe signal indicating that external space is being written to, and that data bus is enabled wait :$,7 input wait request signal when external 3-state access space is accessed 6.1.4 register configuration table 6.2 summarizes the registers of the bus controller. table 6.2 bus controller registers name abbreviation r/w initial value address * bus control register bcr r/w h'd7 h'ffc6 wait state control register wscr r/w h'33 h'ffc7 note: * lower 16 bits of the address. 136 6.2 register descriptions 6.2.1 bus control register (bcr) 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 ios0 1 r/w 2 ? 1 r/w 1 ios1 1 r/w bit initial value read/write bcr is an 8-bit readable/writable register that specifies the external memory space access mode, and the extent of the i/o area when the i/o strobe function has been selected for the $6 pin. bcr is initialized to h'd7 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7idle cycle insert 1 (icis1): reserved. do not write 0 to this bit. bit 6idle cycle insert 0 (icis0): selects whether or not a one-state idle cycle is to be inserted between bus cycles when successive external read and external write cycles are performed. bit 6 icis0 description 0 idle cycle not inserted in case of successive external read and external write cycles 1 idle cycle inserted in case of successive external read and external write cycles (initial value) bit 5burst rom enable (brstrm): selects whether external space is designated as a burst rom interface space. the selection applies to the entire external space . bit 5 brstrm description 0 basic bus interface (initial value) 1 burst rom interface 137 bit 4burst cycle select 1 (brsts1): selects the number of burst cycles for the burst rom interface. bit 4 brsts1 description 0 burst cycle comprises 1 state 1 burst cycle comprises 2 states (initial value) bit 3burst cycle select 0 (brsts0): selects the number of words that can be accessed in a burst rom interface burst access. bit 3 brsts0 description 0 max. 4 words in burst access (initial value) 1 max. 8 words in burst access bit 2reserved: do not write 0 to this bit. bits 1 and 0ios select 1 and 0 (ios1, ios0): see table 6.4. 6.2.2 wait state control register (wscr) 7 rams 0 r/w 6 ram0 0 r/w 5 abw 1 r/w 4 ast 1 r/w 3 wms1 0 r/w 0 wc0 1 r/w 2 wms0 0 r/w 1 wc1 1 r/w bit initial value read/write wscr is an 8-bit readable/writable register that specifies the data bus width, number of access states, wait mode, and number of wait states for external memory space. the on-chip memory and internal i/o register bus width and number of access states are fixed, irrespective of the wscr settings. wscr is initialized to h'33 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7ram select (rams)/bit 6ram area setting (ram0): reserved bits. 138 bit 5bus width control (abw): specifies whether the external memory space is 8-bit access space or 16-bit access space. however, a 16-bit access space cannot be specified for these series, and therefore 0 should not be written to this bit. bit 5 abw description 0 external memory space is designated as 16-bit access space (a 16-bit access space cannot be specified for these series) 1 external memory space is designated as 8-bit access space (initial value) bit 4access state control (ast): specifies whether the external memory space is 2-state access space or 3-state access space, and simultaneously enables or disables wait state insertion. bit 4 ast description 0 external memory space is designated as 2-state access space wait state insertion in external memory space accesses is disabled 1 external memory space is designated as 3-state access space (initial value) wait state insertion in external memory space accesses is enabled bits 3 and 2wait mode select 1 and 0 (wms1, wms0): these bits select the wait mode when external memory space is accessed while the ast bit is set to 1. bit 3 bit 2 wms1 wms0 description 0 0 program wait mode (initial value) 1 wait-disabled mode 1 0 pin wait mode 1 pin auto-wait mode bits 1 and 0wait count 1 and 0 (wc1, wc0): these bits select the number of program wait states when external memory space is accessed while the ast bit is set to 1. bit 1 bit 0 wc1 wc0 description 0 0 no program wait states are inserted 1 1 program wait state is inserted in external memory space accesses 1 0 2 program wait states are inserted in external memory space accesses 1 3 program wait states are inserted in external memory space accesses (initial value) 139 6.3 overview of bus control 6.3.1 bus specifications the external space bus specifications consist of three elements: bus width, number of access states, and wait mode and number of program wait states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller. bus width: a bus width of 8 or 16 bits can be selected with the abw bit. a 16-bit access space cannot be specified for these series. number of access states: two or three access states can be selected with the ast bit. when 2-state access space is designated, wait insertion is disabled. the number of access states on the burst rom interface is determined without regard to the ast bit setting. wait mode and number of program wait states: when 3-state access space is designated by the ast bit, the wait mode and the number of program wait states to be inserted automatically is selected with wms1, wms0, wc1, and wc0. from 0 to 3 program wait states can be selected. table 6.3 shows the bus specifications for each basic bus interface area. table 6.3 bus specifications for each area (basic bus interface) bus specifications (basic bus interface) abw ast wms1 wms0 wc1 wc0 bus width access states program wait states 0 0 cannot be used in the h8s/2128 series or h8s/2124 series. 10 8 2 0 101 8 3 0 * * 00 3 0 11 10 2 13 note: * except when wms1 = 0 and wms0 = 1 140 6.3.2 advanced mode the h8s/2128 and h8s/2124 have 16 address output pins, so there are no pins for output of the upper address bits (a16 to a23) in advanced mode. h'fff000 to h'fffe4f can be accessed by designating the $6 pin as an i/o strobe pin. the accessible external space is therefore h'fff000 to h'fffe4f even when expanded mode with rom enabled is selected in advanced mode. the initial state of the external space is basic bus interface, three-state access space. in rom- enabled expanded mode, the space excluding the on-chip rom, on-chip ram, and internal i/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space. 6.3.3 normal mode the initial state of the external memory space is basic bus interface, three-state access space. in rom-disabled expanded mode, the space excluding the on-chip ram and internal i/o registers is external space. in rom-enabled expanded mode, the space excluding the on-chip rom, on- chip ram, and internal i/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space. 6.3.4 i/o select signal in the h8s/2128 series and h8s/2124 series, an i/o select signal ( ,26 ) can be output, with the signal output going low when the designated external space is accessed. figure 6.2 shows an example of ,26 signal output timing. address bus ios t 1 t 2 t 3 bus cycle external address in ios set range figure 6.2 ,26 ,26 signal output timing 141 enabling or disabling of ,26 signal output is controlled by the setting of the iose bit in syscr. in expanded mode, this pin operates as the $6 output pin after a reset, and therefore the iose bit in syscr must be set to 1 in order to use this pin as the ,26 signal output. see section 8, i/o ports, for details. the range of addresses for which the ,26 signal is output can be set with bits ios1 and ios0 in bcr. the ,26 signal address ranges are shown in table 6.4. table 6.4 ,26 ,26 signal output range settings ios1 ios0 ,26 ,26 signal output range 0 0 h'(ff)f000 to h'(ff)f03f 1 h'(ff)f000 to h'(ff)f0ff 1 0 h'(ff)f000 to h'(ff)f3ff 1 h'(ff)f000 to h'(ff)fe4f (initial value) 6.4 basic bus interface 6.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with the ast bit, and the wms1, wms0, wc1, and wc0 bits (see table 6.3). 6.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. these series only have an upper data bus, and only 8-bit access space alignment is used. in these series, the upper data bus pins are designated d7 to d0. 8-bit access space: figure 6.3 illustrates data alignment control for the 8-bit access space. with the 8-bit access space, the upper data bus (d15 to d8) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. 142 d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 6.3 access sizes and data alignment control (8-bit access space) 16-bit access space (cannot be used in the h8s/2128 series or h8s/2124 series): figure 6.4 illustrates data alignment control for the 16-bit access space. with the 16-bit access space, the upper data bus (d15 to d8) and lower data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d15 d8 d7 d0 upper data bus byte size word size 1st bus cycle 2nd bus cycle longword size ?even address byte size ?odd address lower data bus figure 6.4 access sizes and data alignment control (16-bit access space) 143 6.4.3 valid strobes table 6.5 shows the data buses used and valid strobes for the access spaces. in a read, the 5' signal is valid without discrimination between the upper and lower halves of the data bus. in a write, the +:5 signal is valid for the upper half of the data bus, and the /:5 signal for the lower half. these series only have an upper data bus, and only the 5' and +:5 signals are valid. in these series, the +:5 signal pin is designated :5 . table 6.5 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d15 to d8)* 1 lower data bus (d7 to d0)* 3 8-bit access space byte read 5' valid port, etc. write +:5 * 2 port, etc. 16-bit access space byte read even 5' valid invalid (cannot be used in odd invalid valid the h8s/2128 series write even +:5 valid undefined or h8s/2124 series) odd /:5 undefined valid word read 5' valid valid write +:5 , /:5 valid valid notes: undefined: undefined data is output. invalid: input state; input value is ignored. port, etc.: pins are used as port or on-chip supporting module input/output pins, and not as data bus pins. 1. the pin names in these series are d7 to d0. 2. the pin name in these series is :5 . 3. there are no lower data bus pins in these series. 144 6.4.4 basic timing 8-bit 2-state access space: figure 6.5 shows the bus timing for an 8-bit 2-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. wait states cannot be inserted. these series have no lower data bus (d7 to d0) pins or /:5 pin. in these series, the upper data bus (d15 to d8) pins are designated d7 to d0, and the +:5 signal pin is designated :5 . bus cycle t 1 t 2 address bus as / ios (iose = 1) as / ios (iose = 0) rd d15 to d8 valid d7 to d0 invalid read hwr d15 to d8 valid write figure 6.5 bus timing for 8-bit 2-state access space 145 8-bit 3-state access space: figure 6.6 shows the bus timing for an 8-bit 3-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. wait states can be inserted. these series have no lower data bus (d7 to d0) pins or /:5 pin. in these series, the upper data bus (d15 to d8) pins are designated d7 to d0, and the +:5 signal pin is designated :5 . bus cycle t 1 t 2 address bus as / ios (iose = 1) as / ios (iose = 0) rd d15 to d8 valid d7 to d0 invalid read hwr d15 to d8 valid write t 3 figure 6.6 bus timing for 8-bit 3-state access space 146 6.4.5 wait control when accessing external space, the mcu can extend the bus cycle by inserting one or more wait states (t w ). there are three ways of inserting wait states: program wait insertion, pin wait insertion using the :$,7 pin, and a combination of the two. program wait mode in program wait mode, the number of t w states specified by bits wc1 and wc0 are always inserted between the t 2 and t 3 states when external space is accessed. pin wait mode in pin wait mode, the number of t w states specified by bits wc1 and wc0 are always inserted between the t 2 and t 3 states when external space is accessed. if the :$,7 pin is low at the fall of ? in the last t 2 or t w state, another t w state is inserted. if the :$,7 pin is held low, t w states are inserted until it goes high. pin wait mode is useful for inserting four or more wait states, or for changing the number of t w states for different external devices. pin auto-wait mode in pin auto-wait mode, if the :$,7 pin is low at the fall of the system clock in the t 2 state, the number of t w states specified by bits wc1 and wc0 are inserted between the t 2 and t 3 states when external space is accessed. no additional t w states are inserted even if the :$,7 pin remains low. pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the :$,7 pin. figure 6.7 shows an example of wait state insertion timing. 147 by program wait t 1 address bus as (iose = 0) rd data bus read data read wr write data write note: indicates the timing of wait pin sampling using the ?clock. wait data bus t 2 t w t w t w t 3 by wait pin figure 6.7 example of wait state insertion timing the settings after a reset are: 3-state access, insertion of 3 program wait states, and wait input disabled. 148 6.5 burst rom interface 6.5.1 overview with the h8s/2128 series and h8s/2124 series, external space area 0 can be designated as burst rom space, and burst rom interfacing can be performed. external space can be designated as burst rom space by means of the brstrm bit in bcr. consecutive burst accesses of a maximum of 4 words or 8 words can be performed for cpu instruction fetches only. one or two states can be selected for burst access. 6.5.2 basic timing the number of states in the initial cycle (full access) of the burst rom interface is in accordance with the setting of the ast bit. also, when the ast bit is set to 1, wait state insertion is possible. one or two states can be selected for the burst cycle, according to the setting of the brsts1 bit in bcr. wait states cannot be inserted. when the brsts0 bit in bcr is cleared to 0, burst access of up to 4 words is performed; when the brsts0 bit is set to 1, burst access of up to 8 words is performed. the basic access timing for burst rom space is shown in figure 6.8 (a) and (b). the timing shown in figure 6.8 (a) is for the case where the ast and brsts1 bits are both set to 1, and that in figure 6.8 (b) is for the case where both these bits are cleared to 0. 149 t 1 address bus as / ios (iose = 0) data bus t 2 t 3 t 1 t 2 t 1 full access t 2 rd burst access only lower address changed read data read data read data figure 6.8 (a) example of burst rom access timing (when ast = brsts1 = 1) t 1 address bus as / ios (iose = 0) data bus t 2 t 1 t 1 full access rd burst access only lower address changed read data read data read data figure 6.8 (b) example of burst rom access timing (when ast = brsts1 = 0) 150 6.5.3 wait control as with the basic bus interface, either program wait insertion or pin wait insertion using the :$,7 pin can be used in the initial cycle (full access) of the burst rom interface. see section 6.4.5, wait control. wait states cannot be inserted in a burst cycle. 6.6 idle cycle 6.6.1 operation when the h8s/2128 series or h8s/2124 series chip accesses external space, it can insert a 1- state idle cycle (t i ) between bus cycles when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, with a long output floating time, and high-speed memory, i/o interfaces, and so on. if an external write occurs after an external read while the icis0 bit in bcr is set to 1, an idle cycle is inserted at the start of the write cycle. this is enabled in advanced mode and normal mode. figure 6.9 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t 1 address bus rd bus cycle a data bus t 2 t 3 t 1 t 2 bus cycle b long output floating time data collision (a) idle cycle not inserted t 1 rd t 2 t 3 t i t 1 (b) idle cycle inserted t 2 wr wr address bus data bus bus cycle a bus cycle b figure 6.9 example of idle cycle operation 151 6.6.2 pin states in idle cycle table 6.5 shows pin states in an idle cycle. table 6.5 pin states in idle cycle pins pin state a15 to a0, ,26 contents of next bus cycle d7 to d0 high impedance $6 high 5' high :5 high 6.7 bus arbitration 6.7.1 overview the h8s/2128 series and h8s/2124 series have a bus arbiter that arbitrates bus master operations. there are two bus masters, the cpu and the dtc, which perform read/write operations when they have possession of the bus. each bus master requests the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. the selected bus master then takes possession of the bus and begins its operation. 6.7.2 operation the bus arbiter detects the bus masters bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from both bus masters, the bus request acknowledge signal is sent to the one with the higher priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dtc > cpu (low) 152 6.7.3 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specific times at which each bus master can relinquish the bus. cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the dtc. the timing for transfer of the bus is as follows: the bus is transferred at a break between bus cycles. however, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. see appendix a.5, bus states during instruction execution, for timings at which the bus is not transferred. if the cpu is executing a multiply or divide instruction or similar internal operation, it transfers the bus immediately. if the cpu is in sleep mode, it transfers the bus immediately. dtc: the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc does not release the bus until it has completed a series of processing operations. 153 section 7 data transfer controller [h8s/2128 series] provided in the h8s/2128 series; not provided in the h8s/2124 series. 7.1 overview the h8s/2128 series includes a data transfer controller (dtc). the dtc can be activated by an interrupt or software, to transfer data. 7.1.1 features transfer possible over any number of channels ? transfer information is stored in memory ? one activation source can trigger a number of data transfers (chain transfer) wide range of transfer modes ? normal, repeat, and block transfer modes available ? incrementing, decrementing, and fixing of transfer source and destination addresses can be selected direct specification of 16-mbyte address space possible ? 24-bit transfer source and destination addresses can be specified transfer can be set in byte or word units a cpu interrupt can be requested for the interrupt that activated the dtc ? an interrupt request can be issued to the cpu after one data transfer ends ? an interrupt request can be issued to the cpu after all specified data transfers have ended activation by software is possible module stop mode can be set ? the initial setting enables dtc registers to be accessed. dtc operation is halted by setting module stop mode 154 7.1.2 block diagram figure 7.1 shows a block diagram of the dtc. the dtcs register information is stored in the on-chip ram*. a 32-bit bus connects the dtc to the on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information. note: * when the dtc is used, the rame bit in syscr must be set to 1. interrupt request interrupt controller dtc internal address bus dtc activation request control logic register information mra mrb cra crb dar sar cpu interrupt request on-chip ram internal data bus legend: mra, mrb: dtc mode registers a and b cra, crb: dtc transfer count registers a and b sar: dtc source address register dar: dtc destination address register dtcera to dtcere: dtc enable registers a to e dtvecr: dtc vector register dtcera to dtcere dtvecr figure 7.1 block diagram of dtc 155 7.1.3 register configuration table 7.1 summarizes the dtc registers. table 7.1 dtc registers name abbreviation r/w initial value address * 1 dtc mode register a mra * 2 undefined * 3 dtc mode register b mrb * 2 undefined * 3 dtc source address register sar * 2 undefined * 3 dtc destination address register dar * 2 undefined * 3 dtc transfer count register a cra * 2 undefined * 3 dtc transfer count register b crb * 2 undefined * 3 dtc enable registers dtcer * 4 r/w h'00 h'feee to h'fef2 dtc vector register dtvecr * 4 r/w h'00 h'fef3 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 notes: 1. lower 16 bits of the address. 2. registers within the dtc cannot be read or written to directly. 3. allocated to on-chip ram addresses h'ec00 to h'efff as register information.they cannot be located in external memory space. when the dtc is used, do not clear the rame bit in syscr to 0. 4. the h8s/2124 series does not include an on-chip dtc, and therefore the dtcer and dtvecr register addresses should not be accessed by the cpu. 156 7.2 register descriptions 7.2.1 dtc mode register a (mra) 7 sm1 6 sm0 5 dm1 4 dm0 3 md1 0 sz 2 md0 1 dts bit initial value unde- fined read/write unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined mra is an 8-bit register that controls the dtc operating mode. bits 7 and 6source address mode 1 and 0 (sm1, sm0): these bits specify whether sar is to be incremented, decremented, or left fixed after a data transfer. bit 7 bit 6 sm1 sm0 description 0 sar is fixed 1 0 sar is incremented after a transfer (by 1 when sz = 0; by 2 when sz = 1) 1 sar is decremented after a transfer (by 1 when sz = 0; by 2 when sz = 1) bits 5 and 4destination address mode 1 and 0 (dm1, dm0): these bits specify whether dar is to be incremented, decremented, or left fixed after a data transfer. bit 5 bit 4 dm1 dm0 description 0 dar is fixed 1 0 dar is incremented after a transfer (by 1 when sz = 0; by 2 when sz = 1) 1 dar is decremented after a transfer (by 1 when sz = 0; by 2 when sz = 1) 157 bits 3 and 2dtc mode (md1, md0): these bits specify the dtc transfer mode. bit 3 bit 2 md1 md0 description 0 0 normal mode 1 repeat mode 1 0 block transfer mode 1 bit 1dtc transfer mode select (dts): specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. bit 1 dts description 0 destination side is repeat area or block area 1 source side is repeat area or block area bit 0dtc data transfer size (sz): specifies the size of data to be transferred. bit 0 sz description 0 byte-size transfer 1 word-size transfer 158 7.2.2 dtc mode register b (mrb) 7 chne 6 disel 5 4 3 0 2 1 bit initial value read/write unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined mrb is an 8-bit register that controls the dtc operating mode. bit 7dtc chain transfer enable (chne): specifies chain transfer. in chain transfer, multiple data transfers can be performed consecutively in response to a single transfer request. with data transfer for which chne is set to 1, there is no determination of the end of the specified number of transfers, clearing of the interrupt source flag, or clearing of dtcer. bit 7 chne description 0 end of dtc data transfer (activation waiting state is entered) 1 dtc chain transfer (new register information is read, then data is transferred) bit 6dtc interrupt select (disel): specifies whether interrupt requests to the cpu are disabled or enabled after a data transfer. bit 6 disel description 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 (the dtc clears the interrupt source flag of the activating interrupt to 0) 1 after a data transfer ends, the cpu interrupt is enabled (the dtc does not clear the interrupt source flag of the activating interrupt to 0) bits 5 to 0reserved: in the h8s/2128 series these bits have no effect on dtc operation, and should always be written with 0. 159 7.2.3 dtc source address register (sar) 23 22 21 20 19 43210 bit initial value unde- fined read/write unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 160 7.2.4 dtc destination address register (dar) 23 22 21 20 19 43210 bit initial value unde- fined read/write unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 161 7.2.5 dtc transfer count register a (cra) 15 14 13 12 11109876543210 crah cral bit initial value unde- fined read/write unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined cra is a 16-bit register that designates the number of times data is to be transferred by the dtc. in normal mode, the entire cra register functions as a 16-bit transfer counter (1 to 65,536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. in repeat mode or block transfer mode, cra is divided into two parts: the upper 8 bits (crah) and the lower 8 bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are transferred when the count reaches h'00. this operation is repeated. 162 7.2.6 dtc transfer count register b (crb) 15 14 13 12 11109876543210 bit initial value unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined read/write crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. 163 7.2.7 dtc enable registers (dtcer) 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value read/write the dtc enable registers comprise five 8-bit readable/writable registers, dtcera to dtcere, with bits corresponding to the interrupt sources that can activate the dtc. these bits enable or disable dtc service for the corresponding interrupt sources. the dtc enable registers are initialized to h'00 by a reset and in hardware standby mode. bit ndtc activation enable (dtcen) bit n dtcen description 0 dtc activation by interrupt is disabled (initial value) [clearing conditions] when data transfer ends with the disel bit set to 1 when the specified number of transfers end 1 dtc activation by interrupt is enabled [holding condition] when the disel bit is 0 and the specified number of transfers have not ended (n = 7 to 0) a dtce bit can be set for each interrupt source that can activate the dtc. the correspondence between interrupt sources and dtce bits is shown in table 7.4, together with the vector number generated by the interrupt controller in each case. for dtce bit setting, read/write operations must be performed using bit-manipulation instructions such as bset and bclr. for the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. 164 7.2.8 dtc vector register (dtvecr) 7 swdte 0 r/(w) * 6 dtvec6 0 r/w 5 dtvec5 0 r/w 4 dtvec4 0 r/w 3 dtvec3 0 r/w 0 dtvec0 0 r/w 2 dtvec2 0 r/w 1 dtvec1 0 r/w a value of 1 can always be written to the swdte bit, but 0 can only be written after 1 is read. bit initial value read/write note: * dtvecr is an 8-bit readable/writable register that enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. dtvecr is initialized to h'00 by a reset and in hardware standby mode. bit 7dtc software activation enable (swdte): specifies enabling or disabling of dtc software activation. to clear the swdte bit by software, read swdte when set to 1, then write 0 in the bit. bit 7 swdte description 0 dtc software activation is disabled [clearing condition] when the disel bit is 0 and the specified number of transfers have not ended (initial value) 1 dtc software activation is enabled [holding conditions] when data transfer ends with the disel bit set to 1 when the specified number of transfers end during software-activated data transfer bits 6 to 0dtc software activation vectors 6 to 0 (dtvec6 to dtvec0): these bits specify a vector number for dtc software activation. the vector address is h'0400 + (vector number) << 1 (where << 1 indicates a 1-bit left shift). for example, if dtvec6 to dtvec0 = h'10, the vector address is h'0420. 165 7.2.9 module stop control register (mstpcr) 15 mstp15 0 r/w bit initial value read/write 14 mstp14 0 r/w 13 mstp13 1 r/w 12 mstp12 1 r/w 11 mstp11 1 r/w 10 mstp10 1 r/w 9 mstp9 1 r/w 8 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when the mstp14 bit in mstpcr is set to 1, the dtc operation stops at the end of the bus cycle and a transition is made to module stop mode. note that 1 cannot be written to the mstp14 bit when the dtc is being activated. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 6module stop (mstp14): specifies the dtc module stop mode. mstpcrh bit 6 mstp14 description 0 dtc module stop mode is cleared (initial value) 1 dtc module stop mode is set 166 7.3 operation 7.3.1 overview when activated, the dtc reads register information that is already stored in memory and transfers data on the basis of that register information. after the data transfer, it writes updated register information back to memory. pre-storage of register information in memory makes it possible to transfer data over any required number of channels. setting the chne bit to 1 makes it possible to perform a number of transfers with a single activation. figure 7.2 shows a flowchart of dtc operation. start read dtc vector next transfer read register information data transfer write register information clear activation flag chne = 1? end no no yes yes transfer counter = 0 or disel = 1? clear dtcer interrupt exception handling figure 7.2 flowchart of dtc operation 167 the dtc transfer mode can be normal mode, repeat mode, or block transfer mode. the 24-bit sar designates the dtc transfer source address and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed. table 7.2 outlines the functions of the dtc. table 7.2 dtc functions address registers transfer mode activation source transfer source transfer destination normal mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? up to 65,536 transfers possible repeat mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? after the specified number of transfers (1 to 256), the initial state resumes and operation continues block transfer mode ? one transfer request transfers a block of the specified size ? block size is from 1 to 256 bytes or words ? up to 65,536 transfers possible ? a block area can be designated at either the source or destination irq frt ici, oci 8-bit timer cmi sci txi or rxi a/d converter adi iic iici software 24 bits 24 bits 168 7.3.2 activation sources the dtc operates when activated by an interrupt or by a write to dtvecr by software (software activation). an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dtcer bit. the interrupt request is directed to the dtc when the corresponding bit is set to 1, and to the cpu when the bit is cleared to 0. at the end of one data transfer (or the last of the consecutive transfers in the case of chain transfer) the interrupt source or the corresponding dtcer bit is cleared. table 7.3 shows activation sources and dtcer clearing. the interrupt source flag for rxi0, for example, is the rdrf flag in sci0. table 7.3 activation sources and dtcer clearing activation source when disel bit is 0 and specified number of transfers have not ended when disel bit is 1 or specified number of transfers have ended software activation swdte bit cleared to 0 swdte bit held at 1 interrupt request sent to cpu interrupt activation corresponding dtcer bit held at 1 activation source flag cleared to 0 corresponding dtcer bit cleared to 0 activation source flag held at 1 activation source interrupt request sent to cpu figure 7.3 shows a block diagram of activation source control. for details see section 5, interrupt controller. on-chip supporting module irq interrupt dtvecr selection circuit interrupt controller cpu dtc dtcer clear control select interrupt request source flag cleared clear clear request interrupt mask figure 7.3 block diagram of dtc activation source control 169 when an interrupt has been designated a dtc activation source, existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc is activated in accordance with the default priorities. 7.3.3 dtc vector table figure 7.4 shows the correspondence between dtc vector addresses and register information. table 7.4 shows the correspondence between activation sources, vector addresses, and dtcer bits. when the dtc is activated by software, the vector address is obtained from: h'0400 + dtvecr[6:0] << 1 (where << 1 indicates a 1-bit left shift). for example, if dtvecr is h'10, the vector address is h'0420. the dtc reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. the register information can be placed at predetermined addresses in the on-chip ram. the start address of the register information should be an integral multiple of four. the configuration of the vector address is the same in both normal and advanced modes, a 2- byte unit being used in both cases. these two bytes specify the lower bits of the address in the on-chip ram. 170 table 7.4 interrupt sources, dtc vector addresses, and corresponding dtces interrupt source origin of interrupt source vector number vector address dtce * priority write to dtvecr software dtvecr h'0400 + dtvecr [6:0] << 1 high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 adi (a/d conversion end) a/d 28 h'0438 dtcea3 icia (frt input capture a) frt 48 h'0460 dtcea2 icib (frt input capture b) 49 h'0462 dtcea1 ocia (frt output compare a) 52 h'0468 dtcea0 ocib (frt output compare b) 54 h'046a dtceb7 cmia0 (tmr0 compare-match a) tmr0 64 h'0480 dtceb2 cmib0 (tmr0 compare-match b) 65 h'0482 dtceb1 cmia1 (tmr1 compare-match a) tmr1 68 h'0488 dtceb0 cmib1 (tmr1 compare-match b) 69 h'048a dtcec7 cmiay (tmry compare-match a) tmry 72 h'0490 dtcec6 cmiby (tmry compare-match b) 73 h'0492 dtcec5 rxi0 (reception completed 0) sci channel 0 81 h'04a2 dtcec2 txi0 (transmit data empty 0) 82 h'04a4 dtcec1 rxi1 (reception completed 1) sci channel 1 85 h'04aa dtcec0 txi1 (transmit data empty 1) 86 h'04ac dtced7 iici0 (iic0 1-byte transmission/ reception completed) iic0 (option) 92 h'04b8 dtced4 iici1 (iic1 1-byte transmission/ reception completed) iic1 (option) 94 h'04bc dtced3 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0. register information start address register information chain transfer dtc vector address figure 7.4 correspondence between dtc vector address and register information 171 7.3.4 location of register information in address space figure 7.5 shows how the register information should be located in the address space. locate the mra, sar, mrb, dar, cra, and crb registers, in that order, from the start address of the register information (vector address contents). in chain transfer, locate the register information in consecutive areas. locate the register information in the on-chip ram (addresses: h'ffec00 to h'ffefff). register information start address chain transfer register information for 2nd transfer in chain transfer mra sar mrb dar cra crb 4 bytes lower address cra crb register information mra 0 123 sar mrb dar figure 7.5 location of dtc register information in address space 172 7.3.5 normal mode in normal mode, one operation transfers one byte or one word of data. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt can be requested. table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in normal mode. table 7.5 register information in normal mode name abbreviation function dtc source address register sar transfer source address dtc destination address register dar transfer destination address dtc transfer count register a cra transfer count dtc transfer count register b crb not used transfer sar dar figure 7.6 memory mapping in normal mode 173 7.3.6 repeat mode in repeat mode, one operation transfers one byte or one word of data. from 1 to 256 transfers can be specified. once the specified number of transfers have ended, the initial address register state specified by the transfer counter and repeat area resumes and transfer is repeated. in repeat mode the transfer counter does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in repeat mode. table 7.6 register information in repeat mode name abbreviation function dtc source address register sar transfer source address dtc destination address register dar transfer destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral transfer count dtc transfer count register b crb not used transfer repeat area sar or dar dar or sar figure 7.7 memory mapping in repeat mode 174 7.3.7 block transfer mode in block transfer mode, one operation transfers one block of data. either the transfer source or the transfer destination is specified as a block area. the block size is 1 to 256. when the transfer of one block ends, the initial state of the block size counter and the address register specified in the block area is restored. the other address register is successively incremented or decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt is requested. table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory mapping in block transfer mode. table 7.7 register information in block transfer mode name abbreviation function dtc source address register sar transfer source address dtc destination address register dar transfer destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral block size count dtc transfer count register b crb transfer counter 175 transfer sar or dar dar or sar block area first block nth block ? ? figure 7.8 memory mapping in block transfer mode 176 7.3.8 chain transfer setting the chne bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 7.9 shows memory mapping for chain transfer. source source destination destination dtc vector address register information start address register information chne = 1 register information chne = 0 figure 7.9 memory mapping in chain transfer in the case of transfer with chne set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected. 177 7.3.9 operation timing figures 7.10 to 7.12 show examples of dtc operation timing. dtc activation request dtc request address vector read transfer information read transfer information write data transfer read write figure 7.10 dtc operation timing (normal mode or repeat mode) read write read write data transfer transfer information write transfer information read vector read dtc activation request dtc request address figure 7.11 dtc operation timing (block transfer mode, with block size of 2) read write read write address dtc activation request dtc request data transfer data transfer transfer information write transfer information write transfer information read transfer information read vector read figure 7.12 dtc operation timing (chain transfer) 178 7.3.10 number of dtc execution states table 7.8 lists execution phases for a single dtc data transfer, and table 7.9 shows the number of states required for each execution phase. table 7.8 dtc execution phases mode vector read i register information read/write j data read k data write l internal operation m normal 1 6 1 1 3 repeat 1 6 1 1 3 block transfer 1 6 n n 3 n: block size (initial setting of crah and cral) table 7.9 number of states required for each execution phase object of access on- chip ram on- chip rom internal i/o registers external devices bus width 32 16 8 16 8 8 access states 1 1 2 2 2 3 execution phase vector read s i 1 4 6+2m register information read/write s j 1 byte data read s k 11222 3+m word data read s k 1 1 4 2 4 6+2m byte data write s l 11222 3+m word data write s l 1 1 4 2 4 6+2m internal operation s m 11111 1 the number of execution states is calculated from the formula below. note that s means the sum of all transfers activated by one activation event (the number for which the chne bit is set to one, plus 1). number of execution states = i s i + s (j s j + k s k + l s l ) + m s m for example, when the dtc vector address table is located in on-chip rom, normal mode is set, and data is transferred from the on-chip rom to an internal i/o register, the time required for the dtc operation is 13 states. the time from activation to the end of the data write is 10 states. 179 7.3.11 procedures for using the dtc activation by interrupt: the procedure for using the dtc with interrupt activation is as follows: 1. set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. 2. set the start address of the register information in the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. 5. after the end of one data transfer, or after the specified number of data transfers have ended, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. activation by software: the procedure for using the dtc with software activation is as follows: 1. set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. 2. set the start address of the register information in the dtc vector address. 3. check that the swdte bit is 0. 4. write 1 in the swdte bit and the vector number to dtvecr. 5. check the vector number written to dtvecr. 6. after the end of one data transfer, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the specified number of data transfers have ended, the swdte bit is held at 1 and a cpu interrupt is requested. 180 7.3.12 examples of use of the dtc normal mode: an example is shown in which the dtc is used to receive 128 bytes of data via the sci. 1. set mra to fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci rdr address in sar, the start address of the ram area where the data will be received in dar, and 128 (h'0080) in cra. crb can be set to any value. 2. set the start address of the register information at the dtc vector address. 3. set the corresponding bit in dtcer to 1. 4. set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable the reception complete (rxi) interrupt. since the generation of a receive error during the sci reception operation will disable subsequent reception, the cpu should be enabled to accept receive error interrupts. 5. each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automatically cleared to 0. 6. when cra becomes 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine should perform wrap-up processing. software activation: an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. 1. set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. 2. set the start address of the register information at the dtc vector address (h'04c0). 3. check that the swdte bit in dtvecr is 0. check that there is currently no transfer activated by software. 4. write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. 5. read dtvecr again and check that it is set to the vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer, go back to step 3. 181 6. if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. 7. after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform other wrap-up processing. 7.4 interrupts an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and interrupt controller priority level control. in the case of activation by software, a software-activated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine should clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. 7.5 usage notes module stop: when the mstp14 bit in mstpcr is set to 1, the dtc clock stops, and the dtc enters the module stop state. however, 1 cannot be written in the mstp14 bit while the dtc is operating. when the dtc is placed in the module stop state, the dtcer registers must all be in the cleared state when the mstp14 bit is set to 1. on-chip ram: the mra, mrb, sar, dar, cra, and crb registers are all located in on- chip ram. when the dtc is used, the rame bit in syscr must not be cleared to 0. dtce bit setting: for dtce bit setting, read/write operations must be performed using bit- manipulation instructions such as bset and bclr. for the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register. 182 183 section 8 i/o ports 8.1 overview the h8s/2128 series and h8s/2124 series have six i/o ports (ports 1 to 6), and one input-only port (port 7). tables 8.1 and 8.2 summarize the port functions. the pins of each port also have other functions. each port includes a data direction register (ddr) that controls input/output (not provided for the input-only port) and data registers (dr) that store output data. ports 1 to 3 have a built-in mos input pull-up function. ports 1 to 3 have a mos input pull-up control register (pcr), in addition to ddr and dr, to control the on/off status of the mos input pull-ups. ports 1 to 6 can drive a single ttl load and 30 pf capacitive load. all the i/o ports can drive a darlington transistor when in output mode. ports 1 to 3 can drive an led (10 ma sink current). in the h8s/2128 series, p52 in port 5 and p47 in port 4 are nmos push-pull outputs. note that the h8s/2124 series has subset specifications that do not include some supporting modules. for differences in pin functions, see table 8.1, h8s/2128 series port functions, and table 8.2, h8s/2124 series port functions. 184 table 8.1 h8s/2128 series port functions expanded modes single-chip mode port description pins mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) port 1 8-bit i/o port built-in mos input pull-ups led drive capability p17 to p10/ a7 to a0/ pw7 to pw0/ pwx1, pwx0 lower address output (a7 to a0) when ddr = 0 (after reset): input port when ddr = 1: lower address output (a7 to a0) or pwm timer output (pw7 to pw0, pwx1, pwx0) i/o port also functioning as pwm timer output (pw7 to pw0, pwx1, pwx0) port 2 8-bit i/o port built-in mos input pull-ups led drive capability p27/a15/pw15/ sck1/cblank p26/a14/pw14/ rxd1 p25/a13/pw13/ txd1 p24/a12/pw12/ scl1 p23/a11/pw11/ sda1 p22/a10/pw10 p21/a9/pw9 p20/a8/pw8 upper address output (a15 to a8) when ddr = 0 (after reset): input port or timer connection output (cblank) when ddr = 1: upper address output (a15 to a8), pwm timer output (pw15 to pw8), or timer connection output (cblank), or output ports (p27 to p24) i/o port also functioning as pwm timer output (pw15 to pw8), sci1 i/o pins (txd1, rxd1, sck1) and timer connection output (cblank), i 2 c bus interface 1 (option) i/o pins (scl1, sda1), and i/o port port 3 8-bit i/o port built-in mos input pull-ups led drive capability p37 to p30/ d7 to d0 data bus input/output (d7 to d0) i/o port 185 table 8.1 h8s/2128 series port functions (cont) expanded modes single-chip mode port description pins mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) port 4 8-bit i/o port p47/ :$,7 /sda0 i/o port also functioning as expanded data bus control input ( :$,7 ) and i 2 c bus interface 0 (option) input/output (sda0) i/o port also functioning as i 2 c bus interface 0 (option) input/output (sda0) p46/?/excl when ddr = 0: input port or excl input when ddr = 1 (after reset): ? output when ddr = 0 (after reset): input port or excl input when ddr = 1: ? output p45/ $6 / ,26 p44/ :5 p43/ 5' expanded data bus control output ( $6 / ,26 , :5 , 5' ) i/o port p42/ ,54 p41/ ,54 i/o port also functioning as external interrupt input ( ,54 , ,54 ) p40/ ,54 / $'75* i/o port also functioning as external interrupt input ( ,54 ), and a/d converter external trigger input ( $'75* ) port 5 3-bit i/o port p52/sck0/scl0 p51/rxd0 p50/txd0 i/o port also functioning as sci0 input/output (txd0, rxd0, sck0) and i 2 c bus interface 0 (option) input/output (scl0) 186 table 8.1 h8s/2128 series port functions (cont) expanded modes single-chip mode port description pins mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) port 6 8-bit i/o port p67/tmox/ tmo1/cin7/ hsynco p66/ftob/ tmri1/cin6/ csynci p65/ftid/tmci1/ cin5/hsynci p64/ftic/tmo0/ cin4/clampo p63/ftib/tmri0/ci n3/vfbacki p62/ftia/tmiy/ cin2/vsynci p61/ftoa/cin1/ vsynco p60/ftci/tmix/ tmci0/cin0/ hfbacki i/o port also functioning as frt input/output (ftci, ftoa, ftia, ftib, ftic, ftid, ftob), 8-bit timer 0 and 1 input/output (tmci0, tmri0, tmo0, tmci1, tmri1, tmo1), 8-bit timer x and y input/output (tmox, tmix, tmiy), timer connection input/output (hsynco, csynci, hsynci, clampo, vfbacki, vsynci, vsynco, hfbacki), and expansion a/d converter input (cin7 to cin0) port 7 8-bit input port p77/an7 p76/an6 p75/an5 p74/an4 p73/an3 p72/an2 p71/an1 p70/an0 input port also functioning as a/d converter analog input (an7 to an0) 187 table 8.2 h8s/2124 series port functions expanded modes single-chip mode port description pins mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) port 1 8-bit i/o port built-in mos input pull-ups led drive capability p17 to p10/ a7 to a0 lower address output (a7 to a0) when ddr = 0 (after reset): input port when ddr = 1: lower address output (a7 to a0) i/o port port 2 8-bit i/o port built-in mos input pull-ups led drive capability p27/a15/sck1 p26/a14/rxd1 p25/a13/txd1 p24/a12 p23/a11 p22/a10 p21/a9 p20/a8 upper address output (a15 to a8) when ddr = 0 (after reset): input port when ddr = 1: upper address output (a15 to a8), or output ports (p27 to p24) i/o port also functioning as sci1 i/o pins (txd1, rxd1, sck1) port 3 8-bit i/o port built-in mos input pull-ups led drive capability p37 to p30/ d7 to d0 data bus input/output (d7 to d0) i/o port port 4 8-bit i/o port p47/ :$,7 i/o port also functioning as expanded data bus control input ( :$,7 ) i/o port p46/?/excl when ddr = 0: input port or excl input when ddr = 1 (after reset): ? output when ddr = 0 (after reset): input port or excl input when ddr = 1: ? output p45/ $6 / ,26 p44/ :5 p43/ 5' expanded data bus control output( $6 / ,26 , :5 , 5' ) i/o port p42/ ,54 0 p41/ ,54 1 i/o port also functioning as external interrupt input ( ,54 , ,54 ) 188 table 8.2 h8s/2124 series port functions (cont) expanded modes single-chip mode port description pins mode 1 mode 2, mode 3 (expe = 1) mode 2, mode 3 (expe = 0) port 4 8-bit i/o port p40/ ,54 2/ $'75* i/o port also functioning as external interrupt input ( ,54 ), and a/d converter external trigger input ( $'75* ) i/o port also functioning as external interrupt input ( ,54 ) and a/d converter external trigger input ( $'75* ) port 5 3-bit i/o port p52/sck0 p51/rxd0 p50/txd0 i/o port also functioning as sci0 input/output (txd0, rxd0, sck0) port 6 8-bit i/o port p67/tmo1/cin7 p66/ftob/ tmri1/cin6 p65/ftid/tmci1/ cin5 p64/ftic/tmo0/ cin4 p63/ftib/tmri0/ cin3 p62/ftia/tmiy/ cin2 p61/ftoa/cin1 p60/ftci/tmci0/ cin0 i/o port also functioning as frt input/output (ftci, ftoa, ftia, ftib, ftic, ftid, ftob), 8-bit timer 0 and 1 input/output (tmci0, tmri0, tmo0, tmci1, tmri1, tmo1), 8-bit timer y input (tmiy), and expansion a/d converter input (cin7 to cin0) port 7 8-bit input port p77/an7 p76/an6 p75/an5 p74/an4 p73/an3 p72/an2 p71/an1 p70/an0 input port also functioning as a/d converter analog input (an7 to an0) 189 8.2 port 1 8.2.1 overview port 1 is an 8-bit i/o port. port 1 pins also function as address bus output pins as 8-bit pwm output pins (pw7 to pw0) (h8s/2128 series only), and as 14-bit pwm output pins (pwx1 to pwx0) (h8s/2128 series only). port 1 functions change according to the operating mode. port 1 has a built-in mos input pull-up function that can be controlled by software. figure 8.1 shows the port 1 pin configuration. p17/a7/pw7 p16/a6/pw6 p15/a5/pw5 p14/a4/pw4 p13/a3/pw3 p12/a2/pw2 p11/a1/pw1/pwx1 p10/a0/pw0/pwx0 port 1 port 1 pins a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) pin functions in mode 1 a7 (output)/p17 (input)/pw7 (output) a6 (output)/p16 (input)/pw6 (output) a5 (output)/p15 (input)/pw5 (output) a4 (output)/p14 (input)/pw4 (output) a3 (output)/p13 (input)/pw3 (output) a2 (output)/p12 (input)/pw2 (output) a1 (output)/p11 (input)/pw1 (output)/pwx1 (output) a0 (output)/p10 (input)/pw0 (output)/pwx0 (output) pin functions in modes 2 and 3 (expe = 1) p17 (i/o)/pw7 (output) p16 (i/o)/pw6 (output) p15 (i/o)/pw5 (output) p14 (i/o)/pw4 (output) p13 (i/o)/pw3 (output) p12 (i/o)/pw2 (output) p11 (i/o)/pw1 (output)/pwx1 (output) p10 (i/o)/pw0 (output)/pwx0 (output) pin functions in modes 2 and 3 (expe = 0) figure 8.1 port 1 pin functions 190 8.2.2 register configuration table 8.3 shows the port 1 register configuration. table 8.3 port 1 registers name abbreviation r/w initial value address * port 1 data direction register p1ddr w h'00 h'ffb0 port 1 data register p1dr r/w h'00 h'ffb2 port 1 mos pull-up control register p1pcr r/w h'00 h'ffac note: * lower 16 bits of the address. port 1 data direction register (p1ddr) 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value read/write p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be returned. p1ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. the address output pins maintain their output state in a transition to software standby mode. mode 1 the corresponding port 1 pins are address outputs, regardless of the p1ddr setting. in hardware standby mode, the address outputs go to the high-impedance state. modes 2 and 3 (expe = 1) the corresponding port 1 pins are address outputs or pwm outputs when p1ddr bits are set to 1, and input ports when cleared to 0. p10 and p11 can be designated as pwmx outputs regardless of p1ddr, but to ensure normal execution of external space accesses, this designation should not be used. modes 2 and 3 (expe = 0) the corresponding port 1 pins are output ports or pwm outputs when p1ddr bits are set to 1, and input ports when cleared to 0. p10 and p11 can be designated as pwmx outputs regardless of p1ddr. 191 port 1 data register (p1dr) 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit initial value r/w p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p17 to p10). if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read directly, regardless of the actual pin states. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. p1dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 1 mos pull-up control register (p1pcr) 7 p17pcr 0 r/w 6 p16pcr 0 r/w 5 p15pcr 0 r/w 4 p14pcr 0 r/w 3 p13pcr 0 r/w 0 p10pcr 0 r/w 2 p12pcr 0 r/w 1 p11pcr 0 r/w bit initial value r/w p1pcr is an 8-bit readable/writable register that controls the port 1 built-in mos input pull-ups on a bit-by-bit basis. in modes 2 and 3, the mos input pull-up is turned on when a p1pcr bit is set to 1 while the corresponding p1ddr bit is cleared to 0 (input port setting). p1pcr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 192 8.2.3 pin functions in each mode mode 1: in mode 1, port 1 pins automatically function as address outputs. the port 1 pin functions are shown in figure 8.2. a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) port 1 figure 8.2 port 1 pin functions (mode 1) modes 2 and 3 (expe = 1): in modes 2 and 3 (when expe = 1), port 1 pins function as address outputs, pwm outputs, or input ports, and input or output can be specified on a bit-by-bit basis. when a bit in p1ddr is set to 1, the corresponding pin functions as an address output or pwm output, and when cleared to 0, as an input port. p10 and p11 can be designated as pwmx outputs regardless of p1ddr, but to ensure normal execution of external space accesses, this designation should not be used. the port 1 pin functions are shown in figure 8.3. a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output)/pwx1 (output) a0 (output)/pwx0 (output) port 1 when p1ddr = 1 and pwoera = 0 p17 (input) p16 (input) p15 (input) p14 (input) p13 (input) p12 (input) p11 (input)/pwx1 (output) p10 (input)/pwx0 (output) when p1ddr = 0 pw7 (output) pw6 (output) pw5 (output) pw4 (output) pw3 (output) pw2 (output) pw1 (output)/pwx1 (output) pw0 (output)/pwx0 (output) when p1ddr = 1 and pwoera = 1 figure 8.3 port 1 pin functions (modes 2 and 3 (expe = 1)) 193 modes 2 and 3 (expe = 0): in modes 2 and 3 (when expe = 0), port 1 pins function as pwm outputs or i/o ports, and input or output can be specified on a bit-by-bit basis. when a bit in p1ddr is set to 1, the corresponding pin functions as a pwm output or output port, and when cleared to 0, as an input port. p10 and p11 can be designated as pwmx outputs regardless of p1ddr. the port 1 pin functions are shown in figure 8.4. p17 (i/o) p16 (i/o) p15 (i/o) p14 (i/o) p13 (i/o) p12 (i/o) p11 (i/o)/pwx1 (output) p10 (i/o)/pwx0 (output) port 1 p1n: input pin when p1ddr = 0, output pin when p1ddr = 1 and pwoera = 0 pw7 (output) pw6 (output) pw5 (output) pw4 (output) pw3 (output) pw2 (output) pw1 (output)/pwx1 (output) pw0 (output)/pwx0 (output) when p1ddr = 1 and pwoera = 1 figure 8.4 port 1 pin functions (modes 2 and 3 (expe = 0)) 194 8.2.4 mos input pull-up function port 1 has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit- by-bit basis. when a p1ddr bit is cleared to 0 in mode 2 or 3, setting the corresponding p1pcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the prior state is retained in software standby mode. table 8.4 summarizes the mos input pull-up states. table 8.4 mos input pull-up states (port 1) mode reset hardware standby mode software standby mode in other operations 1 off off off off 2, 3 off off on/off on/off legend: off: mos input pull-up is always off. on/off: on when p1ddr = 0 and p1pcr = 1; otherwise off. 195 8.3 port 2 8.3.1 overview port 2 is an 8-bit i/o port. port 2 pins also function as address bus output pins, 8-bit pwm output pins (pw15 to pw8) (h8s/2128 series only), the timer connection output pin (cblank) (h8s/2128 series only), iic1 i/o pins (scl1, sda1) (option in h8s/2128 series only), and sci1 i/o pins (sck1, rxd1, txd1). port 2 functions change according to the operating mode. port 2 has a built-in mos input pull-up function that can be controlled by software. figure 8.5 shows the port 2 pin configuration. p27/a15/pw15/sck1/cblank p26/a14/pw14/rxd1 p25/a13/pw13/txd1 p24/a12/pw12/scl1 p23/a11/pw11/sda1 p22/a10/pw10 p21/a9/pw9 p20/a8/pw8 port 2 port 2 pins a15 (output) a14 (output) a13 (output) a12 (output) a11 (output) a10 (output) a9 (output) a8 (output) pin functions in mode 1 a15 (output)/p27 (input)/pw15 (output)/sck1(i/o)/cblank (output) a14 (output)/p26 (input)/pw14 (output)/rxd1 (input) a13 (output)/p25 (input)/pw13 (output)/txd1 (output) a12 (output)/p24 (input)/pw12 (output)/scl1 (i/o) a11 (output)/p23 (input)/pw11 (output)/sda1 (i/o) a10 (output)/p22 (input)/pw10 (output) a9 (output)/p21 (input)/pw9 (output) a8 (output)/p20 (input)/pw8 (output) pin functions in modes 2 and 3 (expe = 1) p27 (i/o)/pw15 (output)/sck1(i/o)/cblank (output) p26 (i/o)/pw14 (output)/rxd1 (input) p25 (i/o)/pw13 (output)/txd1 (output) p24 (i/o)/pw12 (output)/scl1 (i/o) p23 (i/o)/pw11 (output)/sda1 (i/o) p22 (i/o)/pw10 (output) p21 (i/o)/pw9 (output) p20 (i/o)/pw8 (output) pin functions in modes 2 and 3 (expe = 0) figure 8.5 port 2 pin functions 196 8.3.2 register configuration table 8.5 shows the port 2 register configuration. table 8.5 port 2 registers name abbreviation r/w initial value address * port 2 data direction register p2ddr w h'00 h'ffb1 port 2 data register p2dr r/w h'00 h'ffb3 port 2 mos pull-up control register p2pcr r/w h'00 h'ffad note: * lower 16 bits of the address. port 2 data direction register (p2ddr) 7 p27ddr 0 w 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 0 p20ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w bit initial value read/write p2ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. p2ddr cannot be read; if it is, an undefined value will be returned. p2ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. the address output pins maintain their output state in a transition to software standby mode. mode 1 the corresponding port 2 pins are address outputs, regardless of the p2ddr setting. in hardware standby mode, the address outputs go to the high-impedance state. modes 2 and 3 (expe = 1) the corresponding port 2 pins are address outputs or pwm outputs when p2ddr bits are set to 1, and input ports when cleared to 0. p27 to p24 are switched from address outputs to output ports by setting the iose bit to 1. p27 to p23 can be used as an on-chip supporting module output pin regardless of the p2ddr setting, but to ensure normal access to external space, p27 should not be set as an on-chip supporting module output pin when port 2 pins are used as address output pins. modes 2 and 3 (expe = 0) the corresponding port 2 pins are output ports or pwm outputs when p2ddr bits are set to 1, and input ports when cleared to 0. 197 p27 to p23 can be used as an on-chip supporting module output pin regardless of the p2ddr setting. port 2 data register (p2dr) 7 p27dr 0 r/w 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 0 p20dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w bit initial value r/w p2dr is an 8-bit readable/writable register that stores output data for the port 2 pins (p27 to p20). if a port 2 read is performed while p2ddr bits are set to 1, the p2dr values are read directly, regardless of the actual pin states. if a port 2 read is performed while p2ddr bits are cleared to 0, the pin states are read. p2dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 2 mos pull-up control register (p2pcr) 7 p27pcr 0 r/w 6 p26pcr 0 r/w 5 p25pcr 0 r/w 4 p24pcr 0 r/w 3 p23pcr 0 r/w 0 p20pcr 0 r/w 2 p22pcr 0 r/w 1 p21pcr 0 r/w bit initial value r/w p2pcr is an 8-bit readable/writable register that controls the port 2 built-in mos input pull-ups on a bit-by-bit basis. in modes 2 and 3, the mos input pull-up is turned on when a p2pcr bit is set to 1 while the corresponding p2ddr bit is cleared to 0 (input port setting). p2pcr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 198 8.3.3 pin functions in each mode mode 1: in mode 1, port 2 pins automatically function as address outputs. the port 2 pin functions are shown in figure 8.6. a15 (output) a14 (output) a13 (output) a12 (output) a11 (output) a10 (output) a9 (output) a8 (output) port 2 figure 8.6 port 2 pin functions (mode 1) modes 2 and 3 (expe = 1): in modes 2 and 3 (when expe = 1), port 2 pins function as address outputs, pwm outputs, or i/o ports, and input or output can be specified on a bit-by-bit basis. when a bit in p2ddr is set to 1, the corresponding pin functions as an address output or pwm output, and when cleared to 0, as an input port. p27 to p24 are switched from address outputs to output ports by setting the iose bit to 1. p27 to p23 can be used as an on-chip supporting module output pin regardless of the p2ddr setting, but to ensure normal access to external space, p27 should not be set as an on-chip supporting module output pin when port 2 pins are used as address output pins. the port 2 pin functions are shown in figure 8.7. a15 (output)/p27 (output) a14 (output)/p26 (output) a13 (output)/p25 (output) a12 (output)/p24 (output) a11 (output) a10 (output) a9 (output) a8 (output) port 2 when p2ddr = 1 and pwoerb = 0 p27 (input)/sck1 (i/o)/cblank (output) p26 (input)/rxd1 (input) p25 (input)/txd1 (output) p24 (input)/scl1 (i/o) p23 (input)/sda1 (i/o) p22 (input) p21 (input) p20 (input) when p2ddr = 0 pw15 (output)/sck1 (i/o)/cblank (output) pw14 (output)/rxd1 (input) pw13 (output)/txd1 (output) pw12 (output)/scl1 (i/o) pw11 (output)/sda1 (i/o) pw10 (output) pw9 (output) pw8 (output) when p2ddr = 1 and pwoerb = 1 figure 8.7 port 2 pin functions (modes 2 and 3 (expe = 1)) 199 modes 2 and 3 (expe = 0): in modes 2 and 3 (when expe = 0), port 2 pins function as pwm outputs, the timer connection output (cblank), iic1 i/o pins (scl1, sda1), sci1 i/o pins (sck1, rxd1, txd1), or i/o ports, and input or output can be specified on a bit-by-bit basis. when a bit in p2ddr is set to 1, the corresponding pin functions as a pwm output or output port, and when cleared to 0, as an input port. p27 to p23 can be used as an on-chip supporting module output pin regardless of the p2ddr setting. the port 2 pin functions are shown in figure 8.8. p27 (i/o)/sck1 (i/o)/cblank (output) p26 (i/o)/rxd1 (input) p25 (i/o)/txd1 (output) p24 (i/o)/scl1 (i/o) p23 (i/o)/sda1 (i/o) p22 (i/o) p21 (i/o) p20 (i/o) port 2 p2n: input pin when p2ddr = 0, output pin when p2ddr = 1 and pwoerb = 0 pw15 (output)/sck1 (i/o)/cblank (output) pw14 (output)/rxd1 (input) pw13 (output)/txd1 (output) pw12 (output)/scl1 (i/o) pw11 (output)/sda1 (i/o) pw10 (output) pw9 (output) pw8 (output) when p2ddr = 1 and pwoerb = 1 figure 8.8 port 2 pin functions (modes 2 and 3 (expe = 0)) 8.3.4 mos input pull-up function port 2 has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit- by-bit basis. when a p2ddr bit is cleared to 0 in mode 2 or 3, setting the corresponding p2pcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the prior state is retained in software standby mode. table 8.6 summarizes the mos input pull-up states. 200 table 8.6 mos input pull-up states (port 2) mode reset hardware standby mode software standby mode in other operations 1 off off off off 2, 3 off off on/off on/off legend: off: mos input pull-up is always off. on/off: on when p2ddr = 0 and p2pcr = 1; otherwise off. 8.4 port 3 8.4.1 overview port 3 is an 8-bit i/o port. port 3 pins also function as data bus i/o pins. port 3 functions change according to the operating mode. port 3 has a built-in mos input pull-up function that can be controlled by software. figure 8.9 shows the port 3 pin configuration. p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 port 3 port 3 pins d7 (i/o) d6 (i/o) d5 (i/o) d4 (i/o) d3 (i/o) d2 (i/o) d1 (i/o) d0 (i/o) pin functions in modes 1, 2 and 3 (expe = 1) p37 (i/o) p36 (i/o) p35 (i/o) p34 (i/o) p33 (i/o) p32 (i/o) p31 (i/o) p30 (i/o) pin functions in modes 2 and 3 (expe = 0) figure 8.9 port 3 pin functions 201 8.4.2 register configuration table 8.7 shows the port 3 register configuration. table 8.7 port 3 registers name abbreviation r/w initial value address * port 3 data direction register p3ddr w h'00 h'ffb4 port 3 data register p3dr r/w h'00 h'ffb6 port 3 mos pull-up control register p3pcr r/w h'00 h'ffae note: * lower 16 bits of the address. port 3 data direction register (p3ddr) 7 p37ddr 0 w 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w bit initial value read/write p3ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. p3ddr cannot be read; if it is, an undefined value will be returned. p3ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. modes 1, 2, and 3 (expe = 1) the input/output direction specified by p3ddr is ignored, and pins automatically function as data i/o pins. after a reset, and in hardware standby mode or software standby mode, the data i/o pins go to the high-impedance state. modes 2 and 3 (expe = 0) the corresponding port 3 pins are output ports when p3ddr bits are set to 1, and input ports when cleared to 0. 202 port 3 data register (p3dr) 7 p37dr 0 r/w 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit initial value read/write p3dr is an 8-bit readable/writable register that stores output data for the port 3 pins (p37 to p30). if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read directly, regardless of the actual pin states. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. p3dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 3 mos pull-up control register (p3pcr) 7 p37pcr 0 r/w 6 p36pcr 0 r/w 5 p35pcr 0 r/w 4 p34pcr 0 r/w 3 p33pcr 0 r/w 0 p30pcr 0 r/w 2 p32pcr 0 r/w 1 p31pcr 0 r/w bit initial value read/write p3pcr is an 8-bit readable/writable register that controls the port 3 built-in mos input pull-ups on a bit-by-bit basis. in modes 2 and 3 (when expe = 0), the mos input pull-up is turned on when a p3pcr bit is set to 1 while the corresponding p3ddr bit is cleared to 0 (input port setting). p3pcr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 203 8.4.3 pin functions in each mode modes 1, 2, and 3 (expe = 1): in modes 1, 2, and 3 (when expe = 1), port 3 pins automatically function as data i/o pins. the port 3 pin functions are shown in figure 8.10. d7 (i/o) d6 (i/o) d5 (i/o) d4 (i/o) d3 (i/o) d2 (i/o) d1 (i/o) d0 (i/o) port 3 figure 8.10 port 3 pin functions (modes 1, 2, and 3 (expe = 1)) modes 2 and 3 (expe = 0): in modes 2 and 3 (when expe = 0), port 3 functions as an i/o port, and input or output can be specified on a bit-by-bit basis. when a bit in p3ddr is set to 1, the corresponding pin functions as an output port, and when cleared to 0, as an input port. the port 3 pin functions are shown in figure 8.11. p37 (i/o) p36 (i/o) p35 (i/o) p34 (i/o) p33 (i/o) p32 (i/o) p31 (i/o) p30 (i/o) port 3 figure 8.11 port 3 pin functions (modes 2 and 3 (expe = 0)) 204 8.4.4 mos input pull-up function port 3 has a built-in mos input pull-up function that can be controlled by software. this mos input pull-up function can be used in modes 2 and 3 (when expe = 0), and can be specified as on or off on a bit-by-bit basis. when a p3ddr bit is cleared to 0 in mode 2 or 3 (when expe = 0), setting the corresponding p3pcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset and in hardware standby mode. the prior state is retained in software standby mode. table 8.8 summarizes the mos input pull-up states. table 8.8 mos input pull-up states (port 3) mode reset hardware standby mode software standby mode in other operations 1, 2, 3 (expe = 1) off off off off 2, 3 (expe = 0) off off on/off on/off legend: off: mos input pull-up is always off. on/off: on when p3ddr = 0 and p3pcr = 1; otherwise off. 205 8.5 port 4 8.5.1 overview port 4 is an 8-bit i/o port. port 4 pins also function as the ,54 to ,54 input pins, a/d converter external trigger input pin ( $'75* ), iic0 i/o pin (sda0) (option in h8s/2128 series only), subclock input pin (excl), bus control signal i/o pins ( $6 / ,26 , 5' , :5 , :$,7 ), and system clock (?) output pin. in the h8s/2128 series, p47 is an nmos push-pull output. sda0 is an nmos open-drain output, and has direct bus drive capability. figure 8.12 shows the port 4 pin configuration. p47/wait/sda0 p46/?excl p45/as/ios p44/wr p43/rd p42/irq0 p41/irq1 p40/irq2/adtrg port 4 port 4 pins wait (input)/p47 (i/o)/sda0 (i/o) ?(output)/p46 (input)/excl (input) as (output)/ios (output) wr (output) rd (output) p42 (i/o)/irq0 (input) p41 (i/o)/irq1 (input) p40 (i/o)/irq2 (input)/adtrg (input) pin functions in modes 1, 2 and 3 (expe = 1) p47 (i/o)/sda0 (i/o) p46 (input)/?(output)/excl (input) p45 (i/o) p44 (i/o) p43 (i/o) p42 (i/o)/irq0 (input) p41 (i/o)/irq1 (input) p40 (i/o)/irq2 (input)/adtrg (input) pin functions in modes 2 and 3 (expe = 0) figure 8.12 port 4 pin functions 206 8.5.2 register configuration table 8.9 summarizes the port 4 registers. table 8.9 port 4 registers name abbreviation r/w initial value address * 1 port 4 data direction register p4ddr w h'40/h'00 * 2 h'ffb5 port 4 data register p4dr r/w h'00 h'ffb7 notes: 1. lower 16 bits of the address. 2. initial value depends on the mode. port 4 data direction register (p4ddr) bit 76543210 p47ddr p46ddr p45ddr p44ddr p43ddr p42ddr p41ddr p40ddr mode 1 initial value 0 1 0 0 0 0 0 0 read/write w w w w w w w w modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 207 p4ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 4. p4ddr cannot be read; if it is, an undefined value will be returned. p4ddr is initialized to h'40 (mode 1) or h'00 (modes 2 and 3) by a reset and in hardware standby mode. it retains its prior state in software standby mode. modes 1, 2, and 3 (expe = 1) pin p47 functions as a bus control input ( :$,7 ), iic0 i/o pin (sda0), or i/o port, according to the wait mode setting. when p47 functions as an i/o port, it becomes an output port when p47ddr is set to 1, and an input port when p47ddr is cleared to 0. pin p46 functions as the ? output pin when p46ddr is set to 1, and as the subclock input (excl) or an input port when p46ddr is cleared to 0. pins p45 to p43 automatically become bus control outputs ( $6 / ,26 , :5 , 5' ), regardless of the input/output direction indicated by p45ddr to p43ddr. pins p42 to p40 become output ports when p42ddr to p40ddr are set to 1, and input ports when p42ddr to p40ddr are cleared to 0. modes 2 and 3 (expe = 0) when the corresponding p4ddr bits are set to 1, pin p46 functions as the ? output pin and pins p47 and p45 to p40 become output ports. when p4ddr bits are cleared to 0, the corresponding pins become input ports. port 4 data register (p4dr) bit 76543210 p47dr p46dr p45dr p44dr p43dr p42dr p41dr p40dr initial value 0 * 000000 read/write r/w r r/w r/w r/w r/w r/w r/w note: * determined by the state of pin p46. p4dr is an 8-bit readable/writable register that stores output data for the port 4 pins (p47 to p40). with the exception of p46, if a port 4 read is performed while p4ddr bits are set to 1, the p4dr values are read directly, regardless of the actual pin states. if a port 4 read is performed while p4ddr bits are cleared to 0, the pin states are read. p4dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 8.5.3 pin functions port 4 pins also function as the ,54 to ,54 input pins, a/d converter input pin ( $'75* ), iic0 i/o pin (sda0), subclock input pin (excl), bus control signal i/o pins ( $6 / ,26 , 5' , :5 , :$,7 ), and system clock (?) output pin. the pin functions differ between the mode 1, 2, and 3 208 (expe = 1) expanded modes and the mode 2 and 3 (expe = 0) single-chip modes. the port 4 pin functions are shown in table 8.10. table 8.10 port 4 pin functions pin selection method and pin functions p47/ :$,7 /sda0 the pin function is switched as shown below according to the combination of operating mode, bit wms1 in wscr, bit ice in iccr of iic0, and bit p47ddr. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) wms1 0 1 ice 0 1 0 1 p47ddr 0 1 0 1 pin function p47 input pin p47 output pin sda0 i/o pin :$,7 input pin p47 input pin p47 output pin sda0 i/o pin in the h8s/2128 series, when this pin is set as the p47 output pin, it is an nmos push-pull output. sda0 is an nmos open-drain output, and has direct bus drive capability. p46/?/excl the pin function is switched as shown below according to the combination of bit excle in lpwrcr and bit p46ddr. p46ddr 0 1 excle 0 1 0 pin function p46 input pin excl input pin ? output pin when this pin is used as the excl input pin, p46ddr should be cleared to 0. p45/ $6 / ,26 the pin function is switched as shown below according to the combination of operating mode, bits iose in syscr, and bit p45ddr. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) p45ddr 0 1 iose 0 1 pin function $6 output pin ,26 output pin p45 input pin p45 output pin p44/ :5 the pin function is switched as shown below according to the combination of operating mode, and bit p44ddr. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) p44ddr 0 1 pin function :5 output pin p44 input pin p44 output pin 209 table 8.10 port 4 pin functions (cont) pin selection method and pin functions p43/ 5' / ,25 the pin function is switched as shown below according to the combination of operating mode, and bit p43ddr. operating mode modes 1, 2, 3 (expe = 1) modes 2, 3 (expe = 0) p43ddr 0 1 pin function 5' output pin p43 input pin p43 output pin p42/ ,54 p42ddr 0 1 pin function p42 input pin p42 output pin ,54 input pin when bit irq0e in ier is set to 1, this pin is used as the ,54 input pin. p41/ ,54 p41ddr 0 1 pin function p41 input pin p41 output pin ,54 input pin when bit irq1e in ier is set to 1, this pin is used as the ,54 input pin. p40/ ,54 / $'75* p40ddr 0 1 pin function p40 input pin p40 output pin ,54 input pin, $'75* input pin when the irq2e bit in ier is set to 1, this pin is used as the ,54 input pin. when trgs1 and trgs0 bit in adcr of the a/d converter are both set to 1, this pin is used as the $'75* input pin. 210 8.6 port 5 8.6.1 overview port 5 is a 3-bit i/o port. port 5 pins also function as sci0 i/o pins (txd0, rxd0, sck0), and the iic0 i/o pin (scl0) (option in h8s/2128 series only). in the h8s/2128 series, p52 and sck0 are nmos push-pull outputs, and scl0 is an nmos open-drain output. port 5 pin functions are the same in all operating modes. figure 8.13 shows the port 5 pin configuration. p52 (i/o)/sck0 (i/o)/scl0 (i/o) p51 (i/o)/rxd0 (input) p50 (i/o)/txd0 (output) port 5 port 5 pins figure 8.13 port 5 pin functions 8.6.2 register configuration table 8.11 shows the port 5 register configuration. table 8.11 port 5 registers name abbreviation r/w initial value address * port 5 data direction register p5ddr w h'f8 h'ffb8 port 5 data register p5dr r/w h'f8 h'ffba note: * lower 16 bits of the address. 211 port 5 data direction register (p5ddr) 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 p50ddr 0 w 2 p52ddr 0 w 1 p51ddr 0 w bit initial value read/write p5ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. p5ddr cannot be read; if it is, an undefined value will be returned. bits 7 to 3 are reserved. setting a p5ddr bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p5ddr is initialized to h'f8 by a reset and in hardware standby mode. it retains its prior state in software standby mode. as sci0 is initialized, the pin states are determined by the iic0 iccr, p5ddr, and p5dr specifications. port 5 data register (p5dr) 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 p50dr 0 r/w 2 p52dr 0 r/w 1 p51dr 0 r/w bit initial value read/write p5dr is an 8-bit readable/writable register that stores output data for the port 5 pins (p52 to p50). if a port 5 read is performed while p5ddr bits are set to 1, the p5dr values are read directly, regardless of the actual pin states. if a port 5 read is performed while p5ddr bits are cleared to 0, the pin states are read. bits 7 to 3 are reserved; they cannot be modified and are always read as 1. p5dr is initialized to h'f8 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 212 8.6.3 pin functions port 5 pins also function as sci0 i/o pins (txd0, rxd0, sck0) and the iic0 i/o pin (scl0). the port 5 pin functions are shown in table 8.12. table 8.12 port 5 pin functions pin selection method and pin functions p52/sck0/scl0 the pin function is switched as shown below according to the combination of bits cke1 and cke0 in scr, bit c/ $ in smr of sci0, bit ice in iccr of iic0, and bit p52ddr. ice 0 1 cke1 0 1 0 c/ $ 010 cke0 0 1 0 p52ddr 0 1 pin function p52 input pin p52 output pin sck0 output pin sck0 output pin sck0 input pin scl0 i/o pin when this pin is used as the scl0 i/o pin, bits cke1 and cke0 in scr of sci0 and bit c/ $ in smr of sci0 must all be cleared to 0. scl0 is an nmos open-drain output, and has direct bus drive capability. in the h8s/2128 series, when set as the p52 output pin or sck0 output pin, this pin is an nmos push-pull output. p51/rxd0 the pin function is switched as shown below according to the combination of bit re in scr of sci0 and bit p51ddr. re 0 1 p51ddr 0 1 pin function p51 input pin p51 output pin rxd input pin p50/txd0 the pin function is switched as shown below according to the combination of bit te in scr of sci0 and bit p50ddr. te 0 1 p50ddr 0 1 pin function p50 input pin p50 output pin txd0 output pin 213 8.7 port 6 8.7.1 overview port 6 is an 8-bit i/o port. port 6 pins also function as the 16-bit free-running timer (frt) i/o pins (ftoa, ftob, ftia to ftid, ftci), timer 0 and 1 (tmr0, tmr1) i/o pins (tmci0, tmri0, tmo0, tmci1, tmri1, tmo1), timer x (tmrx) i/o pins (tmox, tmix) (h8s/2128 series only), the timer y (tmry) input pin (tmiy), timer connection i/o pins (csynci, hsynci, hsynco, hfbacki, vsynci, vsynco, vfbacki, clampo) (h8s/2128 series only), and expansion a/d converter input pins (cin7 to cin0). port 6 pin functions are the same in all operating modes. figure 8.14 shows the port 6 pin configuration. p67 (i/o)/tmox (output)/tmo1 (output)/cin7 (input)/hsynco (output) p66 (i/o)/ftob (output)/tmri1 (input)/cin6 (input)/csynci (input) p65 (i/o)/ftid (input)/tmci1 (input)/cin5 (input)/hsynci (input) p64 (i/o)/ftic (input)/tmo0 (output)/cin4 (input)/clampo (output) p63 (i/o)/ftib (input)/tmri0 (input)/cin3 (input)/vfbacki (input) p62 (i/o)/ftia (input)/cin2 (input)/vsynci (input)/tmiy (input) p61 (i/o)/ftoa (output)/cin1 (input)/vsynco (output) p60 (i/o)/ftci (input)/tmcio (input)/cin0 (input)/hfbacki (input)/tmix (input) port 6 port 6 pins figure 8.14 port 6 pin functions 8.7.2 register configuration table 8.13 shows the port 6 register configuration. table 8.13 port 6 registers name abbreviation r/w initial value address * port 6 data direction register p6ddr w h'00 h'ffb9 port 6 data register p6dr r/w h'00 h'ffbb note: * lower 16 bits of the address. 214 port 6 data direction register (p6ddr) 7 p67ddr 0 w 6 p66ddr 0 w 5 p65ddr 0 w 4 p64ddr 0 w 3 p63ddr 0 w 0 p60ddr 0 w 2 p62ddr 0 w 1 p61ddr 0 w bit initial value read/write p6ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. p6ddr cannot be read; if it is, an undefined value will be returned. setting a p6ddr bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p6ddr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. port 6 data register (p6dr) 7 p67dr 0 r/w 6 p66dr 0 r/w 5 p65dr 0 r/w 4 p64dr 0 r/w 3 p63dr 0 r/w 0 p60dr 0 r/w 2 p62dr 0 r/w 1 p61dr 0 r/w bit initial value read/write p6dr is an 8-bit readable/writable register that stores output data for the port 6 pins (p67 to p60). if a port 6 read is performed while p6ddr bits are set to 1, the p6dr values are read directly, regardless of the actual pin states. if a port 6 read is performed while p6ddr bits are cleared to 0, the pin states are read. p6dr is initialized to h'00 by a reset and in hardware standby mode. it retains its prior state in software standby mode. 215 8.7.3 pin functions port 6 pins also function as the 16-bit free-running timer (frt) i/o pins (ftoa, ftob, ftia to ftid, ftci), timer 0 and 1 (tmr0, tmr1) i/o pins (tmci0, tmri0, tmo0, tmci1, tmri1, tmo1), timer x (tmrx) i/o pins (tmox, tmix), the timer y (tmry) input pin (tmiy), timer connection i/o pins (csynci, hsynci, hsynco, hfbacki, vsynci, vsynco, vfbacki, clampo), and expansion a/d converter input pins (cin7 to cin0). the port 6 pin functions are shown in table 8.14. table 8.14 port 6 pin functions pin selection method and pin functions p67/tmo1/tmox/ cin7/hsynco the pin function is switched as shown below according to the combination of bits os3 to os0 in tcsr of tmr1 and tmrx, bit hoe in tconro of the timer connection function, and bit p67ddr. hoe 0 1 tmrx: os3 to 0 all 0 not all 0 tmr1: os3 to 0 all 0 not all 0 p67ddr 0 1 pin function p67 input pin p67 output pin tmo1 output pin tmox output pin hsynco output pin cin7 input pin it can always be used as the cin7 input pin. p66/ftob/tmri1/ cin6/csynci the pin function is switched as shown below according to the combination of bit oeb in tocr of the frt and bit p66ddr. oeb 0 1 p66ddr 0 1 pin function p66 input pin p66 output pin ftob output pin tmri1 input pin, csynci input pin, cin6 input pin this pin is used as the tmri1 input pin when bits cclr1 and cclr0 are both set to 1 in tcr of tmr1. it can always be used as the csynci or cin6 input pin. 216 table 8.14 port 6 pin functions (cont) pin selection method and pin functions p65/ftid/tmci1/ p65ddr 0 1 cin5/hsynci pin function p65 input pin p65 output pin ftid input pin, tmci1 input pin, hsynci input pin, cin5 input pin this pin is used as the tmci1 input pin when an external clock is selected with bits cks2 to cks0 in tcr of tmr1. it can always be used as the ftid, hsynci or cin5 input pin. p64/ftic/tmo0/ cin4/clampo the pin function is switched as shown below according to the combination of bits os3 to os0 in tcsr of tmr0, bit cloe in tconro of the timer connection function, and bit p64ddr. cloe 0 1 os3 to 0 all 0 not all 0 p64ddr 0 1 pin function p64 input pin p64 output pin tmo0 output pin clampo output pin ftic input pin, cin4 input pin this pin can always be used as the ftic or cin4 input pin. p63/ftib/tmri0/ p63ddr 0 1 cin3/vfbacki pin function p63 input pin p63 output pin ftib input pin, tmri0 input pin, vfbacki input pin, cin3 input pin this pin is used as the tmri0 input pin when bits cclr1 and cclr0 are both set to 1 in tcr of tmr0. it can always be used as the ftib, vfbacki or cin3 input pin. p62/ftia/cin2/ p62ddr 0 1 vsynci/tmiy pin function p62 input pin p62 output pin ftia input pin, vsynci input pin, tmiy input pin, cin2 input pin this pin can always be used as the ftia, tmiy, vsynci or cin2 input pin. 217 table 8.14 port 6 pin functions (cont) pin selection method and pin functions p61/ftoa/cin1/ vsynco the pin function is switched as shown below according to the combination of bit oea in tocr of the frt, bit voe in tconro of the timer connection function, and bit p61ddr. voe 0 1 oea 0 1 0 p61ddr 0 1 pin function p61 input pin p61 output pin ftoa0 output pin vsynco output pin cin1 input pin when this pin is used as the vsynco pin, the oea bit in tocr of the frt must be cleared. this pin can always be used as the cin1 pin. p60/ftci/tmci0/ cin0/hfbacki/ tmix p60ddr pin function 01 p60 i/o pin p60 output pin ftci input pin, tmci0 input pin, hfbacki input pin, cin0 input pin, tmix input pin this pin is used as the ftci input pin when an external clock is selected with bits cks1 and cks0 in tcr of the frt. it is used as the tmci0 input pin when an external clock is selected with bits cks2 to cks0 in tcr of tmr0. it can always be used as the tmix, hfbacki, cin0 input pin. 218 8.8 port 7 8.8.1 overview port 7 is an 8-bit input port. port 7 pins also function as the a/d converter analog input pins (an0 to an7). port 7 functions are the same in all operating modes. figure 8.15 shows the port 7 pin configuration. p77 (input)/an7 (input) p76 (input)/an6 (input) p75 (input)/an5 (input) p74 (input)/an4 (input) p73 (input)/an3 (input) p72 (input)/an2 (input) p71 (input)/an1 (input) p70 (input)/an0 (input) port 7 port 7 pins figure 8.15 port 7 pin functions 219 8.8.2 register configuration table 8.16 shows the port 7 register configuration. port 7 is an input-only port, and does not have a data direction register or data register. table 8.16 port 7 registers name abbreviation r/w initial value address * port 7 input data register p7pin r undefined h'ffbe note: * lower 16 bits of the address. port 7 input data register (p7pin) 7 p77pin * r 6 p76pin * r 5 p75pin * r 4 p74pin * r 3 p73pin * r 0 p70pin * r 2 p72pin * r 1 p71pin * r bit initial value read/write note: * determined by the state of pins p77 to p70. when a p7pin read is performed, the pin states are always read. 8.8.3 pin functions port 7 pins also function as the a/d converter analog input pins (an0 to an7). 220 221 section 9 8-bit pwm timers [h8s/2128 series] 9.1 overview the h8/2128 series has an on-chip pulse width modulation (pwm) timer module with sixteen outputs. sixteen output waveforms are generated from a common time base, enabling pwm output with a high carrier frequency to be produced using pulse division. the pwm timer module has sixteen 8-bit pwm data registers (pwdrs), and an output pulse with a duty cycle of 0 to 100% can be obtained as specified by pwdr and the port data register (p1dr or p2dr). 9.1.1 features the pwm timer module has the following features. operable at a maximum carrier frequency of 1.25 mhz using pulse division (at 20 mhz operation) duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output) direct or inverted pwm output, and pwm output enable/disable control 222 9.1.2 block diagram figure 9.1 shows a block diagram of the pwm timer module. pwdr0 pwdr1 pwdr2 pwdr3 pwdr4 pwdr5 pwdr6 pwdr7 pwdr8 pwdr9 pwdr10 pwdr11 pwdr12 pwdr13 pwdr14 pwdr15 p10/pw0 p11/pw1 p12/pw2 p13/pw3 p14/pw4 p15/pw5 p16/pw6 p17/pw7 p20/pw8 p21/pw9 p22/pw10 p23/pw11 p24/pw12 p25/pw13 p26/pw14 p27/pw15 port/pwm output control comparator 0 comparator 1 comparator 2 comparator 3 comparator 4 comparator 5 comparator 6 comparator 7 comparator 8 comparator 9 comparator 10 comparator 11 comparator 12 comparator 13 comparator 14 comparator 15 pwdprb pwoerb p2ddr p2dr pwdpra pwoera p1ddr p1dr module data bus bus interface internal data bus pwsl clock selection ? internal clock ?2 legend: pwsl: pwdr: pwdpra: pwdprb: pwoera: pwoerb: pcsr: p1ddr: p2ddr: p1dr: p2dr: pwm register select pwm data register pwm data polarity register a pwm data polarity register b pwm output enable register a pwm output enable register b peripheral clock select register port 1 data direction register port 2 data direction register port 1 data register port 2 data register tcnt pcsr ?4 ?8 ?16 figure 9.1 block diagram of pwm timer module 223 9.1.3 pin configuration table 9.1 shows the pwm output pin. table 9.1 pin configuration name abbreviation i/o function pwm output pin 0 to 15 pw0 to pw15 output pwm timer pulse output 0 to 15 9.1.4 register configuration table 9.2 lists the registers of the pwm timer module. table 9.2 pwm timer module registers name abbreviation r/w initial value address * pwm register select pwsl r/w h'20 h'ffd6 pwm data registers 0 to 15 pwdr0 to pwdr15 r/w h'00 h'ffd7 pwm data polarity register a pwdpra r/w h'00 h'ffd5 pwm data polarity register b pwdprb r/w h'00 h'ffd4 pwm output enable register a pwoera r/w h'00 h'ffd3 pwm output enable register b pwoerb r/w h'00 h'ffd2 port 1 data direction register p1ddr w h'00 h'ffb0 port 2 data direction register p2ddr w h'00 h'ffb1 port 1 data register p1dr r/w h'00 h'ffb2 port 2 data register p2dr r/w h'00 h'ffb3 peripheral clock select register pcsr r/w h'00 h'ff82 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 note: * lower 16 bits of the address. 224 9.2 register descriptions 9.2.1 pwm register select (pwsl) bit initial value read/write 7 pwcke 0 r/w 6 pwcks 0 r/w 5 ? 1 4 ? 0 3 rs3 0 r/w 0 rs0 0 r/w 2 rs2 0 r/w 1 rs1 0 r/w pwsl is an 8-bit readable/writable register used to select the pwm timer input clock and the pwm data register. pwsl is initialized to h'20 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. bits 7 and 6pwm clock enable, pwm clock select (pwcke, pwcks): these bits, together with bits pwcka and pwckb in pcsr, select the internal clock input to tcnt in the pwm timer. pwsl pcsr bit 7 bit 6 bit 2 bit 1 pwcke pwcks pwckb pwcka description 0 clock input is disabled (initial value) 1 0 ? (system clock) is selected 1 0 0 ?/2 is selected 1 ?/4 is selected 1 0 ?/8 is selected 1 ?/16 is selected the pwm resolution, pwm conversion period, and carrier frequency depend on the selected internal clock, and can be found from the following equations. resolution (minimum pulse width) = 1/internal clock frequency pwm conversion period = resolution 256 carrier frequency = 16/pwm conversion period thus, with a 20 mhz system clock (?), the resolution, pwm conversion period, and carrier frequency are as shown below. 225 table 9.3 resolution, pwm conversion period, and carrier frequency when ? = 20 mhz internal clock frequency resolution pwm conversion period carrier frequency ? 50 ns 12.8 m s 1250 khz ?/2 100 ns 25.6 m s 625 khz ?/4 200 ns 51.2 m s 312.5 khz ?/8 400 ns 102.4 m s 156.3 khz ?/16 800 ns 204.8 m s 78.1 khz bit 5reserved: this bit is always read as 1 and cannot be modified. bit 4reserved: this bit is always read as 0 and cannot be modified. bits 3 to 0register select (rs3 to rs0): these bits select the pwm data register. bit 3 bit 2 bit 1 bit 0 rs3 rs2 rs1 rs0 register selection 0 0 0 0 pwdr0 selected 1 pwdr1 selected 1 0 pwdr2 selected 1 pwdr3 selected 1 0 0 pwdr4 selected 1 pwdr5 selected 1 0 pwdr6 selected 1 pwdr7 selected 1 0 0 0 pwdr8 selected 1 pwdr9 selected 1 0 pwdr10 selected 1 pwdr11 selected 1 0 0 pwdr12 selected 1 pwdr13 selected 1 0 pwdr14 selected 1 pwdr15 selected 226 9.2.2 pwm data registers (pwdr0 to pwdr15) bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w each pwdr is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. the value set in pwdr corresponds to a 0 or 1 ratio in the conversion period. the upper 4 bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. the lower 4 bits specify how many extra pulses are to be added within the conversion period comprising 16 basic pulses. thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios within the conversion period. for 256/256 (100%) output, port output should be used. pwdr is initialized to h'00 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. 227 9.2.3 pwm data polarity registers a and b (pwdpra and pwdprb) pwdpra bit initial value read/write 7 os7 0 r/w 6 os6 0 r/w 5 os5 0 r/w 4 os4 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w pwdprb bit initial value read/write 7 os15 0 r/w 6 os14 0 r/w 5 os13 0 r/w 4 os12 0 r/w 3 os11 0 r/w 0 os8 0 r/w 2 os10 0 r/w 1 os9 0 r/w each pwdpr is an 8-bit readable/writable register that controls the polarity of the pwm output. bits os0 to os15 correspond to outputs pw0 to pw15. pwdpr is initialized to h'00 by a reset and in hardware standby mode. os description 0 pwm direct output (pwdr value corresponds to high width of output) (initial value) 1 pwm inverted output (pwdr value corresponds to low width of output) 228 9.2.4 pwm output enable registers a and b (pwoera and pwoerb) pwoera bit initial value read/write 7 oe7 0 r/w 6 oe6 0 r/w 5 oe5 0 r/w 4 oe4 0 r/w 3 oe3 0 r/w 0 oe0 0 r/w 2 oe2 0 r/w 1 oe1 0 r/w pwoerb bit initial value read/write 7 oe15 0 r/w 6 oe14 0 r/w 5 oe13 0 r/w 4 oe12 0 r/w 3 oe11 0 r/w 0 oe8 0 r/w 2 oe10 0 r/w 1 oe9 0 r/w each pwoer is an 8-bit readable/writable register that switches between pwm output and port output. bits oe15 to oe0 correspond to outputs pw15 to pw0. to set a pin in the output state, a setting in the port direction register is also necessary. bits p17ddr to p10ddr correspond to outputs pw7 to pw0, and bits p27ddr to p20ddr correspond to outputs pw15 to pw8. pwoer is initialized to h'00 by a reset and in hardware standby mode. ddr oe description 0 0 port input (initial value) 1 port input 1 0 port output or pwm 256/256 output 1 pwm output (0 to 255/256 output) 229 9.2.5 peripheral clock select register (pcsr) bit initial value read/write 7 ? 0 6 ? 0 5 ? 0 4 ? 0 3 ? 0 0 ? 0 2 pwckb 0 r/w 1 pwcka 0 r/w pcsr is an 8-bit readable/writable register that selects the pwm timer input clock. pcsr is initialized to h'00 by a reset, and in hardware standby mode. bits 7 to 3reserved: these bits cannot be modified and are always read as 0. bits 2 and 1pwm clock select (pwckb, pwcka): together with bits pwcke and pwcks in pwsl, these bits select the internal clock input to tcnt in the pwm timer. for details, see section 9.2.1, pwm register select (pwsl). bit 0reserved: do not set this bit to 1. 230 9.2.6 port 1 data direction register (p1ddr) bit initial value read/write 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w p1ddr is an 8-bit write-only register that specifies the input/output direction and pwm output for each pin of port 1 on a bit-by-bit basis. port 1 pins are multiplexed with pins pw0 to pw7. the bit corresponding to a pin to be used for pwm output should be set to 1. for details on p1ddr, see section 8.2, port 1. 231 9.2.7 port 2 data direction register (p2ddr) bit initial value read/write 7 p27ddr 0 w 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 0 p20ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w p2ddr is an 8-bit write-only register that specifies the input/output direction and pwm output for each pin of port j on a bit-by-bit basis. port 2 pins are multiplexed with pins pw8 to pw15. the bit corresponding to a pin to be used for pwm output should be set to 1. for details on p2ddr, see section 8.3, port 2. 232 9.2.8 port 1 data register (p1dr) bit initial value read/write 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w p1dr is an 8-bit readable/writable register used to fix pwm output at 1 (when os = 0) or 0 (when os = 1). for details on p1dr, see section 8.2, port 1. 233 9.2.9 port 2 data register (p2dr) bit initial value read/write 7 p27dr 0 r/w 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 0 p20dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w p2dr is an 8-bit readable/writable register used to fix pwm output at 1 (when os = 0) or 0 (when os = 1). for details on p2dr, see section 8.3, port 2. 234 9.2.10 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. when the mstp11 bit is set to 1, 8-bit pwm timer operation is halted and a transition is made to module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 3module stop (mstp11): specifies pwm module stop mode. mstpcrh bit 3 mstp11 description 0 pwm module stop mode is cleared 1 pwm module stop mode is set (initial value) 235 9.3 operation 9.3.1 correspondence between pwm data register contents and output waveform the upper 4 bits of pwdr specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16, as shown in table 9.4. table 9.4 duty cycle of basic pulse 0123456789abc d ef0 000000 000001 000010 000011 000100 000101 000110 000111 111000 111001 111010 111011 111100 111101 111110 111111 upper 6 bits basic pulse waveform (internal) . . . 236 the lower 4 bits of pwdr specify the position of pulses added to the 16 basic pulses, as shown in table 9.5. an additional pulse consists of a high period (when os = 0) with a width equal to the resolution, added before the rising edge of a basic pulse. when the upper 4 bits of pwdr are 0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. table 9.5 position of pulses added to basic pulses basic pulse no. lower 4 bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 yes 0010 yes yes 0011 yes yes yes 0100 yes yes yes yes 0101 yes yes yes yes yes 0110 yes yes yes yes yes yes 0111 yes yes yes yes yes yes yes 1000 yes yes yes yes yes yes yes yes 1001 yes yes yes yes yes yes yes yes yes 1010 yes yes yes yes yes yes yes yes yes yes 1011 yes yes yes yes yes yes yes yes yes yes yes 1100 yes yes yes yes yes yes yes yes yes yes yes yes 1101 yes yes yes yes yes yes yes yes yes yes yes yes yes 1110 yes yes yes yes yes yes yes yes yes yes yes yes yes yes 1111 yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes additional pulse provided no additional pulse resolution width additional pulse figure 9.2 example of additional pulse timing (when upper 4 bits of pwdr = 1000) 237 section 10 14-bit pwm d/a 10.1 overview the h8s/2128 series and h8s/2124 series have an on-chip 14-bit pulse-width modulator (pwm) with two output channels. each channel can be connected to an external low-pass filter to operate as a 14-bit d/a converter. both channels share the same counter (dacnt) and control register (dacr). 10.1.1 features the features of the 14-bit pwm d/a are listed below. the pulse is subdivided into multiple base cycles to reduce ripple. two resolution settings and two base cycle settings are available the resolution can be set equal to one or two system clock cycles. the base cycle can be set equal to t 64 or t 256, where t is the resolution. four operating rates the two resolution settings and two base cycle settings combine to give a selection of four operating rates. 238 10.1.2 block diagram figure 10.1 shows a block diagram of the pwm d/a module. internal clock ?2 pwx0 pwx1 dadra dadrb dacnt dacr legend: dacr: pwm d/a control register ( 6 bits) dadra: pwm d/a data register a (15 bits) dadrb: pwm d/a data register b (15 bits) dacnt: pwm d/a counter (14 bits) control logic clock selection clock internal data bus basic cycle compare-match a fine-adjustment pulse addition a basic cycle compare-match b fine-adjustment pulse addition b basic cycle overflow comparator a comparator b bus interface module data bus figure 10.1 pwm d/a block diagram 10.1.3 pin configuration table 10.1 lists the pins used by the pwm d/a module. table 10.1 input and output pins channel name abbr. i/o function a pwm output pin 0 pwx0 output pwm output, channel a b pwm output pin 1 pwx1 output pwm output, channel b 239 10.1.4 register configuration table 10.2 lists the registers of the pwm d/a module. table 10.2 register configuration name abbreviation r/w initial value address * 1 pwm d/a control register dacr r/w h'30 h'ffa0 * 2 pwm d/a data register a high dadrah r/w h'ff h'ffa0 * 2 pwm d/a data register a low dadral r/w h'ff h'ffa1 * 2 pwm d/a data register b high dadrbh r/w h'ff h'ffa6 * 2 pwm d/a data register b low dadrbl r/w h'ff h'ffa7 * 2 pwm d/a counter high dacnth r/w h'00 h'ffa6 * 2 pwm d/a counter low dacntl r/w h'03 h'ffa7 * 2 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 notes: 1. lower 16 bits of the address. 2. the same addresses are shared by dadrah and dacr, and by dadrb and dacnt. switching is performed by the regs bit in dacnt or dadrb. 240 10.2 register descriptions 10.2.1 pwm d/a counter (dacnt) 15 7 0 r/w 14 6 0 r/w 13 5 0 r/w 12 4 0 r/w 11 3 0 r/w 8 0 0 r/w 10 2 0 r/w 9 1 0 r/w bit (cpu) bit (counter) initial value read/write 7 8 0 r/w 6 9 0 r/w 5 10 0 r/w 4 11 0 r/w 3 12 0 r/w 0 ? regs 1 r/w 2 13 0 r/w 1 ? ? 1 dacnth dacntl dacnt is a 14-bit readable/writable up-counter that increments on an input clock pulse. the input clock is selected by the clock select bit (cks) in dacr. the cpu can read and write the dacnt value, but since dacnt is a 16-bit register, data transfers between it and the cpu are performed using a temporary register (temp). see section 10.3, bus master interface, for details. dacnt functions as the time base for both pwm d/a channels. when a channel operates with 14-bit precision, it uses all dacnt bits. when a channel operates with 12-bit precision, it uses the lower 12 (counter) bits and ignores the upper two (counter) bits. dacnt is initialized to h'0003 by a reset, in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode, and by the pwme bit. bit 1 of dacntl (cpu) is not used, and is always read as 1. dacntl bit 0register select (regs): dadra and dacr, and dadrb and dacnt, are located at the same addresses. the regs bit specifies which registers can be accessed. the regs bit can be accessed regardless of whether dadrb or dacnt is selected. bit 0 regs description 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed (initial value) 241 10.2.2 d/a data registers a and b (dadra and dadrb) 15 13 da13 1 r/w 14 12 da12 1 r/w 13 11 da11 1 r/w 12 10 da10 1 r/w 11 9 da9 1 r/w 8 6 da6 1 r/w 10 8 da8 1 r/w 9 7 da7 1 r/w bit (cpu) bit (data) dadra initial value read/write 7 5 da5 1 r/w 6 4 da4 1 r/w 5 3 da3 1 r/w 4 2 da2 1 r/w 3 1 da1 1 r/w 0 ? ? 1 2 0 da0 1 r/w 1 ? cfs 1 r/w dadrh dadrl da13 1 r/w da12 1 r/w da11 1 r/w da10 1 r/w da9 1 r/w da6 1 r/w da8 1 r/w da7 1 r/w dadrb initial value read/write da5 1 r/w da4 1 r/w da3 1 r/w da2 1 r/w da1 1 r/w regs 1 r/w da0 1 r/w cfs 1 r/w there are two 16-bit readable/writable d/a data registers: dadra and dadrb. dadra corresponds to pwm d/a channel a, and dadrb to pwm d/a channel b. the cpu can read and write the pwm d/a data register values, but since dadra and dadrb are 16-bit registers, data transfers between them and the cpu are performed using a temporary register (temp). see section 10.3, bus master interface, for details. the least significant (cpu) bit of dadra is not used and is always read as 1. dadr is initialized to h'ffff by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. 242 bits 15 to 3pwm d/a data 13 to 0 (da13 to da0): the digital value to be converted to an analog value is set in the upper 14 bits of the pwm d/a data register. in each base cycle, the dacnt value is continually compared with these upper 14 bits to determine the duty cycle of the output waveform, and to decide whether to output a fine- adjustment pulse equal in width to the resolution. to enable this operation, the data register must be set within a range that depends on the carrier frequency select bit (cfs). if the dadr value is outside this range, the pwm output is held constant. a channel can be operated with 12-bit precision by keeping the two lowest data bits (da0 and da1) cleared to 0 and writing the data to be converted in the upper 12 bits. the two lowest data bits correspond to the two highest counter (dacnt) bits. bit 1carrier frequency select (cfs) bit 1 cfs description 0 base cycle = resolution (t) 64 dadr range = h'0401 to h'fffd 1 base cycle = resolution (t) 256 dadr range = h'0103 to h'fffff (initial value) dadra bit 0reserved: this bit cannot be modified and is always read as 1. dadrb bit 0register select (regs): dadra and dacr, and dadrb and dacnt, are located at the same addresses. the regs bit specifies which registers can be accessed. the regs bit can be accessed regardless of whether dadrb or dacnt is selected. bit 0 regs description 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed (initial value) 243 10.2.3 pwm d/a control register (dacr) 7 test 0 r/w 6 pwme 0 r/w 5 ? 1 4 ? 1 3 oeb 0 r/w 0 cks 0 r/w 2 oea 0 r/w 1 os 0 r/w bit initial value read/write dacr is an 8-bit readable/writable register that selects test mode, enables the pwm outputs, and selects the output phase and operating speed. dacr is initialized to h'30 by a reset, and in the standby modes, watch mode, subactive mode, subsleep mode, and module stop mode. bit 7test mode (test): selects test mode, which is used in testing the chip. normally this bit should be cleared to 0. bit 7 test description 0 pwm (d/a) in user state: normal operation (initial value) 1 pwm (d/a) in test state: correct conversion results unobtainable bit 6pwm enable (pwme): starts or stops the pwm d/a counter (dacnt). bit 6 pwme description 0 dacnt operates as a 14-bit up-counter (initial value) 1 dacnt halts at h'0003 bits 5 and 4reserved: these bits cannot be modified and are always read as 1. bit 3output enable b (oeb): enables or disables output on pwm d/a channel b. bit 3 oeb description 0 pwm (d/a) channel b output (at the pwx1 pin) is disabled (initial value) 1 pwm (d/a) channel b output (at the pwx1 pin) is enabled 244 bit 2output enable a (oea): enables or disables output on pwm d/a channel a. bit 2 oea description 0 pwm (d/a) channel a output (at the pwx0 pin) is disabled (initial value) 1 pwm (d/a) channel a output (at the pwx0 pin) is enabled bit 1output select (os): selects the phase of the pwm d/a output. bit 1 os description 0 direct pwm output (initial value) 1 inverted pwm output bit 0clock select (cks): selects the pwm d/a resolution. if the system clock (?) frequency is 10 mhz, resolutions of 100 ns and 200 ns can be selected. bit 0 cks description 0 operates at resolution (t) = system clock cycle time (t cyc ) (initial value) 1 operates at resolution (t) = system clock cycle time (t cyc ) 2 245 10.2.4 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. when the mstp11 bit is set to 1, 14-bit pwm timer operation is halted and a transition is made to module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 3module stop (mstp11): specifies pwmx module stop mode. mstpcrh bit 3 mstp11 description 0 pwmx module stop mode is cleared 1 pwmx module stop mode is set (initial value) 246 10.3 bus master interface dacnt, dadra, and dadrb are 16-bit registers. the data bus linking the bus master and the on-chip supporting modules, however, is only 8 bits wide. when the bus master accesses these registers, it therefore uses an 8-bit temporary register (temp). these registers are written and read as follows (taking the example of the cpu interface). write when the upper byte is written, the upper-byte write data is stored in temp. next, when the lower byte is written, the lower-byte write data and temp value are combined, and the combined 16-bit value is written in the register. read when the upper byte is read, the upper-byte value is transferred to the cpu and the lower- byte value is transferred to temp. next, when the lower byte is read, the lower-byte value in temp is transferred to the cpu. these registers should always be accessed 16 bits at a time using an mov instruction (by word access or two consecutive byte accesses), and the upper byte should always be accessed before the lower byte. correct data will not be transferred if only the upper byte or only the lower byte is accessed. also note that a bit manipulation instruction cannot be used to access these registers. figure 10.2 shows the data flow for access to dacnt. the other registers are accessed similarly. example 1: write to dacnt mov.w r0, @dacnt ; write r0 contents to dacnt example 2: read dadra mov.w @dadra, r0 ; copy contents of dadra to r0 table 10.3 read and write access methods for 16-bit registers read write register name word byte word byte dadra and dadrb yes yes yes dacnt yes yes notes: yes: permitted type of access. word access includes successive byte accesses to the upper byte (first) and lower byte (second). : this type of access may give incorrect results. 247 cpu (h'aa) upper byte bus interface module data bus upper-byte write temp (h'aa) dacntl ( ) dacnth ( ) cpu (h'57) lower byte bus interface module data bus lower-byte write temp (h'aa) dacntl (h'57) dacnth (h'aa) figure 10.2 (a) access to dacnt (cpu writes h'aa57 to dacnt) 248 cpu (h'aa) upper byte bus interface module data bus upper-byte read temp (h'57) dacntl (h'57) dacnth (h'aa) cpu (h'57) lower byte bus interface module data bus lower-byte read temp (h'57) dacntl ( ) dacnth ( ) figure 10.2 (b) access to dacnt (cpu reads h'aa57 from dacnt) 249 10.4 operation a pwm waveform like the one shown in figure 10.3 is output from the pwmx pin. when os = 0, the value in dadr corresponds to the total width (t l ) of the low (0) pulses output in one conversion cycle (256 pulses when cfs = 0, 64 pulses when cfs = 1). when os = 1, the output waveform is inverted and the dadr value corresponds to the total width (t h ) of the high (1) output pulses. figure 10.4 shows the types of waveform output available. t f t l t l = ? t ln (when os = 0) m n = 1 1 conversion cycle (t 2 14 (= 16384)) basic cycle (t 64 or t 256) t: resolution (when cfs = 0, m = 256; when cfs = 1, m = 64) figure 10.3 pwm d/a operation table 10.4 summarizes the relationships of the cks, cfs, and os bit settings to the resolution, base cycle, and conversion cycle. the pwm output remains flat unless dadr contains at least a certain minimum value. table 10.4 indicates the range of dadr settings that give an output waveform like the one in figure 10.3, and lists the conversion cycle length when low-order dadr bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits. 250 table 10.4 settings and operation (examples when ? = 10 mhz) fixed dadr bits bit data cks resolution t (s) cfs base cycle (s) conversion cycle (s) t l (if os = 0) t h (if os = 1) precision (bits) 3 2 1 0 conversion cycle * (s) 0 0.1 0 6.4 1638.4 1. always low (or high) (dadr = h'0001 to h'03fd) 14 1638.4 2. (data value) t (dadr = h'0401 to h'fffd) 12 0 0 409.6 10 0 0 0 0 102.4 1 25.6 1638.4 1. always low (or high) (dadr = h'0003 to h'00ff) 14 1638.4 2. (data value) t (dadr = h'0103 to h'ffff) 12 0 0 409.6 10 0 0 0 0 102.4 1 0.2 0 12.8 3276.8 1. always low (or high) (dadr = h'0001 to h'03fd) 14 3276.8 2. (data value) t (dadr = h'0401 to h'fffd) 12 0 0 819.2 10 0 0 0 0 204.8 1 51.2 3276.8 1. always low (or high) (dadr = h'0003 to h'00ff) 14 3276.8 2. (data value) t (dadr = h'0103 to h'ffff) 12 0 0 819.2 10 0 0 0 0 204.8 note: * this column indicates the conversion cycle when specific dadr bits are fixed. 251 1. os = 0 (dadr corresponds to t l ) a. cfs = 0 [base cycle = resolution (t) 64] t l1 t l2 t l3 t l255 t l256 t f1 t f2 t f255 t f256 1 conversion cycle t f1 = t f2 = t f3 = ???= t f255 = t f256 = t 64 t l1 + t l2 + t l3 + ???+ t l255 + t l256 = t l figure 10.4 (1) output waveform b. cfs = 1 [base cycle = resolution (t) 256] t l1 t l2 t l3 t l63 t l64 t f1 t f2 t f63 t f64 1 conversion cycle t f1 = t f2 = t f3 = ???= t f63 = t f64 = t 256 t l1 + t l2 + t l3 + ???+ t l63 + t l64 = t l figure 10.4 (2) output waveform 252 2. os = 1 (dadr corresponds to t h ) a. cfs = 0 [base cycle = resolution (t) 64] t h1 t h2 t h3 t h255 t h256 t f1 t f2 t f255 t f256 1 conversion cycle t f1 = t f2 = t f3 = ???= t f255 = t f256 = t 64 t h1 + t h2 + t h3 + ???+ t h255 + t h256 = t h figure 10.4 (3) output waveform b. cfs = 1 [base cycle = resolution (t) 256] t h1 t h2 t h3 t h63 t h64 t f1 t f2 t f63 t f64 1 conversion cycle t f1 = t f2 = t f3 = ???= t f63 = t f64 = t 256 t h1 + t h2 + t h3 + ???+ t h63 + t h64 = t h figure 10.4 (4) output waveform 253 section 11 16-bit free-running timer 11.1 overview the h8s/2128 series and h8s/2124 series have a single-channel on-chip 16-bit free-running timer (frt) module that uses a 16-bit free-running counter as a time base. applications of the frt module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 11.1.1 features the features of the free-running timer module are listed below. selection of four clock sources ? the free-running counter can be driven by an internal clock source (?/2, ?/8, or ?/32), or an external clock input (enabling use as an external event counter). two independent comparators ? each comparator can generate an independent waveform. four input capture channels ? the current count can be captured on the rising or falling edge (selectable) of an input signal. ? the four input capture registers can be used separately, or in a buffer mode. counter can be cleared under program control ? the free-running counters can be cleared on compare-match a. seven independent interrupts ? two compare-match interrupts, four input capture interrupts, and one overflow interrupt can be requested independently. special functions provided by automatic addition function ? the contents of ocrar and ocraf can be added to the contents of ocra automatically, enabling a periodic waveform to be generated without software intervention. ? the contents of icrd can be added automatically to the contents of ocrdm 2, enabling input capture operations in this interval to be restricted. 254 11.1.2 block diagram figure 11.1 shows a block diagram of the free-running timer. external clock source internal clock sources clock select comparator a ocra (h/l) comparator b ocrb (h/l) bus interface internal data bus ?2 ?8 ?32 ftci compare- match a clear clock ftoa ftob overflow icra (h/l) compare- match b input capture frc (h/l) tcsr ftia ftib ftic ftid control logic module data bus tier tcr tocr interrupt signals icia icib icic icid ocia ocib fovi legend: ocra, b: frc: icra, b, c, d: tcsr: output compare register a, b (16 bits) free-running counter (16 bits) input capture register a, b, c, d (16 bits) timer control/status register (8 bits) tier: tcr: tocr: timer interrupt enable register (8 bits) timer control register (8 bits) timer output compare control register (8 bits) icrb (h/l) icrc (h/l) icrd (h/l) ocra r/f (h/l) + + ocrdm l 1 2 comparator m compare-match m figure 11.1 block diagram of 16-bit free-running timer 255 11.1.3 input and output pins table 11.1 lists the input and output pins of the free-running timer module. table 11.1 input and output pins of free-running timer module name abbreviation i/o function counter clock input ftci input frc counter clock input output compare a ftoa output output compare a output output compare b ftob output output compare b output input capture a ftia input input capture a input input capture b ftib input input capture b input input capture c ftic input input capture c input input capture d ftid input input capture d input 256 11.1.4 register configuration table 11.2 lists the registers of the free-running timer module. table 11.2 register configuration name abbreviation r/w initial value address * 1 timer interrupt enable register tier r/w h'01 h'ff90 timer control/status register tcsr r/(w) * 2 h'00 h'ff91 free-running counter frc r/w h'0000 h'ff92 output compare register a ocra r/w h'ffff h'ff94 * 3 output compare register b ocrb r/w h'ffff h'ff94 * 3 timer control register tcr r/w h'00 h'ff96 timer output compare control register tocr r/w h'00 h'ff97 input capture register a icra r h'0000 h'ff98 * 4 input capture register b icrb r h'0000 h'ff9a * 4 input capture register c icrc r h'0000 h'ff9c * 4 input capture register d icrd r h'0000 h'ff9e output compare register ar ocrar r/w h'ffff h'ff98 * 4 output compare register af ocraf r/w h'ffff h'ff9a * 4 output compare register dm ocrdm r/w h'0000 h'ff9c * 4 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 notes: 1. lower 16 bits of the address. 2. bits 7 to 1 are read-only; only 0 can be written to clear the flags. bit 0 is readable/writable. 3. ocra and ocrb share the same address. access is controlled by the ocrs bit in tocr. 4. icra, icrb, and icrc share the same addresses with ocrar, ocraf, and ocrdm. access is controlled by the icrs bit in tocr. 257 11.2 register descriptions 11.2.1 free-running counter (frc) bit initial 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w value write read/ frc is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. the clock source is selected by bits cks1 and cks0 in tcr. frc can also be cleared by compare-match a. when frc overflows from h'ffff to h'0000, the overflow flag (ovf) in tcsr is set to 1. frc is initialized to h'0000 by a reset and in hardware standby mode. 11.2.2 output compare registers a and b (ocra, ocrb) bit initial 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w value write read/ ocra and ocrb are 16-bit readable/writable registers, the contents of which are continually compared with the value in the frc. when a match is detected, the corresponding output compare flags (ocfa or ocfb) is set in tcsr. in addition, if the output enable bit (oea or oeb) in tocr is set to 1, when ocr and frc values match, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). following a reset, the ftoa and ftob output levels are 0 until the first compare-match. ocr is initialized to h'ffff by a reset and in hardware standby mode. 258 11.2.3 input capture registers a to d (icra to icrd) bit initial 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r value write read/ there are four input capture registers, a to d, each of which is a 16-bit read-only register. when the rising or falling edge of the signal at an input capture input pin (ftia to ftid) is detected, the current frc value is copied to the corresponding input capture register (icra to icrd). at the same time, the corresponding input capture flag (icfa to icfd) in tcsr is set to 1. the input capture edge is selected by the input edge select bits (iedga to iedgd) in tcr. icrc and icrd can be used as icra and icrb buffer registers, respectively, and made to perform buffer operations, by means of buffer enable bits a and b (bufea, bufeb) in tcr. figure 11.2 shows the connections when icrc is specified as the icra buffer register (bufea = 1). when icrc is used as the icra buffer, both rising and falling edges can be specified as transitions of the external input signal by setting iedga _ iedgc. when iedga = iedgc, either the rising or falling edge is designated. see table 11.3. note: the frc contents are transferred to the input capture register regardless of the value of the input capture flag (icf). bufea iedga iedgc ftia edge detect and capture signal generating circuit frc icrc icra figure 11.2 input capture buffering (example) 259 table 11.3 buffered input capture edge selection (example) iedga iedgc description 0 0 captured on falling edge of input capture a (ftia) (initial value) 1 captured on both rising and falling edges of input capture a (ftia) 10 1 captured on rising edge of input capture a (ftia) to ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods (1.5?). when triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. icr is initialized to h'0000 by a reset and in hardware standby mode. 11.2.4 output compare registers ar and af (ocrar, ocraf) bit initial 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w value write read/ ocrar and ocraf are 16-bit readable/writable registers. when the ocrams bit in tocr is set to 1, the operation of ocra is changed to include the use of ocrar and ocraf. the contents of ocrar and ocraf are automatically added alternately to ocra, and the result is written to ocra. the write operation is performed on the occurrence of compare-match a. in the first compare-match a after the ocrams bit is set to 1, ocraf is added. the operation due to compare-match a varies according to whether the compare-match follows addition of ocrar or ocraf. the value of the olvla bit in tocr is ignored, and 1 is output on a compare-match a following addition of ocraf, while 0 is output on a compare- match a following addition of ocrar. when the ocra automatically addition function is used, do not set internal clock ?/2 as the frc counter input clock together with an ocrar (or ocraf) value of h'0001 or less. ocrar and ocraf are initialized to h'ffff by a reset and in hardware standby mode. 260 11.2.5 output compare register dm (ocrdm) bit initial 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w value write read/ ocrdm is a 16-bit readable/writable register in which the upper 8 bits are fixed at h'00. when the icrdms bit in tocr is set to 1 and the contents of ocrdm are other than h'0000, the operation of icrd is changed to include the use of ocrdm. the point at which input capture d occurs is taken as the start of a mask interval. next, twice the contents of ocrdm is added to the contents of icrd, and the result is compared with the frc value. the point at which the values match is taken as the end of the mask interval. new input capture d events are disabled during the mask interval. a mask interval is not generated when the icrdms bit is set to 1 and the contents of ocrdm are h'0000. ocrdm is initialized to h'0000 by a reset and in hardware standby mode. 11.2.6 timer interrupt enable register (tier) bit initial value read/write 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 3 ociae 0 r/w 0 ? 1 2 ocibe 0 r/w 1 ovie 0 r/w r/w tier is an 8-bit readable/writable register that enables and disables interrupts. tier is initialized to h'01 by a reset and in hardware standby mode. bit 7input capture interrupt a enable (iciae): selects whether to request input capture interrupt a (icia) when input capture flag a (icfa) in tcsr is set to 1. bit 7 iciae description 0 input capture interrupt request a (icia) is disabled (initial value) 1 input capture interrupt request a (icia) is enabled 261 bit 6input capture interrupt b enable (icibe): selects whether to request input capture interrupt b (icib) when input capture flag b (icfb) in tcsr is set to 1. bit 6 icibe description 0 input capture interrupt request b (icib) is disabled (initial value) 1 input capture interrupt request b (icib) is enabled bit 5input capture interrupt c enable (icice): selects whether to request input capture interrupt c (icic) when input capture flag c (icfc) in tcsr is set to 1. bit 5 icice description 0 input capture interrupt request c (icic) is disabled (initial value) 1 input capture interrupt request c (icic) is enabled bit 4input capture interrupt d enable (icide): selects whether to request input capture interrupt d (icid) when input capture flag d (icfd) in tcsr is set to 1. bit 4 icide description 0 input capture interrupt request d (icid) is disabled (initial value) 1 input capture interrupt request d (icid) is enabled bit 3output compare interrupt a enable (ociae): selects whether to request output compare interrupt a (ocia) when output compare flag a (ocfa) in tcsr is set to 1. bit 3 ociae description 0 output compare interrupt request a (ocia) is disabled (initial value) 1 output compare interrupt request a (ocia) is enabled bit 2output compare interrupt b enable (ocibe): selects whether to request output compare interrupt b (ocib) when output compare flag b (ocfb) in tcsr is set to 1. bit 2 ocibe description 0 output compare interrupt request b (ocib) is disabled (initial value) 1 output compare interrupt request b (ocib) is enabled 262 bit 1timer overflow interrupt enable (ovie): selects whether to request a free-running timer overflow interrupt (fovi) when the timer overflow flag (ovf) in tcsr is set to 1. bit 1 ovie description 0 timer overflow interrupt request (fovi) is disabled (initial value) 1 timer overflow interrupt request (fovi) is enabled bit 0reserved: this bit cannot be modified and is always read as 1. 11.2.7 timer control/status register (tcsr) bit initial value read/write 7 icfa 0 r/(w) * 6 icfb 0 r/(w) * 5 icfc 0 4 icfd 0 3 ocfa 0 0 cclra 0 r/w 2 ocfb 0 r/(w) * 1 ovf 0 r/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 can be written in bits 7 to 1 to clear these flags. tcsr is an 8-bit register used for counter clear selection and control of interrupt request signals. tcsr is initialized to h'00 by a reset and in hardware standby mode. timing is described in section 11.3, operation. bit 7input capture flag a (icfa): this status flag indicates that the frc value has been transferred to icra by means of an input capture signal. when bufea = 1, icfa indicates that the old icra value has been moved into icrc and the new frc value has been transferred to icra. icfa must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 7 icfa description 0 [clearing condition] read icfa when icfa = 1, then write 0 in icfa (initial value) 1 [setting condition] when an input capture signal causes the frc value to be transferred to icra 263 bit 6input capture flag b (icfb): this status flag indicates that the frc value has been transferred to icrb by means of an input capture signal. when bufeb = 1, icfb indicates that the old icrb value has been moved into icrd and the new frc value has been transferred to icrb. icfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6 icfb description 0 [clearing condition] read icfb when icfb = 1, then write 0 in icfb (initial value) 1 [setting condition] when an input capture signal causes the frc value to be transferred to icrb bit 5input capture flag c (icfc): this status flag indicates that the frc value has been transferred to icrc by means of an input capture signal. when bufea = 1, on occurrence of the signal transition in ftic (input capture signal) specified by the iedgc bit, icfc is set but data is not transferred to icrc. therefore, in buffer operation, icfc can be used as an external interrupt signal (by setting the icice bit to 1). icfc must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 5 icfc description 0 [clearing condition] read icfc when icfc = 1, then write 0 in icfc (initial value) 1 [setting condition] when an input capture signal is received 264 bit 4input capture flag d (icfd): this status flag indicates that the frc value has been transferred to icrd by means of an input capture signal. when bufeb = 1, on occurrence of the signal transition in ftid (input capture signal) specified by the iedgd bit, icfd is set but data is not transferred to icrd. therefore, in buffer operation, icfd can be used as an external interrupt by setting the icide bit to 1. icfd must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4 icfd description 0 [clearing condition] read icfd when icfd = 1, then write 0 in icfd (initial value) 1 [setting condition] when an input capture signal is received bit 3output compare flag a (ocfa): this status flag indicates that the frc value matches the ocra value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 3 ocfa description 0 [clearing condition] read ocfa when ocfa = 1, then write 0 in ocfa (initial value) 1 [setting condition] when frc = ocra 265 bit 2output compare flag b (ocfb): this status flag indicates that the frc value matches the ocrb value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 2 ocfb description 0 [clearing condition] read ocfb when ocfb = 1, then write 0 in ocfb (initial value) 1 [setting condition] when frc = ocrb bit 1timer overflow flag (ovf): this status flag indicates that the frc has overflowed (changed from h'ffff to h'0000). this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 1 ovf description 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf (initial value) 1 [setting condition] when frc changes from h'ffff to h'0000 bit 0counter clear a (cclra): this bit selects whether the frc is to be cleared at compare-match a (when the frc and ocra values match). bit 0 cclra description 0 frc clearing is disabled (initial value) 1 frc is cleared at compare-match a 266 11.2.8 timer control register (tcr) 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write tcr is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the frc clock source. tcr is initialized to h'00 by a reset and in hardware standby mode bit 7input edge select a (iedga): selects the rising or falling edge of the input capture a signal (ftia). bit 7 iedga description 0 capture on the falling edge of ftia (initial value) 1 capture on the rising edge of ftia bit 6input edge select b (iedgb): selects the rising or falling edge of the input capture b signal (ftib). bit 6 iedgb description 0 capture on the falling edge of ftib (initial value) 1 capture on the rising edge of ftib bit 5input edge select c (iedgc): selects the rising or falling edge of the input capture c signal (ftic). bit 5 iedgc description 0 capture on the falling edge of ftic (initial value) 1 capture on the rising edge of ftic 267 bit 4input edge select d (iedgd): selects the rising or falling edge of the input capture d signal (ftid). bit 4 iedgd description 0 capture on the falling edge of ftid (initial value) 1 capture on the rising edge of ftid bit 3buffer enable a (bufea): selects whether icrc is to be used as a buffer register for icra. bit 3 bufea description 0 icrc is not used as a buffer register for input capture a (initial value) 1 icrc is used as a buffer register for input capture a bit 2buffer enable b (bufeb): selects whether icrd is to be used as a buffer register for icrb. bit 2 bufeb description 0 icrd is not used as a buffer register for input capture b (initial value) 1 icrd is used as a buffer register for input capture b bits 1 and 0clock select (cks1, cks0): select external clock input or one of three internal clock sources for the frc. external clock pulses are counted on the rising edge of signals input to the external clock input pin (ftci). bit 1 bit 0 cks1 cks0 description 0 0 ?/2 internal clock source (initial value) 1 ?/8 internal clock source 1 0 ?/32 internal clock source 1 external clock source (rising edge) 268 11.2.9 timer output compare control register (tocr) bit initial value read/write 7 icrdms 0 r/w 6 ocrams 0 r/w 5 icrs 0 r/w 4 ocrs 0 3 oea 0 0 olvlb 0 r/w 2 oeb 0 r/w 1 olvla 0 r/w r/w r/w tocr is an 8-bit readable/writable register that enables output from the output compare pins, selects the output levels, switches access between output compare registers a and b, controls the icrd and ocra operating mode, and switches access to input capture registers a, b, and c. tocr is initialized to h'00 by a reset and in hardware standby mode. bit 7input capture d mode select (icrdms): specifies whether icrd is used in the normal operating mode or in the operating mode using ocrdm. bit 7 icrdms description 0 the normal operating mode is specified for icrd (initial value) 1 the operating mode using ocrdm is specified for icrd bit 6output compare a mode select (ocrams): specifies whether ocra is used in the normal operating mode or in the operating mode using ocrar and ocraf. bit 6 ocrams description 0 the normal operating mode is specified for ocra (initial value) 1 the operating mode using ocrar and ocraf is specified for ocra bit 5input capture register select (icrs): the same addresses are shared by icra and ocrar, by icrb and ocraf, and by icrc and ocrdm. the icrs bit determines which registers are selected when the shared addresses are read or written to. the operation of icra, icrb, and icrc is not affected. bit 5 icrs description 0 the icra, icrb, and icrc registers are selected (initial value) 1 the ocrar, ocraf, and ocrdm registers are selected 269 bit 4output compare register select (ocrs): ocra and ocrb share the same address. when this address is accessed, the ocrs bit selects which register is accessed. this bit does not affect the operation of ocra or ocrb. bit 4 ocrs description 0 the ocra register is selected (initial value) 1 the ocrb register is selected bit 3output enable a (oea): enables or disables output of the output compare a signal (ftoa). bit 3 oea description 0 output compare a output is disabled (initial value) 1 output compare a output is enabled bit 2output enable b (oeb): enables or disables output of the output compare b signal (ftob). bit 2 oeb description 0 output compare b output is disabled (initial value) 1 output compare b output is enabled bit 1output level a (olvla): selects the logic level to be output at the ftoa pin in response to compare-match a (signal indicating a match between the frc and ocra values). when the ocrams bit is 1, this bit is ignored. bit 1 olvla description 0 0 output at compare-match a (initial value) 1 1 output at compare-match a bit 0output level b (olvlb): selects the logic level to be output at the ftob pin in response to compare-match b (signal indicating a match between the frc and ocrb values). bit 0 olvlb description 0 0 output at compare-match b (initial value) 1 1 output at compare-match b 270 11.2.10 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when the mstp13 bit is set to 1, frt operation is stopped at the end of the bus cycle, and module stop mode is entered. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 5module stop (mstp13): specifies the frt module stop mode. bit 5 mstpcrh description 0 frt module stop mode is cleared 1 frt module stop mode is set (initial value) 271 11.3 operation 11.3.1 frc increment timing frc increments on a pulse generated once for each period of the selected (internal or external) clock source. internal clock: any of three internal clocks (?/2, ?/8, or ?/32) created by division of the system clock (?) can be selected by making the appropriate setting in bits cks1 and cks0 in tcr. figure 11.3 shows the increment timing. n ?1 frc input clock frc internal clock n n + 1 figure 11.3 increment timing with internal clock source external clock: if external clock input is selected by bits cks1 and cks0 in tcr, frc increments on the rising edge of the external clock signal. the pulse width of the external clock signal must be at least 1.5 system clock (?) periods. the counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. figure 11.4 shows the increment timing. n + 1 n frc input clock frc external clock input pin figure 11.4 increment timing with external clock source 272 11.3.2 output compare output timing when a compare-match occurs, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). figure 11.5 shows the timing of this operation for compare-match a. n + 1 n n + 1 n n ocra compare-match a signal frc olvla output compare a output pin ftoa clear * note: * vertical arrows ( ) indicate instructions executed by software. n figure 11.5 timing of output compare a output 273 11.3.3 frc clear timing frc can be cleared when compare-match a occurs. figure 11.6 shows the timing of this operation. n h'0000 frc compare-match a signal figure 11.6 clearing of frc by compare-match a 11.3.4 input capture input timing input capture input timing: an internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin, as selected by the corresponding iedgx (x = a to d) bit in tcr. figure 11.7 shows the usual input capture timing when the rising edge is selected (iedgx = 1). input capture signal input capture input pin figure 11.7 input capture signal timing (usual case) 274 if the upper byte of icra/b/c/d is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (?) period. figure 11.8 shows the timing for this case. input capture signal input capture input pin t 1 t 2 icra/b/c/d read cycle figure 11.8 input capture signal timing (input capture input when icra/b/c/d is read) buffered input capture input timing: icrc and icrd can operate as buffers for icra and icrb. figure 11.9 shows how input capture operates when icra and icrc are used in buffer mode and iedga and iedgc are set to different values (iedga = 0 and iedgc = 1, or iedg a = 1 and iedgc = 0), so that input capture is performed on both the rising and falling edges of ftia. n n + 1 n n + 1 m n n n mm mn ftia input capture signal frc icra icrc figure 11.9 buffered input capture timing (usual case) 275 when icrc or icrd is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. for example, if icrc is used to buffer icra, when the edge transition selected by the iedgc bit occurs on the ftic input capture line, icfc will be set, and if the iciec bit is set, an interrupt will be requested. the frc value will not be transferred to icrc, however. in buffered input capture, if the upper byte of either of the two registers to which data will be transferred (icra and icrc, or icrb and icrd) is being read when the input signal arrives, input capture is delayed by one system clock (?) period. figure 11.10 shows the timing when bufea = 1. input capture signal ftia t 1 t 2 read cycle: cpu reads icra or icrc figure 11.10 buffered input capture timing (input capture input when icra or icrc is read) 276 11.3.5 timing of input capture flag (icf) setting the input capture flag icfx (x = a, b, c, d) is set to 1 by the internal input capture signal. the frc value is simultaneously transferred to the corresponding input capture register (icrx). figure 11.11 shows the timing of this operation. icfa/b/c/d frc input capture signal n n icra/b/c/d figure 11.11 setting of input capture flag (icfa/b/c/d) 277 11.3.6 setting of output compare flags a and b (ocfa, ocfb) the output compare flags are set to 1 by an internal compare-match signal generated when the frc value matches the ocra or ocrb value. this compare-match signal is generated at the last state in which the two values match, just before frc increments to a new value. accordingly, when the frc and ocr values match, the compare-match signal is not generated until the next period of the clock source. figure 11.12 shows the timing of the setting of ocfa and ocfb. ocra or ocrb compare-match signal frc n n + 1 n ocfa or ocfb figure 11.12 setting of output compare flag (ocfa, ocfb) 278 11.3.7 setting of frc overflow flag (ovf) the frc overflow flag (ovf) is set to 1 when frc overflows (changes from h'ffff to h'0000). figure 11.13 shows the timing of this operation. h'ffff h'0000 overflow signal frc ovf figure 11.13 setting of overflow flag (ovf) 11.3.8 automatic addition of ocra and ocrar/ocraf when the ocrams bit in tocr is set to 1, the contents of ocrar and ocraf are automatically added to ocra alternately, and when an ocra compare-match occurs a write to ocra is performed. the ocra write timing is shown in figure 11.14. ocrar, f ocra frc a n n+a compare-match signal n n+1 figure 11.14 ocra automatic addition timing 279 11.3.9 icrd and ocrdm mask signal generation when the icrdms bit in tocr is set to 1 and the contents of ocrdm are other than h'0000, a signal that masks the icrd input capture function is generated. the mask signal is set by the input capture signal. the mask signal setting timing is shown in figure 11.15. the mask signal is cleared by the sum of the icrd contents and twice the ocrdm contents, and an frc compare-match. the mask signal clearing timing is shown in figure 11.16. input capture mask signal input capture signal figure 11.15 input capture mask signal setting timing compare-match signal icrd + ocrdm 2 frc n input capture mask signal n n+1 figure 11.16 input capture mask signal clearing timing 280 11.4 interrupts the free-running timer can request seven interrupts (three types): input capture a to d (icia, icib, icic, icid), output compare a and b (ocia and ocib), and overflow (fovi). each interrupt can be enabled or disabled by an enable bit in tier. independent signals are sent to the interrupt controller for each interrupt. table 11.4 lists information about these interrupts. table 11.4 free-running timer interrupts interrupt description dtc activation priority icia requested by icfa possible high icib requested by icfb possible icic requested by icfc not possible icid requested by icfd not possible ocia requested by ocfa possible ocib requested by ocfb possible fovi requested by ovf not possible low 11.5 sample application in the example below, the free-running timer is used to generate pulse outputs with a 50% duty cycle and arbitrary phase relationship. the programming is as follows: the cclra bit in tcsr is set to 1. each time a compare-match interrupt occurs, software inverts the corresponding output level bit in tocr (olvla or olvlb). frc counter clear h'ffff ocra ocrb h'0000 ftoa ftob figure 11.17 pulse output (example) 281 11.6 usage notes application programmers should note that the following types of contention can occur in the free-running timer. contention between frc write and clear: if an internal counter clear signal is generated during the state after an frc write cycle, the clear signal takes priority and the write is not performed. figure 11.18 shows this type of contention. t 1 t 2 frc write cycle address frc address internal write signal counter clear signal frc n h'0000 figure 11.18 frc write-clear contention 282 contention between frc write and increment: if an frc increment pulse is generated during the state after an frc write cycle, the write takes priority and frc is not incremented. figure 11.19 shows this type of contention. t 1 t 2 frc write cycle address internal write signal frc input clock frc n m write data frc address figure 11.19 frc write-increment contention 283 contention between ocr write and compare-match: if a compare-match occurs during the state after an ocra or ocrb write cycle, the write takes priority and the compare-match signal is inhibited. figure 11.20 shows this type of contention. if automatic addition of ocrar/ocraf to ocra is selected, and a compare-match occurs in the cycle following the ocra, ocrar, and ocraf write cycle, the ocra, ocrar, and ocraf write takes priority and the compare-match signal is inhibited. consequently, the result of the automatic addition is not written to ocra. t 1 t 2 ocra or ocrb write cycle address internal write signal frc ocr n m write data ocr address n n + 1 compare-match signal inhibited figure 11.20 contention between ocr write and compare-match (when automatic addition function is not used) 284 switching of internal clock and frc operation: when the internal clock is changed, the changeover may cause frc to increment. this depends on the time at which the clock select bits (cks1 and cks0) are rewritten, as shown in table 11.5. when an internal clock is used, the frc clock is generated on detection of the falling edge of the internal clock scaled from the system clock (?). if the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 11.5, the changeover is regarded as a falling edge that triggers the frc increment clock pulse. switching between an internal and external clock can also cause frc to increment. table 11.5 switching of internal clock and frc operation no. timing of switchover by means of cks1 and cks0 bits frc operation 1 switching from low to low n + 1 clock before switchover clock after switchover frc clock frc cks bit rewrite n 2 switching from low to high n + 1 n + 2 clock before switchover clock after switchover frc clock frc cks bit rewrite n 285 table 11.5 switching of internal clock and frc operation (cont) no. timing of switchover by means of cks1 and cks0 bits frc operation 3 switching from high to low n + 1 n n + 2 * clock before switchover clock after switchover frc clock frc cks bit rewrite 4 switching from high to high n + 1 n + 2 n clock before switchover clock after switchover frc clock cks bit rewrite frc note: * generated on the assumption that the switchover is a falling edge; frc is incremented. 286 287 section 12 8-bit timers 12.1 overview the h8s/2128 series and h8s/2124 series include an 8-bit timer module with two channels (tmr0 and tmr1). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare- matches. the 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of a rectangular-wave output with an arbitrary duty cycle. the h8s/2128 series also has two similar 8-bit timer channels (tmrx and tmry), and the h8s/2124 series has one (tmry). these channels can be used in a connected configuration using the timer connection function. tmrx and tmry have greater input/output and interrupt function related restrictions than tmr0 and tmr1. 12.1.1 features selection of clock sources ? tmr0, tmr1: the counter input clock can be selected from six internal clocks and an external clock (enabling use as an external event counter). ? tmrx, tmry: the counter input clock can be selected from three internal clocks and an external clock (enabling use as an external event counter). selection of three ways to clear the counters ? the counters can be cleared on compare-match a or b, or by an external reset signal. timer output controlled by two compare-match signals ? the timer output signal in each channel is controlled by two independent compare-match signals, enabling the timer to be used for various applications, such as the generation of pulse output or pwm output with an arbitrary duty cycle. (note: tmry does not have a timer output pin.) cascading of the two channels (tmr0, tmr1) ? operation as a 16-bit timer can be performed using channel 0 as the upper half and channel 1 as the lower half (16-bit count mode). ? channel 1 can be used to count channel 0 compare-match occurrences (compare-match count mode). multiple interrupt sources for each channel ? tmr0, tmr1, tmry: two compare-match interrupts and one overflow interrupt can be requested independently. ? tmrx: one input capture source is available. 288 12.1.2 block diagram figure 12.1 shows a block diagram of the 8-bit timer module (tmr0 and tmr1). tmrx and tmry have a similar configuration, but cannot be cascaded. tmrx also has an input capture function. for details, see section 13, timer connection. external clock sources internal clock sources tmr0 ?8, ?2 ?64, ?32 ?1024, ?256 clock 1 clock 0 compare-match a1 compare-match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tmo0 tmri0 internal bus tcora0 comparator a0 comparator b0 tcorb0 tcsr0 tcr0 tcora1 comparator a1 tcnt1 comparator b1 tcorb1 tcsr1 tcr1 tmci0 tmci1 tcnt0 overflow 1 overflow 0 compare-match b1 compare-match b0 tmo1 tmri1 clock select control logic clear 0 tmr1 ?8, ?2 ?64, ?128 ?1024, ?2048 tmrx ? ?2 ?4 tmry ?4 ?256 ?2048 figure 12.1 block diagram of 8-bit timer module 289 12.1.3 pin configuration table 12.1 summarizes the input and output pins of the 8-bit timer module. table 12.1 8-bit timer input and output pins channel name symbol * i/o function 0 timer output tmo0 output output controlled by compare-match timer clock input tmci0 input external clock input for the counter timer reset input tmri0 input external reset input for the counter 1 timer output tmo1 output output controlled by compare-match timer clock input tmci1 input external clock input for the counter timer reset input tmri1 input external reset input for the counter x timer output tmox output output controlled by compare-match timer clock/ reset input hfbacki/tmix (tmcix/tmrix) input external clock/reset input for the counter y timer clock/reset input vsynci/tmiy (tmciy/tmriy) input external clock/reset input for the counter note: * the abbreviations tmo, tmci, and tmri are used in the text, omitting the channel number. channel x and y i/o pins have the same internal configuration as channels 0 and 1, and therefore the same abbreviations are used. 290 12.1.4 register configuration table 12.2 summarizes the registers of the 8-bit timer module. table 12.2 8-bit timer registers channel name abbreviation * 3 r/w initial value address * 1 0 timer control register 0 tcr0 r/w h'00 h'ffc8 timer control/status register 0 tcsr0 r/(w) * 2 h'00 h'ffca time constant register a0 tcora0 r/w h'ff h'ffcc time constant register b0 tcorb0 r/w h'ff h'ffce time counter 0 tcnt0 r/w h'00 h'ffd0 1 timer control register 1 tcr1 r/w h'00 h'ffc9 timer control/status register 1 tcsr1 r/(w) * 2 h'10 h'ffcb time constant register a1 tcora1 r/w h'ff h'ffcd time constant register b1 tcorb1 r/w h'ff h'ffcf timer counter 1 tcnt1 r/w h'00 h'ffd1 common serial/timer control register stcr r/w h'00 h'ffc3 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 timer connection register s tconrs r/w h'00 h'fffe x timer control register x tcrx r/w h'00 h'fff0 timer control/status register x tcsrx r/(w) * 2 h'00 h'fff1 time constant register ax tcorax r/w h'ff h'fff6 time constant register bx tcorbx r/w h'ff h'fff7 timer counter x tcntx r/w h'00 h'fff4 time constant register c tcorc r/w h'ff h'fff5 input capture register r ticrr r h'00 h'fff2 input capture register f ticrf r h'00 h'fff3 y timer control register y tcry r/w h'00 h'fff0 timer control/status register y tcsry r/(w) * 2 h'00 h'fff1 time constant register ay tcoray r/w h'ff h'fff2 time constant register by tcorby r/w h'ff h'fff3 timer counter y tcnty r/w h'00 h'fff4 timer input select register tisr r/w h'fe h'fff5 notes: 1. lower 16 bits of the address. 2. only 0 can be written in bits 7 to 5, to clear these flags. 3. the abbreviations tcr, tcsr, tcora, tcorb, and tcnt are used in the text, omitting the channel designation (0, 1, x, or y). each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access. (access is not divided into two 8-bit accesses.) 291 certain of the channel x and channel y registers are assigned to the same address. the tmrx/y bit in tconrs determines which register is accessed. 12.2 register descriptions 12.2.1 timer counter (tcnt) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w tcntx,tcnty bit initial value read/write 15 0 r/w bit initial value read/write 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 tcnt1 each tcnt is an 8-bit readable/writable up-counter. tcnt0 and tcnt1 comprise a single 16-bit register, so they can be accessed together by word access. tcnt increments on pulses generated from an internal or external clock source. this clock source is selected by clock select bits cks2 to cks0 in tcr. tcnt can be cleared by an external reset input signal or compare-match signal. counter clear bits cclr1 and cclr0 in tcr select the method of clearing. when tcnt overflows from h'ff to h'00, the overflow flag (ovf) in tcsr is set to 1. the timer counters are initialized to h'00 by a reset and in hardware standby mode. 292 12.2.2 time constant register a (tcora) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w tcorax, tcoray bit initial value read/write 15 1 r/w bit initial value read/write 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 tcora is an 8-bit readable/writable register. tcora0 and tcora1 comprise a single 16-bit register, so they can be accessed together by word access. tcora is continually compared with the value in tcnt. when a match is detected, the corresponding compare-match flag a (cmfa) in tcsr is set. note, however, that comparison is disabled during the t2 state of a tcora write cycle. the timer output can be freely controlled by these compare-match signals and the settings of output select bits os1 and os0 in tcsr. tcora is initialized to h'ff by a reset and in hardware standby mode. 293 12.2.3 time constant register b (tcorb) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w tcorbx, tcorby bit initial value read/write 15 1 r/w bit initial value read/write 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 tcorb is an 8-bit readable/writable register. tcorb0 and tcorb1 comprise a single 16-bit register, so they can be accessed together by word access. tcorb is continually compared with the value in tcnt. when a match is detected, the corresponding compare-match flag b (cmfb) in tcsr is set. note, however, that comparison is disabled during the t2 state of a tcorb write cycle. the timer output can be freely controlled by these compare-match signals and the settings of output select bits os3 and os2 in tcsr. tcorb is initialized to h'ff by a reset and in hardware standby mode. 294 12.2.4 timer control register (tcr) 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write tcr is an 8-bit readable/writable register that selects the clock source and the time at which tcnt is cleared, and enables interrupts. tcr is initialized to h'00 by a reset and in hardware standby mode. for details of the timing, see section 12.3, operation. bit 7compare-match interrupt enable b (cmieb): selects whether the cmfb interrupt request (cmib) is enabled or disabled when the cmfb flag in tcsr is set to 1. note that a cmib interrupt is not requested by tmrx, regardless of the cmieb value. bit 7 cmieb description 0 cmfb interrupt request (cmib) is disabled (initial value) 1 cmfb interrupt request (cmib) is enabled bit 6compare-match interrupt enable a (cmiea): selects whether the cmfa interrupt request (cmia) is enabled or disabled when the cmfa flag in tcsr is set to 1. note that a cmia interrupt is not requested by tmrx, regardless of the cmiea value. bit 6 cmiea description 0 cmfa interrupt request (cmia) is disabled (initial value) 1 cmfa interrupt request (cmia) is enabled 295 bit 5timer overflow interrupt enable (ovie): selects whether the ovf interrupt request (ovi) is enabled or disabled when the ovf flag in tcsr is set to 1. note that an ovi interrupt is not requested by tmrx, regardless of the ovie value. bit 5 ovie description 0 ovf interrupt request (ovi) is disabled (initial value) 1 ovf interrupt request (ovi) is enabled bits 4 and 3counter clear 1 and 0 (cclr1, cclr0): these bits select the method by which the timer counter is cleared: by compare-match a or b, or by an external reset input. bit 4 bit 3 cclr1 cclr0 description 0 0 clearing is disabled (initial value) 1 cleared on compare-match a 1 0 cleared on compare-match b 1 cleared on rising edge of external reset input bits 2 to 0clock select 2 to 0 (cks2 to cks0): these bits select whether the clock input to tcnt is an internal or external clock. the input clock can be selected from either six or three clocks, all divided from the system clock (?). the falling edge of the selected internal clock triggers the count. when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. some functions differ between channel 0 and channel 1, because of the cascading function. 296 tcr stcr bit 2 bit 1 bit 0 bit 1 bit 0 channel cks2 cks1 cks0 icks1 icks0 description 0 0 0 0 clock input disabled (initial value) 0 0 1 0 ?/8 internal clock source, counted on the falling edge 0 0 1 1 ?/2 internal clock source, counted on the falling edge 0 1 0 0 ?/64 internal clock source, counted on the falling edge 0 1 0 1 ?/32 internal clock source, counted on the falling edge 0 1 1 0 ?/1024 internal clock source, counted on the falling edge 0 1 1 1 ?/256 internal clock source, counted on the falling edge 1 0 0 counted on tcnt1 overflow signal * 1 0 0 0 clock input disabled (initial value) 0 0 1 0 ?/8 internal clock source, counted on the falling edge 0 0 1 1 ?/2 internal clock source, counted on the falling edge 0 1 0 0 ?/64 internal clock source, counted on the falling edge 0 1 0 1 ?/128 internal clock source, counted on the falling edge 0 1 1 0 ?/1024 internal clock source, counted on the falling edge 0 1 1 1 ?/2048 internal clock source, counted on the falling edge 1 0 0 counted on tcnt0 compare-match a * 297 tcr stcr bit 2 bit 1 bit 0 bit 1 bit 0 channel cks2 cks1 cks0 icks1 icks0 description x 0 0 0 clock input disabled (initial value) 0 0 1 counted on ? internal clock source 0 1 0 ?/2 internal clock source, counted on the falling edge 0 1 1 ?/4 internal clock source, counted on the falling edge 1 0 0 clock input disabled y 0 0 0 clock input disabled (initial value) 0 0 1 ?/4 internal clock source, counted on the falling edge 0 1 0 ?/256 internal clock source, counted on the falling edge 0 1 1 ?/2048 internal clock source, counted on the falling edge 1 0 0 clock input disabled common 1 0 1 external clock source, counted at rising edge 1 1 0 external clock source, counted at falling edge 1 1 1 external clock source, counted at both rising and falling edges note: * if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare-match signal, no incrementing clock will be generated. do not use this setting. 298 12.2.5 timer control/status register (tcsr) 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 icie 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write note: * only 0 can be written in bits 7 to 5, and in bit 4 in tcsrx, to clear these flags. tcsry 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 icf 0 r/(w) * 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write tcsrx 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write tcsr1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write tcsr0 tcsr is an 8-bit register that indicates compare-match and overflow statuses (and input capture status in tmrx only), and controls compare-match output. tcsr0, tcsrx, and tcsry are initialized to h'00, and tcsr1 is initialized to h'10, by a reset and in hardware standby mode. 299 bit 7compare-match flag b (cmfb): status flag indicating whether the values of tcnt and tcorb match. bit 7 cmfb description 0 [clearing conditions] read cmfb when cmfb = 1, then write 0 in cmfb when the dtc is activated by a cmib interrupt (initial value) 1 [setting condition] when tcnt = tcorb bit 6compare-match flag a (cmfa): status flag indicating whether the values of tcnt and tcora match. bit 6 cmfa description 0 [clearing conditions] read cmfa when cmfa = 1, then write 0 in cmfa when the dtc is activated by a cmia interrupt (initial value) 1 [setting condition] when tcnt = tcora bit 5 timer overflow flag (ovf): status flag indicating that tcnt has overflowed (changed from h'ff to h'00). bit 5 ovf description 0 [clearing condition] read ovf when ovf = 1, then write 0 in ovf (initial value) 1 [setting condition] when tcnt overflows from h'ff to h'00 300 tcsr0 bit 4a/d trigger enable (adte): enables or disables a/d converter start requests by compare-match a. bit 4 adte description 0 a/d converter start requests by compare-match a are disabled (initial value) 1 a/d converter start requests by compare-match a are enabled tcsr1 bit 4reserved: this bit cannot be modified and is always read as 1. tcsrx bit 4input capture flag (icf): status flag that indicates detection of a rising edge followed by a falling edge in the external reset signal after the icst bit in tconri has been set to 1. bit 4 icf description 0 [clearing condition] read icf when icf = 1, then write 0 in icf (initial value) 1 [setting condition] when a rising edge followed by a falling edge is detected in the external reset signal after the icst bit in tconri has been set to 1 tcsry bit 4input capture interrupt enable (icie): selects enabling or disabling of the interrupt request by icf (icix) when the icf bit in tcsrx is set to 1. bit 4 icie description 0 interrupt request by icf (icix) is disabled (initial value) 1 interrupt request by icf (icix) is enabled 301 bits 3 to 0output select 3 to 0 (os3 to os0): these bits specify how the timer output level is to be changed by a compare-match of tcor and tcnt. os3 and os2 select the effect of compare-match b on the output level, os1 and os0 select the effect of compare-match a on the output level, and both of them can be controlled independently. note, however, that priorities are set such that: trigger output > 1 output > 0 output. if compare- matches occur simultaneously, the output changes according to the compare-match with the higher priority. timer output is disabled when bits os3 to os0 are all 0. after a reset, the timer output is 0 until the first compare-match occurs. bit 3 bit 2 os3 os2 description 0 0 no change when compare-match b occurs (initial value) 1 0 is output when compare-match b occurs 1 0 1 is output when compare-match b occurs 1 output is inverted when compare-match b occurs (toggle output) bit 1 bit 0 os1 os0 description 0 0 no change when compare-match a occurs (initial value) 1 0 is output when compare-match a occurs 1 0 1 is output when compare-match a occurs 1 output is inverted when compare-match a occurs (toggle output) 302 12.2.6 serial/timer control register (stcr) 7 iics 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 flshe 0 r/w 0 icks0 0 r/w 2 ? 0 r/w 1 icks1 0 r/w bit initial value read/write stcr is an 8-bit readable/writable register that controls register access, the iic operating mode (when the on-chip iic option is included), and on-chip flash memory (in f-ztat versions), and also selects the tcnt input clock. for details on functions not related to the 8-bit timers, see section 3.2.4, serial/timer control register (stcr), and the descriptions of the relevant modules. if a module controlled by stcr is not used, do not write 1 to the corresponding bit. stcr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 4i 2 c control (iics, iicx1, iicx0, iice): these bits control the operation of the i 2 c bus interface when the iic option is included on-chip. see section 16, i 2 c bus interface, for details. bit 3flash memory control register enable (flshe): controls the operation of the flash memory in f-ztat versions. see section 19, rom, for details. bit 2reserved: do not write 1 to this bit. bits 1 and 0internal clock select 1 and 0 (icks1, icks0): these bits, together with bits cks2 to cks0 in tcr, select the clock to be input to tcnt. for details, see section 12.2.4, timer control register. 303 12.2.7 system control register (syscr) 7 cs2e 0 r/w 6 iose 0 r/w 5 intm1 0 r 4 intm0 0 r/w 3 xrst 1 r 0 rame 1 r/w 2 nmieg 0 r/w 1 hie 0 r/w bit initial value read/write only bit 1 is described here. for details on functions not related to the 8-bit timers, see sections 3.2.2 and 5.2.1, system control register (syscr), and the descriptions of the relevant modules. bit 1host interface enable (hie): controls cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers. bit 1 hie description 0 cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers, is enabled (initial value) 1 cpu access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers, is disabled 304 12.2.8 timer connection register s (tconrs) 7 tmrx/y 0 r/w 6 isgene 0 r/w 5 homod1 0 r/w 4 homod0 0 r/w 3 vomod1 0 r/w 0 clmod0 0 r/w 2 vomod0 0 r/w 1 clmod1 0 r/w bit initial value read/write tconrs is an 8-bit readable/writable register that controls access to the tmrx and tmry registers and timer connection operation. tconrs is initialized to h'00 by a reset and in hardware standby mode. bit 7tmrx/tmry access select (tmrx/y): the tmrx and tmry registers can only be accessed when the hie bit in syscr is cleared to 0. in the h8s/2128 series, some of the tmrx registers and the tmry registers are assigned to the same memory space addresses (h'fff0 to h'fff5), and the tmrx/y bit determines which registers are accessed. in the h8s/2124 series, there is no control of tmry register access by this bit. bit 7 accessible registers tmrx/y h'fff0 h'fff1 h'fff2 h'fff3 h'fff4 h'fff5 h'fff6 h'fff7 0 (initial value) tmrx tcrx tmrx tcsrx tmrx ticrr tmrx ticrf tmrx tcntx tmrx tcorc tmrx tcorax tmrx tcorbx 1 tmry tcry tmry tcsry tmry tcoray tmry tcorby tmry tcnty tmry tisr 305 12.2.9 input capture register (ticr) [tmrx additional function] 7 0 6 0 5 0 4 0 3 0 0 0 2 0 1 0 bit initial value read/write ticr is an 8-bit internal register to which the contents of tcnt are transferred on the falling edge of external reset input. the cpu cannot read or write to ticr directly. the ticr function is used in timer connection. for details, see section 13, timer connection. 12.2.10 time constant register c (tcorc) [tmrx additional function] 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write tcorc is an 8-bit readable/writable register. the sum of the contents of tcorc and ticr is continually compared with the value in tcnt. when a match is detected, a compare-match c signal is generated. note, however, that comparison is disabled during the t2 state of a tcorc write cycle and a ticr input capture cycle. tcorc is initialized to h'ff by a reset and in hardware standby mode. the tcorc function is used in timer connection. for details, see section 13, timer connection. 12.2.11 input capture registers r and f (ticrr, ticrf) [tmrx additional functions] 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write ticrr and ticrf are 8-bit read-only registers. when the icst bit in tconri is set to 1, ticrr and ticrf capture the contents of tcnt successively on the rise and fall of the external reset input. when one capture operation ends, the icst bit is cleared to 0. ticrr and ticrf are each initialized to h'00 by a reset and in hardware standby mode. 306 the ticrr and ticrf functions are used in timer connection. for details, see section 13, timer connection. 12.2.12 timer input select register (tisr) [tmry additional function] 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 is 0 r/w 2 ? 1 1 ? 1 bit initial value read/write tisr is an 8-bit readable/writable register that selects the external clock/reset signal source for the counter. tisr is initialized to h'fe by a reset and in hardware standby mode. bits 7 to 1reserved: do not write 0 to these bits. bit 0input select (is): selects the internal synchronization signal (ivg signal) or the timer clock/reset input pin (vsynci/tmiy (tmciy/tmriy)) as the external clock/reset signal source for the counter. bit 0 is description 0 ivg signal is selected (h8s/2128 series) external clock/reset input is disabled (h8s/2124 series) (initial value) 1 vsynci/tmiy (tmciy/tmriy) is selected 12.2.13 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. 307 when the mstp12 bit or mstp8 bit is set to 1, 8-bit timer operation is halted on channels 0 and 1 or channels x and y, respectively, and a transition is made to module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 4module stop (mstp12): specifies 8-bit timer (channel 0/1) module stop mode. mstpcrh bit 4 mstp12 description 0 8-bit timer (channel 0/1) module stop mode is cleared 1 8-bit timer (channel 0/1) module stop mode is set (initial value) mstpcrh bit 0module stop (mstp8): specifies 8-bit timer (channel x/y) and timer connection module stop mode. mstpcrh bit 0 mstp8 description 0 8-bit timer (channel x/y) and timer connection module stop mode is cleared 1 8-bit timer (channel x/y) and timer connection module stop mode is set (initial value) 308 12.3 operation 12.3.1 tcnt incrementation timing tcnt is incremented by input clock pulses (either internal or external). internal clock: an internal clock created by dividing the system clock (?) can be selected by setting bits cks2 to cks0 in tcr. figure 12.2 shows the count timing. internal clock tcnt input clock tcnt n ?1 n n + 1 figure 12.2 count timing for internal clock input external clock: three incrementation methods can be selected by setting bits cks2 to cks0 in tcr: at the rising edge, the falling edge, and both rising and falling edges. note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. the counter will not increment correctly if the pulse width is less than these values. figure 12.3 shows the timing of incrementation at both edges of an external clock signal. external clock input pin tcnt input clock tcnt n ?1 n n + 1 figure 12.3 count timing for external clock input 309 12.3.2 compare-match timing setting of compare-match flags a and b (cmfa, cmfb): the cmfa and cmfb flags in tcsr are set to 1 by a compare-match signal generated when the tcor and tcnt values match. the compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated. therefore, when tcor and tcnt match, the compare-match signal is not generated until the next incrementation clock input. figure 12.4 shows this timing. tcnt n n + 1 tcor n compare-match signal cmf figure 12.4 timing of cmf setting timer output timing: when compare-match a or b occurs, the timer output changes as specified by the output select bits (os3 to os0) in tcsr. depending on these bits, the output can remain the same, be set to 0, be set to 1, or toggle. 310 figure 12.5 shows the timing when the output is set to toggle at compare-match a. compare-match a signal timer output pin figure 12.5 timing of timer output timing of compare-match clear: tcnt is cleared when compare-match a or b occurs, depending on the setting of the cclr1 and cclr0 bits in tcr. figure 12.6 shows the timing of this operation. n h'00 compare-match signal tcnt figure 12.6 timing of compare-match clear 311 12.3.3 tcnt external reset timing tcnt is cleared at the rising edge of an external reset input, depending on the settings of the cclr1 and cclr0 bits in tcr. the width of the clearing pulse must be at least 1.5 states. figure 12.7 shows the timing of this operation. clear signal external reset input pin tcnt n h'00 n ?1 figure 12.7 timing of clearing by external reset input 12.3.4 timing of overflow flag (ovf) setting ovf in tcsr is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 12.8 shows the timing of this operation. ovf overflow signal tcnt h'ff h'00 figure 12.8 timing of ovf setting 312 12.3.5 operation with cascaded connection if bits cks2 to cks0 in either tcr0 or tcr1 are set to b'100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer can be used (16-bit timer mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (compare-match count mode). in this case, the timer operates as described below. 16-bit count mode: when bits cks2 to cks0 in tcr0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. setting of compare-match flags ? the cmf flag in tcsr0 is set to 1 when a 16-bit compare-match occurs. ? the cmf flag in tcsr1 is set to 1 when a lower 8-bit compare-match occurs. counter clear specification ? if the cclr1 and cclr0 bits in tcr0 have been set for counter clear at compare- match, the 16-bit counter (tcnt0 and tcnt1 together) is cleared when a 16-bit compare-match occurs. the 16-bit counter (tcnt0 and tcnt1 together) is cleared even if counter clear by the tmri0 pin has also been set. ? the settings of the cclr1 and cclr0 bits in tcr1 are ignored. the lower 8 bits cannot be cleared independently. pin output ? control of output from the tmo0 pin by bits os3 to os0 in tcsr0 is in accordance with the 16-bit compare-match conditions. ? control of output from the tmo1 pin by bits os3 to os0 in tcsr1 is in accordance with the lower 8-bit compare-match conditions. compare-match count mode: when bits cks2 to cks0 in tcr1 are b'100, tcnt1 counts compare-match as for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clearing are in accordance with the settings for each channel. usage note: if the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for tcnt0 and tcnt1 are not generated and thus the counters will stop operating. simultaneous setting of these two modes should therefore be avoided. 313 12.4 interrupt sources the tmr0, tmr1, and tmry 8-bit timers can generate three types of interrupt: compare- match a and b (cmia and cmib), and overflow (ovi). tmrx can generate only an icix interrupt. an interrupt is requested when the corresponding interrupt enable bit is set in tcr or tcsr. independent signals are sent to the interrupt controller for each interrupt. it is also possible to activate the dtc by means of cmia and cmib interrupts from tmr0, tmr1 and tmry. an overview of 8-bit timer interrupt sources is given in tables 12.3 to 12.5. table 12.3 tmr0 and tmr1 8-bit timer interrupt sources interrupt source description dtc activation interrupt priority cmia requested by cmfa possible high cmib requested by cmfb possible ovi requested by ovf not possible low table 12.4 tmrx 8-bit timer interrupt source interrupt source description dtc activation icix requested by icf not possible table 12.5 tmry 8-bit timer interrupt sources interrupt source description dtc activation interrupt priority cmia requested by cmfa possible high cmib requested by cmfb possible ovi requested by ovf not possible low 314 12.5 8-bit timer application example in the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.9. the control bits are set as follows: in tcr, cclr1 is cleared to 0 and cclr0 is set to 1 so that the timer counter is cleared by a tcora compare-match. in tcsr, bits os3 to os0 are set to b'0110, causing 1 output at a tcora compare-match and 0 output at a tcorb compare-match. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 12.9 pulse output (example) 315 12.6 usage notes application programmers should note that the following kinds of contention can occur in the 8- bit timer module. 12.6.1 contention between tcnt write and clear if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. figure 12.10 shows this operation. address tcnt address internal write signal counter clear signal tcnt n h'00 t 1 t 2 tcnt write cycle by cpu figure 12.10 contention between tcnt write and clear 316 12.6.2 contention between tcnt write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the counter is not incremented. figure 12.11 shows this operation. address tcnt address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle by cpu counter write data figure 12.11 contention between tcnt write and increment 317 12.6.3 contention between tcor write and compare-match during the t2 state of a tcor write cycle, the tcor write has priority even if a compare- match occurs and the compare-match signal is disabled. figure 12.12 shows this operation. with tmrx, an icr input capture contends with a compare-match in the same way as with a write to tcorc. in this case, the input capture has priority and the compare-match signal is inhibited. address tcor address internal write signal tcnt tcor nm t 1 t 2 tcor write cycle by cpu tcor write data n n + 1 compare-match signal inhibited figure 12.12 contention between tcor write and compare-match 318 12.6.4 contention between compare-matches a and b if compare-matches a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match a and compare-match b, as shown in table 12.6. table 12.6 timer output priorities output setting priority toggle output high 1 output 0 output no change low 319 12.6.5 switching of internal clocks and tcnt operation tcnt may increment erroneously when the internal clock is switched over. table 12.7 shows the relationship between the timing at which the internal clock is switched (by writing to the cks1 and cks0 bits) and the tcnt operation when the tcnt clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. if clock switching causes a change from high to low level, as shown in no. 3 in table 12.7, a tcnt clock pulse is generated on the assumption that the switchover is a falling edge. this increments tcnt. erroneous incrementation can also happen when switching between internal and external clocks. table 12.7 switching of internal clock and tcnt operation no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2 320 table 12.7 switching of internal clock and tcnt operation (cont) no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 3 switching from high to low * 3 clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2 * 4 4 switching from high to high clock before switchover clock after switchover tcnt clock tcnt cks bit rewrite n n + 1 n + 2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated on the assumption that the switchover is a falling edge; tcnt is incremented. 321 section 13 timer connection [h8s/2128 series] provided in the h8s/2128 series; not provided in the h8s/2124 series. 13.1 overview h8s/2128 series allows interconnection between a combination of input signals, the input/output of the single free-running timer (frt) channel, and the three 8-bit timer channels (tmr1, tmrx, and tmry). this capability can be used to implement complex functions such as pwm decoding and clamp waveform output. all the timers are initially set for independent operation. 13.1.1 features the features of the timer connection facility are as follows. five input pins and four output pins, all of which can be designated for phase inversion. positive logic is assumed for all signals used within the timer connection facility. an edge-detection circuit is connected to the input pins, simplifying signal input detection. tmrx can be used for pwm input signal decoding. tmrx can be used for clamp waveform generation. an external clock signal divided by tmr1 can be used as the frt capture input signal. an internal synchronization signal can be generated using the frt and tmry. a signal generated/modified using an input signal and timer connection can be selected and output. 322 13.1.2 block diagram figure 13.1 shows a block diagram of the timer connection facility. edge detection edge detection vsynci/ ftia/tmiy vfbacki/ ftib/tmri0 ftic phase inversion phase inversion phase inversion phase inversion phase inversion phase inversion ivi signal selection read flag edge detection edge detection edge detection phase inversion phase inversion phase inversion read flag ivi signal frt input selec- tion set sync res vertical sync signal modify ftia ftib ftic ftid 16-bit frt ocra +vr, +vf icrd +1m, +2m compare-match ftoa cma(r) cma(f) ftob cm2m cm1m res set 2f h mask generation 2f h mask/flag blanking waveform generation tmr1 input selection tmci 8-bit tmr1 tmri cmb tmo set ivg signal ivo signal res vertical sync signal generation ivo signal selection tmiy signal selection frt output selection vsynco/ ftoa tmri/tmci tmo 8-bit tmry ihg signal cblank hsynco/ tmo1/ tmox tmox tmo1 output selection iho signal selection cl4 generation cl4 signal clamp0/ ftic/ tmo0 clo signal selection pdc signal pwm decoding 8-bit tmrx cmb tmo cma icr icr +1c compare-match clamp waveform generation tmci tmri cm1c cl1 signal cl2 signal cl3 signal ihi signal ihi signal selection hsynci/ tmci1/ftid csynci/ tmri1/ftob hfbacki/ ftci/tmix/ tmcio figure 13.1 block diagram of timer connection facility 323 13.1.3 input and output pins table 13.1 lists the timer connection input and output pins. table 13.1 timer connection input and output pins name abbreviation input/ output function vertical synchronization signal input pin vsynci input vertical synchronization signal input pin or ftia input pin/tmiy input pin horizontal synchronization signal input pin hsynci input horizontal synchronization signal input pin or ftid input pin/tmci1 input pin composite synchronization signal input pin csynci input composite synchronization signal input pin or tmri1 input pin/ftob output pin spare vertical synchronization signal input pin vfbacki input spare vertical synchronization signal input pin or ftib input pin/tmri0 input pin spare horizontal synchronization signal input pin hfbacki input spare horizontal synchronization signal input pin or ftci input pin/tmci0 input pin/tmix input pin vertical synchronization signal output pin vsynco output vertical synchronization signal output pin or ftoa output pin horizontal synchronization signal output pin hsynco output horizontal synchronization signal output pin or tmo1 output pin/tmox output pin clamp waveform output pin clampo output clamp waveform output pin or tmo0 output pin/ftic input pin blanking waveform output pin cblank output blanking waveform output pin 324 13.1.4 register configuration table 13.2 lists the timer connection registers. timer connection registers can only be accessed when the hie bit in syscr is 0. table 13.2 register configuration name abbreviation r/w initial value address * 1 timer connection register i tconri r/w h'00 h'fffc timer connection register o tconro r/w h'00 h'fffd timer connection register s tconrs r/w h'00 h'fffe edge sense register sedgr r/(w) * 2 h'00 * 3 h'ffff module stop control register mstprh r/w h'3f h'ff86 mstprl r/w h'ff h'ff87 notes: 1. lower 16 bits of the address. 2. bits 7 to 2: only 0 can be written to clear the flags. 3. bits 1 and 0: undefined (reflect the pin states). 13.2 register descriptions 13.2.1 timer connection register i (tconri) bit initial value read/write 7 simod1 0 r/w 6 simod0 0 r/w 5 scone 0 r/w 4 icst 0 r/w 3 hfinv 0 r/w 0 viinv 0 r/w 2 vfinv 0 r/w 1 hiinv 0 r/w tconri is an 8-bit readable/writable register that controls connection between timers, the signal source for synchronization signal input, phase inversion, etc. tconr1 is initialized to h'00 by a reset and in hardware standby mode. 325 bits 7 and 6input synchronization mode select 1 and 0 (simod1, simod0): these bits select the signal source of the ihi and ivi signals. bit 7 bit 6 description simod1 simod0 mode ihi signal ivi signal 0 0 no signal (initial value) hfbacki input vfbacki input 1 s-on-g mode csynci input pdc input 1 0 composite mode hsynci input pdc input 1 separate mode hsynci input vsynci input bit 5synchronization signal connection enable (scone): selects the signal source of the frt fti input and the tmr1 tmci1/tmri1 input. bit 5 description scone mode ftia ftib ftic ftid tmci1 tmri1 0 normal connection (initial value) ftia input ftib input ftic input ftid input tmci1 input tmri1 input 1 synchronization signal connection mode ivi signal tmo1 signal vfbacki input ihi signal ihi signal ivi inverse signal bit 4input capture start bit (icst): the tmrx external reset input (tmrix) is connected to the ihi signal. tmrx has input capture registers (ticr, ticrr, and ticrf). ticrr and ticrf can measure the width of a short pulse by means of a single capture operation under the control of the icst bit. when a rising edge followed by a falling edge is detected on tmrix after the icst bit is set to 1, the contents of tcnt at those points are captured into ticrr and ticrf, respectively, and the icst bit is cleared to 0. bit 4 icst description 0 the ticrr and ticrf input capture functions are stopped [clearing condition] when a rising edge followed by a falling edge is detected on tmrix (initial value) 1 the ticrr and ticrf input capture functions are operating (waiting for detection of a rising edge followed by a falling edge on tmrix) [setting condition] when 1 is written in icst after reading icst = 0 326 bits 3 to 0input synchronization signal inversion (hfinv, vfinv, hiinv, viinv): these bits select inversion of the input phase of the spare horizontal synchronization signal (hfbacki), the spare vertical synchronization signal (vfbacki), the horizontal synchronization signal and composite synchronization signal (hsynci, csynci), and the vertical synchronization signal (vsynci). bit 3 hfinv description 0 the hfbacki pin state is used directly as the hfbacki input (initial value) 1 the hfbacki pin state is inverted before use as the hfbacki input bit 2 vfinv description 0 the vfbacki pin state is used directly as the vfbacki input (initial value) 1 the vfbacki pin state is inverted before use as the vfbacki input bit 1 hiinv description 0 the hsynci and csynci pin states are used directly as the hsynci and csynci inputs (initial value) 1 the hsynci and csynci pin states are inverted before use as the hsynci and csynci inputs bit 0 viinv description 0 the vsynci pin state is used directly as the vsynci input (initial value) 1 the vsynci pin state is inverted before use as the vsynci input 327 13.2.2 timer connection register o (tconro) bit initial value read/write 7 hoe 0 r/w 6 voe 0 r/w 5 cloe 0 r/w 4 cboe 0 r/w 3 hoinv 0 r/w 0 cboinv 0 r/w 2 voinv 0 r/w 1 cloinv 0 r/w tconro is an 8-bit readable/writable register that controls output signal output, phase inversion, etc. tconro is initialized to h'00 by a reset and in hardware standby mode. bits 7 and 4output enable (hoe, voe, cloe, cboe): these bits control enabling/disabling of horizontal synchronization signal (hsynco), vertical synchronization signal (vsynco), clamp waveform (clampo), and blanking waveform (cblank) output. when output is disabled, the state of the relevant pin is determined by the port dr and ddr, frt, tmr, and pwm settings. output enabling/disabling control does not affect the port, frt, or tmr input functions, but some frt and tmr input signal sources are determined by the scone bit in tconri. bit 7 hoe description 0 the p67/tmo1/tmox/cin7/hsynco pin functions as the p67/tmo1/tmox/cin7 pin (initial value) 1 the p67/tmo1/tmox/cin7/hsynco pin functions as the hsynco pin bit 6 voe description 0 the p61/ftoa/cin1/vsynco pin functions as the p61/ftoa/cin1 pin (initial value) 1 the p61/ftoa/cin1/vsynco pin functions as the vsynco pin bit 5 cloe description 0 the p64/ftic/cin4/clampo pin functions as the p64/ftic/cin4 pin (initial value) 1 the p64/ftic/cin4/clampo pin functions as the clampo pin 328 bit 4 cboe description 0 the p27/a15/pw15/cblank pin functions as the p27/a15/pw15 pin (initial value) 1 in mode 1 (expanded mode with on-chip rom disabled): the p27/a15/pw15/cblank pin functions as the a15 pin in modes 2 and 3 (modes with on-chip rom enabled): the p27/a15/pw15/cblank pin functions as the cblank pin bits 3 to 0output synchronization signal inversion (hoinv, voinv, cloinv, cboinv): these bits select inversion of the output phase of the horizontal synchronization signal (hsynco), the vertical synchronization signal (vsynco), the clamp waveform (clampo), and the blank waveform (cblank). bit 3 hoinv description 0 the iho signal is used directly as the hsynco output (initial value) 1 the iho signal is inverted before use as the hsynco output bit 2 voinv description 0 the ivo signal is used directly as the vsynco output (initial value) 1 the ivo signal is inverted before use as the vsynco output bit 1 cloinv description 0 the clo signal (cl1, cl2, cl3, or cl4 signal) is used directly as the clampo output (initial value) 1 the clo signal (cl1, cl2, cl3, or cl4 signal) is inverted before use as the clampo output bit 0 cboinv description 0 the cblank signal is used directly as the cblank output (initial value) 1 the cblank signal is inverted before use as the cblank output 329 13.2.3 timer connection register s (tconrs) bit initial value read/write 7 tmrx/y 0 r/w 6 isgene 0 r/w 5 homod1 0 r/w 4 homod0 0 r/w 3 vomod1 0 r/w 0 clmod0 0 r/w 2 vomod0 0 r/w 1 clmod1 0 r/w tconrs is an 8-bit readable/writable register that selects 8-bit timer tmrx/tmry access and the synchronization signal output signal source and generation method. tconrs is initialized to h'00 by a reset and in hardware standby mode. bit 7tmrx/tmry access select (tmrx/y): the tmrx and tmry registers can only be accessed when the hie bit in syscr is cleared to 0. in the h8s/2128 series, some of the tmrx registers and the tmry registers are assigned to the same memory space addresses (h'fff0 to h'fff5), and the tmrx/y bit determines which registers are accessed. in the h8s/2124 series, there is no control of tmry register access by this bit. bit 7 tmrx/y description 0 the tmrx registers are accessed at addresses h'fff0 to h'fff5 (initial value) 1 the tmry registers are accessed at addresses h'fff0 to h'fff5 bit 6internal synchronization signal select (isgene): selects internal synchronization signals (ihg, ivg, and cl4 signals) as the signal sources for the iho, ivo, and clo signals. bits 5 and 4horizontal synchronization output mode select 1 and 0 (homod1, homod0): these bits select the signal source and generation method for the iho signal. bit 6 bit 5 bit 4 isgene vomod1 vomod0 description 0 0 0 the ihi signal (without 2fh modification) is selected (initial value) 1 the ihi signal (with 2fh modification) is selected 1 0 the cl1 signal is selected 1 1 0 0 the ihg signal is selected 1 10 1 330 bits 3 and 2vertical synchronization output mode select 1 and 0 (vomod1, vomod0): these bits select the signal source and generation method for the ivo signal. bit 6 bit 3 bit 2 isgene vomod1 vomod0 description 0 0 0 the ivi signal (without fall modification or ihi synchronization) is selected (initial value) 1 the ivi signal (without fall modification, with ihi synchronization) is selected 1 0 the ivi signal (with fall modification, without ihi synchronization) is selected 1 the ivi signal (with fall modification and ihi synchronization) is selected 1 0 0 the ivg signal is selected 1 10 1 bits 1 and 0clamp waveform mode select 1 and 0 (clmod1, clmod0): these bits select the signal source for the clo signal (clamp waveform). bit 6 bit 1 bit 0 isgene clmod1 clmod2 description 0 0 0 the cl1 signal is selected (initial value) 1 the cl2 signal is selected 1 0 the cl3 signal is selected 1 1 0 0 the cl4 signal is selected 1 10 1 331 13.2.4 edge sense register (sedgr) bit initial value read/write notes: 1. only 0 can be written, to clear the flags. 2. the initial value is undefined since it depends on the pin states. 7 vedg 0 r/(w) 6 hedg 0 r/(w) 5 cedg 0 r/(w) 4 hfedg 0 r/(w) 3 vfedg 0 r/(w) 0 ivi * 2 r 2 preqf 0 r/(w) 1 ihi * 2 r * 1 * 1 * 1 * 1 * 1 * 1 sedgr is an 8-bit readable/writable register used to detect a rising edge on the timer connection input pins and the occurrence of 2fh modification, and to determine the phase of the ivi and ihi signals. the upper 6 bits of sedgr are initialized to 0 by a reset and in hardware standby mode. the initial value of the lower 2 bits is undefined, since it depends on the pin states. bit 7vsynci edge (vedg): detects a rising edge on the vsynci pin. bit 7 vedg description 0 [clearing condition] when 0 is written in vedg after reading vedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the vsynci pin bit 6hsynci edge (hedg): detects a rising edge on the hsynci pin. bit 6 hedg description 0 [clearing condition] when 0 is written in hedg after reading hedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the hsynci pin 332 bit 5csynci edge (cedg): detects a rising edge on the csynci pin. bit 5 cedg description 0 [clearing condition] when 0 is written in cedg after reading cedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the csynci pin bit 4hfbacki edge (hfedg): detects a rising edge on the hfbacki pin. bit 4 hfedg description 0 [clearing condition] when 0 is written in hfedg after reading hfedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the hfbacki pin bit 3vfbacki edge (vfedg): detects a rising edge on the vfbacki pin. bit 3 vfedg description 0 [clearing condition] when 0 is written in vfedg after reading vfedg = 1 (initial value) 1 [setting condition] when a rising edge is detected on the vfbacki pin bit 2pre-equalization flag (preqf): detects the occurrence of an ihi signal 2fh modification condition. the generation of a falling/rising edge in the ihi signal during a mask interval is expressed as the occurrence of a 2fh modification condition. for details, see section 13.3.4, ihi signal 2fh modification. bit 2 preqf description 0 [clearing condition] when 0 is written in preqf after reading preqf = 1 (initial value) 1 [setting condition] when an ihi signal 2fh modification condition is detected 333 bit 1ihi signal level (ihi): indicates the current level of the ihi signal. signal source and phase inversion selection for the ihi signal depends on the contents of tconri. read this bit to determine whether the input signal is positive or negative, then maintain the ihi signal at positive phase by modifying tconri. bit 1 ihi description 0 the ihi signal is low 1 the ihi signal is high bit 0ivi signal level (ivi): indicates the current level of the ivi signal. signal source and phase inversion selection for the ivi signal depends on the contents of tconri. read this bit to determine whether the input signal is positive or negative, then maintain the ivi signal at positive phase by modifying tconri. bit 0 ivi description 0 the ivi signal is low 1 the ivi signal is high 334 13.2.5 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when the mstp13, mstp12, and mstp8 bits are set to 1, the 16-bit free-running timer, 8-bit timer channels 0 and 1 and channels x and y, and timer connection, respectively, halt and enter module stop mode at the end of the bus cycle. see section 21.5, module stop mode, for details. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 5module stop (mstp13): specifies frt module stop mode. mstpcrh bit 5 mstp13 description 0 frt module stop mode is cleared 1 frt module stop mode is set (initial value) mstpcrh bit 4module stop (mstp12): specifies 8-bit timer channel 0 and 1 module stop mode. mstpcrh bit 4 mstp12 description 0 8-bit timer channel 0 and 1 module stop mode is cleared 1 8-bit timer channel 0 and 1 module stop mode is set (initial value) mstpcrh bit 0module stop (mstp8): specifies 8-bit timer channel x and y and timer connection module stop mode. mstpcrh bit 0 mstp8 description 0 8-bit timer channel x and y and timer connection module stop mode is cleared 1 8-bit timer channel x and y and timer connection module stop mode is set (initial value) 335 13.3 operation 13.3.1 pwm decoding (pdc signal generation) the timer connection facility and tmrx can be used to decode a pwm signal in which 0 and 1 are represented by the pulse width. to do this, a signal in which a rising edge is generated at regular intervals must be selected as the ihi signal. the timer counter (tcnt) in tmrx is set to count the internal clock pulses and to be cleared on the rising edge of the external reset signal (ihi signal). the value to be used as the threshold for deciding the pulse width is written in tcorb. the pwm decoder contains a delay latch which uses the ihi signal as data and compare-match signal b (cmb) as a clock, and the state of the ihi signal (the result of the pulse width decision) at the compare-match signal b timing after tcnt is reset by the rise of the ihi signal is output as the pdc signal. the pulse width setting using ticrr and ticrf of tmrx can be used to determine the pulse width decision threshold. examples of tcr and tcorb settings are shown in tables 13.3 and 13.4, and the timing chart is shown in figure 13.2. table 13.3 examples of tcr settings bit(s) abbreviation contents description 7 6 5 cmieb cmiea ovie 0 0 0 interrupts due to compare-match and overflow are disabled 4 and 3 cclr1, cclr0 11 tcnt is cleared by the rising edge of the external reset signal (ihi signal) 2 to 0 cks2 to cks0 001 incremented on internal clock: ? table 13.4 examples of tcorb (pulse width threshold) settings ?:10 mhz ?: 12 mhz ?: 16 mhz ?: 20 mhz h'07 0.8 s 0.67 s 0.5 s 0.4 s h'0f 1.6 s 1.33 s 1 s 0.8 s h'1f 3.2 s 2.67 s 2 s 1.6 s h'3f 6.4 s 5.33 s 4 s 3.2 s h'7f 12.8 s 10.67 s 8 s 6.4 s 336 ihi signal pdc signal tcnt tcorb (threshold) figure 13.2 timing chart for pwm decoding 13.3.2 clamp waveform generation (cl1/cl2/cl3 signal generation) the timer connection facility and tmrx can be used to generate signals with different duty cycles and rising/falling edges (clamp waveforms) in synchronization with the input signal (ihi signal). three clamp waveforms can be generated: the cl1, cl2, and cl3 signals. in addition, the cl4 signal can be generated using tmry. the cl1 signal rises simultaneously with the rise of the ihi signal, and when the cl1 signal is high, the cl2 signal rises simultaneously with the fall of the ihi signal. the fall of both the cl1 and the cl2 signal can be specified by tcora. the rise of the cl3 signal can be specified as simultaneous with the sampling of the fall of the ihi signal using the system clock, and the fall of the cl3 signal can be specified by tcorc. the cl3 signal falls at the rise of the ihi signal. tcnt in tmrx is set to count internal clock pulses and to be cleared on the rising edge of the external reset signal (ihi signal). the value to be used as the cl1 signal pulse width is written in tcora. write a value of h'02 or more in tcora when internal clock ? is selected as the tmrx counter clock, and a value or h'01 or more when ?/2 is selected. when internal clock ? is selected, the cl1 signal pulse width is (tcora set value + 3 0.5). when the cl2 signal is used, the setting must be made so that this pulse width is greater than the ihi signal pulse width. the value to be used as the cl3 signal pulse width is written in tcorc. the ticr register in tmrx captures the value of tcnt at the inverse of the external reset signal edge (in this case, the falling edge of the ihi signal). the timing of the fall of the cl3 signal is determined by the sum of the contents of ticr and tcorc. caution is required if the rising edge of the ihi signal precedes the fall timing set by the contents of tcorc, since the ihi signal will cause the cl3 signal to fall. 337 examples of tmrx tcr settings are the same as those in table 13.3. the clamp waveform timing charts are shown in figures 13.3 and 13.4. since the rise of the cl1 and cl2 signals is synchronized with the edge of the ihi signal, and their fall is synchronized with the system clock, the pulse width variation is equivalent to the resolution of the system clock. both the rise and the fall of the cl3 signal are synchronized with the system clock and the pulse width is fixed, but there is a variation in the phase relationship with the ihi signal equivalent to the resolution of the system clock. ihi signal cl1 signal cl2 signal tcnt tcora figure 13.3 timing chart for clamp waveform generation (cl1 and cl2 signals) ihi signal cl3 signal tcnt ticr+tcorc ticr figure 13.4 timing chart for clamp waveform generation (cl3 signal) 338 13.3.3 measurement of 8-bit timer divided waveform period the timer connection facility, tmr1, and the free-running timer (frt) can be used to measure the period of an ihi signal divided waveform. since tmr1 can be cleared by a rising edge of the ivi signal, the rise and fall of the ihi signal divided waveform can be virtually synchronized with the ivi signal. this enables period measurement to be carried out efficiently. to measure the period of an ihi signal divided waveform, tcnt in tmr1 is set to count the external clock (ihi signal) pulses and to be cleared on the rising edge of the external reset signal (ivi signal). the value to be used as the division factor is written in tcora, and the tmo output method is specified by the os bits in tcsr. examples of tmr1 tcr and tcsr settings are shown in table 13.5, and the timing chart for measurement of the ivi signal and ihi signal divided waveform periods is shown in figure 13.5. the period of the ihi signal divided waveform is given by (icrd(3) C icrd(2)) the resolution. table 13.5 examples of tcr and tcsr settings register bit(s) abbreviation contents description tcr in tmr1 7 cmieb 0 interrupts due to compare-match and overflow are disabled 6 cmiea 0 5 ovie 0 4 and 3 cclr1, cclr0 11 tcnt is cleared by the rising edge of the external reset signal (ivi signal) 2 to 0 cks2 to cks0 101 tcnt is incremented on the rising edge of the external clock (ihi signal) tcsr in tmr1 3 to 0 os3 to os0 0011 not changed by compare-match b; output inverted by compare-match a (toggle output): division by 512 1001 or when tcorb < tcora, 1 output on compare-match b, and 0 output on compare-match a: division by 256 tcr in frt 6 iedgb 0/1 0: frc value is transferred to icrb on falling edge of input capture input b (ihi divided signal waveform) 1: frc value is transferred to icrb on rising edge of input capture input b (ihi divided signal waveform) 1 and 0 cks1, cks0 01 frc is incremented on internal clock: ?/8 tcsr in frt 0 cclra 0 frc clearing is disabled 339 ivi signal ihi signal divided waveform frc icrb icrb(1) icrb(2) icrb(3) icrb(4) figure 13.5 timing chart for measurement of ivi signal and ihi signal divided waveform periods 13.3.4 ihi signal and 2fh modification by using the timer connection frt, even if there is a part of the ihi signal with twice the frequency, this can be eliminated. in order for this function to operate properly, the duty cycle of the ihi signal must be approximately 30% or less, or approximately 70% or above. the 8-bit ocrdm contents or twice the ocrdm contents can be added automatically to the data captured in icrd in the frt, and compare-matches generated at these points. the interval between the two compare-matches is called a mask interval. a value equivalent to approximately 1/3 the ihi signal period is written in ocrdm. icrd is set so that capture is performed on the rise of the ihi signal. since the ihi signal supplied to the iho signal selection circuit is normally set on the rise of the ihi signal and reset on the fall, its waveform is the same as that of the original ihi signal. when 2fh modification is selected, ihi signal edge detection is disabled during mask intervals. capture is also disabled during these intervals. examples of frt tcr settings are shown in table 13.6, and the 2fh modification timing chart is shown in figure 13.6. 340 table 13.6 examples of tcr, tcsr, tcor, and ocrdm settings register bit(s) abbreviation contents description tcr in frt 4 iedgd 1 frc value is transferred to icrd on the rising edge of input capture input d (ihi signal) 1 and 0 cks1, cks0 01 frc is incremented on internal clock: ?/8 tcsr in frt 0 cclra 0 frc clearing is disabled tcor in frt 7 icrdms 1 icrd is set to the operating mode in which ocrdm is used ocrdm in frt 7 to 0 ocrdm7 to 0 h'01 to h'ff specifies the period during which icrd operation is masked ihi signal (without 2fh modification) ihi signal (with 2fh modification) mask interval icrd + ocrdm 2 icrd + ocrdm frc icrd figure 13.6 2fh modification timing chart 341 13.3.5 ivi signal fall modification and ihi synchronization by using the timer connection tmr1, the fall of the ivi signal can be shifted backward by the specified number of ihi signal waveforms. also, the fall of the ivi signal can be synchronized with the rise of the ihi signal. to perform 8-bit timer divided waveform period measurement, tcnt in tmr1 is set to count external clock (ihi signal) pulses, and to be cleared on the rising edge of the external reset signal (inverse of the ivi signal). the number of ihi signal pulses until the fall of the ivi signal is written in tcorb. since the ivi signal supplied to the ivo signal selection circuit is normally set on the rise of the ivi signal and reset on the fall, its waveform is the same as that of the original ivi signal. when fall modification is selected, a reset is performed on a tmr1 tcorb compare-match. the fall of the waveform generated in this way can be synchronized with the rise of the ihi signal, regardless of whether or not fall modification is selected. examples of tmr1 tcorb, tcr, and tcsr settings are shown in table 13.7, and the fall modification/ihi synchronization timing chart is shown in figure 13.7. table 13.7 examples of tcorb, tcr, and tcsr settings register bit(s) abbreviation contents description tcr in tmr1 7 cmieb 0 interrupts due to compare-match and overflow are disabled 6 cmiea 0 5 ovie 0 4 and 3 cclr1, cclr0 11 tcnt is cleared by the rising edge of the external reset signal (inverse of the ivi signal) 2 to 0 cks2 to cks0 101 tcnt is incremented on the rising edge of the external clock (ihi signal) tcsr in tmr1 3 to 0 os3 to os0 0011 not changed by compare-match b; output inverted by compare-match a (toggle output) 1001 or when tcorb < tcora, 1 output on compare-match b, 0 output on compare- match a tocrb in tmr1 h'03 (example) compare-match on the 4th (example) rise of the ihi signal after the rise of the inverse of the ivi signal 342 0 1 2 3 4 5 tcnt tcnt = tcorb (3) ihi signal ivi signal (pdc signal) ivo signal (without fall modification, with ihi synchronization) ivo signal (with fall modification, without ihi synchronization) ivo signal (with fall modification and ihi synchronization) figure 13.7 fall modification/ihi synchronization timing chart 13.3.6 internal synchronization signal generation (ihg/ivg/cl4 signal generation) by using the timer connection frt and tmry, it is possible to automatically generate internal signals (ihg and ivg signals) corresponding to the ihi and ivi signals. as the ihg signal is synchronized with the rise of the ivg signal, the ihg signal period must be made a divisor of the ivg signal period in order to keep it constant. in addition, the cl4 signal can be generated in synchronization with the ihg signal. the contents of ocra in the frt are updated by the automatic addition of the contents of ocrar or ocraf, alternately, each time a compare-match occurs. a value corresponding to the 0 interval of the ivg signal is written in ocrar, and a value corresponding to the 1 interval of the ivg signal is written in ocraf. the ivg signal is set by a compare-match after an ocrar addition, and reset by a compare-match after an ocraf addition. the ihg signal is the tmry 8-bit timer output. tmry is set to count internal clock pulses, and to be cleared on tcora compare-match, to fix the period and set the timer output. tcorb is set so as to reset the timer output. the ivg signal is connected as the tmry reset input (tmri), and the rise of the ivg signal can be treated in the same way as a tcora compare- match. the cl4 signal is a waveform that rises within one system clock period after the fall of the ihg signal, and has a 1 interval of 6 system clock periods. examples of settings of tcora, tcorb, tcr, and tcsr in tmry, and ocrar, ocraf, and tcr in the frt, are shown in table 13.8, and the ihg signal/ivg signal timing chart is shown in figure 13.8. 343 table 13.8 examples of ocrar, ocraf, tocr, tcora, tcorb, tcr, and tcsr settings register bit(s) abbreviation contents description tcr in tmry 7 cmieb 0 interrupts due to compare-match and overflow are disabled 6 cmiea 0 5 ovie 0 4 and 3 cclr1, cclr0 01 tcnt is cleared by compare-match a 2 to 0 cks2 to cks0 001 tcnt is incremented on internal clock: ?/4 tcsr in tmry 3 to 0 os3 to os0 0110 0 output on compare-match b 1 output on compare-match a tocra in tmry h'3f (example) ihg signal period = ? 256 tocrb in tmry h'03 (example) ihg signal 1 interval = ? 16 tcr in frt 1 and 0 cks1, cks0 01 frc is incremented on internal clock: ?/8 ocrar in frt h'7fef (example) ivg signal 0 interval = ? 262016 ivg signal period = ? 262144 (1024 times ihg signal) ocraf in frt h'000f (example) ivg signal 1 interval = ? 128 tocr in frt 6 ocrams 1 ocra is set to the operating mode in which ocrar and ocraf are used 344 6 system clocks 6 system clocks 6 system clocks ocra (4) = ocra (3) + ocrar ocra (3) = ocra (2) + ocraf ocra (2) = ocra (1) + ocrar ocra (1) = ocra (0) + ocraf ocra frc cl4 signal ihg signal tcora tcorb tcnt ivg signal figure 13.8 ivg signal/ihg signal/cl4 signal timing chart 345 13.3.7 hsynco output with the hsynco output, the meaning of the signal source to be selected and use or non-use of modification varies according to the ihi signal source and the waveform required by external circuitry. the meaning of the hsynco output in each mode is shown in table 13.9. table 13.9 meaning of hsynco output in each mode mode ihi signal iho signal meaning of iho signal no signal hfbacki input ihi signal (without 2fh modification) hfbacki input is output directly ihi signal (with 2fh modification) meaningless unless there is a double-frequency part in the hfbacki input cl1 signal hfbacki input 1 interval is changed before output ihg signal internal synchronization signal is output s-on-g mode csynci input ihi signal (without 2fh modification) csynci input (composite synchronization signal) is output directly ihi signal (with 2fh modification) double-frequency part of csynci input (composite synchronization signal) is eliminated before output cl1 signal csynci input (composite synchronization signal) horizontal synchronization signal part is separated before output ihg signal internal synchronization signal is output composite mode hsynci input ihi signal (without 2fh modification) hsynci input (composite synchronization signal) is output directly ihi signal (with 2fh modification) double-frequency part of hsynci input (composite synchronization signal) is eliminated before output cl1 signal hsynci input (composite synchronization signal) horizontal synchronization signal part is separated before output ihg signal internal synchronization signal is output separate mode hsynci input ihi signal (without 2fh modification) hsynci input (horizontal synchronization signal) is output directly ihi signal (with 2fh modification) meaningless unless there is a double-frequency part in the hsynci input (horizontal synchronization signal) cl1 signal hsynci input (horizontal synchronization signal) 1 interval is changed before output ihg signal internal synchronization signal is output 346 13.3.8 vsynco output with the vsynco output, the meaning of the signal source to be selected and use or non-use of modification varies according to the ivi signal source and the waveform required by external circuitry. the meaning of the vsynco output in each mode is shown in table 13.10. table 13.10 meaning of vsynco output in each mode mode ivi signal ivo signal meaning of ivo signal no signal vfbacki input ivi signal (without fall modification or ihi synchronization) vfbacki input is output directly ivi signal (without fall modification, with ihi synchronization) meaningless unless vfbacki input is synchronized with hfbacki input ivi signal (with fall modification, without ihi synchronization) vfbacki input fall is modified before output ivi signal (with fall modification and ihi synchronization) vfbacki input fall is modified and signal is synchronized with hfbacki input before output ivg signal internal synchronization signal is output s-on-g mode or composite mode pdc signal ivi signal (without fall modification or ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated before output ivi signal (without fall modification, with ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, and signal is synchronized with csynci/hsynci input before output ivi signal (with fall modification, without ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, and fall is modified before output ivi signal (with fall modification and ihi synchronization) csynci/hsynci input (composite synchronization signal) vertical synchronization signal part is separated, fall is modified, and signal is synchronized with csynci/hsynci input before output ivg signal internal synchronization signal is output 347 table 13.10 meaning of vsynco output in each mode (cont) mode ivi signal ivo signal meaning of ivo signal separate mode vsynci input ivi signal (without fall modification or ihi synchronization) vsynci input (vertical synchronization signal) is output directly ivi signal (without fall modification, with ihi synchronization) meaningless unless vsynci input (vertical synchronization signal) is synchronized with hsynci input (horizontal synchronization signal) ivi signal (with fall modification, without ihi synchronization) vsynci input (vertical synchronization signal) fall is modified before output ivi signal (with fall modification and ihi synchronization) vsynci input (vertical synchronization signal) fall is modified and signal is synchronized with hsynci input (horizontal synchronization signal) before output ivg signal internal synchronization signal is output 13.3.9 cblank output using the signals generated/selected with timer connection, it is possible to generate a waveform based on the composite synchronization signal (blanking waveform). one kind of blanking waveform is generated by combining hfbacki and vfbacki inputs, with the phase polarity made positive by means of bits hfinv and vfinv in tconri, with the ivo signal. the composition logic is shown in figure 13.9. reset set cblank signal (positive) hfbacki input (positive) vfbacki input (positive) ivo signal (positive) q falling edge sensing rising edge sensing figure 13.9 cblank output waveform generation 348 349 section 14 watchdog timer (wdt) 14.1 overview these series have an on-chip watchdog timer/watch timer with two channels (wdt0, wdt1). the wdt outputs an overflow signal if a system crash prevents the cpu from writing to the timer counter, allowing it to overflow. at the same time, the wdt can also generate an internal reset signal or internal nmi interrupt signal. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer mode, an interval timer interrupt is generated each time the counter overflows. 14.1.1 features switchable between watchdog timer mode and interval timer mode ? wovi interrupt generation in interval timer mode internal reset or internal interrupt generated when the timer counter overflows ? choice of internal reset or nmi interrupt generation in watchdog timer mode choice of 8 (wdt0) or 16 (wdt1) counter input clocks ? maximum wdt interval: system clock period 131072 256 ? subclock can be selected for the wdt1 input counter maximum interval when the subclock is selected: subclock period 256 256 350 14.1.2 block diagram figures 14.1 (a) and (b) show block diagrams of wdt0 and wdt1. overflow wovi (interrupt request signal) internal reset signal * 1 tcnt tcsr ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 clock clock select internal clock source bus interface module bus internal bus wdt legend: tcsr: timer control/status register tcnt: timer counter notes: 1. 2. for the internal reset signal, the reset of the wdt that overflowed first has priority. the internal nmi interrupt request signal can be output independently by either wdt0 or wdt1. the interrupt controller does not distinguish between nmi interrupt requests from wdt0 and wdt1. internal nmi interrupt request signal * 2 interrupt control reset control figure 14.1 (a) block diagram of wdt0 351 overflow tcnt tcsr ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 clock clock select interrupt control reset control internal clock source bus interface module bus internal bus wdt wovi (interrupt request signal) internal reset signal * 1 internal nmi (interrupt request signal) * 2 legend: tcsr: timer control/status register tcnt: timer counter sub /2 sub /4 sub /8 sub /16 sub /32 sub /64 sub /128 sub /256 notes: 1. 2. for the internal reset signal, the reset of the wdt that overflowed first has priority. the internal nmi interrupt request signal can be output independently by either wdt0 or wdt1. the interrupt controller does not distinguish between nmi interrupt requests from wdt0 and wdt1. figure 14.1 (b) block diagram of wdt1 14.1.3 pin configuration table 14.1 describes the wdt input pin. table 14.1 wdt pin name symbol i/o function external subclock input pin excl input wdt1 prescaler counter input clock 352 14.1.4 register configuration the wdt has four registers, as summarized in table 14.2. these registers control clock selection, wdt mode switching, the reset signal, etc. table 14.2 wdt registers address * 1 channel name abbreviation r/w initial value write * 2 read 0 timer control/status register 0 tcsr0 r/(w) * 3 h'00 h'ffa8 h'ffa8 timer counter 0 tcnt0 r/w h'00 h'ffa8 h'ffa9 1 timer control/status register 1 tcsr1 r/(w) * 3 h'00 h'ffea h'ffea timer counter 1 tcnt1 r/w h'00 h'ffea h'ffeb common system control register syscr r/w h'09 h'ffc4 h'ffc4 notes: 1. lower 16 bits of the address. 2. for details of write operations, see section 14.2.4, notes on register access. 3. only 0 can be written in bit 7, to clear the flag. 14.2 register descriptions 14.2.1 timer counter (tcnt) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write tcnt is an 8-bit readable/writable* up-counter. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from the internal clock source selected by bits cks2 to cks0 in tcsr. when the tcnt value overflows (changes from h'ff to h'00), the ovf flag in tcsr is set to 1, and an internal reset, nmi interrupt, interval timer interrupt (wovi), etc., can be generated, according to the mode selected by the wt/ ,7 bit and rst/ 10, bit. tcnt is initialized to h'00 by a reset, in hardware standby mode, or when the tme bit is cleared to 0. it is not initialized in software standby mode. 353 note: * the method of writing to tcnt is more complicated than for most other registers, to prevent accidental overwriting. for details see section 14.2.4, notes on register access. 14.2.2 timer control/status register (tcsr) tcsr0 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 rsts 0 r/w 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write note: * only 0 can be written, to clear the flag. tcsr1 bit initial value read/write note: * only 0 can be written, to clear the flag. 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w tcsr is an 8-bit readable/writable* register. its functions include selecting the clock source to be input to tcnt, and the timer mode. tcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. note: * the method of writing to tcsr is more complicated than for most other registers, to prevent accidental overwriting. for details see section 14.2.4, notes on register access. 354 bit 7overflow flag (ovf): a status flag that indicates that tcnt has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing conditions] write 0 in the tme bit read tcsr when ovf = 1, then write 0 in ovf (initial value) 1 [setting condition] when tcnt overflows (changes from h'ff to h'00) (when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset.) bit 6timer mode select (wt/ ,7 ,7 ): selects whether the wdt is used as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request (wovi) when tcnt overflows. if used as a watchdog timer, the wdt generates a reset or nmi interrupt when tcnt overflows. bit 6 wt/ ,7 ,7 description 0 interval timer: sends the cpu an interval timer interrupt request (wovi) when tcnt overflows (initial value) 1 watchdog timer: generates a reset or nmi interrupt when tcnt overflows bit 5timer enable (tme): selects whether tcnt runs or is halted. bit 5 tme description 0 tcnt is initialized to h'00 and halted (initial value) 1 tcnt counts tcsr0 bit 4reset select (rsts): reserved. this bit should not be set to 1. 355 tcsr1 bit 4prescaler select (pss): selects the input clock source for tcnt in wdt1. for details, see the description of the cks2 to cks0 bits below. tcsr1 bit 4 pss description 0 tcnt counts ?-based prescaler (psm) divided clock pulses (initial value) 1 tcnt counts ?sub-based prescaler (pss) divided clock pulses bit 3reset or nmi (rst/ 10, 10, ): specifies whether an internal reset or nmi interrupt is requested on tcnt overflow in watchdog timer mode. bit 3 rst/ 10, 10, description 0 an nmi interrupt is requested (initial value) 1 an internal reset is requested bits 2 to 0clock select 2 to 0 (cks2 to cks0): these bits select an internal clock source, obtained by dividing the system clock (?), or subclock (?sub) for input to tcnt. wdt0 input clock selection bit 2 bit 1 bit 0 description cks2 cks1 cks0 clock overflow period * (when ? = 20 mhz) 0 0 0 ?/2 (initial value) 25.6 s 1 ?/64 819.2 s 1 0 ?/128 1.6 ms 1 ?/512 6.6 ms 1 0 0 ?/2048 26.2 ms 1 ?/8192 104.9 ms 1 0 ?/32768 419.4 ms 1 ?/131072 1.68 s note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. 356 wdt1 input clock selection bit 4 bit 2 bit 1 bit 0 description pss cks2 cks1 cks0 clock overflow period * (when ? = 20 mhz and ?sub = 32.768 khz) 0 0 0 0 ?/2 (initial value) 25.6 s 1 ?/64 819.2 s 1 0 ?/128 1.6 ms 1 ?/512 6.6 ms 1 0 0 ?/2048 26.2 ms 1 ?/8192 104.9 ms 1 0 ?/32768 419.4 ms 1 ?/131072 1.68 s 1 0 0 0 ?sub/2 15.6 ms 1 ?sub/4 31.3 ms 1 0 ?sub/8 62.5 ms 1 ?sub/16 125 ms 1 0 0 ?sub/32 250 ms 1 ?sub/64 500 ms 1 0 ?sub/128 1 s 1 ?sub/256 2 s note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. 357 14.2.3 system control register (syscr) 7 cs2e 0 r/w 6 iose 0 r/w 5 intm1 0 r 4 intm0 0 r/w 3 xrst 1 r 0 rame 1 r/w 2 nmieg 0 r/w 1 hie 0 r/w bit initial value read/write only bit 3 is described here. for details on functions not related to the watchdog timer, see sections 3.2.2 and 5.2.1, system control register (syscr), and the descriptions of the relevant modules. bit 3external reset (xrst): indicates the reset source. when the watchdog timer is used, a reset can be generated by watchdog timer overflow in addition to external reset input. xrst is a read-only bit. it is set to 1 by an external reset, and when the rst/ 10, bit is 1, is cleared to 0 by an internal reset due to watchdog timer overflow. bit 3 xrst description 0 reset is generated by an internal reset due to watchdog timer overflow 1 reset is generated by external reset input (initial value) 358 14.2.4 notes on register access the watchdog timers tcnt and tcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr (example of wdt0): these registers must be written to by a word transfer instruction. they cannot be written to with byte transfer instructions. figure 14.2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. for a write to tcnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to tcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to tcnt or tcsr. tcnt write tcsr write address: h'ffa8 address: h'ffa8 h'5a write data 15 8 7 0 h'a5 write data 15 8 7 0 figure 14.2 format of data written to tcnt and tcsr (example of wdt0) reading tcnt and tcsr (example of wdt0): these registers are read in the same way as other registers. the read addresses are h'ffa8 for tcsr, and h'ffa9 for tcnt. 14.3 operation 14.3.1 watchdog timer operation to use the wdt as a watchdog timer, set the wt/ ,7 and tme bits in tcsr to 1. software must prevent tcnt overflows by rewriting the tcnt value (normally by writing h'00) before overflow occurs. this ensures that tcnt does not overflow while the system is operating normally. if tcnt overflows without being rewritten because of a system crash or other error, an internal reset or nmi interrupt request is generated. when the rst/ 10, bit is set to 1, the chip is reset for 518 system clock periods (518 ?) by a counter overflow. this is illustrated in figure 14.3. 359 when the rst/ 10, bit cleared to 0, an nmi interrupt request is generated by a counter overflow. an internal reset request from the watchdog timer and reset input from the 5(6 pin are handled via the same vector. the reset source can be identified from the value of the xrst bit in syscr. if a reset caused by an input signal from the 5(6 pin and a reset caused by wdt overflow occur simultaneously, the 5(6 pin reset has priority, and the xrst bit in syscr is set to 1. an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin are handled via the same vector. simultaneous handling of a watchdog timer nmi interrupt request and an nmi pin interrupt request must therefore be avoided. tcnt value h'00 time h'ff wt/it = 1 tme = 1 h'00 written to tcnt wt/it = 1 tme = 1 h'00 written to tcnt 518 system clock periods internal reset signal overflow ovf = 1 * wt/it: timer mode select bit tme: timer enable bit ovf: overflow flag note: * cleared to 0 by an internal reset when ovf is set to 1. xrst is cleared to 0. figure 14.3 operation in watchdog timer mode 360 14.3.2 interval timer operation to use the wdt as an interval timer, clear the wt/ ,7 bit in tcsr to 0 and set the tme bit to 1. an interval timer interrupt (wovi) is generated each time tcnt overflows, provided that the wdt is operating as an interval timer, as shown in figure 14.4. this function can be used to generate interrupt requests at regular intervals. tcnt count h'00 time h'ff wt/it = 0 tme = 1 wovi overflow overflow overflow overflow legend: wovi: interval timer interrupt request generation wovi wovi wovi figure 14.4 operation in interval timer mode 361 14.3.3 timing of setting of overflow flag (ovf) the ovf bit in tcsr is set to 1 if tcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure 14.5. if nmi request generation is selected in watchdog timer mode, when tcnt overflows the ovf bit in tcsr is set to 1 and at the same time an nmi interrupt is requested. tcnt h'ff h'00 overflow signal (internal signal) ovf figure 14.5 timing of ovf setting 14.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. when nmi interrupt request generation is selected in watchdog timer mode, an overflow generates an nmi interrupt request. 362 14.5 usage notes 14.5.1 contention between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t 2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 14.6 shows this operation. address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 14.6 contention between tcnt write and increment 14.5.2 changing value of cks2 to cks0 if bits cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits cks2 to cks0. 14.5.3 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, or vice versa, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. 363 14.5.4 counter value in transitions between high-speed mode, subactive mode, and watch mode if the mode is switched between high-speed mode and subactive mode or between high-speed mode and watch mode when wdt1 is used as a realtime clock counter, an error will occur in the counter value when the internal clock is switched. when the mode is switched from high-speed mode to subactive mode or watch mode, the increment timing is delayed by approximately 2 or 3 clock cycles when the wdt1 control clock is switched from the main clock to the subclock. also, since the main clock oscillator is halted during subclock operation, when the mode is switched from watch mode or subactive mode to high-speed mode, the clock is not supplied until internal oscillation stabilizes. as a result, after oscillation is started, counter incrementing is halted during the oscillation stabilization time set by bits sts2 to sts0 in sbycr, and there is a corresponding discrepancy in the counter value. caution is therefore required when using wdt1 as the realtime clock counter. no error occurs in the counter value while wdt1 is operating in the same mode. 364 365 section 15 serial communication interface (sci) 15.1 overview these series are equipped with a serial communication interface (sci) with two independent channels. the sci can handle both asynchronous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). 15.1.1 features sci features are listed below. choice of asynchronous or synchronous serial communication mode asynchronous mode ? serial data communication is executed using an asynchronous system in which synchronization is achieved character by character serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia) ? a multiprocessor communication function is provided that enables serial data communication with a number of processors ? choice of 12 serial data transfer formats data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even, odd, or none multiprocessor bit: 1 or 0 ? receive error detection: parity, overrun, and framing errors ? break detection: break can be detected by reading the rxd pin level directly in case of a framing error synchronous mode ? serial data communication is synchronized with a clock serial data communication can be carried out with other chips that have a synchronous communication function ? one serial data transfer format data length: 8 bits ? receive error detection: overrun errors detected 366 full-duplex communication capability ? the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ? double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data lsb-first or msb-first transfer can be selected ? this selection can be made regardless of the communication mode (with the exception of 7-bit data transfer in asynchronous mode)* note: * lsb-first transfer is used in the examples in this section. built-in baud rate generator allows any bit rate to be selected choice of serial clock source: internal clock from baud rate generator or external clock from sck pin four interrupt sources ? four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive error) that can issue requests independently ? the transmit-data-empty interrupt and receive-data-full interrupt can activate the data transfer controller (dtc) to execute data transfer 367 15.1.2 block diagram figure 15.1 shows a block diagram of the sci. bus interface tdr rsr rdr module data bus tsr ssr scmr scr smr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock ?4 ?16 ?64 txi tei rxi eri legend: rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register scmr: serial interface mode register brr: bit rate register figure 15.1 block diagram of sci 15.1.3 pin configuration table 15.1 shows the serial pins used by the sci. table 15.1 sci pins channel pin name symbol * i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output note: * the abbreviations sck, rxd, and txd are used in the text, omitting the channel number. 368 15.1.4 register configuration the sci has the internal registers shown in table 15.2. these registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. table 15.2 sci registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ffd8 * 3 bit rate register 0 brr0 r/w h'ff h'ffd9 * 3 serial control register 0 scr0 r/w h'00 h'ffda transmit data register 0 tdr0 r/w h'ff h'ffdb serial status register 0 ssr0 r/(w) * 2 h'84 h'ffdc receive data register 0 rdr0 r h'00 h'ffdd serial interface mode register 0 scmr0 r/w h'f2 h'ffde * 3 1 serial mode register 1 smr1 r/w h'00 h'ff83 * 3 bit rate register 1 brr1 r/w h'ff h'ff89 * 3 serial control register 1 scr1 r/w h'00 h'ff8a transmit data register 1 tdr1 r/w h'ff h'ff8b serial status register 1 ssr1 r/(w) * 2 h'84 h'ff8c receive data register 1 rdd1 r h'00 h'ff8d serial interface mode register 1 scmr1 r/w h'f2 h'ff8e * 3 common module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 notes: 1. lower 16 bits of the address. 2. only 0 can be written, to clear flags. 3. some serial communication interface registers are assigned to the same addresses as other registers. in this case, register selection is performed by the iice bit in the serial timer control register (stcr). 369 15.2 register descriptions 15.2.1 receive shift register (rsr) 7 6 5 4 3 0 2 1 bit read/write rsr is a register used to receive serial data. the sci sets serial data input from the rxd pin in rsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly read or written to by the cpu. 15.2.2 receive data register (rdr) 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write rdr is a register that stores received serial data. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr where it is stored, and completes the receive operation. after this, rsr is receive- enabled. since rsr and rdr function as a double buffer in this way, continuous receive operations can be performed. rdr is a read-only register, and cannot be written to by the cpu. rdr is initialized to h'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. 370 15.2.3 transmit shift register (tsr) 7 6 5 4 3 0 2 1 bit read/write tsr is a register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from tdr to tsr, and transmission started, automatically. however, data transfer from tdr to tsr is not performed if the tdre bit in ssr is set to 1. tsr cannot be directly read or written to by the cpu. 15.2.4 transmit data register (tdr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write tdr is an 8-bit register that stores data for serial transmission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts serial transmission. continuous serial transmission can be carried out by writing the next transmit data to tdr during serial transmission of the data in tsr. tdr can be read or written to by the cpu at all times. tdr is initialized to h'ff by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. 371 15.2.5 serial mode register (smr) 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value read/write smr is an 8-bit register used to set the scis serial transfer format and select the baud rate generator clock source. smr can be read or written to by the cpu at all times. smr is initialized to h'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bit 7communication mode (c/ $ $ ): selects asynchronous mode or synchronous mode as the sci operating mode. bit 7 c/ $ $ description 0 asynchronous mode (initial value) 1 synchronous mode bit 6character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and lsb-first/msb- first selection is not available. 372 bit 5parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5 pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ ( bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ ( bit. bit 4parity mode (o/ ( ( ): selects either even or odd parity for use in parity addition and checking. the o/ ( bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ ( bit setting is invalid in synchronous mode, when parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. bit 4 o/ ( ( description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 373 bit 3stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bit setting is only valid in asynchronous mode. if synchronous mode is set the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, the pe bit and o/ ( bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. for details of the multiprocessor communication function, see section 15.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected 374 bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock source for the baud rate generator. the clock source can be selected from ?, ?/4, ?/16, and ?/64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.8, bit rate register. bit 1 bit 0 cks1 cks0 description 0 0 ? clock (initial value) 1 ?/4 clock 1 0 ?/16 clock 1 ?/64 clock 15.2.6 serial control register (scr) 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value read/write scr is a register that performs enabling or disabling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scr can be read or written to by the cpu at all times. scr is initialized to h'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bit 7transmit interrupt enable (tie): enables or disables transmit-data-empty interrupt (txi) request generation when serial transmit data is transferred from tdr to tsr and the tdre flag in ssr is set to 1. bit 7 tie description 0 transmit-data-empty interrupt (txi) request disabled * (initial value) 1 transmit-data-empty interrupt (txi) request enabled note: * txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. 375 bit 6receive interrupt enable (rie): enables or disables receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request generation when serial receive data is transferred from rsr to rdr and the rdrf flag in ssr is set to 1. bit 6 rie description 0 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * (initial value) 1 receive-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf, fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. bit 5transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5 te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in ssr is fixed at 1. 2. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transmission format before setting the te bit to 1. bit 4receive enable (re): enables or disables the start of serial reception by the sci. bit 4 re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. smr setting must be performed to decide the reception format before setting the re bit to 1. 376 bit 3multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when receiving with the mp bit in smr set to 1. the mpie bit setting is invalid in synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data with mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. bit 2transmit end interrupt enable (teie): enables or disables transmit-end interrupt (tei) request generation if there is no valid transmit data in tdr when the msb is transmitted. bit 2 teie description 0 transmit-end interrupt (tei) request disabled * (initial value) 1 transmit-end interrupt (tei) request enabled * note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. 377 bits 1 and 0clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as an i/o port, the serial clock output pin, or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in synchronous mode, and in the case of external clock operation (cke1 = 1). the setting of bits cke1 and cke0 must be carried out before the scis operating mode is determined using smr. for details of clock source selection, see table 15.9 in section 15.3, operation. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock/sck pin functions as i/o port * 1 synchronous mode internal clock/sck pin functions as serial clock output * 1 1 asynchronous mode internal clock/sck pin functions as clock output * 2 synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate. 378 15.2.7 serial status register (ssr) 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value read/write note: only 0 can be written, to clear the flag. ssr is an 8-bit register containing status flags that indicate the operating status of the sci, and multiprocessor bits. ssr can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. ssr is initialized to h'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bit 7transmit data register empty (tdre): indicates that data has been transferred from tdr to tsr and the next serial data can be written to tdr. bit 7 tdre description 0 [clearing conditions] when 0 is written in tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) when the te bit in scr is 0 when data is transferred from tdr to tsr and data can be written to tdr 379 bit 6receive data register full (rdrf): indicates that the received data is stored in rdr. bit 6 rdrf description 0 [clearing conditions] (initial value) when 0 is written in rdrf after reading rdrf = 1 when the dtc is activated by an rxi interrupt and reads data from rdr 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. bit 5overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5 orer description 0 [clearing condition] (initial value) * 1 when 0 is written in orer after reading orer = 1 1 [setting condition] when the next serial reception is completed while rdrf = 1 * 2 notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. 380 bit 4framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4 fer description 0 [clearing condition] (initial value) * 1 when 0 is written in fer after reading fer = 1 1 [setting condition] when the sci checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. bit 3parity error (per): indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. bit 3 per description 0 [clearing condition] (initial value) * 1 when 0 is written in per after reading per = 1 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ ( bit in smr * 2 notes: 1. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in synchronous mode, serial transmission cannot be continued, either. 381 bit 2transmit end (tend): indicates that there is no valid data in tdr when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified. bit 2 tend description 0 [clearing conditions] when 0 is written in tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) when the te bit in scr is 0 when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1multiprocessor bit (mpb): when reception is performed using a multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. mpb is a read-only bit, and cannot be modified. bit 1 mpb description 0 [clearing condition] (initial value) * when data with a 0 multiprocessor bit is received 1 [setting condition] when data with a 1 multiprocessor bit is received note: * retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format. bit 0multiprocessor bit transfer (mpbt): when transmission is performed using a multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode. bit 0 mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted 382 15.2.8 bit rate register (brr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write brr is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in smr. brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. as baud rate generator control is performed independently for each channel, different values can be set for each channel. table 15.3 shows sample brr settings in asynchronous mode, and table 15.4 shows sample brr settings in synchronous mode. 383 table 15.3 brr settings for various bit rates (asynchronous mode) operating frequency ? (mhz) ? = 2 mhz ? = 2.097152 mhz ? = 2.4576 mhz ? = 3 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 C0.04 1 174 C0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 C0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 C2.48 0 15 0.00 0 19 C2.34 9600 0 6 C2.48 0 7 0.00 0 9 C2.34 19200 0 3 0.00 0 4 C2.34 31250 0 1 0.00 0 2 0.00 38400 0 1 0.00 operating frequency ? (mhz) ? = 3.6864 mhz ? = 4 mhz ? = 4.9152 mhz ? = 5 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 C0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 C1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 C1.70 0 4 0.00 38400 0 2 0.00 0 3 0.00 0 3 1.73 384 table 15.3 brr settings for various bit rates (asynchronous mode) (cont) operating frequency ? (mhz) ? = 6 mhz ? = 6.144 mhz ? = 7.3728 mhz ? = 8 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 C0.44 2 108 0.08 2 130 C0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 C2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 C2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 7 0.00 38400 0 4 C2.34 0 4 0.00 0 5 0.00 operating frequency ? (mhz) ? = 9.8304 mhz ? = 10 mhz ? = 12 mhz ? = 12.288 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 C0.26 2 177 C0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 C1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 C2.34 0 19 0.00 31250 0 9 C1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 C2.34 0 9 0.00 385 table 15.3 brr settings for various bit rates (asynchronous mode) (cont) operating frequency ? (mhz) ? = 14 mhz ? = 14.7456 mhz ? = 16 mhz ? = 17.2032 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 248 C0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00 2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00 4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00 9600 0 45 C0.93 0 47 0.00 0 51 0.16 0 55 0.00 19200 0 22 C0.93 0 23 0.00 0 25 0.16 0 27 0.00 31250 0 13 0.00 0 14 C1.70 0 15 0.00 0 16 1.20 38400 0 11 0.00 0 12 0.16 0 13 0.00 operating frequency ? (mhz) ? = 18 mhz ? = 19.6608 mhz ? = 20 mhz bit rate (bits/s) n n error (%) n n error (%) n n error (%) 110 3 79 C0.12 3 86 0.31 3 88 C0.25 150 2 233 0.16 2 255 0.00 3 64 0.16 300 2 116 0.16 2 127 0.00 2 129 0.16 600 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 58 C0.69 0 63 0.00 0 64 0.16 19200 0 28 1.02 0 31 0.00 0 32 C1.36 31250 0 17 0.00 0 19 C1.70 0 19 0.00 38400 0 14 C2.34 0 15 0.00 0 15 1.73 386 table 15.4 brr settings for various bit rates (synchronous mode) operating frequency ? (mhz) bit rate ? = 2 mhz ? = 4 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz (bits/s) n n n n n n n n n n n n 110 3 70 250 2 124 2 249 3 124 3 249 500 1 249 2 124 2 249 3 124 1 k 1 124 1 249 2 124 2 249 2.5 k 0 199 1 99 1 199 1 249 2 99 2 124 5 k 0 99 0 199 1 99 1 124 1 199 1 249 10 k 0 49 0 99 0 199 0 249 1 99 1 124 25 k 0 19 0 39 0 79 0 99 0 159 0 199 50 k 0 9 0 19 0 39 0 49 0 79 0 99 100 k 0 4 0 9 0 19 0 24 0 39 0 49 250 k 0 1 0 3 0 7 0 9 0 15 0 19 500 k 0 0 * 0103040709 1 m 0 0 * 01 0304 2.5 m 0 0 * 01 5 m 00 * note: as far as possible, the setting should be made so that the error is no more than 1%. legend: blank: cannot be set. : can be set, but there will be a degree of error. * : continuous transfer is not possible. 387 the brr setting is found from the following equations. asynchronous mode: n = 10 6 ?1 64 2 2n? b f synchronous mode: n = 10 6 ?1 8 2 2n? b f where b: bit rate (bits/s) n: brr setting for baud rate generator (0 n 255) ?: operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) smr setting n clock cks1 cks0 0? 0 0 1 ?/4 0 1 2 ?/16 1 0 3 ?/64 1 1 the bit rate error in asynchronous mode is found from the following equation: error (%) = ?1 100 (n + 1) b 64 2 2n? f 10 6 ? ? 388 table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. tables 15.6 and 15.7 show the maximum bit rates with external clock input. table 15.5 maximum bit rate for each frequency (asynchronous mode) ? (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 389 table 15.6 maximum bit rate with external clock input (asynchronous mode) ? (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 390 table 15.7 maximum bit rate with external clock input (synchronous mode) ? (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 15.2.9 serial interface mode register (scmr) 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 bit initial value read/write scmr is an 8-bit readable/writable register used to select sci functions. scmr is initialized to h'f2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bits 7 to 4reserved: these bits cannot be modified and are always read as 1. bit 3data transfer direction (sdir): selects the serial/parallel conversion format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first 391 bit 2data invert (sinv): specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the o/ ( bit in smr. bit 2 sinv description 0 tdr contents are transmitted without modification (initial value) receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form bit 1reserved: this bit cannot be modified and is always read as 1. bit 0serial communication interface mode select (smif): reserved bit. 1 should not be written in this bit. bit 0 smif description 0 normal sci mode (initial value) 1 reserved mode 15.2.10 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when bits mstp7 and mstp6 are set to 1, sci0 and sci1 operation, respectively, stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 21.5., module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. 392 bit 7module stop (mstp7): specifies the sci0 module stop mode. bit 7 mstp7 description 0 sci0 module stop mode is cleared 1 sci0 module stop mode is set (initial value) bit 6module stop (mstp6): specifies the sci1 module stop mode. bit 6 mstp6 description 0 sci1 module stop mode is cleared 1 sci1 module stop mode is set (initial value) 15.3 operation 15.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or synchronous mode and the transmission format is made using smr as shown in table 15.8. the sci clock is determined by a combination of the c/ $ bit in smr and the cke1 and cke0 bits in scr, as shown in table 15.9. asynchronous mode data length: choice of 7 or 8 bits choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) detection of framing, parity, and overrun errors, and breaks, during reception choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) 393 synchronous mode transfer format: fixed 8-bit data detection of overrun errors during reception choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip ? when external clock is selected: the built-in baud rate generator is not used, and the sci operates on the input serial clock table 15.8 smr settings and serial transfer format selection smr settings sci transfer format bit 7 bit 6 bit 2 bit 5 bit 3 data multi- processor parity stop bit c/ $ $ chr mp pe stop mode length bit bit length 00000 asynchronous 8-bit data no no 1 bit 1 mode 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 0 1 0 asynchronous 8-bit data yes no 1 bit 1 mode (multi- 2 bits 10 processor 7-bit data 1 bit 1 format) 2 bits 1 synchronous mode 8-bit data no none 394 table 15.9 smr and scr settings and sci clock source selection smr scr setting sci transfer clock bit 7 bit 1 bit 0 clock c/ $ $ cke1 cke0 mode source sck pin function 0 0 0 asynchronous internal sci does not use sck pin 1 mode outputs clock with same frequency as bit rate 1 0 external inputs clock with frequency of 16 times 1 the bit rate 1 0 0 synchronous internal outputs serial clock 1 mode 1 0 external inputs serial clock 1 395 15.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by-character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 15.2 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit(s) 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 15.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) 396 data transfer format: table 15.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected by settings in smr. table 15.10 serial transfer formats (asynchronous mode) smr settings serial transfer format and frame length chr pe mp stop 1 2 3 4 5 6 7 8 9 10 11 12 0000 s 8-bit data stop 0001 s 8-bit data stop stop 0100 s 8-bit data p stop 0101 s 8-bit data p stop stop 1000 s 7-bit data stop 1001 s 7-bit data stop stop 1100 s 7-bit data p stop 1101 s 7-bit data p stop stop 0 1 0 s 8-bit data mpb stop 0 1 1 s 8-bit data mpb stop stop 1 1 0 s 7-bit data mpb stop 1 1 1 s 7-bit data mpb stop stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit 397 clock: either an internal clock generated by the built-in baud rate generator or an external clock input at the sck pin can be selected as the scis serial clock, according to the setting of the c/ $ bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 15.9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.3. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 figure 15.3 relation between output clock and transfer data phase (asynchronous mode) data transfer operations sci initialization (asynchronous mode): before transmitting and receiving data, first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. 398 figure 15.4 shows a sample sci initialization flowchart. wait 399 serial data transmission (asynchronous mode): figure 15.5 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no 400 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. a format in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. 401 figure 15.6 shows an example of the operation for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 15.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) 402 serial data reception (asynchronous mode): figure 15.7 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. yes 403 404 in serial reception, the sci operates as described below. 1. the sci monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in rsr in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. ? parity check: the sci checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the o/ ( bit in smr. ? stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. ? status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from rsr to rdr. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error* is detected in the error check, the operation is as shown in table 15.11. note: * subsequent receive operations cannot be performed when a receive error has occurred. also note that the rdrf flag is not set to 1 in reception, and so the error flags must be cleared to 0. 4. if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive-data-full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer, per, or fer flag changes to 1, a receive-error interrupt (eri) request is generated. 405 table 15.11 receive errors and conditions for occurrence receive error abbreviation occurrence condition data transfer overrun error orer when the next data reception is completed while the rdrf flag in ssr is set to 1 receive data is not transferred from rsr to rdr framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr parity error per when the received data differs from the parity (even or odd) set in smr receive data is transferred from rsr to rdr figure 15.8 shows an example of the operation for reception in asynchronous mode. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit rxi interrupt request generated eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine figure 15.8 example of sci operation in reception (example with 8-bit data, parity, one stop bit) 406 15.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing transmission lines. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. figure 15.9 shows an example of inter-processor communication using a multiprocessor format. 407 data transfer format: there are four data transfer formats. when a multiprocessor format is specified, the parity bit specification is invalid. for details, see table 15.10. clock: see the section on asynchronous mode. transmitting station receiving station a (id = 01) receiving station b (id = 02) receiving station c (id = 03) receiving station d (id = 04) serial communication line serial data id transmission cycle: receiving station specification data transmission cycle: data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend: mpb: multiprocessor bit figure 15.9 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) 408 data transfer operations multiprocessor serial data transmission: figure 15.10 shows a sample flowchart for multiprocessor serial data transmission. the following procedure should be used for multiprocessor serial data transmission. no 409 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit-data-empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. multiprocessor bit one multiprocessor bit (mpbt value) is output. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a transmit-end interrupt (tei) request is generated. figure 15.11 shows an example of sci operation for transmission using a multiprocessor format. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit multi- proce- ssor bit stop bit start bit data multi- proces- sor bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 15.11 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit) 410 multiprocessor serial data reception: figure 15.12 shows a sample flowchart for multiprocessor serial reception. the following procedure should be used for multiprocessor serial data reception. yes 411 412 figure 15.13 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine if not this station? id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station? id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id2) start bit mpb stop bit start bit data (data2) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine matches this station? id, so reception continues, and data is received in rxi interrupt handling routine mpie bit set to 1 again id2 (b) data matches station? id data2 id1 figure 15.13 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit) 413 15.3.4 operation in synchronous mode in synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 15.14 shows the general format for synchronous serial communication. don? care don? care one unit of transfer data (character or frame) bit 0 serial data serial clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * note: * high except in continuous transfer * figure 15.14 data format in synchronous communication in synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data is guaranteed valid at the rising edge of the serial clock. in synchronous serial communication, one character consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in synchronous mode, the sci receives data in synchronization with the rising edge of the serial clock. 414 data transfer format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the built-in baud rate generator or an external serial clock input at the sck pin can be selected, according to the setting of the c/ $ bit in smr and the cke1 and cke0 bits in scr. for details on sci clock source selection, see table 15.9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. when only receive operations are performed, however, the serial clock is output until an overrun error occurs or the re bit is cleared to 0. to perform receive operations in units of one character, select an external clock as the clock source. data transfer operations sci initialization (synchronous mode): before transmitting and receiving data, first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the settings of the rdrf, per, fer, and orer flags, or the contents of rdr. figure 15.15 shows a sample sci initialization flowchart. 415 wait 416 serial data transmission (synchronous mode): figure 15.16 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no 417 in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit-data-empty interrupt (txi) is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). 3. the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scr is set to 1 at this time, a transmit-end interrupt (tei) request is generated. 4. after completion of serial transmission, the sck pin is held in a constant state. figure 15.17 shows an example of sci operation in transmission. transfer direction bit 0 serial data serial clock 1 frame tdre tend bit 1 bit 7 bit 0 bit 1 bit 7 bit 6 data written to tdr and tdre flag cleared to 0 in txi interrupt handling routine tei interrupt request generated txi interrupt request generated txi interrupt request generated figure 15.17 example of sci operation in transmission 418 serial data reception (synchronous mode): figure 15.18 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. when changing the operating mode from asynchronous to synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible. yes 419 in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with serial clock input or output. 2. the received data is stored in rsr in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0 and the receive data can be transferred from rsr to rdr. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error is detected in the error check, the operation is as shown in table 15.11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. 3. if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive-data-full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer flag changes to 1, a receive-error interrupt (eri) request is generated. figure 15.19 shows an example of sci operation in reception. bit 7 serial data serial clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt handling routine rxi interrupt request generated eri interrupt request generated by overrun error figure 15.19 example of sci operation in reception 420 simultaneous serial data transmission and reception (synchronous mode): figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. yes 421 15.4 sci interrupts the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full interrupt (rxi) request, and transmit-data-empty interrupt (txi) request. table 15.12 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in scr. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dtc to perform data transfer. the tdre flag is cleared to 0 automatically when data transfer is performed by the dtc. the dtc cannot be activated by a tei interrupt request. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt can activate the dtc to perform data transfer. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dtc. the dtc cannot be activated by an eri interrupt request. table 15.12 sci interrupt sources channel interrupt source description dtc activation priority * 0 eri receive error (orer, fer, or per) not possible high rxi receive data register full (rdrf) possible txi transmit data register empty (tdre) possible tei transmit end (tend) not possible 1 eri receive error (orer, fer, or per) not possible rxi receive data register full (rdrf) possible txi transmit data register empty (tdre) possible tei transmit end (tend) not possible low note: * the table shows the initial state immediately after a reset. relative channel priorities can be changed by the interrupt controller. the tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. the tend flag is cleared at the same time as the tdre flag. consequently, if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt will have priority for acceptance, and the tdre flag and tend flag may be cleared. note that the tei interrupt will not be accepted in this case. 422 15.5 usage notes the following points should be noted when using the sci. relation between writes to tdr and the tdre flag: the tdre flag in ssr is a status flag that indicates that transmit data has been transferred from tdr to tsr. when the sci transfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr regardless of the state of the tdre flag. however, if new data is written to tdr when the tdre flag is cleared to 0, the data stored in tdr will be lost since it has not yet been transferred to tsr. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to tdr. operation when multiple receive errors occur simultaneously: if a number of receive errors occur at the same time, the state of the status flags in ssr is as shown in table 15.13. if there is an overrun error, data is not transferred from rsr to rdr, and the receive data is lost. table 15.13 state of ssr status flags and transfer of receive data ssr status flags receive data transfer rdrf orer fer per rsr to rdr receive errors 1 1 0 0 x overrun error 0 0 1 0 o framing error 0 0 0 1 o parity error 1 1 1 0 x overrun error + framing error 1 1 0 1 x overrun error + parity error 0 0 1 1 o framing error + parity error 1 1 1 1 x overrun error + framing error + parity error notes: o: receive data is transferred from rsr to rdr. x: receive data is not transferred from rsr to rdr. break detection and processing: when a framing error (fer) is detected, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the parity error flag (per) may also be set. note that, since the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 423 sending a break: the txd pin has a dual function as an i/o port whose direction (input or output) is determined by dr and ddr. this feature can be used to send a break. between serial transmission initialization and setting of the te bit to 1, the mark state is replaced by the value of dr (the pin does not function as the txd pin until the te bit is set to 1). consequently, ddr and dr for the port corresponding to the txd pin should first be set to 1. to send a break during serial transmission, first clear dr to 0, then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. receive error flags and transmit operations (synchronous mode only): transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. receive data sampling timing and reception margin in asynchronous mode: in asynchronous mode, the sci operates on a base clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the base clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the base clock. this is illustrated in figure 15.21. internal base clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 15.21 receive data sampling timing in asynchronous mode 424 thus the receive margin in asynchronous mode is given by equation (1) below. m = 0.5 ? 1 2n d ?0.5 n ?(l ?0.5)f ? (1 + f) 100% .......... (1) where m: receive margin (%) n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in equation (1), a receive margin of 46.875% is given by equation (2) below. when d = 0.5 and f = 0, m = 1 2 16 100% = 46.875% 0.5 .......... (2) however, this is only a theoretical value, and a margin of 20% to 30% should be allowed in system design. restrictions on use of dtc when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ? clock cycles after tdr is updated by the dtc. misoperation may occur if the transmit clock is input within 4 clock cycles after tdr is updated. (figure 15.22) when rdr is read by the dtc, be sure to set the activation source to the relevant sci receive-data-full interrupt (rxi). t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when operating on an external clock, set t > 4 states. tdre figure 15.22 example of synchronous transmission by dtc 425 section 16 i 2 c bus interface (iic) [h8s/2128 series option] a two-channel i 2 c bus interface is available as an option in the h8s/2128 series. the i 2 c bus interface is not available for the h8s/2124 series. observe the following notes when using this option. 1. for mask-rom versions, a w is added to the part number in products in which this optional function is used. example: hd6432127rwf 2. the product number is identical for f-ztat versions. however, be sure to inform your hitachi sales representative if you will be using this option. 16.1 overview a two-channel i 2 c bus interface is available for the h8s/2128 series as an option. the i 2 c bus interface conforms to and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. each i 2 c bus interface channel uses only one data line (sda) and one clock line (scl) to transfer data, saving board and connector space. 16.1.1 features selection of addressing format or non-addressing format ? i 2 c bus format: addressing format with acknowledge bit, for master/slave operation ? serial format: non-addressing format without acknowledge bit, for master operation only conforms to philips i 2 c bus interface (i 2 c bus format) two ways of setting slave address (i 2 c bus format) start and stop conditions generated automatically in master mode (i 2 c bus format) selection of acknowledge output levels when receiving (i 2 c bus format) automatic loading of acknowledge bit when transmitting (i 2 c bus format) wait function in master mode (i 2 c bus format) a wait can be inserted by driving the scl pin low after data transfer, excluding acknowledgement. the wait can be cleared by clearing the interrupt flag. wait function in slave mode (i 2 c bus format) a wait request can be generated by driving the scl pin low after data transfer, excluding acknowledgement. the wait request is cleared when the next transfer becomes possible. 426 three interrupt sources ? data transfer end (including transmission mode transition with i 2 c bus format and address reception after loss of master arbitration) ? address match: when any slave address matches or the general call address is received in slave receive mode (i 2 c bus format) ? stop condition detection selection of 16 internal clocks (in master mode) direct bus drive (with scl and sda pins) ? two pinsp52/scl0 and p47/sda0(normally nmos push-pull outputs) function as nmos open-drain outputs when the bus drive function is selected. ? two pinsp24/scl1 and p23/sda1(normally cmos pins) function as nmos-only outputs when the bus drive function is selected. automatic switching from formatless mode to i 2 c bus format (channel 0 only) ? formatless operation (no start/stop conditions, non-addressing mode) in slave mode ? operation using a common data pin (sda) and independent clock pins (vsynci, scl) ? ? automatic switching from formatless mode to i 2 c bus format on the fall of the scl pin 427 16.1.2 block diagram figure 16.1 shows a block diagram of the i 2 c bus interface. figure 16.2 shows an example of i/o pin connections to external circuits. channel 0 i/o pins and channel 1 i/o pins differ in structure, and have different specifications for permissible applied voltages. for details, see section 22, electrical characteristics. ps noise canceler noise canceler clock control formatless dedicated clock (channel 0 only) bus state decision circuit arbitration decision circuit output data control circuit address comparator sar, sarx interrupt generator icdrs icdrr icdrt icsr icmr iccr internal data bus interrupt request scl sda legend: iccr: icmr: icsr: icdr: sar: sarx: ps: i 2 c bus control register i 2 c bus mode register i 2 c bus status register i 2 c bus data register slave address register slave address register x prescaler figure 16.1 block diagram of i 2 c bus interface 428 scl in scl out sda in sda out (slave 1) scl sda scl in scl out sda in sda out (slave 2) scl sda scl in scl out sda in sda out (master) h8s/2128 series chip scl sda vcc vcc scl sda figure 16.2 i 2 c bus interface connections (example: h8s/2128 series chip as master) 16.1.3 input/output pins table 16.1 summarizes the input/output pins used by the i 2 c bus interface. table 16.1 i 2 c bus interface pins channel name abbreviation i/o function 0 serial clock scl0 i/o iic0 serial clock input/output serial data sda0 i/o iic0 serial data input/output formatless serial clock vsynci input iic0 formatless serial clock input 1 serial clock scl1 i/o iic1 serial clock input/output serial data sda1 i/o iic1 serial data input/output note: in the text, the channel subscript is omitted, and only scl and sda are used. 429 16.1.4 register configuration table 16.2 summarizes the registers of the i 2 c bus interface. table 16.2 register configuration channel name abbreviation r/w initial value address * 1 0i 2 c bus control register iccr0 r/w h'01 h'ffd8 i 2 c bus status register icsr0 r/w h'00 h'ffd9 i 2 c bus data register icdr0 r/w h'ffde * 2 i 2 c bus mode register icmr0 r/w h'00 h'ffdf * 2 slave address register sar0 r/w h'00 h'ffdf * 2 second slave address register sarx0 r/w h'01 h'ffde * 2 1i 2 c bus control register iccr1 r/w h'01 h'ff88 i 2 c bus status register icsr1 r/w h'00 h'ff89 i 2 c bus data register icdr1 r/w h'ff8e * 2 i 2 c bus mode register icmr1 r/w h'00 h'ff8f * 2 slave address register sar1 r/w h'00 h'ff8f * 2 second slave address register sarx1 r/w h'01 h'ff8e * 2 common serial/timer control register stcr r/w h'00 h'ffc3 ddc switch register ddcswr r/w h'0f h'fee6 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 notes: 1. lower 16 bits of the address. 2. the register that can be written or read depends on the ice bit in the i 2 c bus control register. the slave address register can be accessed when ice = 0, and the i 2 c bus mode register can be accessed when ice = 1. the i 2 c bus interface registers are assigned to the same addresses as other registers. register selection is performed by means of the iice bit in the serial/timer control register (stcr). 430 16.2 register descriptions 16.2.1 i 2 c bus data register (icdr) bit initial value read/write 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w icdrr bit initial value read/write 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r icdrs bit initial value read/write 7 icdrs7 ? 6 icdrs6 ? 5 icdrr5 ? 4 icdrs4 ? 3 icdrs3 ? 0 icdrs0 ? 2 icdrs2 ? 1 icdrs1 ? icdrt bit initial value read/write 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w tdre, rdrf (internal flags) bit initial value read/write ? rdrf 0 ? tdre 0 431 icdr is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. icdr is divided internally into a shift register (icdrs), receive buffer (icdrr), and transmit buffer (icdrt). icdrs cannot be read or written by the cpu, icdrr is read-only, and icdrt is write-only. data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as tdre and rdrf. if iic is in transmit mode and the next data is in icdrt (the tdre flag is 0) following transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrt to icdrs. if iic is in receive mode and no previous data remains in icdrr (the rdrf flag is 0) following transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrs to icdrr. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. icdr is assigned to the same address as sarx, and can be written and read only when the ice bit is set to 1 in iccr. the value of icdr is undefined after a reset. the tdre and rdrf flags are set and cleared under the conditions shown below. setting the tdre and rdrf flags affects the status of the interrupt flags. 432 tdre description 0 the next transmit data is in icdr (icdrt), or transmission cannot (initial value) be started [clearing conditions] when transmit data is written in icdr (icdrt) in transmit mode (trs = 1) when a stop condition is detected in the bus line state after a stop condition is issued with the i 2 c bus format or serial format selected when a stop condition is detected with the i 2 c bus format selected in receive mode (trs = 0) (a 0 write to trs during transfer is valid after reception of a frame containing an acknowledge bit) 1 the next transmit data can be written in icdr (icdrt) [setting conditions] in transmit mode (trs = 1), when a start condition is detected in the bus line state after a start condition is issued in master mode with the i 2 c bus format or serial format selected when using formatless mode in transmit mode (trs = 1) when data is transferred from icdrt to icdrs (data transfer from icdrt to icdrs when trs = 1 and tdre = 0, and icdrs is empty) when a switch is made from receive mode (trs = 0) to transmit mode (trs = 1 ) after detection of a start condition rdrf description 0 the data in icdr (icdrr) is invalid (initial value) [clearing condition] when icdr (icdrr) receive data is read in receive mode 1 the icdr (icdrr) receive data can be read [setting condition] when data is transferred from icdrs to icdrr (data transfer from icdrs to icdrr in case of normal termination with trs = 0 and rdrf = 0) 433 16.2.2 slave address register (sar) bit initial value read/write 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w sar is an 8-bit readable/writable register that stores the slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. sar is assigned to the same address as icmr, and can be written and read only when the ice bit is cleared to 0 in iccr. sar is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 1slave address (sva6 to sva0): set a unique address in bits sva6 to sva0, differing from the addresses of other slave devices connected to the i 2 c bus. 434 bit 0format select (fs): used together with the fsx bit in sarx and the sw bit in ddcswr to select the communication format. i 2 c bus format: addressing format with acknowledge bit synchronous serial format: non-addressing format without acknowledge bit, for master mode only formatless mode (channel 0 only): non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected the fs bit also specifies whether or not sar slave address recognition is performed in slave mode. ddcswr bit 6 sar bit 0 sarx bit 0 sw fs fsx operating mode 000 i 2 c bus format sar and sarx slave addresses recognized 1i 2 c bus format sar slave address recognized sarx slave address ignored (initial value) 10 i 2 c bus format sar slave address ignored sarx slave address recognized 1 synchronous serial format sar and sarx slave addresses ignored 1 0 0 formatless mode (start/stop conditions not detected) 1 acknowledge bit used 10 1 formatless mode * (start/stop conditions not detected) no acknowledge bit note: * do not set this mode when automatic switching to the i 2 c bus format is performed by means of the ddcswr setting. 435 16.2.3 second slave address register (sarx) bit initial value read/write 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w sarx is an 8-bit readable/writable register that stores the second slave address and selects the communication format. when the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of sarx match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. sarx is assigned to the same address as icdr, and can be written and read only when the ice bit is cleared to 0 in iccr. sarx is initialized to h'01 by a reset and in hardware standby mode. bits 7 to 1second slave address (svax6 to svax0): set a unique address in bits svax6 to svax0, differing from the addresses of other slave devices connected to the i 2 c bus. bit 0format select x (fsx): used together with the fs bit in sar and the sw bit in ddcswr to select the communication format. i 2 c bus format: addressing format with acknowledge bit synchronous serial format: non-addressing format without acknowledge bit, for master mode only formatless mode: non-addressing format with or without acknowledge bit, slave mode only, start/stop conditions not detected the fsx bit also specifies whether or not sarx slave address recognition is performed in slave mode. for details, see the description of the fs bit in sar. 436 16.2.4 i 2 c bus mode register (icmr) bit initial value read/write 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w icmr is an 8-bit readable/writable register that selects whether the msb or lsb is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. icmr is assigned to the same address as sar. icmr can be written and read only when the ice bit is set to 1 in iccr. icmr is initialized to h'00 by a reset and in hardware standby mode. bit 7msb-first/lsb-first select (mls): selects whether data is transferred msb-first or lsb-first. if the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. do not set this bit to 1 when the i 2 c bus format is used. bit 7 mls description 0 msb-first (initial value) 1 lsb-first 437 bit 6wait insertion bit (wait): selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the i 2 c bus format. when wait is set to 1, after the fall of the clock for the final data bit, the iric flag is set to 1 in iccr, and a wait state begins (with scl at the low level). when the iric flag is cleared to 0 in iccr, the wait ends and the acknowledge bit is transferred. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. the iric flag in iccr is set to 1 on completion of the acknowledge bit transfer, regardless of the wait setting. the setting of this bit is invalid in slave mode. bit 6 wait description 0 data and acknowledge bits transferred consecutively (initial value) 1 wait inserted between data and acknowledge bits 438 bits 5 to 3serial clock select (cks2 to cks0): these bits, together with the iicx1 (channel 1) or iicx0 (channel 0) bit in the stcr register, select the serial clock frequency in master mode. they should be set according to the required transfer rate. stcr bit 5 or 6 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock ? = 5 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz 0 0 0 0 ?/28 179 khz 286 khz 357 khz 571 khz * 714 khz * 1 ?/40 125 khz 200 khz 250 khz 400 khz 500 khz * 1 0 ?/48 104 khz 167 khz 208 khz 333 khz 417 khz * 1 ?/64 78.1 khz 125 khz 156 khz 250 khz 313 khz 1 0 0 ?/80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 ?/100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 1 0 ?/112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 1 ?/128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 0 ?/56 89.3 khz 143 khz 179 khz 286 khz 357 khz 1 ?/80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 0 ?/96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 1 ?/128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 ?/160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 1 ?/200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 1 0 ?/224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 ?/256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz note: * outside the i 2 c bus interface specification range (normal mode: max. 100 khz; high-speed mode: max. 400 khz). 439 bits 2 to 0bit counter (bc2 to bc0): bits bc2 to bc0 specify the number of bits to be transferred next. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the data is transferred with one addition acknowledge bit. bits bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low. the bit counter is initialized to 000 by a reset and when a start condition is detected. the value returns to 000 at the end of a data transfer, including the acknowledge bit. bit 2 bit 1 bit 0 bits/frame bc2 bc1 bc0 synchronous serial format i 2 c bus format 0 0 0 8 9 (initial value) 11 2 10 2 3 13 4 100 4 5 15 6 10 6 7 17 8 440 16.2.5 i 2 c bus control register (iccr) bit initial value read/write note: * only 0 can be written, to clear the flag. 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * iccr is an 8-bit readable/writable register that enables or disables the i 2 c bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or disables acknowledgement, confirms the i 2 c bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. iccr is initialized to h'01 by a reset and in hardware standby mode. bit 7i 2 c bus interface enable (ice): selects whether or not the i 2 c bus interface is to be used. when ice is set to 1, port pins function as scl and sda input/output pins and transfer operations are enabled. when ice is cleared to 0, the i 2 c bus interface module is disabled. the sar and sarx registers can be accessed when ice is 0. the icmr and icdr registers can be accessed when ice is 1. bit 7 ice description 0i 2 c bus interface module disabled, with scl and sda signal pins set to port function sar and sarx can be accessed (initial value) 1i 2 c bus interface module enabled for transfer operations (pins scl and sca are driving the bus) icmr and icdr can be accessed bit 6i 2 c bus interface interrupt enable (ieic): enables or disables interrupts from the i 2 c bus interface to the cpu. bit 6 ieic description 0 interrupts disabled (initial value) 1 interrupts enabled 441 bit 5master/slave select (mst) bit 4transmit/receive select (trs) mst selects whether the i 2 c bus interface operates in master mode or slave mode. trs selects whether the i 2 c bus interface operates in transmit mode or receive mode. in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. in slave receive mode with the addressing format (fs = 0 or fsx = 0), hardware automatically selects transmit or receive mode according to the r/w bit in the first frame after a start condition. modification of the trs bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. mst and trs select the operating mode as follows. bit 5 bit 4 mst trs operating mode 0 0 slave receive mode (initial value) 1 slave transmit mode 1 0 master receive mode 1 master transmit mode bit 5 mst description 0 slave mode [clearing conditions] 1. when 0 is written by software 2. when bus arbitration is lost after transmission is started in i 2 c bus format master mode (initial value) 1 master mode [setting conditions] 1. when 1 is written by software (in cases other than clearing condition 2) 2. when 1 is written in mst after reading mst = 0 (in case of clearing condition 2) 442 bit 4 trs description 0 receive mode [clearing conditions] 1. when 0 is written by software (in cases other than setting condition 3) 2. when 0 is written in trs after reading trs = 1 (in case of clearing condition 3) 3. when bus arbitration is lost after transmission is started in i 2 c bus format master mode 4. when the sw bit in ddcswr changes from 1 to 0 (initial value) 1 transmit mode [setting conditions] 1. when 1 is written by software (in cases other than clearing conditions 3 and 4) 2. when 1 is written in trs after reading trs = 0 (in case of clearing conditions 3 and 4) 3. when a 1 is received as the r/w bit of the first frame in i 2 c bus format slave mode bit 3acknowledge bit judgement selection (acke): specifies whether the value of the acknowledge bit returned from the receiving device when using the i 2 c bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. when the acke bit is 0, the value of the received acknowledge bit is not indicated by the ackb bit, which is always 0. in the h8s/2128 series, the dtc can be used to perform continuous transfer. the dtc is activated when the irtr interrupt flag is set to 1 (irtr is one of two interrupt flags, the other being iric). when the acke bit is 0, the tdre, iric, and irtr flags are set on completion of data transmission, regardless of the value of the acknowledge bit. when the acke bit is 1, the tdre, iric, and irtr flags are set on completion of data transmission when the acknowledge bit is 0, and the iric flag alone is set on completion of data transmission when the acknowledge bit is 1. when the dtc is activated, the tdre, iric, and irtr flags are cleared to 0 after the specified number of data transfers have been executed. consequently, interrupts are not generated during continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the acke bit is set to 1, the dtc is not activated and an interrupt is generated, if enabled. depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. bit 3 acke description 0 the value of the acknowledge bit is ignored, and continuous transfer is performed (initial value) 1 if the acknowledge bit is 1, continuous transfer is interrupted 443 bit 2bus busy (bbsy): the bbsy flag can be read to check whether the i 2 c bus (scl, sda) is busy or free. in master mode, this bit is also used to issue start and stop conditions. a high-to-low transition of sda while scl is high is recognized as a start condition, setting bbsy to 1. a low-to-high transition of sda while scl is high is recognized as a stop condition, clearing bbsy to 0. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, use a mov instruction to write 0 in bbsy and 0 in scp. it is not possible to write to bbsy in slave mode; the i 2 c bus interface must be set to master transmit mode before issuing a start condition. mst and trs should both be set to 1 before writing 1 in bbsy and 0 in scp. bit 2 bbsy description 0 bus is free [clearing condition] when a stop condition is detected (initial value) 1 bus is busy [setting condition] when a start condition is detected bit 1i 2 c bus interface interrupt request flag (iric): indicates that the i 2 c bus interface has issued an interrupt request to the cpu. iric is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. iric is set at different times depending on the fs bit in sar and the wait bit in icmr. see section 16.3.6, iric setting timing and scl control. the conditions under which iric is set also differ depending on the setting of the acke bit in iccr. iric is cleared by reading iric after it has been set to 1, then writing 0 in iric. when the dtc is used, iric is cleared automatically and transfer can be performed continuously without cpu intervention. 444 bit 1 iric description 0 waiting for transfer, or transfer in progress (initial value) [clearing conditions] 1. when 0 is written in iric after reading iric = 1 2. when icdr is written or read by the dtc (when the tdre or rdrf flag is cleared to 0) (this is not always a clearing condition; see the description of dtc operation for details) 1 interrupt requested [setting conditions] i 2 c bus format master mode 1. when a start condition is detected in the bus line state after a start condition is issued (when the tdre flag is set to 1 because of first frame transmission) 2. when a wait is inserted between the data and acknowledge bit when wait = 1 3. at the end of data transfer (at the rise of the 9th transmit/receive clock pulse, and, when a wait is inserted, at the fall of the 8th transmit/receive clock pulse) 4. when a slave address is received after bus arbitration is lost (when the al flag is set to 1) 5. when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) i 2 c bus format slave mode 1. when the slave address (sva, svax) matches (when the aas and aasx flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) 2. when the general call address is detected (when fs = 0 and the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) 3. when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) 4. when a stop condition is detected (when the stop or estp flag is set to 1) synchronous serial format, and formatless mode 1. at the end of data transfer (when the tdre or rdrf flag is set to 1) 2. when a start condition is detected with serial format selected 3. when the sw bit is set to 1 in ddcswr 445 when, with the i 2 c bus format selected, iric is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set iric to 1. although each source has a corresponding flag, caution is needed at the end of a transfer. when the tdre or rdrf internal flag is set, the readable irtr flag may or may not be set. the irtr flag (the dtc start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (sva) or general call address match in i 2 c bus format slave mode. even when the iric flag and irtr flag are set, the tdre or rdrf internal flag may not be set. the iric and irtr flags are not cleared at the end of the specified number of transfers in continuous transfer using the dtc. the tdre or rdrf flag is cleared, however, since the specified number of icdr reads or writes have been completed. table 16.3 shows the relationship between the flags and the transfer states. table 16.3 flags and transfer states mst trs bbsy estp stop irtr aasx al aas adz ackb state 1/01/0000000000 idle state (flag clearing required) 11000000000 start condition issuance 11100100000 start condition established 11/0100000000/1 master mode wait 11/0100100000/1 master mode transmit/receive end 0010001/011/01/00 arbitration lost 00100000100 sar match by first frame in slave mode 00100000110 general call address match 00100010000 sarx match 01/0100000000/1 slave mode transmit/receive end (except after sarx match) 0 0 1/0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 slave mode transmit/receive end (after sarx match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 stop condition detected 446 bit 0start condition/stop condition prohibit (scp): controls the issuing of start and stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. bit 0 scp description 0 writing 0 issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1 writing is ignored (initial value) 16.2.6 i 2 c bus status register (icsr) bit initial value read/write note: * only 0 can be written, to clear the flags. 7 estp 0 r/(w) * 6 stop 0 r/(w) * 5 irtr 0 r/(w) * 4 aasx 0 r/(w) * 3 al 0 r/(w) * 0 ackb 0 r/w 2 aas 0 r/(w) * 1 adz 0 r/(w) * icsr is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. icsr is initialized to h'00 by a reset and in hardware standby mode. bit 7error stop condition detection flag (estp): indicates that a stop condition has been detected during frame transfer in i 2 c bus format slave mode. bit 7 estp description 0 no error stop condition [clearing conditions] 1. when 0 is written in estp after reading estp = 1 2. when the iric flag is cleared to 0 (initial value) 1 in i 2 c bus format slave mode error stop condition detected [setting condition] when a stop condition is detected during frame transfer in other modes no meaning 447 bit 6normal stop condition detection flag (stop): indicates that a stop condition has been detected after completion of frame transfer in i 2 c bus format slave mode. bit 6 stop description 0 no normal stop condition [clearing conditions] 1. when 0 is written in stop after reading stop = 1 2. when the iric flag is cleared to 0 (initial value) 1 in i 2 c bus format slave mode normal stop condition detected [setting condition] when a stop condition is detected after completion of frame transfer in other modes no meaning bit 5i 2 c bus interface continuous transmission/reception interrupt request flag (irtr): indicates that the i 2 c bus interface has issued an interrupt request to the cpu, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which dtc activation is possible. when the irtr flag is set to 1, the iric flag is also set to 1 at the same time. irtr flag setting is performed when the tdre or rdrf flag is set to 1. irtr is cleared by reading irtr after it has been set to 1, then writing 0 in irtr. irtr is also cleared automatically when the iric flag is cleared to 0. bit 5 irtr description 0 waiting for transfer, or transfer in progress [clearing conditions] 1. when 0 is written in irtr after reading irtr = 1 2. when the iric flag is cleared to 0 (initial value) 1 continuous transfer state [setting condition] in i 2 c bus interface slave mode when the tdre or rdrf flag is set to 1 when aasx = 1 in other modes when the tdre or rdrf flag is set to 1 448 bit 4second slave address recognition flag (aasx): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits svax6 to svax0 in sarx. aasx is cleared by reading aasx after it has been set to 1, then writing 0 in aasx. aasx is also cleared automatically when a start condition is detected. bit 4 aasx description 0 second slave address not recognized [clearing conditions] 1. when 0 is written in aasx after reading aasx = 1 2. when a start condition is detected 3. in master mode (initial value) 1 second slave address recognized [setting condition] when the second slave address is detected in slave receive mode while fsx = 0 bit 3arbitration lost (al): this flag indicates that arbitration was lost in master mode. the i 2 c bus interface monitors the bus. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. al is cleared by reading al after it has been set to 1, then writing 0 in al. in addition, al is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 3 al description 0 bus arbitration won [clearing conditions] 1. when icdr data is written (transmit mode) or read (receive mode) 2. when 0 is written in al after reading al = 1 (initial value) 1 arbitration lost [setting conditions] 1. if the internal sda and sda pin disagree at the rise of scl in master transmit mode 2. if the internal scl line is high at the fall of scl in master transmit mode 449 bit 2slave address recognition flag (aas): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar, or if the general call address (h'00) is detected. aas is cleared by reading aas after it has been set to 1, then writing 0 in aas. in addition, aas is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 2 aas description 0 slave address or general call address not recognized [clearing conditions] 1. when icdr data is written (transmit mode) or read (receive mode) 2. when 0 is written in aas after reading aas = 1 3. in master mode (initial value) 1 slave address or general call address recognized [setting condition] when the slave address or general call address is detected in slave receive mode while fs = 0 bit 1general call address recognition flag (adz): in i 2 c bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (h'00). adz is cleared by reading adz after it has been set to 1, then writing 0 in adz. in addition, adz is reset automatically by write access to icdr in transmit mode, or read access to icdr in receive mode. bit 1 adz description 0 general call address not recognized [clearing conditions] 1. when icdr data is written (transmit mode) or read (receive mode) 2. when 0 is written in adz after reading adz = 1 3. in master mode (initial value) 1 general call address recognized [setting condition] when the general call address is detected in slave receive mode while fsx = 0 or fs = 0 450 bit 0acknowledge bit (ackb): stores acknowledge data. in transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ackb. in receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. when this bit is read, in transmission (when trs = 1), the value loaded from the bus line (returned by the receiving device) is read. in reception (when trs = 0), the value set by internal software is read. bit 0 ackb description 0 receive mode: 0 is output at acknowledge output timing (initial value) transmit mode: indicates that the receiving device has acknowledged the data (signal is 0) 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data (signal is 1) 16.2.7 serial/timer control register (stcr) bit initial value read/write 7 ? 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 flshe 0 r/w 0 icks0 0 r/w 2 ? 0 r/w 1 icks1 0 r/w stcr is an 8-bit readable/writable register that controls register access, the i 2 c interface operating mode (when the on-chip iic option is included), and on-chip flash memory (f-ztat versions), and selects the tcnt input clock source. for details of functions not related to the i 2 c bus interface, see section 3.2.4, serial/timer control register (stcr), and the descriptions of the relevant modules. if a module controlled by stcr is not used, do not write 1 to the corresponding bit. stcr is initialized to h'00 by a reset and in hardware standby mode. bit 7reserved: this bit must not be set to 1. bits 6 and 5i 2 c transfer select 1 and 0 (iicx1, iicx0): these bits, together with bits cks2 to cks0 in icmr, select the transfer rate in master mode. for details, see section 16.2.4, i 2 c bus mode register (icmr). 451 bit 4i 2 c master enable (iice): controls cpu access to the i 2 c bus interface data and control registers (iccr, icsr, icdr/sarx, icmr/sar). bit 4 iice description 0 cpu access to i 2 c bus interface data and control registers is disabled (initial value) 1 cpu access to i 2 c bus interface data and control registers is enabled bit 3flash memory control register enable (flshe): controls the operation of the flash memory in f-ztat versions. for details, see section 19, rom. bit 2reserved: this bit must not be set to 1. bits 1 and 0internal clock source select 1 and 0 (icks1, icsk0): these bits, together with bits cks2 to cks0 in tcr, select the clock input to the timer counters (tcnt). for details, see section 12.2.4, timer control register. 16.2.8 ddc switch register (ddcswr) bit initial value read/write notes: 1. only 0 can be written, to clear the flag. 2. always read as 1. 7 swe 0 r/w 6 sw 0 r/w 5 ie 0 r/w 4 if 0 r/(w) * 1 3 clr3 1 w * 2 0 clr0 1 w * 2 2 clr2 1 w * 2 1 clr1 1 w * 2 ddcswr is an 8-bit readable/writable register that controls the iic channel 0 automatic format switching function and iic internal latch clearance. ddcswr is initialized to h'0f by a reset and in hardware standby mode. bit 7ddc mode switch enable (swe): selects the function for automatically switching iic channel 0 from formatless mode to the i 2 c bus format. bit 7 swe description 0 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is disabled (initial value) 1 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is enabled 452 bit 6ddc mode switch (sw): selects either formatless mode or the i 2 c bus format for iic channel 0. bit 6 sw description 0 iic channel 0 is used with the i 2 c bus format [clearing conditions] 1. when 0 is written by software 2. when a falling edge is detected on the scl pin when swe = 1 (initial value) 1 iic channel 0 is used in formatless mode [setting condition] when 1 is written in sw after reading sw = 0 bit 5ddc mode switch interrupt enable bit (ie): enables or disables an interrupt request to the cpu when automatic format switching is executed for iic channel 0. bit 5 ie description 0 interrupt when automatic format switching is executed is disabled (initial value) 1 interrupt when automatic format switching is executed is enabled bit 4ddc mode switch interrupt flag (if): flag that indicates an interrupt request to the cpu when automatic format switching is executed for iic channel 0. bit 4 if description 0 no interrupt is requested when automatic format switching is executed [clearing condition] when 0 is written in if after reading if = 1 (initial value) 1 an interrupt is requested when automatic format switching is executed [setting condition] when a falling edge is detected on the scl pin when swe = 1 453 bits 3 to 0iic clear 3 to 0 (clr3 to clr0): these bits control initialization of the internal state of iic0 and iic1. these bits can only be written to; if read they will always return a value of 1. when a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module(s),and the internal state of the iic module(s) is initialized. the write data for these bits is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. when clearing is required again, all the bits must be written to in accordance with the setting. bit 3 bit 2 bit 1 bit 0 clr3 clr2 clr1 clr0 description 0 0 setting prohibited 1 0 0 setting prohibited 1 iic0 internal latch cleared 1 0 iic1 internal latch cleared 1 iic0 and iic1 internal latches cleared 1 invalid setting 454 16.2.9 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. when the mstp4 or mstp3 bit is set to 1, operation of the corresponding iic channel is halted at the end of the bus cycle, and a transition is made to module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrl bit 4module stop (mstp4): specifies iic channel 0 module stop mode. mstpcrl bit 4 mstp4 description 0 iic channel 0 module stop mode is cleared 1 iic channel 0 module stop mode is set (initial value) mstpcrl bit 3module stop (mstp3): specifies iic channel 1 module stop mode. mstpcrl bit 3 mstp3 description 0 iic channel 1 module stop mode is cleared 1 iic channel 1 module stop mode is set (initial value) 455 16.3 operation 16.3.1 i 2 c bus data format the i 2 c bus interface has serial and i 2 c bus formats. the i 2 c bus formats are addressing formats with an acknowledge bit. these are shown in figures 16.3 (a) and (b). the first frame following a start condition always consists of 8 bits. iic channel 0 only is capable of formatless operation, as shown in figure 16.3 (c). the serial format is a non-addressing format with no acknowledge bit. this is shown in figure 16.4. figure 16.5 shows the i 2 c bus timing. the symbols used in figures 16.3 to 16.5 are explained in table 16.4. s sla r/ w a data a a/ a p 1111 n 7 1 m (a) i 2 c bus format (fs = 0 or fsx = 0) (b) i 2 c bus format (start condition retransmission, fs = 0 or fsx = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 3 1) s sla r/ w a data 111 n1 7 1 m1 s sla r/ w a data a/ a p 111 n2 7 1 m2 11 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 3 1) 11 (c) formatless (iic0 only, fs = 0 or fsx = 0) data a a data 11 n 8 1 m 1 a/ a n: transfer bit count (n = 1 to 8) m: transfer frame count (m 3 1) figure 16.3 i 2 c bus data formats (i 2 c bus formats) 456 s data data p 11 n 8 1 m fs = 1 and fsx = 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 3 1) figure 16.4 i 2 c bus data format (serial format) sda scl s 1-7 sla 8 r/w 9 a 1-7 data 89 1-7 89 a data p a/ a figure 16.5 i 2 c bus timing table 16.4 i 2 c bus data format symbols legend s start condition. the master device drives sda from high to low while scl is high sla slave address, by which the master device selects a slave device r/ : indicates the direction of data transfer: from the slave device to the master device when r/ : is 1, or from the master device to the slave device when r/ : is 0 a acknowledge. the receiving device (the slave in master transmit mode, or the master in master receive mode) drives sda low to acknowledge a transfer data transferred data. the bit length is set by bits bc2 to bc0 in icmr. the msb-first or lsb-first format is selected by bit mls in icmr p stop condition. the master device drives sda from low to high while scl is high 457 16.3.2 master transmit operation in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the transmission procedure and operations are described below. [1] set the ice bit in iccr to 1. set bits mls, wait, and cks2 to cks0 in icmr, and bit iicx in stcr, according to the operating mode. [2] read the bbsy flag in iccr to confirm that the bus is free, then set bits mst and trs to 1 in iccr to select master transmit mode. next, write 1 to bbsy and 0 to scp. this changes sda from high to low when scl is high, and generates the start condition. the tdre internal flag is then set to 1, and the iric and irtr flags are also set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. [3] with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction. write the data (slave address + r/w) to icdr. the tdre internal flag is then cleared to 0. the written address data is transferred to icdrs, and the tdre internal flag is set to 1 again. this is identified as indicating the end of the transfer, and so the iric flag is cleared to 0. the master device sequentially sends the transmit clock and the data written to icdr using the timing shown in figure 16.6. the selected slave device (i.e. the slave device with the matching slave address) drives sda low at the 9th transmit clock pulse and returns an acknowledge signal. [4] when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. if the tdre internal flag has been set to 1, after one frame has been transmitted scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. [5] to continue transfer, write the next data to be transmitted into icdr. after the data has been transferred to icdrs and the tdre internal flag has been set to 1, clear the iric flag to 0. transmission of the next frame is performed in synchronization with the internal clock. data can be transmitted sequentially by repeating steps [4] and [5]. to end transmission, clear the iric flag, write h'ff dummy data to icdr after the last data has been transmitted (when icdrt does not contain the next transmit data), and then write 0 to bbsy and scp in iccr when the iric flag is set again. this changes sda from low to high when scl is high, and generates the stop condition. 458 sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 slave address bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrt icdrs tdre scl (master output) start condition issuance interrupt request generation interrupt request generation data 1 address + r/w data 1 address + r/w [2] write bbsy = 1 and scp = 0 (start condition issuance) [3] icdr write [5] icdr write [5] iric clearance [3] iric clearance user processing slave address data 1 r/w [4] a figure 16.6 example of master transmit mode operation timing (mls = wait = 0) 459 to transmit data continuously: [6] before the rise of the 9th transmit clock pulse for the data being transmitted, clear the iric flag to 0 and then write the next transmit data to icdr. [7] when one frame of data has been transmitted, the iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. at the same time, the next transmit data written into icdr (icdrt) is transferred to icdrs, the tdre internal flag is set to 1, and then the next frame is transmitted in synchronization with the internal clock. data can be transmitted continuously by repeating steps [6] and [7]. sda (master output) sda (slave output) 2 1 23 1 4 36 58 79 bit 7 bit 6 bit 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrt icdrs tdre scl (master output) interrupt request generation data 2 data 1 [6] icdr write icdr write [6] icdr write [6] iric clearance [6] iric clearance user processing data 1 data 1 data 2 data 3 data 2 [7] [7] a figure 16.7 example of master transmit mode continuous transmit operation timing (mls = wait = 0) 16.3.3 master receive operation in master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. the slave device transmits data. the reception procedure and operations in master receive mode are described below. [1] clear the trs bit in iccr to 0 to switch from transmit mode to receive mode. also clear the ackb bit in icsr to 0 (acknowledge data setting). 460 [2] when icdr is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. in order to determine the end of reception, the iric flag in iccr must be cleared beforehand. [3] the master device drives sda at the 9th receive clock pulse to return an acknowledge signal. when one frame of data has been received, the iric flag in iccr is set to 1 at the rise of the 9th receive clock pulse. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the rdrf internal flag has been cleared to 0, it is set to 1, and the receive operation continues. if reception of the next frame ends before the icdr read/iric flag clearing in [4] is performed, scl is automatically fixed low in synchronization with the internal clock. [4] read icdr and clear the iric flag in iccr to 0. the rdrf flag is cleared to 0. data can be received continuously by repeating steps [3] and [4]. as the rdrf internal flag is cleared to 0 when reception is started after initially switching from master transmit mode to master receive mode, reception of the next frame of data is started automatically. to halt reception, the trs bit must be set to 1 before the rise of the receive clock for the next frame. to halt reception, set the tsr bit to 1, read icdr, then write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 9 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) interrupt request generation master transmit mode master receive mode data 1 [1] trs cleared to 0 [2] icdr read (dummy read) [4] icdr read [4] iric clearance [2] iric clearance user processing data 1 data 1 data 2 [3] a a interrupt request generation figure 16.8 example of master receive mode operation timing (mls = wait = ackb = 0) 461 16.3.4 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. the reception procedure and operations in slave receive mode are described below. [1] set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. [2] when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. [3] when the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. if the 8th data bit (r/w) is 0, the trs bit in iccr remains cleared to 0, and slave receive operation is performed. [4] at the 9th clock pulse of the receive frame, the slave device drives sda low and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the rdrf internal flag has been cleared to 0, it is set to 1, and the receive operation continues. if the rdrf internal flag has been set to 1, the slave device drives scl low from the fall of the receive clock until data is read into icdr. [5] read icdr and clear the iric flag in iccr to 0. the rdrf flag is cleared to 0. receive operations can be performed continuously by repeating steps [4] and [5]. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0. 462 sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) start condition issuance scl (slave output) interrupt request generation address + r/w [5] icdr read [5] iric clearance user processing slave address data 1 [4] a r/w address + r/w figure 16.9 example of slave receive mode operation timing (1) (mls = ackb = 0) sda (master output) sda (slave output) 2 14 36 58 79 8 79 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) scl (slave output) interrupt request generation interrupt request generation data 2 data 2 data 1 data 1 [5] icdr read [5] iric clearance user processing data 2 data 1 [4] [4] a a figure 16.10 example of slave receive mode operation timing (2) (mls = ackb = 0) 463 16.3.5 slave transmit operation in slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. the transmission procedure and operations in slave transmit mode are described below. [1] set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. [2] when the slave address matches in the first frame following detection of the start condition, the slave device drives sda low at the 9th clock pulse and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. .if the 8th data bit (r/w) is 1, the trs bit in iccr is set to 1, and the mode changes to slave transmit mode automatically. the tdrf flag is set to 1. the slave device drives scl low from the fall of the transmit clock until icdr data is written. [3] after clearing the iric flag to 0, write data to icdr. the tdre internal flag is cleared to 0. the written data is transferred to icdrs, and the tdre internal flag and the iric and irtr flags are set to 1 again. after clearing the iric flag to 0, write the next data to icdr. the slave device sequentially sends the data written into icdr in accordance with the clock output by the master device at the timing shown in figure 16.11. [4] when one frame of data has been transmitted, the iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. if the tdre internal flag has been set to 1, this slave device drives scl low from the fall of the transmit clock until data is written to icdr. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. as this acknowledge signal is stored in the ackb bit in icsr, this bit can be used to determine whether the transfer operation was performed normally. when the tdre internal flag is 0, the data written into icdr is transferred to icdrs, transmission is started, and the tdre internal flag and the iric and irtr flags are set to 1 again. [5] to continue transmission, clear the iric flag to 0, then write the next data to be transmitted into icdr. the tdre flag is cleared to 0. transmit operations can be performed continuously by repeating steps [4] and [5]. to end transmission, write h'ff to icdr to release sda on the slave side. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0. 464 sda (slave output) sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrt tdre scl (master output) interrupt request generation interrupt request generation slave receive mode slave transmit mode data 1 data 2 [3] iric clearance [5] iric clearance [3] icdr write [3] icdr write [5] icdr write user processing data 1 data 1 data 2 data 2 a r/w a [3] [2] interrupt request generation figure 16.11 example of slave transmit mode operation timing (mls = 0) 465 16.3.6 iric setting timing and scl control the interrupt request flag (iric) is set at different times depending on the wait bit in icmr, the fs bit in sar, and the fsx bit in sarx. if the tdre or rdrf internal flag is set to 1, scl is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. figure 16.12 shows the iric set timing and scl control. (a) when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 a 8 1 1 a 7 1 89 7 (b) when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) scl sda iric user processing clear iric clear iric write to icdr (transmit) or read icdr (receive) scl sda iric user processing (c) when fs = 1 and fsx = 1 (synchronous serial format) clear iric write to icdr (transmit) or read icdr (receive) 8 89 8 7 1 8 7 1 figure 16.12 iric setting timing and scl control 466 16.3.7 automatic switching from formatless mode to i 2 c bus format setting the sw bit to 1 in ddcswr enables formatless mode to be selected as the iic0 operating mode. switching from formatless mode to the i 2 c bus format (slave mode) is performed automatically when a falling edge is detected on the scl pin. the following four preconditions are necessary for this operation: a common data pin (sda) for formatless and i 2 c bus format operation separate clock pins for formatless operation (vsynci) and i 2 c bus format operation (scl) a fixed 1 level for the scl pin during format operation settings of bits other than trs in iccr that allow i 2 c bus format operation automatic switching is performed from formatless mode to the i 2 c bus format when the sw bit in ddcswr is automatically cleared to 0 on detection of a falling edge on the scl pin. switching from the i 2 c bus format to formatless mode is achieved by having software set the sw bit in ddcswr to 1. in formatless mode, bits (such as msl and trs) that control the i 2 c bus interface operating mode must not be modified. when switching from the i 2 c bus format to formatless mode, set the trs bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless mode, then set the sw bit to 1. after automatic switching from formatless mode to the i 2 c bus format (slave mode), in order to wait for slave address reception, the trs bit is automatically cleared to 0. if a falling edge is detected on the scl pin during formatless operation, the i 2 c bus interface format is switched at that point, without waiting for a stop condition. 467 16.3.8 operation using the dtc the i 2 c bus format provides for selection of the slave device and transfer direction by means of the slave address and the r/w bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. therefore, continuous data transfer using the dtc must be carried out in conjunction with cpu processing by means of interrupts. table 16.5 shows some examples of processing using the dtc. these examples assume that the number of transfer data bytes is known in slave mode. table 16.5 examples of operation using the dtc item master transmit mode master receive mode slave transmit mode slave receive mode slave address + r/w bit transmission/ reception transmission by dtc (icdr write) transmission by cpu (icdr write) reception by cpu (icdr read) reception by cpu (icdr read) dummy data read processing by cpu (icdr read) actual data transmission/ reception transmission by dtc (icdr write) reception by dtc (icdr read) transmission by dtc (icdr write) reception by dtc (icdr read) dummy data (h'ff) write processing by dtc (icdr write) last frame processing not necessary reception by cpu (icdr read) not necessary reception by cpu (icdr read) transfer request processing after last frame processing 1st time: clearing by cpu 2nd time: end condition issuance by cpu not necessary automatic clearing on detection of end condition during transmission of dummy data (h'ff) not necessary setting of number of dtc transfer data frames transmission: actual data count + 1 (+1 equivalent to slave address + r/w bits) reception: actual data count transmission: actual data count + 1 (+1 equivalent to dummy data (h'ff)) reception: actual data count 468 16.3.9 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 16.13 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded latches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. system clock period sampling clock c dq latch c dq latch scl or sda input signal match detector internal scl or sda signal sampling clock figure 16.13 block diagram of noise canceler 469 16.3.10 sample flowcharts figures 16.14 to 16.17 show sample flowcharts for using the i 2 c bus interface in each mode. [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] start initialize read bbsy in iccr no bbsy = 0? yes set mst = 1 and trs = 1 in iccr write bbsy = 1 and scp = 0 in iccr write transmit data in icdr read iric in iccr no yes iric = 1? clear iric in iccr clear iric in iccr read ackb in icsr ackb = 0? no yes no yes transmit mode? write transmit data in icdr read iric in iccr iric = 1? no yes read ackb in icsr end of transmission (ackb = 1)? no yes write bbsy = 0 and scp = 0 in iccr end master receive mode [1] test the status of the scl and sda lines. [2] select master transmit mode. [3] generate a start condition. [4] set transmit data for the first byte (slave address + r/w). [5] wait for 1 byte to be transmitted. [6] test for acknowledgement by the designated slave device. [7] set transmit data for the second and subsequent bytes. [8] wait for 1 byte to be transmitted. [9] test for end of transfer. [10] generate a stop condition. figure 16.14 flowchart for master transmit mode (example) 470 master receive mode set trs = 0 in iccr set ackb = 0 in icsr clear iric in iccr last receive? read icdr read iric in iccr clear iric in iccr iric = 1? yes no no yes set ackb = 1 in icsr read icdr read iric in iccr iric = 1? clear iric in iccr set trs = 1 in iccr read icdr write bbsy = 0 and scp = 0 in iccr end [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] yes no [1] select receive mode. [2] set acknowledge data. [3] start receiving. the first read is a dummy read. [4] wait for 1 byte to be received. [5] set acknowledge data for the last receive. [6] start the last receive. [7] wait for 1 byte to be received. [8] select transmit mode. [9] read the last receive data (if icdr is read without selecting transmit mode, receive operations will resume). [10] generate a stop condition. figure 16.15 flowchart for master receive mode (example) 471 start initialize set mst = 0 and trs = 0 in iccr set ackb = 0 in icsr read iric in iccr iric = 1? yes no clear iric in iccr read aas and adz in icsr aas = 1 and adz = 0? read trs in iccr trs = 0? no yes no yes yes no yes yes no no [1] [2] [3] [4] [5] [6] [7] [8] last receive? read icdr read iric in iccr iric = 1? clear iric in iccr set ackb = 1 in icsr read icdr read iric in iccr read icdr iric = 1? clear iric in iccr end general call address processing * description omitted slave transmit mode [1] select slave receive mode. [2] wait for the first byte to be received (slave address). [3] start receiving. the first read is a dummy read. [4] wait for the transfer to end. [5] set acknowledge data for the last receive. [6] start the last receive. [7] wait for the transfer to end. [8] read the last receive data. figure 16.16 flowchart for slave receive mode (example) 472 slave transmit mode write transmit data in icdr read iric in iccr iric = 1? clear iric in iccr clear iric in iccr clear iric in iccr clear iric in iccr read ackb in icsr set trs = 0 in iccr end of transmission (ackb = 1)? yes no no yes end [1] [2] [3] read icdr [5] [4] [1] set transmit data for the second and subsequent bytes. [2] wait for 1 byte to be transmitted. [3] test for end of transfer. [4] select slave receive mode. [5] dummy read (to release the scl line). figure 16.17 flowchart for slave transmit mode (example) 473 16.3.11 initialization of internal state the iic has a function for forcible initialization of its internal state if a deadlock occurs during communication. initialization is executed in accordance with the setting of bits clr3 to clr0 in the ddcswr register. for details see section 16.2.8, ddc switch register (ddcswr). (1) scope of initialization the initialization executed by this function covers the following items: tdre and rdrf internal flags transmit/receive sequencer and internal operating clock counter internal latches for retaining the output state of the scl and sda pins (wait, clock, data output, etc.) the following items are not initialized: actual register values (icdr, sar, sarx, icmr, iccr, icsr, ddcswr, stcr) internal latches used to retain register read information for setting/clearing flags in the icmr, iccr, icsr, and ddcswr registers the value of the icmr register bit counter (bc2 to bc0) generated interrupt sources (interrupt sources transferred to the interrupt controller) (2) notes on initialization interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. the write data for bits clr3 to clr0 is not retained. to perform iic clearance, bits clr3 to clr0 must be written to simultaneously using an mov instruction. do not use a bit manipulation instruction such as bclr. similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. if a flag clearing setting is made during transmission/reception, the iic module will stop transmitting/receiving at that point and the scl and sda pins will be released. when transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. 474 the value of the bbsy bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the scl and sda pins, the bbsy bit may be cleared as a result. similarly, state switching of other bits and flags may also have an effect. to prevent problems caused by these factors, the following procedure should be used when initializing the iic state. (1) execute initialization of the internal state according to the setting of bits clr3 to clr0. (2) execute a stop condition issuance instruction (write 0 to bbsy and scp) to clear the bbst bit to 0, and wait for two transfer rate clock cycles. (3) re-execute initialization of the internal state according to the setting of bits clr3 to clr0. (4) initialize (re-set) the iic registers. 16.4 usage notes in master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. to output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that scl and sda are both low, then issue the instruction that generates the stop condition. note that scl may not yet have gone low when bbsy is cleared to 0. either of the following two conditions will start the next transfer. pay attention to these conditions when reading or writing to icdr. ? write access to icdr when ice = 1 and trs = 1 (including automatic transfer from icdrt to icdrs) ? read access to icdr when ice = 1 and trs = 0 (including automatic transfer from icdrs to icdrr) table 16.6 shows the timing of scl and sda output in synchronization with the internal clock. timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. 475 table 16.6 i 2 c bus timing (scl and sda output) item symbol output timing unit notes scl output cycle time t sclo 28t cyc to 256t cyc ns figure 22.25 scl output high pulse width t sclho 0.5t sclo ns (reference) scl output low pulse width t scllo 0.5t sclo ns sda output bus free time t bufo 0.5t sclo C 1t cyc ns start condition output hold time t staho 0.5t sclo C 1t cyc ns retransmission start condition output setup time t staso 1t sclo ns stop condition output setup time t stoso 0.5t sclo + 2t cyc ns data output setup time (master) t sdaso 1t scllo C 3t cyc ns data output setup time (slave) 1t scll C (6t cyc or 12t cyc * ) data output hold time t sdaho 3t cyc ns note: * 6t cyc when iicx is 0, 12t cyc when 1. scl and sda input is sampled in synchronization with the internal clock. the ac timing therefore depends on the system clock cycle t cyc , as shown in table 22.9 in section 22, electrical characteristics. note that the i 2 c bus interface ac timing specifications will not be met with a system clock frequency of less than 5 mhz. the i 2 c bus interface specification for the scl rise time t sr is under 1000 ns (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if t sr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. the scl rise time is determined by the pull-up resistance and load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the scl rise time does not exceed the values given in the table 16.7 below. 476 table 16.7 permissible scl rise time (t sr ) values time indication iicx t cyc indicatio n i 2 c bus specification (max.) ? = 5 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz 0 7.5t cyc normal mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 1 17.5t cyc normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns the i 2 c bus interface specifications for the scl and sda rise and fall times are under 1000 ns and 300 ns. the i 2 c bus interface scl and sda output timing is prescribed by t scyc and t cyc , as shown in table 16.6. however, because of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maximum transfer rate. table 16.8 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. t bufo fails to meet the i 2 c bus interface specifications at any frequency. the solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. t scllo in high-speed mode and t staso in standard mode fail to satisfy the i 2 c bus interface specifications for worst-case calculations of t sr /t sf . possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. 477 table 16.8 i 2 c bus timing (with maximum influence of t sr /t sf ) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) ? = 5 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz t sclho 0.5t sclo (Ct sr ) standard mode C1000 4000 4000 4000 4000 4000 4000 high-speed mode C300 600 950 950 950 950 950 t scllo 0.5t sclo (Ct sf ) standard mode C250 4700 4750 4750 4750 4750 4750 high-speed mode C250 1300 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 t bufo 0.5t sclo C1t cyc standard mode C1000 4700 3800 * 1 3875 * 1 3900 * 1 3938 * 1 3950 * 1 ( Ct sr ) high-speed mode C300 1300 750 * 1 825 * 1 850 * 1 888 * 1 900 * 1 t staho 0.5t sclo C1t cyc standard mode C250 4000 4550 4625 4650 4688 4700 (Ct sf ) high-speed mode C250 600 800 875 900 938 950 t staso 1t sclo (Ct sr ) standard mode C1000 4700 9000 9000 9000 9000 9000 high-speed mode C300 600 2200 2200 2200 2200 2200 t stoso 0.5t sclo + 2t cyc standard mode C1000 4000 4400 4250 4200 4125 4100 (Ct sr ) high-speed mode C300 600 1350 1200 1150 1075 1050 t sdaso (master) 1t scllo * 3 C 3t cyc standard mode C1000 250 3100 3325 3400 3513 3550 (Ct sr ) high-speed mode C300 100 400 625 700 813 850 t sdaso (slave) 1t scll * 3 C 12t cyc * 2 standard mode C1000 250 1300 2200 2500 2950 3100 (Ct sr ) high-speed mode C300 100 C1400 * 1 C500 * 1 C200 * 1 250 400 478 table 16.8 i 2 c bus timing (with maximum influence of t sr /t sf ) (cont) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) ? = 5 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz ? = 20 mhz t sdaho 3t cyc standard mode 0 0 600 375 300 188 150 high-speed mode 0 0 600 375 300 188 150 notes: 1. does not meet the i 2 c bus interface specification. remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. value when the iicx bit is set to 1. when the iicx bit is cleared to 0, the value is (t scll C 6t cyc ). 3. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high- speed mode: 1300 ns min.). 479 note on icdr read at end of master reception to halt reception at the end of a receive operation in master receive mode, set the trs bit to 1 and write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. after this, receive data can be read by means of an icdr read, but if data remains in the buffer the icdrs receive data will not be transferred to icdr, and so it will not be possible to read the second byte of data. if it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the trs bit cleared to 0). when reading the receive data, first confirm that the bbsy bit in the iccr register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the icdr register with trs cleared to 0. note that if the receive data (icdr data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to bbsy and scp in iccr) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. clearing of the mst bit after completion of master transmission/reception, or other modifications of iic control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 16.18 (after confirming that the bbsy bit has been cleared to 0 in the iccr register). sda scl internal clock bbsy bit master receive mode icdr reading prohibited bit 0 a 8 9 stop condition (a) start condition execution of stop condition issuance instruction (0 written to bbsy and scp) confirmation of stop condition generation (0 read from bbsy) start condition issuance figure 16.18 points for attention concerning reading of master receive data 480 481 section 17 a/d converter 17.1 overview the h8s/2128 series and h8s/2124 series incorporate a 10-bit successive-approximations a/d converter that allows up to eight analog input channels to be selected. in addition to the eight analog input channels, up to 8 channels of digital input can be selected for a/d conversion. since the conversion precision falls to the equivalent of 6-bit resolution when digital input is selected, digital input is ideal for use by a comparator identifying multi- valued inputs, for example. 17.1.1 features a/d converter features are listed below. 10-bit resolution eight (analog) or 8 (digital) input channels settable analog conversion voltage range ? the analog conversion voltage range is set using the analog power supply voltage pin (avcc) as the analog reference voltage high-speed conversion ? minimum conversion time: 6.7 s per channel (at 20 mhz operation) choice of single mode or scan mode ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels four data registers ? conversion results are held in a 16-bit data register for each channel sample and hold function three kinds of conversion start ? choice of software or timer conversion start trigger (8-bit timer), or $'75* pin a/d conversion end interrupt generation ? an a/d conversion end interrupt (adi) request can be generated at the end of a/d conversion 482 17.1.2 block diagram figure 17.1 shows a block diagram of the a/d converter. module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit ?8 ?16 adi interrupt signal bus interface adcsr adcr addrd addrc addrb addra avcc avss an0 an1 an2 an3 an4 an5 an6/cin0 to cin7 an7 adtrg conversion start trigger from 8-bit timer successive approximations register multiplexer legend: adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d figure 17.1 block diagram of a/d converter 483 17.1.3 pin configuration table 17.1 summarizes the input pins used by the a/d converter. the avcc and avss pins are the power supply pins for the analog block in the a/d converter. table 17.1 a/d converter pins pin name symbol i/o function analog power supply pin avcc input analog block power supply analog ground pin avss input analog block ground and a/d conversion reference voltage analog input pin 0 an0 input analog input channel 0 analog input pin 1 an1 input analog input channel 1 analog input pin 2 an2 input analog input channel 2 analog input pin 3 an3 input analog input channel 3 analog input pin 4 an4 input analog input channel 4 analog input pin 5 an5 input analog input channel 5 analog input pin 6 an6 input analog input channel 6 analog input pin 7 an7 input analog input channel 7 a/d external trigger input pin $'75* input external trigger input for starting a/d conversion expansion a/d input pins 0 to 7 cin0 to cin7 input expansion a/d conversion input (digital input pin) channels 0 to 7 484 17.1.4 register configuration table 17.2 summarizes the registers of the a/d converter. table 17.2 a/d converter registers name abbreviation r/w initial value address * 1 a/d data register ah addrah r h'00 h'ffe0 a/d data register al addral r h'00 h'ffe1 a/d data register bh addrbh r h'00 h'ffe2 a/d data register bl addrbl r h'00 h'ffe3 a/d data register ch addrch r h'00 h'ffe4 a/d data register cl addrcl r h'00 h'ffe5 a/d data register dh addrdh r h'00 h'ffe6 a/d data register dl addrdl r h'00 h'ffe7 a/d control/status register adcsr r/(w) * 2 h'00 h'ffe8 a/d control register adcr r/w h'3f h'ffe9 module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 keyboard comparator control register kbcomp r/w h'00 h'fee4 notes: 1. lower 16 bits of the address. 2. only 0 can be written in bit 7, to clear the flag. 485 17.2 register descriptions 17.2.1 a/d data registers a to d (addra to addrd) 15 ad9 0 r bit initial value read/write 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 ? 0 r 4 ? 0 r 3 ? 0 r 2 ? 0 r 1 ? 0 r 0 ? 0 r there are four 16-bit read-only addr registers, addra to addrd, used to store the results of a/d conversion. the 10-bit data resulting from a/d conversion is transferred to the addr register for the selected channel and stored there. the upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of addr, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. bits 5 to 0 are always read as 0. the correspondence between the analog input channels and addr registers is shown in table 17.3. the addr registers can always be read by the cpu. the upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (temp). for details, see section 17.3, interface to bus master. the addr registers are initialized to h'0000 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. table 17.3 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register an0 an4 addra an1 an5 addrb an2 an6 or cin0 to cin7 addrc an3 an7 addrd 486 17.2.2 a/d control/status register (adcsr) 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w bit initial value read/write note: * only 0 can be written in bit 7, to clear the flag. adcsr is an 8-bit readable/writable register that controls a/d conversion operations. adcsr is initialized to h'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bit 7a/d end flag (adf): status flag that indicates the end of a/d conversion. bit 7 adf description 0 [clearing conditions] (initial value) when 0 is written in the adf flag after reading adf = 1 when the dtc is activated by an adi interrupt and addr is read 1 [setting conditions] single mode: when a/d conversion ends scan mode: when a/d conversion ends on all specified channels bit 6a/d interrupt enable (adie): selects enabling or disabling of interrupt (adi) requests at the end of a/d conversion. bit 6 adie description 0 a/d conversion end interrupt (adi) request is disabled (initial value) 1 a/d conversion end interrupt (adi) request is enabled 487 bit 5a/d start (adst): selects starting or stopping of a/d conversion. holds a value of 1 during a/d conversion. the adst bit can be set to 1 by software, a timer conversion start trigger, or the a/d external trigger input pin ( $'75* ). bit 5 adst description 0 a/d conversion stopped (initial value) 1 single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode bit 4scan mode (scan): selects single mode or scan mode as the a/d conversion operating mode. see section 17.4, operation, for single mode and scan mode operation. only set the scan bit while conversion is stopped. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3clock select (cks): sets the a/d conversion time. only change the conversion time while adst = 0. bit 3 cks description 0 conversion time = 266 states (max.) (initial value) 1 conversion time = 134 states (max.) 488 bits 2 to 0channel select 2 to 0 (ch2 to ch0): together with the scan bit, these bits select the analog input channel(s). one analog input channel can be switched to digital input. only set the input channel while conversion is stopped. group selection channel selection description ch2 ch1 ch0 single mode scan mode 0 0 0 an0 (initial value) an0 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3 1 0 0 an4 an4 1 an5 an4, an5 1 0 an6 or cin0 to cin7 an4, an5, an6 or cin0 to cin7 1 an7 an4, an5, an6 or cin0 to cin7 an7 489 17.2.3 a/d control register (adcr) 7 trgs1 0 r/w 6 trgs0 0 r/w 5 ? 1 4 ? 1 3 ? 1 0 ? 1 2 ? 1 1 ? 1 bit initial value read/write adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion operations. adcr is initialized to h'3f by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. bits 7 and 6timer trigger select 1 and 0 (trgs1, trgs0): these bits select enabling or disabling of the start of a/d conversion by a trigger signal. only set bits trgs1 and trgs0 while conversion is stopped. bit 7 bit 6 trgs1 trgs0 description 0 0 start of a/d conversion by external trigger is disabled (initial value) 1 start of a/d conversion by external trigger is disabled 1 0 start of a/d conversion by external trigger (8-bit timer) is enabled 1 start of a/d conversion by external trigger pin is enabled bits 5 to 0reserved: these bits cannot be modified and are always read as 1. 490 17.2.4 keyboard comparator control register (kbcomp) bit 76543210 ire ircks2 ircks1 ircks0 kbade kbch2 kbch1 kbch0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w kbcomp is an 8-bit readable/writable register that selects the cin input channels for a/d conversion. kbcomp is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 4reserved bit 3keyboard a/d enable: selects either analog input pin (an6) or digital input pin (cin0 to cin7) for a/d converter channel 6 input. if digital input pins are selected, input on a/d converter channel 7 will not be converted correctly. bits 2 to 0keyboard a/d channel select 2 to 0 (kbch2 to kbch0): these bits select the channels for a/d conversion from among the digital input pins. only set the input channel while a/d conversion is stopped. bit 3 bit 2 bit 1 bit 0 a/d converter a/d converter kbade kbch2 kbch1 kbch0 channel 6 input channel 7 input 0 an6 an7 1 0 0 0 cin0 undefined 1 cin1 undefined 1 0 cin2 undefined 1 cin3 undefined 1 0 0 cin4 undefined 1 cin5 undefined 1 0 cin6 undefined 1 cin7 undefined 491 17.2.5 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr, comprising two 8-bit readable/writable registers, performs module stop mode control. when the mstp9 bit in mstpcr is set to 1, a/d converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 21.5, module stop mode. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstpcrh bit 1module stop (mstp9): specifies the a/d converter module stop mode. mstpcrh bit 1 mstp9 description 0 a/d converter module stop mode is cleared 1 a/d converter module stop mode is set (initial value) 492 17.3 interface to bus master addra to addrd are 16-bit registers, but the data bus to the bus master is only 8 bits wide. therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (temp). a data read from addr is performed as follows. when the upper byte is read, the upper byte value is transferred to the cpu and the lower byte value is transferred to temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading addr, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 17.2 shows the data flow for addr access. bus master (h'aa) addrnh (h'aa) addrnl (h'40) lower byte read addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) module data bus module data bus bus interface upper byte read bus master (h'40) bus interface figure 17.2 addr access operation (reading h'aa40) 493 17.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode. 17.4.1 single mode (scan = 0) single mode is selected when a/d conversion is to be performed on a single channel only. a/d conversion is started when the adst bit is set to 1 by software, or by external trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. on completion of conversion, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. the adf flag is cleared by writing 0 after reading adcsr. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when channel 1 (an1) is selected in single mode are described next. figure 17.3 shows a timing diagram for this example. 1. single mode is selected (scan = 0), input channel an1 is selected (ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion is completed, the result is transferred to addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the routine reads adcsr, then writes 0 to the adf flag. 6. the routine reads and processes the conversion result (addrb). 7. execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps 2 to 7 are repeated. 494 adie adst adf state of channel 0 (an0) a/d conversion starts 2 1 addra addrb addrc addrd state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) note: * vertical arrows ( ) indicate instructions executed by software. set * set * clear * clear * a/d conversion result 1 a/d conversion a/d conversion result 2 read conversion result read conversion result idle idle idle idle idle idle a/d conversion set * figure 17.3 example of a/d converter operation (single mode, channel 1 selected) 495 17.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by software, or by timer or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0; an4 when ch2 = 1). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1 or an5) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the addr registers corresponding to the channels. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when three channels (an0 to an2) are selected in scan mode are described next. figure 17.4 shows a timing diagram for this example. 1. scan mode is selected (scan = 1), scan group 0 is selected (ch2 = 0), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1) 2. when a/d conversion of the first channel (an0) is completed, the result is transferred to addra. next, conversion of the second channel (an1) starts automatically. 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion of all the selected channels (an0 to an2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. 5. steps 2 to 4 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0). 496 adst adf addra addrb addrc addrd state of channel 0 (an0) state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) set * 1 clear * 1 idle notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. clear * 1 idle idle a/d conversion time idle continuous a/d conversion execution a/d conversion 1 idle idle idle idle idle transfer * 2 a/d conversion 3 a/d conversion 2 a/d conversion 5 a/d conversion 4 a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion result 4 figure 17.4 example of a/d converter operation (scan mode, channels an0 to an2 selected) 497 17.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 17.5 shows the a/d conversion timing. table 17.4 indicates the a/d conversion time. as indicated in figure 17.5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 17.4. in scan mode, the values given in table 17.4 apply to the first conversion time. in the second and subsequent conversions the conversion time is fixed at 256 states when cks = 0 or 128 states when cks = 1. (1) (2) t d t spl t conv input sampling timing adf address write signal legend: (1): adcsr write cycle (2): adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 17.5 a/d conversion timing 498 table 17.4 a/d conversion time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max a/d conversion start delay t d 10176 9 input sampling time t spl 6331 a/d conversion time t conv 259 266 131 134 note: values in the table are the number of states. 17.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs1 and trgs0 bits are set to 11 in adcr, external trigger input is enabled at the $'75* pin. a falling edge at the $'75* pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the adst bit is set to 1 by software. figure 17.6 shows the timing. ? adtrg internal trigger signal adst a/d conversion figure 17.6 external trigger input timing 17.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in adcsr. 499 17.6 usage notes the following points should be noted when using the a/d converter. setting range of analog power supply and other pins: 1. analog input voltage range the voltage applied to the ann analog input pins during a/d conversion should be in the range av ss ann av cc (n = 0 to 7). 2. digital input voltage range the voltage applied to the cinn digital input pins should be in the range av ss cinn av cc and v ss cinn v cc (n = 0 to 7). 3. relation between av cc , av ss and v cc , v ss as the relationship between av cc , av ss and v cc , v ss , set av ss = v ss . if the a/d converter is not used, the avcc and avss pins must on no account be left open. if conditions 1 to 3 above are not met, the reliability of the device may be adversely affected. notes on board design: in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an0 to an7), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable digital ground (vss) on the board. notes on noise countermeasures: a protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an7) should be connected between avcc and avss as shown in figure 17.7. also, the bypass capacitors connected to avcc and the filter capacitor connected to an0 to an7 must be connected to avss. if a filter capacitor is connected as shown in figure 17.7, the input currents at the analog input pins (an0 to an7) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the current input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding the circuit constants. 500 avcc * 1 an0 to an7 avss notes: figures are reference values. 1. 2. r in : input impedance r in * 2 100 0.1 f 0.01 f 10 f figure 17.7 example of analog input protection circuit table 17.5 analog pin specifications item min max unit analog input capacitance 20 pf permissible signal source impedance 10 * k w note: * when v cc = 4.0 v to 5.5 v and ? 12 mhz 20 pf to a/d converter an0 to an7 10 k note: figures are reference values. figure 17.8 analog input pin equivalent circuit 501 a/d conversion precision definitions: h8s/2128 series and h8s/2124 series a/d conversion precision definitions are given below. resolution the number of a/d converter digital output codes offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 17.10). full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'111111111 (h'3ff) (see figure 17.10). quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 17.9). nonlinearity error the error with respect to the ideal a/d conversion characteristic between the zero voltage and the full-scale voltage. does not include the offset error, full-scale error, or quantization error. absolute precision the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error. 502 h'3ff h'3fe h'3fd h'004 h'003 h'002 h'001 h'000 1 1024 2 1024 1023 1024 1022 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage figure 17.9 a/d conversion precision definitions (1) fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 17.10 a/d conversion precision definitions (2) 503 permissible signal source impedance: h8s/2128 series and h8s/2124 series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k w (vcc = 4.0 to 5.5 v, when ? 12 mhz or cks = 0) or less. this specification is provided to enable the a/d converters sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k w (vcc = 4.0 to 5.5 v, when ? 12 mhz or cks = 0), charging may be insufficient and it may not be possible to guarantee the a/d conversion precision. however, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k w , and the signal source impedance is ignored. but since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/sec or greater). when converting a high-speed analog signal, a low-impedance buffer should be inserted. influences on absolute precision: adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd such as av ss . care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. a/d converter equivalent circuit h8s/2128 series or h8s/2124 series chip 20 pf c in = 15 pf 10 k low-pass filter c to 0.1 f sensor output impedance, up to 10 k w sensor input figure 17.11 example of analog input circuit 504 505 section 18 ram 18.1 overview the h8s/2128, h8s/2124 and h8s/2123 have 4 kbytes of on-chip high-speed static ram, and the h8s/2127, h8s/2126, h8s/2122 and h8s/2120 have 2 kbytes. the on-chip ram is connected to the bus master by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. this makes it possible to perform fast word data transfer. the on-chip ram can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr). 18.1.1 block diagram figure 18.1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffe080 h'ffe082 h'ffe084 h'ffeffe h'ffe081 h'ffe083 h'ffe085 h'ffefff h'ffff00 h'ffff7e h'ffff01 h'ffff7f figure 18.1 block diagram of ram (h8s/2128, h8s/2124, h8s/2123) 506 18.1.2 register configuration the on-chip ram is controlled by syscr. table 18.1 shows the register configuration. table 18.1 register configuration name abbreviation r/w initial value address * system control register syscr r/w h'09 h'ffc4 note: * lower 16 bits of the address. 18.2 system control register (syscr) 7 cs2e 0 r/w 6 iose 0 r/w 5 intm1 0 r 4 intm0 0 r/w 3 xrst 1 r 0 rame 1 r/w 2 nmieg 0 r/w 1 hie 0 r/w bit initial value read/write the on-chip ram is enabled or disabled by the rame bit in syscr. for details of other bits in syscr, see section 3.2.2, system control register (syscr). bit 0ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 507 18.3 operation 18.3.1 expanded mode (modes 1, 2, and 3 (expe = 1)) when the rame bit is set to 1, accesses to h8s/2128, h8s/2124, and h8s/2123 addresses h'(ff)e080 to h'(ff)efff and h'(ff)ff00 to h'(ff)ff7f, and h8s/2127, h8s/2126, h8s/2122, and h8s/2120 addresses h'(ff)e880 to h'(ff)efff and h'(ff)ff00 to h'(ff)ff7f, are directed to the on-chip ram. when the rame bit is cleared to 0, accesses to addresses h'(ff)e080 to h'(ff)efff and h'(ff)ff00 to h'(ff)ff7f, are directed to the off-chip address space. since the on-chip ram is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. each type of access is performed in one state. even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. word data must start at an even address. 18.3.2 single-chip mode (modes 2 and 3 (expe = 0)) when the rame bit is set to 1, accesses to h8s/2128, h8s/2124, and h8s/2123 addresses h'(ff)e080 to h'(ff)efff and h'(ff)ff00 to h'(ff)ff7f, and h8s/2127, h8s/2126, h8s/2122, and h8s/2120 addresses h'(ff)e880 to h'(ff)efff and h'(ff)ff00 to h'(ff)ff7f, are directed to the on-chip ram. when the rame bit is cleared to 0, the on-chip ram is not accessed. a read will always return h'ff, and writes are invalid. since the on-chip ram is connected to the bus master by a 16-bit data bus, it can be written to and read in byte or word units. each type of access is performed in one state. even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. word data must start at an even address. 508 509 section 19 rom 19.1 overview the h8s/2128 and h8s/2124 have 128 kbytes of on-chip rom (flash memory or mask rom), the h8s/2123 has 96 kbytes, the h8s/2127 and h8s/2122 have 64 kbytes and the h8s/2126 and h8s/2120 have 32 kbytes. the rom is connected to the bus master by a 16-bit data bus. the cpu accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed. the mode pins (md1 and md0) and the expe bit in mdcr can be set to enable or disable the on-chip rom. the flash memory versions of the h8s/2128 can be erased and programmed on-board as well as with a general-purpose prom programmer. 19.1.1 block diagram figure 19.1 shows a block diagram of the rom. h'000000 h'000002 h'01fffe h'000001 h'000003 h'01ffff internal data bus (upper 8 bits) internal data bus (lower 8 bits) figure 19.1 rom block diagram (h8s/2128, h8s/2124) 510 19.1.2 register configuration the h8s/2128 series and h8s/2124 series on-chip rom is controlled by the operating mode and register mdcr. the register configuration is shown in table 19.1. table 19.1 rom register register name abbreviation r/w initial value address * mode control register mdcr r/w undefined depends on the operating mode h'ffc5 note: * lower 16 bits of the address. 19.2 register descriptions 19.2.1 mode control register (mdcr) bit initial value read/write 7 expe * r/w * 6 ? 0 5 ? 0 4 ? 0 3 ? 0 0 mds0 * r 2 ? 0 1 mds1 * r note: * determined by the md1 and md0 pins. mdcr is an read-only 8-bit register used to set the h8s/2128 series or h8s/2124 series operating mode and monitor the current operating mode. the expe bit is initialized in accordance with the mode pin states by a reset and in hardware standby mode. bit 7expanded mode enable (expe): sets expanded mode. in mode 1, expe is fixed at 1 and cannot be modified. in modes 2 and 3, expe has an initial value of 0 and can be read or written. bit 7 expe description 0 single-chip mode selected 1 expanded mode selected 511 bits 6 to 2reserved: these bits cannot be modified and are always read as 0. bits 1 and 0mode select 1 and 0 (mds1, mds0): these bits indicate values that reflects the input levels of mode pins md1 and md0 (the current operating mode). bits mds1 and mds0 correspond to pins md1 and md0, respectively. these are read-only bits, and cannot be modified. when mdcr is read, the input levels of mode pins md1 and md0 are latched in these bits. 19.3 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data is accessed in one state. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address. the mode pins (md1 and md0) and the expe bit in mdcr can be set to enable or disable the on-chip rom, as shown in table 19.2. in normal mode, the maximum amount of rom that can be used is 56 kbytes. table 19.2 operating modes and rom operating mode mode pins mdcr mcu operating mode cpu operating mode description md1 md0 expe on-chip rom mode 1 normal expanded mode with on-chip rom disabled 0 1 1 disabled mode 2 advanced single-chip mode 1 0 0 enabled * advanced expanded mode with on-chip rom enabled 1 mode 3 normal single-chip mode 1 0 enabled normal expanded mode with on-chip rom enabled 1 (max. 56 kbytes) note: * 128 kbytes in the h8s/2128 and h8s/2124, 96 kbytes in the h8s/2123, 64 kbytes in the h8s/2127 and h8s/2122 and 32 kbytes in the h8s/2126 and h8s/2120. 512 19.4 overview of flash memory 19.4.1 features the features of the flash memory are summarized below. four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode programming/erase methods the flash memory is programmed 32 bytes at a time. erasing is performed by block erase (in single-block units). when erasing multiple blocks, the individual blocks must be erased sequentially. block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28- kbyte, and 32-kbyte. programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. reprogramming capability the flash memory can be reprogrammed up to 100 times. on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode automatic bit rate adjustment with data transfer in boot mode, the bit rate of the h8s/2128 series chip can be automatically adjusted to match the transfer bit rate of the host. protect modes there are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. writer mode flash memory can be programmed/erased in writer mode, using a prom programmer, as well as in on-board programming mode. 513 19.4.2 block diagram module bus bus interface/controller flash memory (128 kbytes) operating mode flmcr2 internal address bus internal data bus (16 bits) mode pins ebr1 ebr2 flmcr1 * * * * legend: flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr1: erase block register 1 ebr2: erase block register 2 note: * these registers are used only in the flash memory version. in the mask rom version, a read at any of these addresses will return an undefined value, and writes are invalid. figure 19.2 block diagram of flash memory 514 19.4.3 flash memory operating modes mode transitions: when the mode pins are set in the reset state and a reset-start is executed, the mcu enters one of the operating modes shown in figure 19.3. in user mode, flash memory can be read but not programmed or erased. flash memory can be programmed and erased in boot mode, user program mode, and writer mode. boot mode on-board programming mode user program mode user mode with on-chip rom enabled reset state writer mode res = 0 swe = 1 swe = 0 * 2 * 1 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. 1. md0 = md1 = 0, p42 = 0, p41 = p40 = 1 2. md1 = md0 = 0, p42 = p41 = p40 = 1 res = 0 res = 0 res = 0 md1 = 1 figure 19.3 flash memory mode transitions 515 on-board programming modes boot mode flash memory h8s/2128 series chip ram host programming control program sci application program (old version) programming control program new application program programming control program new application program flash memory h8s/2128 series chip ram host sci application program (old version) boot program area new application program flash memory h8s/2128 series chip ram host sci flash memory erase boot program flash memory h8s/2128 series chip program execution state ram host sci new application program boot program 1. initial state the flash memory is in the erased state when the device is shipped. the description here applies to the case where the old program version or data is being rewritten. the user should prepare the programming control program and new application program beforehand in the host. 2. sci communication check when boot mode is entered, the boot program in the h8s/2128 series chip (originally incorporated in the chip) is started, an sci communication check is carried out, and the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, entire flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram by sci communication is executed, and the new application program in the host is written into the flash memory. boot program boot program boot program area programming control program figure 19.4 boot mode 516 user program mode flash memory h8s/2128 series chip ram host programming/ erase control program sci boot program new application program flash memory h8s/2128 series chip ram host sci new application program flash memory h8s/2128 series chip ram host sci flash memory erase boot program new application program flash memory h8s/2128 series chip program execution state ram host sci boot program boot program application program (old version) new application program 1. initial state (1) the program that will transfer the programming/ erase control program to on-chip ram should be written into the flash memory by the user beforehand. (2) the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer executes the transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program transfer program transfer program figure 19.5 user program mode (example) 517 differences between boot mode and user program mode boot mode user program mode entire memory erase yes yes block erase no yes programming control program * program/program-verify erase/erase-verify program/program-verify note: * to be provided by the user, in accordance with the recommended algorithm. block configuration: the flash memory is divided into two 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. address h'00000 address h'1ffff 128 kbytes 32 kbytes 32 kbytes 8 kbytes 28 kbytes 1 kbyte 1 kbyte 1 kbyte 1 kbyte 16 kbytes 8 kbytes figure 19.6 flash memory block configuration 518 19.4.4 pin configuration the flash memory is controlled by means of the pins shown in table 19.3. table 19.3 flash memory pins pin name abbreviation i/o function reset 5(6 input reset mode 1 md1 input sets mcu operating mode mode 0 md0 input sets mcu operating mode port 42 p42 input sets mcu operating mode when md1 = md0 = 0 port 41 p41 input sets mcu operating mode when md1 = md0 = 0 port 40 p40 input sets mcu operating mode when md1 = md0 = 0 transmit data txd0 output serial transmit data output receive data rxd0 input serial receive data input 19.4.5 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 19.4. in order for these registers to be accessed, the flshe bit must be set to 1 in stcr. table 19.4 flash memory registers register name abbreviation r/w initial value address * 1 flash memory control register 1 flmcr1 * 5 r/w * 3 h'80 h'ff80 * 2 flash memory control register 2 flmcr2 * 5 r/w * 3 h'00 * 4 h'ff81 * 2 erase block register 1 ebr1 * 5 r/w * 3 h'00 * 4 h'ff82 * 2 erase block register 2 ebr2 * 5 r/w * 3 h'00 * 4 h'ff83 * 2 serial/timer control register stcr r/w h'00 h'ffc3 notes: 1. lower 16 bits of the address. 2. flash memory registers share addresses with other registers. register selection is performed by the flshe bit in the serial/timer control register (stcr). 3. in modes in which the on-chip flash memory is disabled, a read will return h'00, and writes are invalid. 4. when the swe bit in flmcr1 is not set, these registers are initialized to h'00. 5. flmcr1, flmcr2, ebr1, and ebr2 are 8-bit registers. only byte accesses are valid for these registers, the access requiring 2 states. these registers are used only in the flash memory version. in the mask rom version, a read at any of these addresses will return an undefined value, and writes are invalid. 519 19.5 register descriptions 19.5.1 flash memory control register 1 (flmcr1) bit 76543210 fwe swe ev pv e p initial value 10000000 read/write r r/w r/w r/w r/w r/w flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode is entered by setting swe to 1 and setting the corresponding bit. program mode is entered by setting swe to 1, then setting the psu bit in flmcr2, and finally setting the p bit. erase mode is entered by setting swe to 1, then setting the esu bit in flmcr2, and finally setting the e bit. flmcr1 is initialized to h'80 by a reset, and in hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch mode. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes to the ev and pv bits in flmcr1 are enabled only when swe = 1; writes to the e bit only when swe = 1, and esu = 1; and writes to the p bit only when swe = 1, and psu = 1. bit 7flash write enable bit (fwe): controls programming and erasing of on-chip flash memory. this bit cannot be modified and is always read as 1. bit 6software write enable bit (swe): enables or disables flash memory programming. swe should be set before setting bits esu, psu, ev, pv, e, p, and eb9 to eb0, and should not be cleared at the same time as these bits. bit 6 swe description 0 writes disabled (initial value) 1 writes enabled bit 5 and 4reserved: these bits cannot be modified and are always read as 0. 520 bit 3erase-verify (ev): selects erase-verify mode transition or clearing. do not set the swe, esu, psu, pv, e, or p bit at the same time. bit 3 ev description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when swe = 1 bit 2program-verify (pv): selects program-verify mode transition or clearing. do not set the swe, esu, psu, ev, e, or p bit at the same time. bit 2 pv description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when swe = 1 bit 1erase (e): selects erase mode transition or clearing. do not set the swe, esu, psu, ev, pv, or p bit at the same time. bit 1 e description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when swe = 1, and esu = 1 521 bit 0program (p): selects program mode transition or clearing. do not set the swe, psu, esu, ev, pv, or e bit at the same time. bit 0 p description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when swe = 1, and psu = 1 522 19.5.2 flash memory control register 2 (flmcr2) bit 76543210 fler esupsu initial value 00000000 read/write r r/wr/w flmcr2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode. flmcr2 is initialized to h'00 by a reset, and in hardware standby mode. the esu and psu bits are cleared to 0 in software standby mode, subactive mode, subsleep mode, and watch mode. when on-chip flash memory is disabled, a read will return h'00 and writes are invalid. bit 7flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. bit 7 fler description 0 flash memory is operating normally (initial value) flash memory program/erase protection (error protection) is disabled [clearing condition] reset, hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 19.8.3, error protection bits 6 to 2reserved: these bits cannot be modified and are always read as 0. 523 bit 1erase setup (esu): prepares for a transition to erase mode. set this bit to 1 before setting the e bit to 1 in flmcr1. do not set the swe, psu, ev, pv, e, or p bit at the same time. bit 1 esu description 0 erase setup cleared (initial value) 1 erase setup [setting condition] when swe = 1 bit 0program setup (psu): prepares for a transition to program mode. set this bit to 1 before setting the p bit to 1 in flmcr1. do not set the swe, esu, ev, pv, e, or p bit at the same time. bit 0 psu description 0 program setup cleared (initial value) 1 program setup [setting condition] when swe = 1 524 19.5.3 erase block registers 1 and 2 (ebr1, ebr2) bit 76543210 ebr1 eb9eb8 initial value 00000000 read/write r/w * r/w * bit 76543210 ebr2 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value 00000000 read/write r/w * r/w r/w r/w r/w r/w r/w r/w note: * in normal mode, these bits cannot be modified and are always read as 0. ebr1 and ebr2 are registers that specify the flash memory erase area block by block; bits 1 and 0 in ebr1 and bits 7 to 0 in ebr2 are readable/writable bits. ebr1 and ebr2 are each initialized to h'00 by a reset, in hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch mode, when the swe bit in flmcr1 is not set. when a bit in ebr1 or ebr2 is set to 1, the corresponding block can be erased. other blocks are erase- protected. set only one bit in ebr1 or ebr2 (more than one bit cannot be set). when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. the flash memory block configuration is shown in table 19.5. table 19.5 flash memory erase blocks block (size) 128-kbyte versions address eb0 (1 kb) h'(00)0000 to h'(00)03ff eb1 (1 kb) h'(00)0400 to h'(00)07ff eb2 (1 kb) h'(00)0800 to h'(00)0bff eb3 (1 kb) h'(00)0c00 to h'(00)0fff eb4 (28 kb) h'(00)1000 to h'(00)7fff eb5 (16 kb) h'(00)8000 to h'(00)bfff eb6 (8 kb) h'(00)c000 to h'(00)dfff eb7 (8 kb) h'00e000 to h'00ffff eb8 (32 kb) h'010000 to h'017fff eb9 (32 kb) h'018000 to h'01ffff 525 19.5.4 serial/timer control register (stcr) bit 76543210 iics iicx1 iicx0 iice flshe icks1 icks0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w r/w stcr is an 8-bit readable/writable register that controls register access, the iic operating mode (when the on-chip iic option is included), and on-chip flash memory (in f-ztat versions), and also selects the tcnt input clock. for details on functions not related to on-chip flash memory, see section 3.2.4, serial/timer control register (stcr), and descriptions of individual modules. if a module controlled by stcr is not used, do not write 1 to the corresponding bit. stcr is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 4i 2 c control (iics, iicx1, iicx0, iice): these bits control the operation of the i 2 c bus interface. for details, see section 16, i 2 c bus interface. bit 3flash memory control register enable (flshe): setting the flshe bit to 1 enables read/write access to the flash memory control registers. if flshe is cleared to 0, the flash memory control registers are deselected. in this case, the flash memory control register contents are retained. bit 3 flshe description 0 flash memory control registers deselected (initial value) 1 flash memory control registers selected bit 2reserved: do not write 1 to this bit. bits 1 and 0internal clock source select 1 and 0 (icks1, icks0): these bits control 8-bit timer operation. see section 12, 8-bit timers, for details. 526 19.6 on-board programming modes when pins are set to on-board programming mode, a transition is made to in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 19.6. for a diagram of the transitions to the various flash memory modes, see figure 19.3. only advanced mode setting is possible for boot mode. in the case of user program mode, user program mode is established in advanced mode or normal mode, depending on the setting of the md0 pin. in normal mode, only programming of a 56-kbyte area of flash memory is possible. table 19.6 setting on-board programming modes mode pin mode name cpu operating mode md1 md0 p42 p41 p40 boot mode advanced mode 0 0 1 * 1 * 1 * user program mode advanced mode 1 0 normal mode 1 note: * can be used as i/o ports after boot mode is initiated. 527 19.6.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the channel 0 sci to be used is set to asynchronous mode. when a reset-start is executed after the h8s/2128 series mcus pins have been set to boot mode, the boot program built into the mcu is started and the programming control program prepared in the host is serially transmitted to the mcu via the sci. in the mcu, the user program received via the sci is written into the user program area in on-chip ram. after the transfer is completed, control branches to the start address of the user program area and the user program execution state is entered (flash memory programming is performed). the transferred user program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 19.7, and the boot program mode execution procedure in figure 19.8. rxd0 txd0 sci0 h8s/2128 series chip flash memory write data reception verify data transmission host on-chip ram figure 19.7 system configuration in boot mode 528 note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot program mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate mcu measures low period of h'00 data transmitted by host mcu calculates bit rate and sets value in bit rate register after bit rate adjustment, transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, mcu transfers part of boot program to ram host transmits number of user program bytes (n), upper byte followed by lower byte mcu transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits user program sequentially in byte units mcu transmits received user program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, mcu transmits one h'aa data byte to host transmit one h'aa data byte to host, and execute programming control program transferred to on-chip ram n + 1 ? n figure 19.8 boot mode execution procedure 529 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period (1 or more bits) figure 19.9 rxd0 input signal when using automatic sci bit rate adjustment when boot mode is initiated, the h8s/2128 series mcu measures the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. the mcu calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the mcu. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the hosts transmission bit rate and the mcus system clock frequency, there will be a discrepancy between the bit rates of the host and the mcu. to ensure correct sci operation, the hosts transfer bit rate should be set to (2400, 4800, or 9600) bps. table 19.7 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the mcus bit rate is possible. the boot program should be executed within this system clock range. table 19.7 system clock frequencies for which automatic adjustment of h8s/2128 series bit rate is possible host bit rate system clock frequency for which automatic adjustment of h8s/2128 series bit rate is possible 9600 bps 8 mhz to 20 mhz 4800 bps 4 mhz to 20 mhz 2400 bps 2 mhz to 18 mhz 530 on-chip ram area divisions in boot mode: in boot mode, the 128-byte area from h'(ff)ff00 to h'(ff)ff7f is reserved for use by the boot program, as shown in figure 19.10. the area to which the programming control program is transferred is the 3968-byte area from h'(ff)e080 to h'(ff)efff. the boot program area can be used when the programming control program transferred into ram enters the execution state. a stack area should be set up as required. h'(ff)e080 h'(ff)efff programming control program area (3,968 bytes) h'(ff)ff00 h'(ff)ff7f boot program area * (128 bytes) note: * the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note that the boot program remains stored in this area after a branch is made to the programming control program. figure 19.10 ram areas in boot mode 531 notes on use of boot mode: when the chip comes out of reset in boot mode, it measures the low period of the input at the scis rxd0 pin. the reset should end with rxd0 high. after the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the rxd0 input. in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. interrupts cannot be used while the flash memory is being programmed or erased. the rxd0 and txd0 lines should be pulled up on the board. before branching to the programming control program (ram area address h'(ff)e080), the chip terminates transmit and receive operations by the on-chip sci (channel 0) (by clearing the re and te bits in scr to 0), but the adjusted bit rate remains set in brr. the transmit data output pin, txd0, goes to the high-level output state (p50ddr = 1, p50dr = 1). the contents of the cpus internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. the initial values of other on-chip registers are not changed. boot mode can be entered by making the pin settings shown in table 19.6 and executing a reset-start. when the chip detects the boot mode setting at reset release* 1 , p42, p41, and p40 can be used as i/o ports. boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the mode pin and executing reset release* 1 . boot mode can also be cleared by a wdt overflow reset. the mode pin input levels must not be changed in boot mode. if the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins ( $6 , 5' , :5 ) will change according to the change in the microcomputers operating mode* 2 . therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. notes: 1. mode pin input must satisfy the mode programming setup time (t mds = 4 states) with respect to the reset release timing. 2. ports with multiplexed address functions will output a low level as the address signal if a state in which the mode pin setting is for mode 1 is entered during a reset. in other modes, the port pins go to the high-impedance state. the bus control output signals will output a high level if a state in which the mode pin setting is for mode 1 is entered during a reset. in other modes, the port pins go to the high-impedance state. 532 19.6.2 user program mode when set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board supply of programming data, and storing a program/erase control program in part of the program area as necessary. to select user program mode, select a mode that enables the on-chip flash memory (mode 2 or 3). in this mode, on-chip supporting modules other than flash memory operate as they normally would in mode 2 and 3. the flash memory itself cannot be read while the swe bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip ram or external memory. figure 19.11 shows the procedure for executing the program/erase control program when transferred to on-chip ram. branch to flash memory application program branch to program/erase control program in ram area execute program/erase control program (flash memory rewriting) transfer program/erase control program to ram md1, md0 = 10, 11 reset-start write the transfer program (and the program/erase control program if necessary) beforehand note: the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. figure 19.11 user program mode execution procedure 533 19.7 programming/erasing flash memory in the on-board programming modes, flash memory programming and erasing is performed by software, using the cpu. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes can be made by setting the psu and esu bits in flmcr2, and the p, e, pv, and ev bits in flmcr1. the flash memory cannot be read while being programmed or erased. therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip ram or external memory. notes: 1. operation is not guaranteed if setting/resetting of the swe, ev, pv, e, and p bits in flmcr1, and the esu and psu bits in flmcr2, is executed by a program in flash memory. 2. perform programming in the erased state. do not perform additional programming on previously programmed addresses. 19.7.1 program mode follow the procedure shown in the program/program-verify flowchart in figure 19.12 to write data or programs to flash memory. performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carried out 32 bytes at a time. the wait times (x, y, z, a , b , g , e , h ) after setting/clearing individual bits in flash memory control registers 1 and 2 (flmcr1, flmcr2) and the maximum number of writes (n) are shown in table 22.12 in section 22.5, flash memory characteristics. following the elapse of (x) s or more after the swe bit is set to 1 in flash memory control register 1 (flmcr1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. the lower 8 bits of the first address written to must be h'00, h'20, h'40, h'60, h'80, h'a0, h'c0, or h'e0. thirty-two consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. set a value greater than (y + z + a + b ) s as the wdt overflow period. after this, preparation for program mode (program setup) is carried out by setting the psu bit in flmcr2, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the p bit in flmcr1. the time during which the p bit is set is the flash memory 534 programming time. make a program setting so that the time for one programming operation is within the range of (z) s. 19.7.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of a given programming time, the programming mode is exited (the p bit in flmcr1 is cleared, then the psu bit in flmcr2 is cleared at least ( a ) s later). the watchdog timer is cleared after the elapse of ( b ) s or more, and the operating mode is switched to program-verify mode by setting the pv bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of ( g ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least ( e ) s after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.12) and transferred to the reprogram data area. after 32 bytes of data have been verified, exit program- verify mode, wait for at least ( h ) s, then clear the swe bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. however, ensure that the program/program-verify sequence is not repeated more than n times on the same bits. 535 set swe bit in flmcr1 wait (x) m s n = 1 m = 0 write 32-byte data in ram reprogram data area consecutively to flash memory enable wdt set psu bit in flmcr2 wait (y) m s set p bit in flmcr1 wait (z) m s start of programming clear p bit in flmcr1 wait ( a ) m s wait ( b ) m s ng ng ng ng ok ok ok wait ( g ) m s wait ( e ) m s * 5 * 3 * 4 * 2 * 5 * 5 * 5 * 5 * 5 * 5 * 5 store 32-byte program data in program data area and reprogram data area * 4 * 1 * 5 wait ( h ) m s clear psu bit in flmcr2 disable wdt set pv bit in flmcr1 h'ff dummy write to verify address read verify data reprogram data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 end of programming program data = verify data? end of 32-byte data verification? m = 0? increment address programming failure ok clear swe bit in flmcr1 n 3 n? n ? n + 1 notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00, h'20, h'40, h'60, h'80, h'a0, h'c0, or h'e0. a 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 16-bit (word) units. 3. if a bit for which programming has been completed in the 32-byte programming loop fails the following verify phase, additional programming is performed for that bit. 4. an area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in ram. the contents of the latter are rewritten as programming progresses. 5. see section 22.5, flash memory characteristics, for the values of x, y, z, a , b , g , e , h , and n. start program data reprogram data comments reprogramming is not performed if program data and verify data match programming incomplete; reprogram ? still in erased state; no action ram program data storage area (32 bytes) reprogram data storage area (32 bytes) transfer reprogram data to reprogram data area verify data 1 0 1 1 0 1 0 1 0 0 1 1 end of programming perform programming in the erased state. do not perform additional programming on previously programmed addresses. figure 19.12 program/program-verify flowchart 536 19.7.3 erase mode flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.13. the wait times (x, y, z, a , b , g , e , h ) after setting/clearing individual bits in flash memory control registers 1 and 2 (flmcr1, flmcr2) and the maximum number of erases (n) are shown in table 22.12 in section 22.5, flash memory characteristics. to perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (ebr1 or ebr2) at least (x) s after setting the swe bit to 1 in flash memory control register 1 (flmcr1). next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. set a value greater than (y + z + a + b ) ms as the wdt overflow period. after this, preparation for erase mode (erase setup) is carried out by setting the esu bit in flmcr2, and after the elapse of (y) s or more, the operating mode is switched to erase mode by setting the e bit in flmcr1. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed (z) ms. note: with flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 19.7.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the erase time, erase mode is exited (the e bit in flmcr1 is cleared, then the esu bit in flmcr2 is cleared at least ( a ) s later), the watchdog timer is cleared after the elapse of ( b ) s or more, and the operating mode is switched to erase-verify mode by setting the ev bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of ( g ) s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least ( e ) s after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. however, ensure that the erase/erase-verify sequence is not repeated more than n times. when verification is completed, exit erase-verify mode, and wait for at least ( h ) s. if erasure has been completed on all the erase blocks, clear the swe bit in flmcr1. if there are any unerased blocks, make a 1 bit setting in ebr1 or ebr2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. 537 end of erasing start set swe bit in flmcr1 set esu bit in flmcr2 set e bit in flmcr1 wait (x) m s wait (y) m s n = 1 set ebr1, ebr2 enable wdt * 2 * 2 * 4 wait (z) ms * 2 wait ( a ) m s * 2 wait ( b ) m s * 2 wait ( g ) m s set block start address to verify address * 2 wait ( e ) m s * 2 * 3 * 2 wait ( h ) m s * 2 * 2 * 5 start of erase clear e bit in flmcr1 clear esu bit in flmcr2 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait ( h ) m s clear ev bit in flmcr1 clear swe bit in flmcr1 disable wdt halt erase * 1 verify data = all 1? last address of block? end of erasing of all erase blocks? erase failure clear swe bit in flmcr1 n 3 n? ng ng ng ng ok ok ok ok n ? n + 1 increment address notes: 1. preprogramming (setting erase block data to all 0) is not necessary. 2. see section 22.5, flash memory characteristics, for the values of x, y, z, a , b , g , e , h , and n. 3. verify data is read in 16-bit (w) units. 4. set only one bit in ebr1or ebr2. more than one bit cannot be set. 5. erasing is performed in block units. to erase a number of blocks, the individual blocks must be erased sequentially. figure 19.13 erase/erase-verify flowchart (single-block erase) 538 19.8 flash memory protection there are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.8.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control registers 1 and 2 (flmcr1, flmcr2) and erase block registers 1 and 2 (ebr1, ebr2). (see table 19.8.) table 19.8 hardware protection functions item description program erase reset/standby protection in a reset (including a wdt overflow reset) and in hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch mode, flmcr1, flmcr2, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. in a reset via the 5(6 pin, the reset state is not entered unless the 5(6 pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the 5(6 pin low for the 5(6 pulse width specified in the ac characteristics section. yes yes 539 19.8.2 software protection software protection can be implemented by setting the swe bit in flmcr1 and erase block registers 1 and 2 (ebr1, ebr2). when software protection is in effect, setting the p or e bit in flash memory control register 1 (flmcr1) does not cause a transition to program mode or erase mode. (see table 19.9.) table 19.9 software protection functions item description program erase swe bit protection clearing the swe bit to 0 in flmcr1 sets the program/erase-protected state for all blocks. (execute in on-chip ram or external memory.) yes yes block specification protection erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (ebr1, ebr2). setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. yes 19.8.3 error protection in error protection, an error is detected when mcu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the mcu malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. 540 fler bit setting conditions are as follows: when flash memory is read during programming/erasing (including a vector read or instruction fetch) immediately after exception handling (excluding a reset) during programming/erasing when a sleep instruction (transition to software standby, sleep, subactive, subsleep, or watch mode) is executed during programming/erasing when the bus is released during programming/erasing error protection is released only by a reset and in hardware standby mode. figure 19.14 shows the flash memory state transition diagram. rd vf pr er fler = 0 error occurrence * 1 res = 0 or stby = 0 res = 0 or stby = 0 rd vf pr er fler = 0 reset or standby (hardware protection) rd vf * 4 pr er fler = 1 rd vf pr er fler = 1 error protection mode error protection mode (software standby) software standby mode flmcr1, flmcr2 (except fler bit), ebr1, ebr2 initialization state * 3 flmcr1, flmcr2, ebr1, ebr2 initialization state software standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd: memory read not possible vf: verify-read not possible pr: programming not possible er: erasing not possible legend: res = 0 or stby = 0 error occurrence (software standby) * 2 normal operation mode program mode erase mode notes: 1. when an error occurs other than due to a sleep instruction, or when a sleep instruction is executed for a transition to subactive mode 2. when an error occurs due to a sleep instruction (except subactive mode) 3. except sleep mode 4. vf in subactive mode figure 19.14 flash memory state transitions 541 19.9 interrupt handling when programming/erasing flash memory all interrupts, including nmi, should be disabled when flash memory is being programmed or erased (when the p or e bit is set in flmcr1), and while the boot program is executing in boot mode* 1 , to give priority to the program or erase operation. there are three reasons for this: 1. an interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly* 2 , possibly resulting in mcu runaway. 3. if an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, in on-board programming mode alone there are conditions for disabling interrupts, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operation. all interrupt requests, including nmi, must therefore be disabled inside and outside the mcu when programming or erasing flash memory. interrupts are also disabled in the error-protection state while the p or e bit remains set in flmcr1. notes: 1. interrupt requests must be disabled inside and outside the mcu until the programming control program has completed initial programming. 2. the vector may not be read correctly in this case for the following two reasons: ? if flash memory is read while being programmed or erased (while the p or e bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). ? if the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 542 19.10 flash memory writer mode 19.10.1 prom mode setting programs and data can be written and erased in writer mode as well as in the on-board programming modes. in writer mode, the on-chip rom can be freely programmed using a prom programmer that supports hitachi microcomputer device types with 128-kbyte on-chip flash memory. flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. table 19.10 shows writer mode pin settings. table 19.10 writer mode pin settings pin names setting/external circuit connection mode pins: md1, md0 low-level input to md1, md0 67%< pin high-level input (hardware standby mode not set) 5(6 pin power-on reset circuit xtal and extal pins oscillation circuit other setting pins: p47, p42, p41, p40, p67 low-level input to p42, p67, high-level input to p47, p41, p40 543 19.10.2 socket adapters and memory map in writer mode, a socket adapter is mounted on the prom programmer to match the package concerned. ensure that the socket adapter is obtained from a writer manufacturer supporting the hitachi microcomputer device type with 128-kbyte on-chip flash memory.. figure 19.15 shows the memory map in writer mode. for pin names in writer mode, see section 1.3.2, pin functions in each operating mode. h8s/2128 h'000000 mcu mode writer mode h'01ffff h'00000 h'1ffff on-chip rom area figure 19.15 memory map in writer mode 19.10.3 writer mode operation table 19.11 shows how the different operating modes are set when using writer mode, and table 19.12 lists the commands used in writer mode. details of each mode are given below. memory read mode memory read mode supports byte reads. auto-program mode auto-program mode supports programming of 128 bytes at a time. status polling is used to confirm the end of auto-programming. auto-erase mode auto-erase mode supports automatic erasing of the entire flash memory. status polling is used to confirm the end of auto-erasing. status read mode status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the fo6 signal. in status read mode, error information is output if an error occurs. 544 table 19.11 settings for each operating mode in writer mode pin names mode &( &( 2( 2( :( :( fo0 to fo7 fa0 to fa17 read l l h data output ain output disable l h h hi-z x command write l h l data input ain * 2 chip disable * 1 h x x hi-z x legend: h: high level l: low level hi-z: high impedance x: dont care notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. ain indicates that there is also address input in auto-program mode. table 19.12 writer mode commands number 1st cycle 2nd cycle command name of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 legend: ra: read address pa: program address notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 545 19.10.4 memory read mode after the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. to read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. command writes can be performed in memory read mode, just as in the command wait state. once memory read mode has been entered, consecutive reads can be performed. after power-on, memory read mode is entered. table 19.13 ac characteristics in memory read mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s &( hold time t ceh 0ns &( setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns :( rise time t r 30 ns :( fall time t f 30 ns ce fa17 to fa0 fo7 to fo0 data oe we command write t wep t ceh t dh t ds t f t r t nxtc note: data is latched on the rising edge of we . t ces memory read mode address stable data figure 19.16 memory read mode timing waveforms after command write 546 table 19.14 ac characteristics when entering another mode from memory read mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s &( hold time t ceh 0ns &( setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns :( rise time t r 30 ns :( fall time t f 30 ns ce h'xx oe we other mode command write memory read mode t wep t ceh t dh t ds t nxtc t ces address stable data t f t r note: do not enable we and oe at the same time. fa17 to fa0 fo7 to fo0 figure 19.17 timing waveforms when entering another mode from memory read mode 547 table 19.15 ac characteristics in memory read mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes access time t acc 20 s &( output delay time t ce 150 ns 2( output delay time t oe 150 ns output disable delay time t df 100 ns data output hold time t oh 5ns ce vil vil vih oe we t acc t acc address stable address stable data data t oh t oh fa17 to fa0 fo7 to fo0 figure 19.18 timing waveforms for &( &( / 2( 2( enable state read ce vih oe we t ce t acc t oe t oh t oh t df t ce t acc t oe address stable address stable data data t df fa17 to fa0 fo7 to fo0 figure 19.19 timing waveforms for &( &( / 2( 2( clocked read 548 19.10.5 auto-program mode ac characteristics table 19.16 ac characteristics in auto-program mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s &( hold time t ceh 0ns &( setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t wsts 1ms status polling access time t spa 150 ns address setup time t as 0ns address hold time t ah 60 ns memory write time t write 1 3000 ms :( rise time t r 30 ns :( fall time t f 30 ns data ce fo6 fo7 oe we t nxtc t wsts t nxtc t ces t ds t dh t wep t as t ah t ceh address stable programming wait data transfer 1 byte to 128 bytes h'40 data fo0 to 5 = 0 t f t r t spa t write (1 to 3000 ms) programming normal end identification signal programming operation end identification signal fa17 to fa0 fo7 to fo0 figure 19.20 auto-program mode timing waveforms 549 notes on use of auto-program mode in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. the lower 8 bits of the transfer address must be h'00 or h'80. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. memory address transfer is performed in the second cycle (figure 19.20). do not perform transfer after the second cycle. do not perform a command write during a programming operation. perform one auto-programming operation for a 128-byte block for each address. characteristics are not guaranteed for two or more programming operations. confirm normal end of auto-programming by checking fo6. alternatively, status read mode can also be used for this purpose (fo7 status polling uses the auto-program operation end identification pin). the status polling fo6 and fo7 pin information is retained until the next command write. until the next command write is performed, reading is possible by enabling &( and 2( . 19.10.6 auto-erase mode ac characteristics table 19.17 ac characteristics in auto-erase mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s &( hold time t ceh 0ns &( setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t ests 1ms status polling access time t spa 150 ns memory erase time t erase 100 40000 ms :( rise time t r 30 ns :( fall time t f 30 ns 550 ce fo6 fo7 oe we t ests t nxtc t nxtc t ces t ceh t dh cl in dl in t wep fo0 to fo5 = 0 h'20 h'20 erase normal end confirmation signal t f t r t ds t spa t erase (100 to 40000 ms) erase end identification signal fa17 to fa0 fo7 to fo0 figure 19.21 auto-erase mode timing waveforms notes on use of auto-erase-program mode auto-erase mode supports only entire memory erasing. do not perform a command write during auto-erasing. confirm normal end of auto-erasing by checking fo6. alternatively, status read mode can also be used for this purpose (fo7 status polling uses the auto-erase operation end identification pin). the status polling fo6 and fo7 pin information is retained until the next command write. until the next command write is performed, reading is possible by enabling &( and 2( . 551 19.10.7 status read mode status read mode is used to identify what type of abnormal end has occurred. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. the return code is retained until a command write for other than status read mode is performed. table 19.18 ac characteristics in status read mode (conditions: v cc = 5.0 v 10%, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s &( hold time t ceh 0ns &( setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns 2( output delay time t oe 150 ns disable delay time t df 100 ns &( output delay time t ce 150 ns :( rise time t r 30 ns :( fall time t f 30 ns ce oe we t ces t nxtc t nxtc t df note: fo2 and fo3 are undefined. t ces t dh t wep t wep data t dh t oe t ce t nxtc h'71 t f t r t f t r t ceh t ds t ds h'71 t ceh fa17 to fa0 fo7 to fo0 figure 19.22 status read mode timing waveforms 552 table 19.19 status read mode return commands pin name fo7 fo6 fo5 fo4 fo3 fo2 fo1 fo0 attribute normal end identification command error programming error erase error programming or erase count exceeded effective address error initial value 00000000 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 programming error: 1 otherwise: 0 erase error: 1 otherwise: 0 count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: fo2 and fo3 are undefined. 19.10.8 status polling the fo7 status polling flag indicates the operating status in auto-program or auto-erase mode. the fo6 status polling flag indicates a normal or abnormal end in auto-program or auto- erase mode. table 19.20 status polling output truth table pin names internal operation in progress abnormal end normal end fo7 0 1 0 1 fo6 0 0 1 1 fo0 to fo5 0 0 0 0 553 19.10.9 writer mode transition time commands cannot be accepted during the oscillation stabilization period or the writer mode setup period. after the writer mode setup time, a transition is made to memory read mode. table 19.21 command wait state transition time specifications item symbol min max unit notes standby release (oscillation stabilization time) t osc1 20 ms prom mode setup time t bmv 10 ms v cc hold time t dwn 0ms v cc res memory read mode command wait state command wait state normal/ abnormal end identification auto-program mode auto-erase mode command accepted t osc1 t bmv t dwn don't care figure 19.23 oscillation stabilization time and writer mode setup and power supply fall sequence 554 19.10.10 notes on memory programming when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. when performing programming using writer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by hitachi. for other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming should be performed once only on the same address block. 555 19.11 flash memory programming and erasing precautions precautions concerning the use of on-board programming mode and writer mode are summarized below. use the specified voltages and timing for programming and erasing: applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports hitachi microcomputer device types with 128-kbyte on-chip flash memory. do not select the hn28f101 setting for the prom programmer, and only use the specified socket adapter. incorrect use will result in damaging the device. powering on and off: when applying or disconnecting v cc , fix the 5(6 pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. use the recommended algorithm when programming and erasing flash memory: the recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. when setting the p or e bit in flmcr1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. do not set or clear the swe bit during program execution in flash memory: clear the swe bit before executing a generated or reading data in flash memory. when the swe bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). do not use interrupts while flash memory is being programmed or erased: all interrupt requests, including nmi, should be disabled when programming or erasing flash memory to give priority to program/erase operations. do not perform additional programming. erase the memory before reprogramming: in on- board programming, perform only one programming operation on a 32-byte programming unit block. in prom mode, too, perform only one programming operation on a 128-byte programming unit block. programming should be carried out with the entire programming unit block erased. before programming, check that the chip is correctly mounted in the prom programmer: overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. do not touch the socket adapter or chip during programming: touching either of these can cause contact faults and write errors. 556 557 section 20 clock pulse generator 20.1 overview the h8s/2128 series and h8s/2124 series have a built-in clock pulse generator (cpg) that generates the system clock (?), the bus master clock, and internal clocks. the clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock input circuit, and waveform shaping circuit. 20.1.1 block diagram figure 20.1 shows a block diagram of the clock pulse generator. extal xtal oscillator duty adjustment circuit excl subclock input circuit waveform shaping circuit medium-speed clock divider system clock to ?pin wdt1 count clock internal clock to supporting modules bus master clock to cpu, dtc ?2 to ?32 sub bus master clock selection circuit clock selection circuit figure 20.1 block diagram of clock pulse generator 558 20.1.2 register configuration the clock pulse generator is controlled by the standby control register (sbycr) and low-power control register (lpwrcr). table 20.1 shows the register configuration. table 20.1 cpg registers name abbreviation r/w initial value address * standby control register sbycr r/w h'00 h'ff84 low-power control register lpwrcr r/w h'00 h'ff85 note: * lower 16 bits of the address. 20.2 register descriptions 20.2.1 standby control register (sbycr) bit 76543210 ssby sts2 sts1 sts0 sck2 sck1 sck0 initial value 00000000 read/write r/w r/w r/w r/w r/w r/w r/w sbycr is an 8-bit readable/writable register that performs power-down mode control. only bits 0 to 2 are described here. for a description of the other bits, see section 21.2.1, standby control register (sbycr). sbycr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 559 bits 2 to 0system clock select 2 to 0 (sck2 to sck0): these bits select the bus master clock for high-speed mode and medium-speed mode. when operating the device after a transition to subactive mode or watch mode bits sck2 to sck0 should all be cleared to 0. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is ?/2 1 0 medium-speed clock is ?/4 1 medium-speed clock is ?/8 1 0 0 medium-speed clock is ?/16 1 medium-speed clock is ?/32 1 20.2.2 low-power control register (lpwrcr) bit 76543210 dton lson nesel excle initial value 00000000 read/write r/w r/w r/w r/w lpwrcr is an 8-bit readable/writable register that performs power-down mode control. only bit 4 is described here. for a description of the other bits, see section 21.2.2, low-power control register (lpwrcr). lpwrcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 4subclock input enable (excle): controls subclock input from the excl pin. bit 4 excle description 0 subclock input from excl pin is disabled (initial value) 1 subclock input from excl pin is enabled 560 20.3 oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 20.3.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 20.2. select the damping resistance r d according to table 20.2. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22pf figure 20.2 connection of crystal resonator (example) table 20.2 damping resistance value frequency (mhz) 24810121620 r d ( w ) 1 k5002000000 crystal resonator: figure 20.3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 20.3 and the same frequency as the system clock (?). xtal c l at-cut parallel-resonance type extal c 0 lr s figure 20.3 crystal resonator equivalent circuit 561 table 20.3 crystal resonator parameters frequency (mhz) 24810121620 r s max ( w ) 500 120 80 70 60 50 40 c 0 max (pf) 7777777 note on board design: when a crystal resonator is connected, the following points should be noted. other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. see figure 20.4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. c l2 signal a signal b c l1 h8s/2128 series or h8s/2124 series chip xtal extal avoid figure 20.4 example of incorrect board design 562 20.3.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 20.5. if the xtal pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and wach mode. extal xtal external clock input open (a) xtal pin left open extal xtal external clock input (b) complementary clock input at xtal pin figure 20.5 external clock input (examples) 563 external clock: the external clock signal should have the same frequency as the system clock (?). table 20.4 and figure 20.6 show the input conditions for the external clock. table 20.4 external clock input conditions v cc = 2.7 to 5.5 v v cc = 5.0 v 10% item symbol min max min max unit test conditions external clock input low pulse width t exl 40 20 ns figure 20.6 external clock input high pulse width t exh 40 20 ns external clock rise time t exr 10 5 ns external clock fall time t exf 10 5 ns clock low pulse width t cl 0.4 0.6 0.4 0.6 t cyc ? 3 5 mhz figure 22.4 80 80 ns ? < 5 mhz clock high pulse width t ch 0.4 0.6 0.4 0.6 t cyc ? 3 5 mhz 80 80 ns ? < 5 mhz t exh t exl t exr t exf v cc 0.5 extal figure 20.6 external clock input timing 564 table 20.5 shows the external clock output settling delay time, and figure 20.7 shows the external clock output settling delay timing. the oscillator and duty adjustment circuit have a function for adjusting the waveform of the external clock input at the extal pin. when the prescribed clock signal is input at the extal pin, internal clock signal output is fixed after the elapse of the external clock output settling delay time (t dext ). as the clock signal output is not fixed during the t dext period, the reset signal should be driven low to maintain the reset state. table 20.5 external clock output settling delay time conditions: v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss = av ss = 0 v item symbol min max unit notes external clock output settling delay time t dext * 500 s figure 20.7 note: * t dext includes 5(6 pulse width (t resw ). t dext * res (internal or external) extal stby v cc 2.7v v ih note: * t dext includes res pulse width (t resw ). figure 20.7 external clock output settling delay timing 565 20.4 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (?). 20.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate ?/2, ?/4, ?/8, ?/16, and ?/32 clocks. 20.6 bus master clock selection circuit the bus master clock selection circuit selects the system clock (?) or one of the medium-speed clocks (?/2, ?/4, ?/8, ?/16, or ?/32) to be supplied to the bus master, according to the settings of bits sck2 to sck0 in sbycr. 566 20.7 subclock input circuit the subclock input circuit controls the subclock input from the excl pin. inputting the subclock: when a subclock is used, a 32.768 khz external clock should be input from the excl pin. in this case, clear bit p46ddr to 0 in p4ddr and set bit excle to 1 in lpwrcr. the subclock input conditions are shown in table 20.6 and figure 20.8. table 20.6 subclock input conditions v cc = 2.7 to 5.5 v item symbol min typ max unit test conditions subclock input low pulse width t excll 15.26 s figure 20.8 subclock input high pulse width t exclh 15.26 s subclock input rise time t exclr 10ns subclock input fall time t exclf 10ns t exclh t excll t exclr t exclf v cc 0.5 excl figure 20.8 subclock input timing when subclock is not needed: do not enable subclock input when the subclock is not needed. 20.8 subclock waveform shaping circuit to eliminate noise in the subclock input from the excl pin, this circuit samples the clock using a clock obtained by dividing the ? clock. the sampling frequency is set with the nesel bit in lpwrcr. for details, see section 21.2.2, low-power control register (lpwrcr). the clock is not sampled in subactive mode, subsleep mode, or watch mode. 567 section 21 power-down state 21.1 overview in addition to the normal program execution state, the h8s/2128 series and h8s/2124 series have a power-down state in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. the h8s/2128 series and h8s/2124 series operating modes are as follows: 1. high-speed mode 2. medium-speed mode 3. subactive mode 4. sleep mode 5. subsleep mode 6. watch mode 7. module stop mode 8. software standby mode 9. hardware standby mode of these, 2 to 9 are power-down modes. sleep mode and subsleep mode are cpu modes, medium-speed mode is a cpu and bus master mode, subactive mode is a cpu, bus master, and on-chip supporting module mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the cpu). certain combinations of these modes can be set. after a reset, the mcu is in high-speed mode and module stop mode (excluding the dtc). table 21.1 shows the internal chip states in each mode, and table 21.2 shows the conditions for transition to the various modes. figure 21.1 shows a mode transition diagram. 568 table 21.1 h8s/2128 series and h8s/2124 series internal states in each mode function high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby system clock oscillator function- ing function- ing function- ing function- ing halted halted halted halted halted subclock input function- ing function- ing function- ing function- ing function- ing function- ing function- ing halted halted cpu operation instruc- tions function- ing medium- speed halted function- ing halted subclock operation halted halted halted registers retained retained retained retained undefined external interrupts nmi function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing halted irq0 irq1 irq2 on-chip supporting module dtc function- ing medium- speed function- ing function- ing/halted (retained) halted (retained) halted (retained) halted (retained) halted (retained) halted (reset) operation wdt1 function- ing function- ing function- ing function- ing subclock operation subclock operation subclock operation halted (retained) halted (reset) wdt0 halted tmr0, 1 function- ing/halted (retained) frt (retained) halted halted tmrx, y (retained) (retained) timer connec- tion iic0 iic1 sci0 function- ing/halted halted (reset) halted (reset) halted (reset) halted (reset) sci1 (reset) pwm pwmx a/d ram function- ing function- ing function- ing (dtc) function- ing retained function- ing retained retained retained i/o function- ing function- ing function- ing function- ing retained function- ing retained retained high impedance note: halted (retained) means that internal register values are retained. the internal state is operation suspended. halted (reset) means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 569 hardware standby mode stby pin = low notes: when a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. ? from any state except hardware standby mode, a transition to the reset state occurs whenever res goes low. ? from any state, a transition to hardware standby mode occurs when stby goes low. ? when a transition is made to watch mode or subactive mode, high-speed mode must be set. sleep mode (main clock) ssby = 0, lson = 0 software standby mode ssby = 1 pss = 0, lson = 0 watch mode (subclock) ssby = 1 pss = 1, dton = 0 subsleep mode (subclock) ssby = 0 pss = 1, lson = 1 medium-speed mode (main clock) subactive mode (subclock) high-speed mode (main clock) reset state stby pin = high res pin = low res pin = high program execution state sleep instruction ssby = 1, pss = 1, dton = 1, lson = 0 clock switching exception handling after oscillation setting time (sts2 to sts0) sleep instruction ssby = 1, pss = 1, dton = 1, lson = 1 clock switching exception handling sck2 to sck0 1 0 sck2 to sck0 = 0 program-halted state sleep instruction any interrupt * 3 sleep instruction external interrupt * 4 sleep instruction interrupt * 1 , lson bit = 0 sleep instruction interrupt * 1 , lson bit = 1 interrupt * 2 sleep instruction : transition after exception handling : power-down mode * 1 nmi, irq0 to irq2, and wdt1 interrupts * 2 nmi, irq0 to irq2, and wdt0 interrupts, wdt1 interrupt, tmr0 interrupt, tmr1 interrupt * 3 all interrupts * 4 nmi, irq0 to irq2 figure 21.1 mode transitions 570 table 21.2 power-down mode transition conditions control bit states at time of transition state before transition ssby pss lson dton state after transition by sleep instruction state after return by interrupt high-speed/ medium-speed 0 * 0 * sleep high-speed/ medium-speed 0 * 1 * 100 * software standby high-speed/ medium-speed 101 * 1 1 0 0 watch high-speed 1 1 1 0 watch subactive 1101 1111subactive subactive 0 0 ** 010 * 011 * subsleep subactive 10 ** 1 1 0 0 watch high-speed 1 1 1 0 watch subactive 1 1 0 1 high-speed 1111 * : dont care : do not set. 571 21.1.1 register configuration the power-down state is controlled by the sbycr, lpwrcr, tcsr (wdt1), and mstpcr registers. table 21.3 summarizes these registers. table 21.3 power-down state registers name abbreviation r/w initial value address * standby control register sbycr r/w h'00 h'ff84 low-power control register lpwrcr r/w h'00 h'ff85 timer control/status register (wdt1) tcsr r/w h'00 h'ffea module stop control register mstpcrh r/w h'3f h'ff86 mstpcrl r/w h'ff h'ff87 note: * lower 16 bits of the address. 21.2 register descriptions 21.2.1 standby control register (sbycr) 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ? 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value read/write sbycr is an 8-bit readable/writable register that performs power-down mode control. sbycr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 572 bit 7software standby (ssby): determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a sleep instruction. the ssby setting is not changed by a mode transition due to an interrupt, etc. bit 7 ssby description 0 transition to sleep mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to subsleep mode after execution of sleep instruction in subactive mode (initial value) 1 transition to software standby mode, subactive mode, or watch mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to watch mode or high-speed mode after execution of sleep instruction in subactive mode bits 6 to 4standby timer select 2 to 0 (sts2 to sts0): these bits select the time the mcu waits for the clock to stabilize when software standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. with crystal oscillation, refer to table 21.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation settling time). with an external clock, any selection can be made. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states (initial value) 1 standby time = 16384 states 1 0 standby time = 32768 states 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 standby time = 262144 states 1 0 reserved 1 standby time = 16 states * note: * this setting must not be used in the flash memory version. bit 3reserved: this bit cannot be modified and is always read as 0. 573 bits 2 to 0system clock select (sck2 to sck0): these bits select the clock for the bus master in high-speed mode and medium-speed mode. when operating the device after a transition to subactive mode or watch mode, bits sck2 to sck0 should all be cleared to 0. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is ?/2 1 0 medium-speed clock is ?/4 1 medium-speed clock is ?/8 1 0 0 medium-speed clock is ?/16 1 medium-speed clock is ?/32 1 21.2.2 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 excle 0 r/w 3 ? 0 0 ? 0 2 ? 0 1 ? 0 bit initial value read/write lpwrcr is an 8-bit readable/writable register that performs power-down mode control. lpwrcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 574 bit 7direct-transfer on flag (dton): specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a power- down transition by executing a sleep instruction. the operating mode to which the transition is made after sleep instruction execution is determined by a combination of other control bits. bit 7 dton description 0 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (initial value) 1 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode * , or a transition is made to sleep mode or software standby mode when a sleep instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode note: * when a transition is made to watch mode or subactive mode, high-speed mode must be set. bit 6low-speed on flag (lson): determines the operating mode in combination with other control bits when making a power-down transition by executing a sleep instruction. also controls whether a transition is made to high-speed mode or to subactive mode when watch mode is cleared. bit 6 lson description 0 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode * when a sleep instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode after watch mode is cleared, a transition is made to high-speed mode (initial value) 1 when a sleep instruction is executed in high-speed mode a transition is made to watch mode or subactive mode * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode after watch mode is cleared, a transition is made to subactive mode note: * when a transition is made to watch mode or subactive mode, high-speed mode must be set. 575 bit 5noise elimination sampling frequency select (nesel): selects the frequency at which the subclock (?sub) input from the excl pin is sampled with the clock (?) generated by the system clock oscillator. when ? = 5 mhz or higher, clear this bit to 0. bit 5 nesel description 0 sampling at ? divided by 32 (initial value) 1 sampling at ? divided by 4 bit 4subclock input enable (excle): controls subclock input from the excl pin. bit 4 excle description 0 subclock input from excl pin is disabled (initial value) 1 subclock input from excl pin is enabled bits 3 to 0reserved: these bits cannot be modified and are always read as 0. 21.2.3 timer control/status register (tcsr) tcsr1 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write note: * only 0 can be written in bit 7, to clear the flag. tcsr1 is an 8-bit readable/writable register that performs selection of the wdt1 tcnt input clock, mode, etc. only bit 4 is described here. for details of the other bits, see section 14.2.2, timer control/status register (tcsr). tcsr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. 576 bit 4prescaler select (pss): selects the wdt1 tcnt input clock. this bit also controls the operation in a power-down mode transition. the operating mode to which a transition is made after execution of a sleep instruction is determined in combination with other control bits. for details, see the description of clock select 2 to 0 in section 14.2.2, timer control/status register (tcsr). bit 4 pss description 0 tcnt counts ?-based prescaler (psm) divided clock pulses when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode or software standby mode (initial value) 1 tcnt counts ?sub-based prescaler (psm) divided clock pulses when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, watch mode * , or subactive mode * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode, watch mode, or high-speed mode note: * when a transition is made to watch mode or subactive mode, high-speed mode must be set. 577 21.2.4 module stop control register (mstpcr) 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl mstpcr comprises two 8-bit readable/writable registers that perform module stop mode control. mstpcr is initialized to h'3fff by a reset and in hardware standby mode. it is not initialized in software standby mode. mstrcrh and mstpcrl bits 7 to 0module stop (mstp 15 to mstp 0): these bits specify module stop mode. see table 21.3 for the method of selecting on-chip supporting modules. mstpcrh, mstpcrl bits 7 to 0 mstp15 to mstp0 description 0 module stop mode is cleared (initial value of mstp15, mstp14) 1 module stop mode is set (initial value of mstp13 to mstp0) 578 21.3 medium-speed mode when the sck2 to sck0 bits in sbycr are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. in medium-speed mode, the cpu operates on the operating clock (?/2, ?/4, ?/8, ?/16, or ?/32) specified by the sck2 to sck0 bits. the bus master other than the cpu (the dtc) also operates in medium-speed mode. on-chip supporting modules other than the bus masters always operate on the high-speed clock (?). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if ?/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr and the lson bit in lpwrcr are cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. if a sleep instruction is executed when the ssby bit in sbycr is set to 1, and the lson bit in lpwrcr and the pss bit in tcsr (wdt1) are both cleared to 0, a transition is made to software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the 5(6 pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. the same applies in the case of a reset caused by overflow of the watchdog timer. when the 67%< pin is driven low, a transition is made to hardware standby mode. figure 21.2 shows the timing for transition to and clearance of medium-speed mode. bus master clock ? supporting module clock internal address bus internal write signal medium-speed mode sbycr sbycr figure 21.2 medium-speed mode transition and clearance timing 579 21.4 sleep mode 21.4.1 sleep mode if a sleep instruction is executed when the ssby bit in sbycr and the lson bit in lpwrcr are both cleared to 0, the cpu enters sleep mode. in sleep mode, cpu operation stops but the contents of the cpus internal registers are retained. other supporting modules do not stop. 21.4.2 clearing sleep mode sleep mode is cleared by any interrupt, or with the 5(6 pin or 67%< pin. clearing with an interrupt: when an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. sleep mode will not be cleared if interrupts are disabled, or if interrupts other than nmi have been masked by the cpu. clearing with the 5(6 5(6 pin: when the 5(6 pin is driven low, the reset state is entered. when the 5(6 pin is driven high after the prescribed reset input period, the cpu begins reset exception handling. clearing with the 67%< 67%< pin: when the 67%< pin is driven low, a transition is made to hardware standby mode. 21.5 module stop mode 21.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. table 21.4 shows mstp bits and the corresponding on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. in module stop mode, the internal states of modules other than the sci, a/d converter, 8-bit pwm module, and 14-bit pwm module, are retained. after reset release, all modules other than the dtc are in module stop mode. 580 when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. table 21.4 mstp bits and corresponding on-chip supporting modules register bit module mstpcrh mstp15 mstp14 * data transfer controller (dtc) mstp13 16-bit free-running timer (frt) mstp12 8-bit timers (tmr0, tmr1) mstp11 * 8-bit pwm timer (pwm), 14-bit pwm timer (pwmx) mstp10 * mstp9 a/d converter mstp8 8-bit timers (tmrx, tmry), timer connection mstpcrl mstp7 serial communication interface 0 (sci0) mstp6 serial communication interface 1 (sci1) mstp5 * mstp4 * i 2 c bus interface (iic) channel 0 (option) mstp3 * i 2 c bus interface (iic) channel 1 (option) mstp2 * mstp1 * mstp0 * note: bits 10, 5, 2, 1, and 0 can be read or written to, but do not affect operation. * must be set to 1 in the h8s/2124 series. 21.5.2 usage note if there is conflict between dtc module stop mode setting and a dtc bus request, the bus request has priority and the mstp bit will not be set to 1. write 1 to the mstp bit again after the dtc bus cycle. when using an h8s/2124 series mcu, the mstp bits for nonexistent modules must be set to 1. 581 21.6 software standby mode 21.6.1 software standby mode if a sleep instruction is executed when the ssby bit in sbycr is set to 1, the lson bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt1) is cleared to 0, software standby mode is entered. in this mode, the cpu, on-chip supporting modules, and oscillator all stop. however, the contents of the cpus internal registers, ram data, and the states of on-chip supporting modules other than the sci, pwm, and pwmx, and of the i/o ports, are retained. in this mode the oscillator stops, and therefore power dissipation is significantly reduced. 21.6.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pin ,54 , ,54 , or ,54 ), or by means of the 5(6 pin or 67%< pin. clearing with an interrupt: when an nmi, irq0, irq1, or irq2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits sts2 to sts0 in syscr, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. software standby mode cannot be cleared with an irq0, irq1, or irq2 interrupt if the corresponding enable bit has been cleared to 0 or has been masked by the cpu. clearing with the 5(6 5(6 pin: when the 5(6 pin is driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire chip. note that the 5(6 pin must be held low until clock oscillation stabilizes. when the 5(6 pin goes high, the cpu begins reset exception handling. clearing with the 67%< 67%< pin: when the 67%< pin is driven low, a transition is made to hardware standby mode. 582 21.6.3 setting oscillation settling time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. using a crystal oscillator: set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation settling time). table 21.5 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 21.5 oscillation settling time settings sts2 sts1 sts0 standby time 20 mhz 16 mhz 12 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 0 0 0 8192 states 0.41 0.51 0.65 0.8 1.0 1.3 2.0 4.1 ms 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2 1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2 16.4 1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4 32.8 1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 65.5 1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2 1 0 reserved s 1 16 states * 0.8 1.0 1.3 1.6 2.0 2.7 4.0 8.0 : recommended time setting * : dont care note: * this setting must not be used in the flash memory version. using an external clock: any value can be set. normally, use of the minimum time is recommended. 583 21.6.4 software standby mode application example figure 21.3 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. oscillator nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down state) oscillation settling time t osc2 nmi exception handling figure 21.3 software standby mode application example 584 21.6.5 usage note in software standby mode, i/o port states are retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. current dissipation increases while waiting for oscillation to settle. 21.7 hardware standby mode 21.7.1 hardware standby mode when the 67%< pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the 67%< pin low. do not change the state of the mode pins (md1 and md0) while the chip is in hardware standby mode. hardware standby mode is cleared by means of the 67%< pin and the 5(6 pin. when the 67%< pin is driven high while the 5(6 pin is low, the reset state is set and clock oscillation is started. ensure that the 5(6 pin is held low until the clock oscillation settles (at least 8 msthe oscillation settling timewhen using a crystal oscillator). when the 5(6 pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 585 21.7.2 hardware standby mode timing figure 21.4 shows an example of hardware standby mode timing. when the 67%< pin is driven low after the 5(6 pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the 67%< pin high, waiting for the oscillation settling time, then changing the 5(6 pin from low to high. oscillator res stby oscillation settling time reset exception handling figure 21.4 hardware standby mode timing 21.8 watch mode 21.8.1 watch mode if a sleep instruction is executed in high-speed mode or subactive mode when the ssby in sbycr is set to 1, the dton bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt1) is set to 1, the cpu makes a transition to watch mode. in this mode, the cpu and all on-chip supporting modules except wdt1 stop. as long as the prescribed voltage is supplied, the contents of some of the cpus internal registers and on-chip ram are retained, and i/o ports retain their states prior to the transition. 21.8.2 clearing watch mode watch mode is cleared by an interrupt (wovi1 interrupt, nmi pin, or pin ,54 , ,54 , or ,54 ), or by means of the 5(6 pin or 67%< pin. clearing with an interrupt: when an interrupt request signal is input, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode if the lson bit in lpwrcr is cleared to 0, or to subactive mode if the lson bit is set to 1. when making a 586 transition to high-speed mode, after the elapse of the time set in bits sts2 to sts0 in sbycr, stable clocks are supplied to the entire chip, and interrupt exception handling is started. watch mode cannot be cleared with an irq0, irq1, or irq2 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the cpu. see section 21.6.3, setting oscillation settling time after clearing software standby mode, for the oscillation settling time setting when making a transition from watch mode to high-speed mode. clearing with the 5(6 5(6 pin: see clearing with the 5(6 pin in section 21.6.2, clearing software standby mode. clearing with the 67%< 67%< pin: when the 67%< pin is driven low, a transition is made to hardware standby mode. 21.9 subsleep mode 21.9.1 subsleep mode if a sleep instruction is executed in subactive mode when the ssby in sbycr is cleared to 0, the lson bit in lpwrcr is set to 1, and the pss bit in tcsr (wdt1) is set to 1, the cpu makes a transition to subsleep mode. in this mode, the cpu and all on-chip supporting modules except tmr0, tmr1, wdt0, and wdt1 stop. as long as the prescribed voltage is supplied, the contents of some of the cpus internal registers and on-chip ram are retained, and i/o ports retain their states prior to the transition. 21.9.2 clearing subsleep mode subsleep mode is cleared by an interrupt (on-chip supporting module interrupt, nmi pin, or pin ,54 , ,54 , or ,54 ), or by means of the 5(6 pin or 67%< pin. clearing with an interrupt: when an interrupt request signal is input, subsleep mode is cleared and interrupt exception handling is started. subsleep mode cannot be cleared with an irq0 to irq2 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the cpu. clearing with the 5(6 5(6 pin: see clearing with the 5(6 pin in section 21.6.2, clearing software standby mode. 587 clearing with the 67%< 67%< pin: when the 67%< pin is driven low, a transition is made to hardware standby mode 21.10 subactive mode 21.10.1 subactive mode if a sleep instruction is executed in high-speed mode when the ssby bit in sbycr, the dton bit in lpwrcr, and the pss bit in tcsr (wdt1) are all set to 1, the cpu makes a transition to subactive mode. when an interrupt is generated in watch mode, if the lson bit in lpwrcr is set to 1, a transition is made to subactive mode. when an interrupt is generated in subsleep mode, a transition is made to subactive mode. in subactive mode, the cpu performs sequential program execution at low speed on the subclock. in this mode, all on-chip supporting modules except tmr0, tmr1, wdt0, and wdt1 stop. when operating the device in subactive mode, bits sck2 to sck0 in sbycr must all be cleared to 0. 21.10.2 clearing subactive mode subsleep mode is cleared by a sleep instruction, or by means of the 5(6 pin or 67%< pin. clearing with a sleep instruction: when a sleep instruction is executed while the ssby bit in sbycr is set to 1, the dton bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt1) is set to 1, subactive mode is cleared and a transition is made to watch mode. when a sleep instruction is executed while the ssby bit in sbycr is cleared to 0, the lson bit in lpwrcr is set to 1, and the pss bit in tcsr (wdt1) is set to 1, a transition is made to subsleep mode. when a sleep instruction is executed while the ssby bit in sbycr is set to 1, the dton bit is set to 1 and the lson bit is cleared to 0 in lpwrcr, and the pss bit in tcsr (wdt1) is set to 1, a transition is made directly to high-speed mode. fort details of direct transition, see section 21.11, direct transition. clearing with the 5(6 5(6 pin: see clearing with the 5(6 pin in section 21.6.2, clearing software standby mode. clearing with the 67%< 67%< pin: when the 67%< pin is driven low, a transition is made to hardware standby mode 588 21.11 direct transition 21.11.1 overview of direct transition there are three operating modes in which the cpu executes programs: high-speed mode, medium-speed mode, and subactive mode. a transition between high-speed mode and subactive mode without halting the program is called a direct transition. a direct transition can be carried out by setting the dton bit in lpwrcr to 1 and executing a sleep instruction. after the transition, direct transition interrupt exception handling is started. direct transition from high-speed mode to subactive mode: if a sleep instruction is executed in high-speed mode while the ssby bit in sbycr, the lson bit and dton bit in lpwrcr, and the pss bit in tscr (wdt1) are all set to 1, a transition is made to subactive mode. direct transition from subactive mode to high-speed mode: if a sleep instruction is executed in subactive mode while the ssby bit in sbycr is set to 1, the lson bit is cleared to 0 and the dton bit is set to 1 in lpwrcr, and the pss bit in tscr (wdt1) is set to 1, after the elapse of the time set in bits sts2 to sts0 in sbycr, a transition is made to directly to high-speed mode. 589 section 22 electrical characteristics 22.1 absolute maximum ratings table 22.1 lists the absolute maximum ratings. table 22.1 absolute maximum ratings C preliminary C item symbol value unit power supply voltage v cc C0.3 to +7.0 v input voltage (except ports 6, and 7) v in C0.3 to v cc +0.3 v input voltage (cin input not selected for port 6) v in C0.3 to v cc +0.3 v input voltage (cin input selected for port 6) v in lower voltage of C0.3 to v cc +0.3 and av cc +0.3 v input voltage (port 7) v in C0.3 to av cc + 0.3 v analog power supply voltage av cc C0.3 to +7.0 v analog input voltage v an C0.3 to av cc +0.3 v operating temperature t opr regular specifications: C20 to +75 c wide-range specifications: C40 to +85 c operating temperature (flash memory programming/ erasing) t opr regular specifications: 0 to +75 wide-range specifications: 0 to +85 c storage temperature t stg C55 to +125 c caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. 590 22.2 dc characteristics table 22.2 lists the dc characteristics. table 22.3 lists the permissible output currents. table 22.2 dc characteristics (1) C preliminary C conditions: v cc = 5.0 v 10%, av cc * 1 = 5.0 v 10%, v ss = av ss * 1 = 0 v, t a = C20 to +75c* 8 (regular specifications), t a = C40 to +85c* 8 (wide-range specifications) item symbol min typ max unit test conditions schmitt p67 to p60 * 2, * 5 , (1) v t C 1.0 v trigger input ,54 to ,54 * 3 v t + v cc 0.7 v voltage v t + C v t C 0.4 v input high voltage 5(6 , 67%< , nmi, md1, md0 (2) v ih v cc C 0.7 v cc +0.3 v extal v cc 0.7 v cc +0.3 v port 7 2.0 av cc +0.3 v input pins except (1) and (2) above 2.0 v cc +0.3 v input low voltage 5(6 , 67%< , md1, md0 (3) v il C0.3 0.5 v nmi, extal, input pins except (1) and (3) above C0.3 0.8 v output high voltage all output pins (except p47, and v oh v cc C 0.5 v i oh = C200 a p52 * 4 ) 3.5 v i oh = C1 ma p47, p52 * 4 2.5 v i oh = C1 ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage ports 1 to 3 1.0 v i ol = 10 ma input leakage 5(6 w i in w 10.0 a v in = 0.5 to v cc C 0.5 v current 67%< , nmi, md1, md0 1.0 a port 7 1.0 a v in = 0.5 to av cc C 0.5 v 591 table 22.2 dc characteristics (1) (cont) C preliminary C conditions: v cc = 5.0 v 10%, av cc * 1 = 5.0 v 10%, v ss = av ss * 1 = 0 v, t a = C20 to +75c* 8 (regular specifications), t a = C40 to +85c* 8 (wide-range specifications) item symbol min typ max unit test conditions three-state leakage current (off state) ports 1 to 6 w i tsi w 1.0 a v in = 0.5 to v cc C 0.5 v input pull-up mos current ports 1 to 3 Ci p 50 300 a v in = 0 v input capacitance 5(6 (4) c in 80pfv in = 0 v f = 1 mhz nmi 50 pf t a = 25c p52, p47, p24, p23 20pf input pins except (4) above 15pf current normal operation i cc 70 90 ma f = 20 mhz dissipation * 6 sleep mode 55 75 ma f = 20 mhz standby mode * 7 0.01 5.0 a t a 50c 20.0 a 50c < t a analog power during a/d conversion al cc 1.5 3.0 ma supply current idle 0.01 5.0 a av cc = 2.0 v to 5.5 v analog power supply voltage * 1 av cc 4.5 5.5 v operating 2.0 5.5 v idle/not used ram standby voltage v ram 2.0 v notes: 1. do not leave the avcc, and avss pins open even if the a/d converter is not used. even if the a/d converter is not used, apply a value in the range 2.0 v to 5.5 v to avcc by connection to the power supply (v cc ), or some other method. 2. p67 to p60 include supporting module inputs multiplexed on those pins. 3. ,54 includes the $'75* signal multiplexed on that pin. 4. in the h8s/2128 series, p52/sck0/scl0 and p47/sda0 are nmos push-pull outputs. an external pull-up resistor is necessary to provide high-level output from scl0 and sda0 (ice = 1). in the h8s/2128 series, p52/sck0 and p47 (ice = 0) high levels are driven by nmos. 5. the upper limit of the port 6 applied voltage is v cc + 0.3 v when cin input is not selected, and the lower of v cc + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 6. current dissipation values are for v ih min = v cc C 0.5 v and v il max = 0.5 v with all output pins unloaded and the on-chip pull-up moss in the off state. 7. the values are for v ram v cc < 4.5 v, v ih min = v cc 0.9, and v il max = 0.3 v. 8. for flash memory program/erase operations, the applicable range is t a = 0 to +75c (regular specifications) or t a = 0 to +85c (wide-range specifications). 592 table 22.2 dc characteristics (2) C preliminary C conditions: v cc = 4.0 v to 5.5 v* 8 , av cc * 1 = 4.0 v to 5.5 v, v ss = av ss * 1 = 0 v, t a = C20 to +75c* 8 (regular specifications), t a = C40 to +85c* 8 (wide-range specifications) item symbol min typ max unit test conditions schmitt p67 to p60 * 2, * 5 , (1) v t C 1.0 v v cc = trigger input ,54 to ,54 * 3 v t + v cc 0.7 v 4.5 v to 5.5 v voltage v t + C v t C 0.4 v v t C 0.8 v v cc < 4.5 v v t + v cc 0.7 v v t + C v t C 0.3 v input high voltage 5(6 , 67%< , nmi, md1, md0 (2) v ih v cc C 0.7 v cc +0.3 v extal v cc 0.7 v cc +0.3 v port 7 2.0 av cc +0.3 v input pins except (1) and (2) above 2.0 v cc +0.3 v input low voltage 5(6 , 67%< , md1, md0 (3) v il C0.3 0.5 v nmi, extal, input pins except (1) and (3) above C0.3 0.8 v output high all output pins v oh v cc C 0.5 v i oh = C200 a voltage (except p47, and p52 * 4 ) 3.5 v i oh = C1 ma, v cc = 4.5 v to 5.5 v 3.0 v i oh = C1 ma, v cc < 4.5 v p47, p52 * 4 2.0 v i oh = C1 ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage ports 1 to 3 1.0 v i ol = 10 ma input 5(6 w i in w 10.0 a v in = 0.5 to leakage current 67%< , nmi, md1, md0 1.0 a v cc C 0.5 v port 7 1.0 a v in = 0.5 to av cc C 0.5 v 593 table 22.2 dc characteristics (2) (cont) C preliminary C conditions: v cc = 4.0 v to 5.5 v* 8 , av cc * 1 = 4.0 v to 5.5 v, v ss = av ss * 1 = 0 v, t a = C20 to +75c* 8 (regular specifications), t a = C40 to +85c* 8 (wide-range specifications) item symbol min typ max unit test conditions three-state leakage current (off state) ports 1 to 6 w i tsi w 1.0 a v in = 0.5 to v cc C 0.5 v input pull-up mos ports 1 to 3 Ci p 50 300 a v in = 0 v, v cc = 4.5 v to 5.5 v current 30 200 a v in = 0 v, v cc < 4.5 v input capacitance 5(6 (4) c in 80pfv in = 0 v, f = 1 mhz, nmi 50 pf t a = 25c p52, p47, p24, p23 20pf input pins except (4) above 15pf current normal operation i cc 55 75 ma f = 16 mhz dissipation * 6 sleep mode 42 62 ma f = 16 mhz standby mode * 7 0.01 5.0 a t a 50c 20.0 a 50c < t a analog power during a/d conversion al cc 1.5 3.0 ma supply current idle 0.01 5.0 a av cc = 2.0 v to 5.5 v analog power supply voltage * 1 av cc 4.0 5.5 v operating 2.0 5.5 v idle/not used ram standby voltage v ram 2.0 v notes: 1. do not leave the avcc, and avss pins open even if the a/d converter is not used. even if the a/d converter is not used, apply a value in the range 2.0 v to 5.5 v to avcc by connection to the power supply (v cc ), or some other method. 2. p67 to p60 include supporting module inputs multiplexed on those pins. 3. ,54 includes the $'75* signal multiplexed on that pin. 4. in the h8s/2128 series, p52/sck0/scl0 and p47/sda0 are nmos push-pull outputs. an external pull-up resistor is necessary to provide high-level output from scl0 and sda0 (ice = 1). in the h8s/2128 series, p52/sck0 and p47 (ice = 0) high levels are driven by nmos. 5. the upper limit of the port 6 applied voltage is v cc + 0.3 v when cin input is not selected, and the lower of v cc + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 6. current dissipation values are for v ih min = v cc C 0.5 v and v il max = 0.5 v with all output pins unloaded and the on-chip pull-up moss in the off state. 7. the values are for v ram v cc < 4.0 v, v ih min = v cc 0.9, and v il max = 0.3 v. 8. for flash memory program/erase operations, the applicable ranges are v cc = 4.5 v to 5.5 v and t a = 0 to +75c (regular specifications) or t a = 0 to +85c (wide-range specifications). 594 table 22.2 dc characteristics (3) C preliminary C conditions (mask rom version): v cc = 2.7 v to 5.5 v, av cc * 1 = 2.7 v to 5.5 v, v ss = av ss * 1 = 0 v, t a = C20 to +75c (flash memory version): v cc = 3.0 v to 5.5 v, av cc * 1 = 3.0 v to 5.5 v, v ss = av ss * 1 = 0 v, t a = C20 to +75c* 8 item symbol min typ max unit test conditions schmitt p67 to p60 * 2, * 5 , (1) v t C v cc 0.2 v trigger input ,54 to ,54 * 3 v t + v cc 0.7 v voltage v t + C v t C v cc 0.05 v input high voltage 5(6 , 67%< , nmi, md1, md0 (2) v ih v cc 0.9 v cc +0.3 v extal v cc 0.7 v cc +0.3 v port 7 v cc 0.7 av cc +0.3 v input pins except (1) and (2) above v cc 0.7 v cc +0.3 v input low voltage 5(6 , 67%< , md1, md0 (3) v il C0.3 v cc 0.1 v nmi, extal, input pins except C0.3 v cc 0.2 v v cc < 4.0 v (1) and (3) above 0.8 v v cc = 4.0 v to 5.5 v output high all output pins v oh v cc C 0.5 v i oh = C200 a voltage (except p47, and p52 * 4 ) v cc C 1.0 v i oh = C1 ma (v cc < 4.0 v) p47, p52 * 4 1.0 v i oh = C1 ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage ports 1 to 3 1.0 v i ol = 5 ma (v cc < 4.0 v), i ol = 10 ma (4.0 v v cc 5.5 v) input 5(6 w i in w 10.0 a v in = 0.5 to leakage current 67%< , nmi, md1, md0 1.0 a v cc C 0.5 v port 7 1.0 a v in = 0.5 to av cc C 0.5 v 595 table 22.2 dc characteristics (3) (cont) C preliminary C conditions (mask rom version): v cc = 2.7 v to 5.5 v, av cc * 1 = 2.7 v to 5.5 v, v ss = av ss * 1 = 0 v, t a = C20 to +75c (flash memory version): v cc = 3.0 v to 5.5 v, av cc * 1 = 3.0 v to 5.5 v, v ss = av ss * 1 = 0 v, t a = C20 to +75c* 8 item symbol min typ max unit test conditions three-state leakage current (off state) ports 1 to 6 w i tsi w 1.0 a v in = 0.5 to v cc C 0.5 v input pull-up mos current ports 1 to 3 Ci p 10 150 a v in = 0 v, v cc = 2.7 v to 3.6 v input capacitance 5(6 (4) c in 80pfv in = 0 v, f = 1 mhz, nmi 50 pf ta = 25c p52, p47, p24, p23 20pf input pins except (4) above 15pf current normal operation i cc 40 52 ma f = 10 mhz dissipation * 6 sleep mode 30 42 ma f = 10 mhz standby mode * 7 0.01 5.0 a t a 50c 20.0 a 50c < t a analog power during a/d conversion al cc 1.5 3.0 ma supply current idle 0.01 5.0 a av cc = 2.0 v to 5.5 v analog power supply voltage * 1 av cc 2.7 5.5 v operating 2.0 5.5 v idle/not used ram standby voltage v ram 2.0 v notes: 1. do not leave the avcc, and avss pins open even if the a/d converter is not used. even if the a/d converter is not used, apply a value in the range 2.0 v to 5.5 v to avcc by connection to the power supply (v cc ), or some other method. 2. p67 to p60 include supporting module inputs multiplexed on those pins. 3. ,54 includes the $'75* signal multiplexed on that pin. 4. in the h8s/2128 series, p52/sck0/scl0 and p47/sda0 are nmos push-pull outputs. an external pull-up resistor is necessary to provide high-level output from scl0 and sda0 (ice = 1). in the h8s/2128 series, p52/sck0 and p47 (ice = 0) high levels are driven by nmos. 5. the upper limit of the port 6 applied voltage is v cc + 0.3 v when cin input is not selected, and the lower of v cc + 0.3 v and av cc + 0.3 v when cin input is selected. when a pin is in output mode, the output voltage is equivalent to the applied voltage. 6. current dissipation values are for v ih min = v cc C 0.5 v and v il max = 0.5 v with all output pins unloaded and the on-chip pull-up moss in the off state. 7. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v. 8. for flash memory program/erase operations, the applicable range is v cc = 3.0 v to 3.6 v and t a = 0 to +75c. 596 table 22.3 permissible output currents C preliminary C conditions:v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to +75c (regular specifications), ta = C40 to +85c (wide-range specifications) item symbol min typ max unit permissible output low current (per pin) scl1, scl0, sda1, sda0 i ol 20ma ports 1, 2, 3 10 ma other output pins 2 ma permissible output total of ports 1, 2, and 3 ? i ol 80ma low current (total) total of all output pins, including the above 120 ma permissible output high current (per pin) all output pins Ci oh 2 ma permissible output high current (total) total of all output pins ? Ci oh 40ma notes: 1. to protect chip reliability, do not exceed the output current values in table 22.3. 2. when driving a darlington pair or led, always insert a current-limiting resistor in the output line, as show in figures 22.1 and 22.2. table 22.3 permissible output currents (cont) C preliminary C conditions: v cc = 2.7 to 5.5 v, v ss = 0 v, ta = C20 to +75c item symbol min typ max unit permissible output low current (per pin) scl1, scl0, sda1, sda0 i ol 10ma ports 1, 2, 3 2 ma other output pins 1 ma permissible output total of ports 1, 2, and 3 ? i ol 40ma low current (total) total of all output pins, including the above 60ma permissible output high current (per pin) all output pins Ci oh 2 ma permissible output high current (total) total of all output pins ? Ci oh 30ma notes: 1. to protect chip reliability, do not exceed the output current values in table 22.3. 2. when driving a darlington pair or led, always insert a current-limiting resistor in the output line, as show in figures 22.1 and 22.2. 597 table 22.4 bus drive characteristics C preliminary C conditions: v cc = 2.7 to 5.5 v, v ss = 0 v, ta = C20 to +75c applicable pins: scl1, scl0, sda1, sda0 (bus drive function selected) item symbol min typ max unit test conditions schmitt trigger input voltage v t C v cc 0.3 v v cc = 2.7 v to 5.5 v v t + v cc 0.7 v cc = 2.7 v to 5.5 v v t + C v t C v cc 0.05 v cc = 2.7 v to 5.5 v input high voltage v ih v cc 0.7 v cc + 0.5 v v cc = 2.7 v to 5.5 v input low voltage v il C0.5 v cc 0.3 v cc = 2.7 v to 5.5 v output low voltage v ol 0.8 v i ol = 16 ma, v cc = 4.5 v to 5.5 v 0.5 i ol = 8 ma 0.4 i ol = 3 ma input capacitance c in 20pfv in = 0 v, f = 1 mhz, t a = 25c three-state leakage current (off state) | i tsi | 1.0 a v in = 0.5 to v cc C 0.5 v scl, sda output fall time t of 20 + 0.1cb 250 ns v cc = 2.7 v to 5.5 v 2 k w h8s/2128 series or h8s/2124 series chip port darlington pair figure 22.1 darlington pair drive circuit (example) 598 600 w h8s/2128 series or h8s/2124 series chip ports 1 to 3 led figure 22.2 led drive circuit (example) 22.3 ac characteristics figure 22.3 shows the test conditions for the ac characteristics. c chip output pin r h r l c = 30 pf: all ports r l = 2.4 k w r h = 12 k w i/o timing test levels ? low level: 0.8 v ? high level: 2.0 v 5 v figure 22.3 output load circuit 599 22.3.1 clock timing table 22.5 shows the clock timing. the clock timing specified here covers clock (?) output and clock pulse generator (crystal) and external clock input (extal pin) oscillation settling times. for details of external clock input (extal pin and excl pin) timing, see section 20, clock pulse generator. table 22.5 clock timing C preliminary C condition a:v cc = 5.0 v 10%, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b:v cc = 4.0 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c:v cc = 2.7 v to 5.5 v*, v ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz test item symbol min max min max min max unit conditions clock cycle time t cyc 50 500 62.5 500 100 500 ns figure 22.4 clock high pulse width t ch 17 20 30 ns figure 22.4 clock low pulse width t cl 17 20 30 ns clock rise time t cr 8 10 20 ns clock fall time t cf 8 10 20 ns oscillation settling time at reset (crystal) t osc1 10 10 20 ms figure 22.5 figure 22.6 oscillation settling time in software standby (crystal) t osc2 8 8 8 ms external clock output stabilization delay time t dext 500 500 500 s note: * for the low-voltage f-ztat version, v cc = 3.0 v to 5.5 v. 600 t ch t cyc t cf t cl t cr figure 22.4 system clock timing t osc1 t osc1 extal v cc stby res t dext t dext figure 22.5 oscillation settling timing nmi irqi (i = 0, 1, 2) t osc2 figure 22.6 oscillation setting timing (exiting software standby mode) 601 22.3.2 control signal timing table 22.6 shows the control signal timing. the only external interrupts that can operate on the subclock (? = 32.768 khz) are nmi and irq0, 1, and irq2. table 22.6 control signal timing C preliminary C condition a:v cc = 5.0 v 10%, v ss = 0 v, ? = 32.768 khz, 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b:v cc = 4.0 v to 5.5 v, v ss = 0 v, ? = 32.768 khz, 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c:v cc = 2.7 v to 5.5 v*, v ss = 0 v, ? = 32.768 khz, 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz test item symbol min max min max min max unit conditions 5(6 setup time t ress 200 200 300 ns figure 22.7 5(6 pulse width t resw 20 20 20 t cyc nmi setup time (nmi) t nmis 150 150 250 ns figure 22.8 nmi hold time (nmi) t nmih 10 10 10 nmi pulse width (exiting software standby mode) t nmiw 200 200 200 ns irq setup time ( ,54 to ,54 ) t irqs 150 150 250 ns irq hold time ( ,54 to ,54 ) t irqh 10 10 10 ns irq pulse width ( ,54 to ,54 ) (exiting software standby mode) t irqw 200 200 200 ns note: * for the low-voltage f-ztat version, v cc = 3.0 v to 5.5 v. 602 t resw t ress t ress res figure 22.7 reset input timing t irqs t nmis t nmih irq edge input nmi t irqs t irqh irqi (i = 2 to 0) irq level input t nmiw t irqw figure 22.8 interrupt input timing 603 22.3.3 bus timing table 22.7 shows the bus timing. operation in external expansion mode is not guaranteed when operating on the subclock (? = 32.768 khz). table 22.7 bus timing C preliminary C condition a:v cc = 5.0 v 10%, v ss = 0 v, ? = 2 mhz to maximum operating frequency,t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b:v cc = 4.0 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency,t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c:v cc = 2.7 v to 5.5 v*, v ss = 0 v, ? = 2 mhz to maximum operating frequency,t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz test item symbol min max min max min max unit conditions address delay time t ad 20 30 40 ns figure 22.9 to address setup time t as 0.5 t cyc C 15 0.5 t cyc C 20 0.5 t cyc C 30 ns figure 22.13 address hold time t ah 0.5 t cyc C 10 0.5 t cyc C 15 0.5 t cyc C 20 ns &6 delay time ( ,26 ) t csd 20 30 40 ns $6 delay time t asd 30 45 60 ns 5' delay time 1 t rsd1 30 45 60 ns 5' delay time 2 t rsd2 30 45 60 ns read data setup time t rds 15 20 35 ns read data hold time t rdh 0 0 0 ns read data access time 1 t acc1 1.0 t cyc C 30 1.0 t cyc C 40 1.0 t cyc C 60 ns read data access time 2 t acc2 1.5 t cyc C 25 1.5 t cyc C 35 1.5 t cyc C 50 ns 604 table 22.7 bus timing (cont) C preliminary C condition a:v cc = 5.0 v 10%, v ss = 0 v, ? = 2 mhz to maximum operating frequency,t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b:v cc = 4.0 v to 5.5 v, v ss = 0 v, ? = 2 mhz to maximum operating frequency,t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c:v cc = 2.7 v to 5.5 v*, v ss = 0 v, ? = 2 mhz to maximum operating frequency,t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz test item symbol min max min max min max unit conditions read data access time 3 t acc3 2.0 t cyc C 30 2.0 t cyc C 40 2.0 t cyc C 60 ns figure 22.9 to read data access time 4 t acc4 2.5 t cyc C 25 2.5 t cyc C 35 2.5 t cyc C 50 ns figure 22.13 read data access time 5 t acc5 3.0 t cyc C 30 3.0 t cyc C 40 3.0 t cyc C 60 ns :5 delay time 1 t wrd1 30 45 60 ns :5 delay time 2 t wrd2 30 45 60 ns :5 pulse width 1 t wsw1 1.0 t cyc C 20 1.0 t cyc C 30 1.0 t cyc C 40 ns :5 pulse width 2 t wsw2 1.5 t cyc C 20 1.5 t cyc C 30 1.5 t cyc C 40 ns write data delay time t wdd 30 45 60 ns write data setup time t wds 0 0 0 ns write data hold time t wdh 10 15 20 ns :$,7 setup time t wts 30 45 60 ns :$,7 hold time t wth 5 5 10 ns note: * for the low-voltage f-ztat version, v cc = 3.0 v to 5.5 v. 605 t rsd2 t 1 t ad as * a15 to a0, ios * note: * as and ios are the same pin. the function is selected by the iose bit in syscr. t asd rd (read) t csd t 2 t as t as t as t asd t acc2 t rsd1 t acc3 t rds t rdh t wrd2 t wrd2 t wdd t wsw1 t wdh d7 to d0 (read) wr (write) d7 to d0 (write) t ah t ah figure 22.9 basic bus timing (two-state access) 606 t rsd2 t 2 as * a15 to a0, ios * t asd rd (read) t 3 t as t as t ah t ah t asd t acc4 t rsd1 t acc5 t rds t rdh t wrd1 t wrd2 t wds t wsw2 t wdh d7 to d0 (read) wr (write) d7 to d0 (write) t 1 t wdd t ad t csd note: * as and ios are the same pin. the function is selected by the iose bit in syscr. figure 22.10 basic bus timing (three-state access) 607 t w as * a15 to a0, ios * rd (read) t 3 d7 to d0 (read) wr (write) d7 to d0 (write) t 2 t wts t 1 t wth t wts t wth wait note: * as and ios are the same pin. the function is selected by the iose bit in syscr. figure 22.11 basic bus timing (three-state access with one wait state) 608 t rsd2 t 1 as * a15 to a0, ios * t 2 t ah t acc3 t rds d7 to d0 (read) t 2 or t 3 t as t 1 t asd t asd t rdh t ad rd (read) note: * as and ios are the same pin. the function is selected by the iose bit in syscr. figure 22.12 burst rom access timing (two-state access) 609 t rsd2 t 1 as * a15 to a0, ios * t 1 t acc1 d7 to d0 (read) t 2 or t 3 t rdh t ad rd (read) t rds note: * as and ios are the same pin. the function is selected by the iose bit in syscr. figure 22.13 burst rom access timing (one-state access) 610 22.3.4 timing of on-chip supporting modules tables 22.8 and 22.9 show the on-chip supporting module timing. the only on-chip supporting modules that can operate in subclock operation (? = 32.768 khz) are the i/o ports, external interrupts (nmi and irq0, 1, and irq2), the watchdog timer, and the 8-bit timer (channels 0 and 1). table 22.8 timing of on-chip supporting modules C preliminary C condition a:v cc = 5.0 v 10%, v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b:v cc = 4.0 v to 5.5 v, v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c:v cc = 2.7 v to 5.5 v* 2 , v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz test item symbol min max min max min max unit conditions i/o ports output data delay time t pwd 50 50 100 ns figure 22.14 input data setup time t prs 30 30 50 input data hold time t prh 30 30 50 frt timer output delay time t ftod 50 50 100 ns figure 22.15 timer input setup time t ftis 30 30 50 timer clock input setup time t ftcs 30 30 50 figure 22.16 timer clock single edge t ftcwh 1.5 1.5 1.5 t cyc pulse width both edges t ftcwl 2.5 2.5 2.5 611 table 22.8 timing of on-chip supporting modules (cont) C preliminary C condition a:v cc = 5.0 v 10%, v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b:v cc = 4.0 v to 5.5 v, v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c:v cc = 2.7 v to 5.5 v* 2 , v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz test item symbol min max min max min max unit conditions tmr timer output delay time t tmod 50 50 100 ns figure 22.17 timer reset input setup time t tmrs 30 30 50 figure 22.19 timer clock input setup time t tmcs 30 30 50 figure 22.18 timer clock single edge t tmcwh 1.5 1.5 1.5 t cyc pulse width both edges t tmcwl 2.5 2.5 2.5 pwm, pwmx pulse output delay time t pwod 50 50 100 ns figure 22.20 sci input clock asynchro- nous t scyc 4 4 4 t cyc figure 22.21 cycle synchro- nous 6 6 6 input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr 1.5 1.5 1.5 t cyc input clock fall time t sckf 1.5 1.5 1.5 612 table 22.8 timing of on-chip supporting modules (cont) C preliminary C condition a:v cc = 5.0 v 10%, v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b:v cc = 4.0 v to 5.5 v, v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c:v cc = 2.7 v to 5.5 v* 2 , v ss = 0 v, ? = 32.768 khz* 1 , 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz test item symbol min max min max min max unit conditions sci transmit data delay time (synchronous) t txd 50 50 100 ns figure 22.22 receive data setup time (synchronous) t rxs 50 50 100 ns receive data hold time (synchronous) t rxh 50 50 100 ns a/d converter trigger input setup time t trgs 30 30 50 ns figure 22.23 notes: 1. only supporting modules that can be used in subclock operation 2. for the low-voltage f-ztat version, v cc = 3.0 v to 5.5 v 613 ports 1 to 7 (read) t 2 t 1 t pwd t prh t prs ports 1 to 6 (write) figure 22.14 i/o port input/output timing t ftis t ftod ftoa, ftob ftia, ftib, ftic, ftid figure 22.15 frt input/output timing t ftcs ftci t ftcwh t ftcwl figure 22.16 frt clock input timing 614 tmo0, tmo1 tmox t tmod figure 22.17 8-bit timer output timing tmci0, tmci1 tmix, tmiy t tmcs t tmcs t tmcwh t tmcwl figure 22.18 8-bit timer clock input timing tmri0, tmri1 tmix, tmiy t tmrs figure 22.19 8-bit timer reset input timing pw15 to pw0, pwx1, pwx0 t pwod figure 22.20 pwm, pwmx output timing 615 sck0, sck1 t sckw t sckr t sckf t scyc figure 22.21 sck clock input timing txd0, txd1 (transmit data) rxd0, rxd1 (receive data) sck0, sck1 t rxs t rxh t txd figure 22.22 sci input/output timing (synchronous mode) adtrg t trgs figure 22.23 a/d converter external trigger input timing 616 table 22.9 i 2 c bus timing C preliminary C conditions:v cc = 2.7 v to 5.5 v, v ss = 0 v, ? = 5 mhz to maximum operating frequency, t a = C20 to +75c item symbol min typ max unit test conditions notes scl clock cycle time t scl 12 t cyc figure 22.24 scl clock high pulse width t sclh 3 t cyc scl clock low pulse width t scll 5 t cyc scl, sda input rise time t sr 7.5 * t cyc scl, sda input fall time t sf 300 ns scl, sda input spike pulse elimination time t sp 1t cyc sda input bus free time t buf 5 t cyc start condition input hold time t stah 3 t cyc retransmission start condition input setup time t stas 3 t cyc stop condition input setup time t stos 3 t cyc data input setup time t sdas 0.5 t cyc data input hold time t sdah 0 ns scl, sda capacitive load c b 400 pf note: * 17.5t cyc can be set according to the clock selected for use by the i 2 c module. for details, see section 16.4, usage notes. 617 sda0, sda1 v il v ih t buf p * p * s * t stah t sclh t sr t scll t scl t sf t sdah sr * t sdas t stas t sp t stos note: * s, p, and sr indicate the following conditions. s: p: sr: start condition stop condition retransmission start condition scl0, scl1 figure 22.24 i 2 c bus interface input/output timing (option) 618 22.4 a/d conversion characteristics tables 22.10 and 22.11 list the a/d conversion characteristics. table 22.10 a/d conversion characteristics (an7 to an0 input: 134/266-state conversion) C preliminary C condition a: v cc = 5.0 v 10%, av cc = 5.0 v 10% v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c: v cc = 2.7 v to 5.5 v* 5 , av cc = 2.7 v to 5.5 v* 5 v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time 6.7 8.4 13.4 s analog input capacitance 20 20 20 pf permissible signal- source 10 * 3 10 * 3 10 * 1 k w impedance 5 * 4 5 * 4 5 * 2 nonlinearity error 3.0 3.0 7.0 lsb offset error 3.5 3.5 7.5 lsb full-scale error 3.5 3.5 7.5 lsb quantization error 0.5 0.5 0.5 lsb absolute accuracy 4.0 4.0 8.0 lsb notes: 1. when 4.0 v av cc 5.5 v 2. when 2.7 v av cc < 4.0 v 3. when conversion time 3 11. 17 s (cks = 1 and ? 12 mhz, or cks = 0) 4. when conversion time < 11. 17 s (cks = 1 and ? > 12 mhz) 5. for the low-voltage f-ztat version, v cc = 3.0 v to 5.5 v and av cc = 3.0 v to 5.5 v. 619 table 22.11 a/d conversion characteristics (cin7 to cin0 input: 134/266-state conversion) C preliminary C condition a: v cc = 5.0 v 10%, av cc = 5.0 v 10% v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition b: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c (regular specifications), t a = C40 to +85c (wide-range specifications) condition c: v cc = 2.7 v to 5.5 v* 5 , av cc = 2.7 v to 5.5 v* 5 v ss = av ss = 0 v, ? = 2 mhz to maximum operating frequency, t a = C20 to +75c condition a condition b condition c 20 mhz 16 mhz 10 mhz item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time 6.7 8.4 13.4 s analog input capacitance 20 20 20 pf permissible signal- source 10 * 3 10 * 3 10 * 1 k w impedance 5 * 4 5 * 4 5 * 2 nonlinearity error 5.0 5.0 11.0 lsb offset error 5.5 5.5 11.5 lsb full-scale error 5.5 5.5 11.5 lsb quantization error 0.5 0.5 0.5 lsb absolute accuracy 6.0 6.0 12.0 lsb notes: 1. when 4.0 v av cc 5.5 v 2. when 2.7 v av cc < 4.0 v 3. when conversion time 3 11. 17 s (cks = 1 and ? 12 mhz, or cks = 0) 4. when conversion time < 11. 17 s (cks = 1 and ? > 12 mhz) 5. for the low-voltage f-ztat version, v cc = 3.0 v to 5.5 v and av cc = 3.0 v to 5.5 v. 620 22.5 flash memory characteristics table 22.12 shows the flash memory characteristics. table 22.12 flash memory characteristics conditions (5 v version): v cc = 5.0 v 10%, v ss = 0 v, t a = 0 to +75c (regular specifications),t a = 0 to +85c (wide-range specifications) conditions for low-voltage version: v cc = 3.0 v to 3.6 v, v ss = 0 v, t a = 0 to +75c (programming/erasing operating temperature) item symbol min typ max unit test condition programming time * 1, * 2, * 4 tp 10 200 ms/ 32 bytes erase time * 1, * 3, * 5 te 100 1200 ms/ block reprogramming count n wec 100 times programming wait time after swe-bit setting * 1 x10s wait time after psu-bit setting * 1 y50s wait time after p-bit setting * 1, * 4 z 150 200 s wait time after p-bit clear * 1 a 10 s wait time after psu-bit clear * 1 b 10 s wait time after pv-bit setting * 1 g 4s wait time after dummy write * 1 e 2s wait time after pv-bit clear * 1 h 4s maximum programming count * 1, * 4, * 5 n 1000 times tp = 200 s 621 table 22.12 flash memory characteristics (cont) conditions (5 v version): v cc = 5.0 v 10%, v ss = 0 v, t a = 0 to +75c (regular specifications),t a = 0 to +85c (wide-range specifications) conditions for low-voltage version: v cc = 3.0 v to 3.6 v, v ss = 0 v, t a = 0 to +75c (programming/erasing operating temperature) item symbol min typ max unit test condition erase wait time after swe-bit setting * 1 x10s wait time after esu-bit setting * 1 y 200 s wait time after e-bit setting * 1, * 6 z510ms wait time after e-bit clear * 1 a 10 s wait time after esu-bit clear * 1 b 10 s wait time after ev-bit setting * 1 g 20 s wait time after dummy write * 1 e 2s wait time after ev-bit clear * 1 h 5s maximum erase count * 1, * 6, * 7 n 120 times te = 10 ms notes: 1. set the times according to the program/erase algorithms. 2. programming time per 32 bytes (shows the total period for which the p-bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time.) 4. maximum programming time (tp (max) = wait time after p-bit setting (z) maximum programming count (n)) 5. number of times when the wait time after p-bit setting (z) = 200 s. the number of writes should be set according to the actual set value of z to allow programming within the maximum programming time (tp). 6. maximum erase time (te (max) = wait time after e-bit setting (z) maximum erase count (n)) 7. number of times when the wait time after e-bit setting (z) = 10 ms. the number of erases should be set according to the actual set value of z to allow erasing within the maximum erase time (te). 622 22.6 usage note the f-ztat and mask rom versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. however, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, on-chip rom, layout patterns, etc. when system evaluation testing is carried out using the f-ztat version, the same evaluation tests should also be conducted for the mask rom version when changing over to that version. 623 appendix a instruction set a.1 instruction operation notation rd general register (destination) * 1 rs general register (source) * 1 rn general register * 1 ern general register (32-bit register) mac multiply-and-accumulate register (32-bit register) * 2 (ead) destination operand (eas) source operand exr extend register ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication division logical and logical or ? exclusive logical or ? transfer from left-hand operand to right-hand operand, or transition from left- hand state to right-hand state ? not (logical complement) ( ) < > operand contents :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length notes: 1. general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). 2. mac instructions cannot be used in the h8s/2128 series and h8s/2124 series. 624 condition code notation symbol meaning changes according operation result. * indeterminate (value not guaranteed). 0 always cleared to 0. 1 always set to 1. not affected by operation result. 625 table a.1 instruction set 1. data transfer instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc mov mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa:16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 #xx:8 ? rd8 rs8 ? rd8 @ers ? rd8 @(d:16,ers) ? rd8 @(d:32,ers) ? rd8 @ers ? rd8,ers32+1 ? ers32 @aa:8 ? rd8 @aa:16 ? rd8 @aa:32 ? rd8 rs8 ? @erd rs8 ? @(d:16,erd) rs8 ? @(d:32,erd) erd32-1 ? erd32,rs8 ? @erd rs8 ? @aa:8 rs8 ? @aa:16 rs8 ? @aa:32 #xx:16 ? rd16 rs16 ? rd16 @ers ? rd16 @(d:16,ers) ? rd16 @(d:32,ers) ? rd16 @ers ? rd16,ers32+2 ? ers32 @aa:16 ? rd16 @aa:32 ? rd16 rs16 ? @erd rs16 ? @(d:16,erd) rs16 ? @(d:32,erd) erd32-2 ? erd32,rs16 ? @erd rs16 ? @aa:16 rs16 ? @aa:32 b b b b b b b b b b b b b b b b w w w w w w w w w w w w w w 2 4 2 2 2 2 2 2 4 8 4 8 4 8 4 8 2 2 2 2 2 4 6 2 4 6 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 3 5 3 3 4 2 3 5 3 3 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced size 626 table a.1 instruction set (cont) 1. data transfer instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc mov pop push ldm stm movfpe movtpe mov.l #xx:32,erd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16,erd mov.l @aa:32,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 pop.w rn pop.l ern push.w rn push.l ern ldm @sp+,(erm-ern) stm (erm-ern),@-sp movfpe @aa:16,rd movtpe rs,@aa:16 #xx:32 ? rd32 ers32 ? erd32 @ers ? erd32 @(d:16,ers) ? erd32 @(d:32,ers) ? erd32 @ers ? erd32,ers32+4 ? ers32 @aa:16 ? erd32 @aa:32 ? erd32 ers32 ? @erd ers32 ? @(d:16,erd) ers32 ? @(d:32,erd) erd32-4 ? erd32,ers32 ? @erd ers32 ? @aa:16 ers32 ? @aa:32 @sp ? rn16,sp+2 ? sp @sp ? ern32,sp+4 ? sp sp-2 ? sp,rn16 ? @sp sp-4 ? sp,ern32 ? @sp (@sp ? ern32,sp+4 ? sp) repeated for each restored register. (sp-4 ? sp,ern32 ? @sp) repeated for each saved register. l l l l l l l l l l l l l l w l w l l l 6 2 4 4 6 10 6 10 4 4 6 8 6 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 1 4 5 7 5 5 6 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] 7/9/11 [1] [2] [2] 2 4 2 4 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced size cannot be used with the h8s/2128 series and h8s/2124 series. ? ? 627 table a.1 instruction set (cont) 2. arithmetic instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc add addx adds inc daa sub subx subs dec add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd addx #xx:8,rd addx rs,rd adds #1,erd adds #2,erd adds #4,erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd daa rd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subx #xx:8,rd subx rs,rd subs #1,erd subs #2,erd subs #4,erd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd rd8+#xx:8 ? rd8 rd8+rs8 ? rd8 rd16+#xx:16 ? rd16 rd16+rs16 ? rd16 erd32+#xx:32 ? erd32 erd32+ers32 ? erd32 rd8+#xx:8+c ? rd8 rd8+rs8+c ? rd8 erd32+1 ? erd32 erd32+2 ? erd32 erd32+4 ? erd32 rd8+1 ? rd8 rd16+1 ? rd16 rd16+2 ? rd16 erd32+1 ? erd32 erd32+2 ? erd32 rd8 decimal adjust ? rd8 rd8-rs8 ? rd8 rd16-#xx:16 ? rd16 rd16-rs16 ? rd16 erd32-#xx:32 ? erd32 erd32-ers32 ? erd32 rd8-#xx:8-c ? rd8 rd8-rs8-c ? rd8 erd32-1 ? erd32 erd32-2 ? erd32 erd32-4 ? erd32 rd8-1 ? rd8 rd16-1 ? rd16 rd16-2 ? rd16 erd32-1 ? erd32 erd32-2 ? erd32 b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w l l 2 4 6 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 2 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 3 1 1 1 1 1 1 1 1 1 1 1 ? ? ? * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? [3] [3] [4] [4] ? ? ? ? ? ? ? ? * [3] [3] [4] [4] ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced ? ? ? ? ? [5] [5] ? ? ? [5] [5] ? ? size 628 table a.1 instruction set (cont) 2. arithmetic instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc das mulxu mulxs divxu divxs cmp neg extu exts tas das rd mulxu.b rs,rd mulxu.w rs,erd mulxs.b rs,rd mulxs.w rs,erd divxu.b rs,rd divxu.w rs,erd divxs.b rs,rd divxs.w rs,erd cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd tas @erd rd8 decimal adjust ? rd8 rd8 rs8 ? rd16 (unsigned multiplication) rd16 rs16 ? erd32 (unsigned multiplication) rd8 rs8 ? rd16 (signed multiplication) rd16 rs16 ? erd32 (signed multiplication) rd16 rs8 ? rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32 rs16 ? erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 ? rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 ? erd32 (ed: remainder, rd: quotient) (signed division) rd8-#xx:8 rd8-rs8 rd16-#xx:16 rd16-rs16 erd32-#xx:32 erd32-ers32 0-rd8 ? rd8 0-rd16 ? rd16 0-erd32 ? erd32 0 ? ( 629 table a.1 instruction set (cont) 2. arithmetic instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc mac clrmac ldmac stmac mac @ern+,@erm+ clrmac ldmac ers,mach ldmac ers,macl stmac mach,erd stmac macl,erd cannot be used with the h8s/2128 series and h8s/2124 series. [2] operation condition code no. of states * 1 normal advanced size 630 table a.1 instruction set (cont) 3. logic instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc and or xor not and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd not.b rd not.w rd not.l erd rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd16 #xx:16 ? rd16 rd16 rs16 ? rd16 erd32 #xx:32 ? erd32 erd32 ers32 ? erd32 rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd16 #xx:16 ? rd16 rd16 rs16 ? rd16 erd32 #xx:32 ? erd32 erd32 ers32 ? erd32 rd8 ? #xx:8 ? rd8 rd8 ? rs8 ? rd8 rd16 ? #xx:16 ? rd16 rd16 ? rs16 ? rd16 erd32 ? #xx:32 ? erd32 erd32 ? ers32 ? erd32 ?rd8 ? rd8 ?rd16 ? rd16 ?erd32 ? erd32 b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced size 631 table a.1 instruction set (cont) 4. shift instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc shal shar shll shlr rotxl shal.b rd shal.b #2,rd shal.w rd shal.w #2,rd shal.l erd shal.l #2,erd shar.b rd shar.b #2,rd shar.w rd shar.w #2,rd shar.l erd shar.l #2,erd shll.b rd shll.b #2,rd shll.w rd shll.w #2,rd shll.l erd shll.l #2,erd shlr.b rd shlr.b #2,rd shlr.w rd shlr.w #2,rd shlr.l erd shlr.l #2,erd rotxl.b rd rotxl.b #2,rd rotxl.w rd rotxl.w #2,rd rotxl.l erd rotxl.l #2,erd b b w w l l b b w w l l b b w w l l b b w w l l b b w w l l 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced size c msb lsb 0 c 0 msb lsb 0 c msb lsb c msb lsb c msb lsb 632 table a.1 instruction set (cont) 4. shift instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc rotxr rotl rotr rotxr.b rd rotxr.b #2,rd rotxr.w rd rotxr.w #2,rd rotxr.l erd rotxr.l #2,erd rotl.b rd rotl.b #2,rd rotl.w rd rotl.w #2,rd rotl.l erd rotl.l #2,erd rotr.b rd rotr.b #2,rd rotr.w rd rotr.w #2,rd rotr.l erd rotr.l #2,erd b b w w l l b b w w l l b b w w l l 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced size c msb lsb c msb lsb c msb lsb 633 table a.1 instruction set (cont) 5. bit manipulation instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc bset bclr bnot bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 (#xx:3 of rd8) ? 1 (#xx:3 of @erd) ? 1 (#xx:3 of @aa:8) ? 1 (#xx:3 of @aa:16) ? 1 (#xx:3 of @aa:32) ? 1 (rn8 of rd8) ? 1 (rn8 of @erd) ? 1 (rn8 of @aa:8) ? 1 (rn8 of @aa:16) ? 1 (rn8 of @aa:32) ? 1 (#xx:3 of rd8) ? 0 (#xx:3 of @erd) ? 0 (#xx:3 of @aa:8) ? 0 (#xx:3 of @aa:16) ? 0 (#xx:3 of @aa:32) ? 0 (rn8 of rd8) ? 0 (rn8 of @erd) ? 0 (rn8 of @aa:8) ? 0 (rn8 of @aa:16) ? 0 (rn8 of @aa:32) ? 0 (#xx:3 of rd8) ? [?(#xx:3 of rd8)] (#xx:3 of @erd) ? [?(#xx:3 of @erd)] (#xx:3 of @aa:8) ? [?(#xx:3 of @aa:8)] (#xx:3 of @aa:16) ? [?(#xx:3 of @aa:16)] (#xx:3 of @aa:32) ? [?(#xx:3 of @aa:32)] (rn8 of rd8) ? [?(rn8 of rd8)] (rn8 of @erd) ? [?(rn8 of @erd)] (rn8 of @aa:8) ? [?(rn8 of @aa:8)] (rn8 of @aa:16) ? [?(rn8 of @aa:16)] (rn8 of @aa:32) ? [?(rn8 of @aa:32)] b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 4 4 4 4 4 4 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size 634 table a.1 instruction set (cont) 5. bit manipulation instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc btst bld bild bst bist btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 ?(#xx:3 of rd8) ? z ?(#xx:3 of @erd) ? z ?(#xx:3 of @aa:8) ? z ?(#xx:3 of @aa:16) ? z ?(#xx:3 of @aa:32) ? z ?(rn8 of rd8) ? z ?(rn8 of @erd) ? z ?(rn8 of @aa:8) ? z ?(rn8 of @aa:16) ? z ?(rn8 of @aa:32) ? z (#xx:3 of rd8) ? c (#xx:3 of @erd) ? c (#xx:3 of @aa:8) ? c (#xx:3 of @aa:16) ? c (#xx:3 of @aa:32) ? c ?(#xx:3 of rd8) ? c ?(#xx:3 of @erd) ? c ?(#xx:3 of @aa:8) ? c ?(#xx:3 of @aa:16) ? c ?(#xx:3 of @aa:32) ? c c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c ? (#xx:3 of @aa:16) c ? (#xx:3 of @aa:32) ?c ? (#xx:3 of rd8) ?c ? (#xx:3 of @erd) ?c ? (#xx:3 of @aa:8) ?c ? (#xx:3 of @aa:16) ?c ? (#xx:3 of @aa:32) b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 4 4 4 4 4 4 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 4 4 5 6 1 4 4 5 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size 635 table a.1 instruction set (cont) 5. bit manipulation instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc band biand bor bior bxor bixor band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 c (#xx:3 of rd8) ? c c (#xx:3 of @erd) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of @aa:16) ? c c (#xx:3 of @aa:32) ? c c [?(#xx:3 of rd8)] ? c c [?(#xx:3 of @erd)] ? c c [?(#xx:3 of @aa:8)] ? c c [?(#xx:3 of @aa:16)] ? c c [?(#xx:3 of @aa:32)] ? c c (#xx:3 of rd8) ? c c (#xx:3 of @erd) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of @aa:16) ? c c (#xx:3 of @aa:32) ? c c [?(#xx:3 of rd8)] ? c c [?(#xx:3 of @erd)] ? c c [?(#xx:3 of @aa:8)] ? c c [?(#xx:3 of @aa:16)] ? c c [?(#xx:3 of @aa:32)] ? c c ? (#xx:3 of rd8) ? c c ? (#xx:3 of @erd) ? c c ? (#xx:3 of @aa:8) ? c c ? (#xx:3 of @aa:16) ? c c ? (#xx:3 of @aa:32) ? c c ? [?(#xx:3 of rd8)] ? c c ? [?(#xx:3 of @erd)] ? c c ? [?(#xx:3 of @aa:8)] ? c c ? [?(#xx:3 of @aa:16)] ? c c ? [?(#xx:3 of @aa:32)] ? c b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 4 4 4 4 4 4 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 4 6 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size 636 table a.1 instruction set (cont) 6. branch instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc bcc bra d:8(bt d:8) bra d:16(bt d:16) brn d:8(bf d:8) brn d:16(bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8(bhs d:8) bcc d:16(bhs d:16) bcs d:8(blo d:8) bcs d:16(blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 if condition is true then pc ? pc+d else next; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size always never c z=0 c z=1 c=0 c=1 z=0 z=1 v=0 v=1 n=0 n=1 n ? v=0 n ? v=1 z (n ? v)=0 z (n ? v)=1 branch condition 637 table a.1 instruction set (cont) 6. branch instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc jmp bsr jsr rts jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts pc ? ern pc ? aa:24 pc ? @aa:8 pc ? @-sp,pc ? pc+d:8 pc ? @-sp,pc ? pc+d:16 pc ? @-sp,pc ? ern pc ? @-sp,pc ? aa:24 pc ? @-sp,pc ? @aa:8 pc ? @sp+ ? ? ? ? ? ? ? ? 2 2 4 4 ? ? ? ? ? ? ? ? 2 3 2 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size 4 3 4 3 4 4 4 5 4 5 4 5 6 5 638 table a.1 instruction set (cont) 7. system control instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc trapa rte sleep ldc trapa #xx:2 rte sleep ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr ldc @aa:32,ccr ldc @aa:32,exr pc ? @-sp,ccr ? @-sp, exr ? @-sp, 639 table a.1 instruction set (cont) 7. system control instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc stc andc orc xorc nop stc ccr,rd stc exr,rd stc ccr,@erd stc exr,@erd stc ccr,@(d:16,erd) stc exr,@(d:16,erd) stc ccr,@(d:32,erd) stc exr,@(d:32,erd) stc ccr,@-erd stc exr,@-erd stc ccr,@aa:16 stc exr,@aa:16 stc ccr,@aa:32 stc exr,@aa:32 andc #xx:8,ccr andc #xx:8,exr orc #xx:8,ccr orc #xx:8,exr xorc #xx:8,ccr xorc #xx:8,exr nop ccr ? rd8 exr ? rd8 ccr ? @erd exr ? @erd ccr ? @(d:16,erd) exr ? @(d:16,erd) ccr ? @(d:32,erd) exr ? @(d:32,erd) erd32-2 ? erd32,ccr ? @erd erd32-2 ? erd32,exr ? @erd ccr ? @aa:16 exr ? @aa:16 ccr ? @aa:32 exr ? @aa:32 ccr #xx:8 ? ccr exr #xx:8 ? exr ccr #xx:8 ? ccr exr #xx:8 ? exr ccr ? #xx:8 ? ccr exr ? #xx:8 ? exr pc ? pc+2 b b w w w w w w w w w w w w b b b b b b 2 4 2 4 2 4 2 2 4 4 6 6 10 10 4 4 6 6 8 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 3 3 4 4 6 6 4 4 4 4 5 5 1 2 1 2 1 2 1 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? operation condition code no. of states * 1 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? size 640 table a.1 instruction set (cont) 8. block transfer instructions mnemonic addressing mode and instruction length (bytes) #xx rn @ern @(d,ern) @-ern/@ern+ @aa @(d,pc) @@aa ihnzvc eepmov eepmov.b eepmov.w if r4l 1 0 repeat @er5 ? @er6 er5+1 ? er5 er6+1 ? er6 r4l-1 ? r4l until r4l=0 else next; if r4 1 0 repeat @er5 ? @er6 er5+1 ? er5 er6+1 ? er6 r4-1 ? r4 until r4=0 else next; ? 4+2n * 2 4+2n * 2 4 4 ? ? ? operation condition code no. of states * 1 normal advanced ? ? size notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value set in r4l or r4. [1] 7 states when the number of saved/restored registers is 2, 9 states when 3, and 11 states when 4. [2] cannot be used with the h8s/2128 series and h8s/2124 series. [3] set to 1 when there is a carry from or borrow to bit 11; otherwise cleared to 0. [4] set to 1 when there is a carry from or borrow to bit 27; otherwise cleared to 0. [5] if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. [6] set to 1 if the divisor is negative; otherwise cleared to 0. [7] set to 1 if the divisor is zero; otherwise cleared to 0. [8] set to 1 if the quotient is negative; otherwise cleared to 0. [9] when exr is valid, the number of states is increased by 1. 641 a.2 instruction codes table a.2 instruction codes add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd adds #1,erd adds #2,erd adds #4,erd addx #xx:8,rd addx rs,rd and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd andc #xx:8,ccr andc #xx:8,exr band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion add adds addx and andc band bcc b b w w l l l l l b b b b w w l l b b b b b b b ? ? ? 1 0 0 ers imm erd 0 0 0 0 0 0 erd erd erd erd erd erd ers imm imm 0 erd 0 imm 0 imm 0 0 0 8 0 7 0 7 0 0 0 0 9 0 e 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 rd 8 9 9 a a b b b rd e rd 6 9 6 a 1 6 1 6 c e a a 0 8 1 8 rd rd rd rd rd rd rd 0 1 rd 0 0 0 0 0 6 0 7 7 6 6 6 6 0 0 76 0 76 0 imm imm imm imm abs disp disp rs 1 rs 1 0 8 9 rs rs 6 rs 6 f 4 1 3 0 1 imm imm abs disp disp imm imm abs imm 642 table a.2 instruction codes (cont) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bcc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 a 8 b 8 c 8 d 8 e 8 f 8 2 3 4 5 6 7 8 9 a b c d e f disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 643 table a.2 instruction codes (cont) bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bclr biand bild bior b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 1 0 1 0 1 0 imm erd erd imm erd imm erd imm erd 0 1 1 1 imm imm imm imm 0 1 1 1 imm imm imm imm 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 2 d f a a 2 d f a a 6 c e a a 7 c e a a 4 c e a a 1 3 rn 1 3 1 3 1 3 1 3 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 0 0 7 7 6 6 7 7 7 7 7 7 2 2 2 2 6 6 7 7 4 4 rn rn 0 0 0 0 0 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs 0 0 1 1 1 1 1 1 imm imm imm imm imm imm imm imm 644 table a.2 instruction codes (cont) bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bist bixor bld bnot b b b b b b b b b b b b b b b b b b b b b b b b b 1 0 1 0 0 0 0 0 0 imm erd imm erd imm erd imm erd erd imm imm imm imm imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 1 1 0 0 0 0 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 d f a a 5 c e a a 7 c e a a 1 d f a a 1 d f a a 1 3 1 3 1 3 1 3 rn 1 3 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 8 8 rd 0 8 8 6 6 7 7 7 7 7 7 6 6 7 7 5 5 7 7 1 1 1 1 rn rn 0 0 0 0 0 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1 rn 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1 rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs 645 table a.2 instruction codes (cont) bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bsr d:8 bsr d:16 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bor bset bsr bst btst b b b b b b b b b b b b b b b ? ? b b b b b b b b b b b b 0 0 0 0 0 0 0 0 0 0 imm erd imm erd erd imm erd imm erd erd abs abs abs disp abs abs imm imm imm imm imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 0 0 0 0 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 4 c e a a 0 d f a a 0 d f a a 5 c 7 d f a a 3 c e a a 3 c 1 3 1 3 rn 1 3 0 1 3 1 3 rn rd 0 0 0 rd 0 8 8 rd 0 8 8 0 rd 0 8 8 rd 0 0 0 rd 0 7 7 7 7 6 6 6 6 7 7 6 4 4 0 0 0 0 7 7 3 3 3 rn rn rn 0 0 0 0 0 0 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 abs abs abs disp abs abs abs abs abs abs abs 646 table a.2 instruction codes (cont) btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 clrmac cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd daa rd das rd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd divxs.b rs,rd divxs.w rs,erd divxu.b rs,rd divxu.w rs,erd eepmov.b eepmov.w mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion btst bxor clrmac cmp daa das dec divxs divxu eepmov b b b b b b b b ? b b w w l l b b b w w l l b w b w ? 0 0 1 imm erd ers 0 0 0 0 0 erd erd erd erd erd imm imm 0 erd 0 imm 0 imm 0 0 7 6 6 7 7 7 6 6 a 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 e a a 5 c e a a rd c 9 d a f f f a b b b b 1 1 1 3 b b 1 3 1 3 rs 2 rs 2 0 0 0 5 d 7 f d d rs rs 5 d 0 0 rd 0 0 0 rd rd rd rd rd rd rd rd 0 0 rd c 4 6 7 7 5 5 5 5 3 5 5 1 3 9 9 rn rs rs 8 8 0 0 0 rd f f 6 7 3 5 rn 0 0 6 7 3 5 rn 0 0 abs abs imm abs abs imm abs abs imm cannot be used with the h8s/2128 series and h8s/2124 series. 647 table a.2 instruction codes (cont) exts.w rd exts.l erd extu.w rd extu.l erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd jmp @ern jmp @aa:24 jmp @@aa:8 jsr @ern jsr @aa:24 jsr @@aa:8 ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion exts extu inc jmp jsr ldc w l w l b w w l l ? ? ? ? ? ? b b b b w w w w w w w w w w 0 0 ern ern 0 0 0 0 erd erd erd erd ers ers ers ers ers ers ers ers 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 7 7 a b b b b 9 a b d e f 7 1 3 3 1 1 1 1 1 1 1 1 1 1 d f 5 7 0 5 d 7 f 4 0 1 4 4 4 4 4 4 4 4 4 4 rd rd rd rd rd 0 0 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 6 6 6 6 7 7 6 6 6 6 7 9 9 f f 8 8 d d b b 0 0 0 0 0 0 0 0 0 0 0 0 6 6 b b 2 2 0 0 abs abs abs abs imm imm disp disp abs abs disp disp 648 table a.2 instruction codes (cont) 0 0 rd abs rs rd ldc @aa:32,ccr ldc @aa:32,exr ldm.l @sp+, (ern-ern+1) ldm.l @sp+, (ern-ern+2) ldm.l @sp+, (ern-ern+3) ldmac ers,mach ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa:16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion ldc ldm ldmac mac mov w w l l l l l ? b b b b b b b b b b b b b b b b w w w w w 0 0 0 0 1 1 0 1 0 0 0 ers ers ers ers erd erd erd erd ers ers ers 0 0 0 ern+1 ern+2 ern+3 0 0 0 0 0 f 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 1 1 1 1 1 rd c 8 e 8 c rd a a 8 e 8 c rs a a 9 d 9 f 8 4 4 1 2 3 rs 0 2 8 a 0 rs 0 1 0 0 0 rd rd rd 0 rd rd rd rs rs 0 rs rs rs rd rd rd rd 0 6 6 6 6 6 6 6 6 b b d d d a a b 2 2 7 7 7 2 a 2 imm abs abs disp abs disp abs imm disp abs abs abs abs disp disp disp cannot be used with the h8s/2128 series and h8s/2124 series. 649 table a.2 instruction codes (cont) mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,rd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16 ,erd mov.l @aa:32 ,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) * mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 movfpe @aa:16,rd movtpe rs,@aa:16 mulxs.b rs,rd mulxs.w rs,erd mulxu.b rs,rd mulxu.w rs,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion mov movfpe movtpe mulxs mulxu w w w w w w w w w l l l l l l l l l l l l l l b b b w b w 0 1 1 0 1 1 ers erd erd erd erd ers 0 0 0 erd erd erd ers ers ers ers erd erd erd erd 0 0 0 0 0 0 0 0 0 0 0 erd erd erd erd erd ers ers ers ers ers erd 0 0 erd ers 0 0 0 0 1 1 0 1 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 d b b 9 f 8 d b b a f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 0 2 8 a 0 0 0 0 0 0 0 0 0 0 0 0 0 c c rs rs rd rd rd rs rs 0 rs rs rs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd 6 6 6 7 6 6 6 6 6 7 6 6 6 5 5 b 9 f 8 d b b 9 f 8 d b b 0 2 a 0 2 8 a rs rs rs 0 0 rd 6 6 b b 2 a abs disp abs abs abs imm disp abs disp abs disp abs abs disp disp cannot be used with the h8s/2128 series and h8s/2124 series. 650 table a.2 instruction codes (cont) neg.b rd neg.w rd neg.l erd nop not.b rd not.w rd not.l erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd orc #xx:8,ccr orc #xx:8,exr pop.w rn pop.l ern push.w rn push.l ern rotl.b rd rotl.b #2, rd rotl.w rd rotl.w #2, rd rotl.l erd rotl.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion neg nop not or orc pop push rotl b w l ? b w l b b w w l l b b w l w l b b w w l l 0 0 0 0 0 erd erd erd erd erd 1 1 1 0 1 1 1 c 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 7 7 7 0 7 7 7 rd 4 9 4 a 1 4 1 d 1 d 1 2 2 2 2 2 2 8 9 b 0 0 1 3 rs 4 rs 4 f 4 7 0 f 0 8 c 9 d b f rd rd 0 rd rd rd rd rd 0 1 rn 0 rn 0 rd rd rd rd imm imm 6 0 6 6 4 4 d d ers 0 0 0 erd ern ern 0 7 f imm imm imm 651 table a.2 instruction codes (cont) rotr.b rd rotr.b #2, rd rotr.w rd rotr.w #2, rd rotr.l erd rotr.l #2, erd rotxl.b rd rotxl.b #2, rd rotxl.w rd rotxl.w #2, rd rotxl.l erd rotxl.l #2, erd rotxr.b rd rotxr.b #2, rd rotxr.w rd rotxr.w #2, rd rotxr.l erd rotxr.l #2, erd rte rts shal.b rd shal.b #2, rd shal.w rd shal.w #2, rd shal.l erd shal.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion rotr rotxl rotxr rte rts shal b b w w l l b b w w l l b b w w l l ? ? b b w w l l 0 0 0 0 0 0 0 0 erd erd erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 c 9 d b f rd rd rd rd rd rd rd rd rd rd rd rd 0 0 rd rd rd rd 652 table a.2 instruction codes (cont) shar.b rd shar.b #2, rd shar.w rd shar.w #2, rd shar.l erd shar.l #2, erd shll.b rd shll.b #2, rd shll.w rd shll.w #2, rd shll.l erd shll.l #2, erd shlr.b rd shlr.b #2, rd shlr.w rd shlr.w #2, rd shlr.l erd shlr.l #2, erd sleep stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion shar shll shlr sleep stc b b w w l l b b w w l l b b w w l l ? b b w w w w w w w w 0 0 0 0 0 0 erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 rd rd rd rd rd rd rd rd rd rd rd rd 0 rd rd 0 1 0 1 0 1 0 1 erd erd erd erd erd erd erd erd 1 1 1 1 0 0 1 1 6 6 6 6 7 7 6 6 9 9 f f 8 8 d d 0 0 0 0 0 0 0 0 6 6 b b a a 0 0 disp disp disp disp 653 table a.2 instruction codes (cont) stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 stm.l (ern-ern+1), @-sp stm.l (ern-ern+2), @-sp stm.l (ern-ern+3), @-sp stmac mach,erd stmac macl,erd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subs #1,erd subs #2,erd subs #4,erd subx #xx:8,rd subx rs,rd tas @erd trapa #x:2 xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion stc stm stmac sub subs subx tas trapa xor w w w w l l l l l b w w l l l l l b b b ? b b w w l l 1 00 ers imm 0 0 0 0 0 0 erd erd erd erd erd erd erd ers 0 0 0 0 ern ern ern erd 0 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 b 1 0 5 d 1 7 6 7 0 1 1 1 1 1 1 1 8 9 9 a a b b b rd e 1 7 rd 5 9 5 a 1 4 4 4 4 1 2 3 rs 3 rs 3 0 8 9 rs e rs 5 rs 5 f 0 1 0 1 0 0 0 rd rd rd rd 0 0 rd rd rd 0 6 6 6 6 6 6 6 7 6 b b b b d d d b 5 8 8 a a f f f 0 0 0 0 c abs abs abs abs imm imm imm imm imm imm cannot be used with the h8s/2128 series and h8s/2124 series. 654 table a.2 instruction codes (cont) xorc #xx:8,ccr xorc #xx:8,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion xorc b b 0 0 5 1 4 1 0 5 imm imm note: bit 7 of the 4th byte of the mov.l ers, @ (d:32, erd) instruction can be either 0 or 1. legend address registers 32-bit registers register field general register register field general register register field general register 000 001 ? ? ? 111 er0 er1 ? ? ? er7 0000 0001 ? ? ? 0111 1000 1001 ? ? ? 1111 r0 r1 ? ? ? r7 e0 e1 ? ? ? e7 0000 0001 ? ? ? 0111 1000 1001 ? ? ? 1111 r0h r1h ? ? ? r7h r0l r1l ? ? ? r7l 16-bit register 8-bit register imm: abs: disp: rs, rd, rn: ers, erd, ern, erm: the correspondence between register fields and general registers is shown in the following table. immediate data (2, 3, 8, 16, or 32 bits) absolute address (8, 16, 24, or 32 bits) displacement (8, 16, or 32 bits) register field (4 bits, indicating an 8-bit or 16-bit register. rs, rd, and rn correspond to operand formats rs, rd, and rn, respectively.) register field (3 bits, indicating an address register or 32-bit register. ers, erd, ern, and erm correspond to operand formats ers, erd, ern, and erm, respectively.) * 655 a.3 operation code map table a.3 shows the operation code map. table a.3 operation code map (1) instruction code: 1st byte 2nd byte ah al bh bl instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. 0 nop bra mulxu bset ah al 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 brn divxu bnot 2 bhi mulxu bclr 3 bls divxu btst stc stmac ldc ldmac 4 orc or bcc rts or bor bior 6 andc and bne rte and 5 xorc xor bcs bsr xor bxor bixor band biand 7 ldc beq trapa bst bist bld bild 8 bvc mov 9 bvs a bpl jmp b bmi eepmov c bge bsr d blt mov e addx subx bgt jsr f ble mov.b add addx cmp subx or xor and mov add sub mov mov cmp table a.3 (3) ** note: * cannot be used with the h8s/2128 series and h8s/2124 series. table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) table a.3 (2) 656 table a.3 operation code map (2) instruction code: 1st byte 2nd byte ah al bh bl 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 6a 79 7a 0 mov inc adds daa dec subs das bra mov mov mov shll shlr rotxl rotxr not 1 ldm brn add add 2 bhi mov cmp cmp 3 stm not bls sub sub 4 shll shlr rotxl rotxr bcc movfpe or or 5 inc extu dec bcs xor xor 6 mac bne and and 7 inc shll shlr rotxl rotxr extu dec beq ldc stc 8 sleep bvc mov adds shal shar rotl rotr neg subs 9 bvs a clrmac bpl mov b neg bmi add mov sub cmp c shal shar rotl rotr bge movtpe d inc exts dec blt e tas bgt f inc shal shar rotl rotr exts dec ble bh ah al * * note: * cannot be used with the h8s/2128 series and h8s/2124 series. * * table a.3 (4) table a.3 (4) table a.3 (3) table a.3 (3) table a.3 (3) 657 table a.3 operation code map (3) instruction code: 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. notes: 1. r is the register specification field. 2. aa is the absolute address specification. ah al bh bl ch cl 01c05 01d05 01f06 7cr06 * 1 7cr07 * 1 7dr06 * 1 7dr07 * 1 7eaa6 * 2 7eaa7 * 2 7faa6 * 2 7faa7 * 2 0 mulxs bset bset bset bset 1 divxs bnot bnot bnot bnot 2 mulxs bclr bclr bclr bclr 3 divxs btst btst btst btst 4 or 5 xor 6 and 789abcdef bor bior bxor bixor band biand bld bild bst bist bor bior bxor bixor band biand bld bild bst bist 658 table a.3 operation code map (4) instruction code: 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of fh is 0. instruction when most significant bit of fh is 1. 5th byte 6th byte eh el fh fl instruction code: 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl indicates case where msb of hh is 0. indicates case where msb of hh is 1. note: * aa is the absolute address specification. 5th byte 6th byte eh el fh fl 7th byte 8th byte gh gl hh hl 6a10aaaa6 * 6a10aaaa7 * 6a18aaaa6 * 6a18aaaa7 * ahalbhblchcldhdleh el 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef 6a30aaaaaaaa6 * 6a30aaaaaaaa7 * 6a38aaaaaaaa6 * 6a38aaaaaaaa7 * ahalbhbl ... fhflgh gl 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef 659 a.4 number of states required for execution the tables in this section can be used to calculate the number of states required for instruction execution by the h8s/2000 cpu. table a.5 shows the number of instruction fetch, data read/write, and other cycles occurring in each instruction, and table a.4 shows the number of states required per cycle according to the bus size. the number of states required for execution of an instruction can be calculated from these two tables as follows: number of states = i s i + j s j + k s k + l s l + m s m + n s n examples of calculation of number of states required for execution examples: advanced mode, external address space designated for the program area and stack area, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 8-bit bus width. 1. bset #0,@ffffc7:8 from table a.5, i = l = 2 and j = k = m = n = 0 from table a.4, s i = 8 and s l = 2 number of states = 2 8 + 2 2 = 20 2. jsr @@30 from table a.5, i = j = k = 2 and l = m = n = 0 from table a.4, s i = s j = s k = 8 number of states = 2 8 + 2 8 + 2 8 = 48 660 table a.4 number of states per cycle access conditions on-chip external device supporting module 8-bit bus 16-bit bus * execution state (cycle) on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 2 4 6 + 2m 2 3 + m branch address fetch s j stack operation s k byte data access s l 2 2 3 + m word data access s m 4 4 6 + 2m internal operation s n 1111111 legend: m: number of wait states inserted into external device access note: * cannot be used in the h8s/2128 series and h8s/2124 series. 661 table a.5 number of cycles per instruction instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8,rd 1 add.b rs,rd 1 add.w #xx:16,rd 2 add.w rs,rd 1 add.l #xx:32,erd 3 add.l ers,erd 1 adds adds #1/2/4,erd 1 addx addx #xx:8,rd 1 addx rs,rd 1 and and.b #xx:8,rd 1 and.b rs,rd 1 and.w #xx:16,rd 2 and.w rs,rd 1 and.l #xx:32,erd 3 and.l ers,erd 2 andc andc #xx:8,ccr 1 andc #xx:8,exr 2 band band #xx:3,rd 1 band #xx:3,@erd 2 1 band #xx:3,@aa:8 2 1 band #xx:3,@aa:16 3 1 band #xx:3,@aa:32 4 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 662 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n bcc bgt d:8 2 ble d:8 2 bra d:16 (bt d:16) 2 1 brn d:16 (bf d:16) 2 1 bhi d:16 2 1 bls d:16 2 1 bcc d:16 (bhs d:16) 2 1 bcs d:16 (blo d:16) 2 1 bne d:16 2 1 beq d:16 2 1 bvc d:16 2 1 bvs d:16 2 1 bpl d:16 2 1 bmi d:16 2 1 bge d:16 2 1 blt d:16 2 1 bgt d:16 2 1 ble d:16 2 1 bclr bclr #xx:3,rd 1 bclr #xx:3,@erd 2 2 bclr #xx:3,@aa:8 2 2 bclr #xx:3,@aa:16 3 2 bclr #xx:3,@aa:32 4 2 bclr rn,rd 1 bclr rn,@erd 2 2 bclr rn,@aa:8 2 2 bclr rn,@aa:16 3 2 bclr rn,@aa:32 4 2 biand biand #xx:3,rd 1 biand #xx:3,@erd 2 1 biand #xx:3,@aa:8 2 1 biand #xx:3,@aa:16 3 1 biand #xx:3,@aa:32 4 1 663 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n bild bild #xx:3,rd 1 bild #xx:3,@erd 2 1 bild #xx:3,@aa:8 2 1 bild #xx:3,@aa:16 3 1 bild #xx:3,@aa:32 4 1 bior bior #xx:8,rd 1 bior #xx:8,@erd 2 1 bior #xx:8,@aa:8 2 1 bior #xx:8,@aa:16 3 1 bior #xx:8,@aa:32 4 1 bist bist #xx:3,rd 1 bist #xx:3,@erd 2 2 bist #xx:3,@aa:8 2 2 bist #xx:3,@aa:16 3 2 bist #xx:3,@aa:32 4 2 bixor bixor #xx:3,rd 1 bixor #xx:3,@erd 2 1 bixor #xx:3,@aa:8 2 1 bixor #xx:3,@aa:16 3 1 bixor #xx:3,@aa:32 4 1 bld bld #xx:3,rd 1 bld #xx:3,@erd 2 1 bld #xx:3,@aa:8 2 1 bld #xx:3,@aa:16 3 1 bld #xx:3,@aa:32 4 1 bnot bnot #xx:3,rd 1 bnot #xx:3,@erd 2 2 bnot #xx:3,@aa:8 2 2 bnot #xx:3,@aa:16 3 2 bnot #xx:3,@aa:32 4 2 bnot rn,rd 1 bnot rn,@erd 2 2 bnot rn,@aa:8 2 2 bnot rn,@aa:16 3 2 bnot rn,@aa:32 4 2 664 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n bor bor #xx:3,rd 1 bor #xx:3,@erd 2 1 bor #xx:3,@aa:8 2 1 bor #xx:3,@aa:16 3 1 bor #xx:3,@aa:32 4 1 bset bset #xx:3,rd 1 bset #xx:3,@erd 2 2 bset #xx:3,@aa:8 2 2 bset #xx:3,@aa:16 3 2 bset #xx:3,@aa:32 4 2 bset rn,rd 1 bset rn,@erd 2 2 bset rn,@aa:8 2 2 bset rn,@aa:16 3 2 bset rn,@aa:32 4 2 bsr bsr d:8 normal 2 1 advanced 2 2 bsr d:16 normal 2 1 1 advanced 2 2 1 bst bst #xx:3,rd 1 bst #xx:3,@erd 2 2 bst #xx:3,@aa:8 2 2 bst #xx:3,@aa:16 3 2 bst #xx:3,@aa:32 4 2 btst btst #xx:3,rd 1 btst #xx:3,@erd 2 1 btst #xx:3,@aa:8 2 1 btst #xx:3,@aa:16 3 1 btst #xx:3,@aa:32 4 1 btst rn,rd 1 btst rn,@erd 2 1 btst rn,@aa:8 2 1 btst rn,@aa:16 3 1 btst rn,@aa:32 4 1 665 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n bxor bxor #xx:3,rd 1 bxor #xx:3,@erd 2 1 bxor #xx:3,@aa:8 2 1 bxor #xx:3,@aa:16 3 1 bxor #xx:3,@aa:32 4 1 clrmac clrmac cannot be used with the h8s/2128 series and h8s/2124 series. cmp cmp.b #xx:8,rd 1 cmp.b rs,rd 1 cmp.w #xx:16,rd 2 cmp.w rs,rd 1 cmp.l #xx:32,erd 3 cmp.l ers,erd 1 daa daa rd 1 das das rd 1 dec dec.b rd 1 dec.w #1/2,rd 1 dec.l #1/2,erd 1 divxs divxs.b rs,rd 2 11 divxs.w rs,erd 2 19 divxu divxu.b rs,rd 1 11 divxu.w rs,erd 1 19 eepmov eepmov.b 2 2n+2 * 2 eepmov.w 2 2n+2 * 2 exts exts.w rd 1 exts.l erd 1 extu extu.w rd 1 extu.l erd 1 inc inc.b rd 1 inc.w #1/2,rd 1 inc.l #1/2,erd 1 jmp jmp @ern 2 jmp @aa:24 2 1 jmp @@aa:8 normal 2 1 1 advanced 2 2 1 666 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n jsr jsr @ern normal 2 1 advanced 2 2 jsr @aa:24 normal 2 1 1 advanced 2 2 1 jsr @@aa:8 normal 2 1 1 advanced 2 2 2 ldc ldc #xx:8,ccr 1 ldc #xx:8,exr 2 ldc rs,ccr 1 ldc rs,exr 1 ldc @ers,ccr 2 1 ldc @ers,exr 2 1 ldc @(d:16,ers),ccr 3 1 ldc @(d:16,ers),exr 3 1 ldc @(d:32,ers),ccr 5 1 ldc @(d:32,ers),exr 5 1 ldc @ers+,ccr 2 1 1 ldc @ers+,exr 2 1 1 ldc @aa:16,ccr 3 1 ldc @aa:16,exr 3 1 ldc @aa:32,ccr 4 1 ldc @aa:32,exr 4 1 ldm ldm.l @sp+, (ern-ern+1) 2 4 1 ldm.l @sp+, (ern-ern+2) 2 6 1 ldm.l @sp+, (ern-ern+3) 2 8 1 ldmac ldmac ers, mach cannot be used with the h8s/2128 series and h8s/2124 series. ldmac ers, macl mac mac @ern+, @erm+ mov mov.b #xx:8,rd 1 mov.b rs,rd 1 mov.b @ers,rd 1 1 mov.b @(d:16,ers),rd 2 1 mov.b @(d:32,ers),rd 4 1 mov.b @ers+,rd 1 1 1 mov.b @aa:8,rd 1 1 mov.b @aa:16,rd 2 1 667 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n mov mov.b @aa:32,rd 3 1 mov.b rs,@erd 1 1 mov.b rs,@(d:16,erd) 2 1 mov.b rs,@(d:32,erd) 4 1 mov.b rs,@-erd 1 1 1 mov.b rs,@aa:8 1 1 mov.b rs,@aa:16 2 1 mov.b rs,@aa:32 3 1 mov.w #xx:16,rd 2 mov.w rs,rd 1 mov.w @ers,rd 1 1 mov.w @(d:16,ers),rd 2 1 mov.w @(d:32,ers),rd 4 1 mov.w @ers+,rd 1 1 1 mov.w @aa:16,rd 2 1 mov.w @aa:32,rd 3 1 mov.w rs,@erd 1 1 mov.w rs,@(d:16,erd) 2 1 mov.w rs,@(d:32,erd) 4 1 mov.w rs,@-erd 1 1 1 mov.w rs,@aa:16 2 1 mov.w rs,@aa:32 3 1 mov.l #xx:32,erd 3 mov.l ers,erd 1 mov.l @ers,erd 2 2 mov.l @(d:16,ers),erd 3 2 mov.l @(d:32,ers),erd 5 2 mov.l @ers+,erd 2 2 1 mov.l @aa:16,erd 3 2 mov.l @aa:32,erd 4 2 mov.l ers,@erd 2 2 mov.l ers,@(d:16,erd) 3 2 mov.l ers,@(d:32,erd) 5 2 mov.l ers,@-erd 2 2 1 mov.l ers,@aa:16 3 2 mov.l ers,@aa:32 4 2 668 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n movfpe movfpe @:aa:16,rd cannot be used with the h8s/2128 series and h8s/2124 series. movtpe movtpe rs,@:aa:16 mulxs mulxs.b rs,rd 2 11 mulxs.w rs,erd 2 19 mulxu mulxu.b rs,rd 1 11 mulxu.w rs,erd 1 19 neg neg.b rd 1 neg.w rd 1 neg.l erd 1 nop nop 1 not not.b rd 1 not.w rd 1 not.l erd 1 or or.b #xx:8,rd 1 or.b rs,rd 1 or.w #xx:16,rd 2 or.w rs,rd 1 or.l #xx:32,erd 3 or.l ers,erd 2 orc orc #xx:8,ccr 1 orc #xx:8,exr 2 pop pop.w rn 1 1 1 pop.l ern 2 2 1 push push.w rn 1 1 1 push.l ern 2 2 1 rotl rotl.b rd 1 rotl.b #2,rd 1 rotl.w rd 1 rotl.w #2,rd 1 rotl.l erd 1 rotl.l #2,erd 1 669 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n rotr rotr.b rd 1 rotr.b #2,rd 1 rotr.w rd 1 rotr.w #2,rd 1 rotr.l erd 1 rotr.l #2,erd 1 rotxl rotxl.b rd 1 rotxl.b #2,rd 1 rotxl.w rd 1 rotxl.w #2,rd 1 rotxl.l erd 1 rotxl.l #2,erd 1 rotxr rotxr.b rd 1 rotxr.b #2,rd 1 rotxr.w rd 1 rotxr.w #2,rd 1 rotxr.l erd 1 rotxr.l #2,erd 1 rte rte 2 2/3 * 1 1 rts rts normal 2 1 1 advanced 2 2 1 shal shal.b rd 1 shal.b #2,rd 1 shal.w rd 1 shal.w #2,rd 1 shal.l erd 1 shal.l #2,erd 1 shar shar.b rd 1 shar.b #2,rd 1 shar.w rd 1 shar.w #2,rd 1 shar.l erd 1 shar.l #2,erd 1 670 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n shll shll.b rd 1 shll.b #2,rd 1 shll.w rd 1 shll.w #2,rd 1 shll.l erd 1 shll.l #2,erd 1 shlr shlr.b rd 1 shlr.b #2,rd 1 shlr.w rd 1 shlr.w #2,rd 1 shlr.l erd 1 shlr.l #2,erd 1 sleep sleep 1 1 stc stc.b ccr,rd 1 stc.b exr,rd 1 stc.w ccr,@erd 2 1 stc.w exr,@erd 2 1 stc.w ccr,@(d:16,erd) 3 1 stc.w exr,@(d:16,erd) 3 1 stc.w ccr,@(d:32,erd) 5 1 stc.w exr,@(d:32,erd) 5 1 stc.w ccr,@-erd 2 1 1 stc.w exr,@-erd 2 1 1 stc.w ccr,@aa:16 3 1 stc.w exr,@aa:16 3 1 stc.w ccr,@aa:32 4 1 stc.w exr,@aa:32 4 1 stm stm.l (ern-ern+1),@-sp 2 4 1 stm.l (ern-ern+2),@-sp 2 6 1 stm.l (ern-ern+3),@-sp 2 8 1 sub sub.b rs,rd 1 sub.w #xx:16,rd 2 sub.w rs,rd 1 sub.l #xx:32,erd 3 sub.l ers,erd 1 671 table a.5 number of cycles per instruction (cont) instruction mnemonic instruction fetch i branch address read j stack operation k byte data access l word data access m internal operation n subs subs #1/2/4,erd 1 subx subx #xx:8,rd 1 subx rs,rd 1 tas tas @erd 2 2 trapa trapa #x:2 normal 2 1 2/3 * 1 2 advanced 2 2 2/3 * 1 2 xor xor.b #xx:8,rd 1 xor.b rs,rd 1 xor.w #xx:16,rd 2 xor.w rs,rd 1 xor.l #xx:32,erd 3 xor.l ers,erd 2 xorc xorc #xx:8,ccr 1 xorc #xx:8,exr 2 notes: 1. 2 when exr is invalid, 3 when valid. 2. when n bytes of data are transferred. 672 a.5 bus states during instruction execution table a.6 indicates the types of cycles that occur during instruction execution by the cpu. see table a.4 for the number of states per cycle. how to read the table: instruction jmp@aa:24 r:w 2nd internal operation 2 state r:w ea 123 4 567 8 end of instruction order of execution read effective address (word-size read) no read or write read 2nd word of current instruction (word-size read) legend r:b byte-size read r:w word-size read w:b byte-size write w:w word-size write :m transfer of the bus is not performed immediately after this cycle 2nd address of 2nd word (3rd and 4th bytes) 3rd address of 3rd word (5th and 6th bytes) 4th address of 4th word (7th and 8th bytes) 5th address of 5th word (9th and 10th bytes) next start address of instruction following executing instruction ea effective address vec vector address 673 figure a.1 shows timing waveforms for the address bus and the 5' , :5 signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. address bus rd wr r:w 2nd fetching 2nd byte of branch instruction fetching 1st byte of branch instruction fetching 4th byte of instruction fetching 3rd byte of instruction r:w ea high level internal operation figure a.1 address bus, 5' 5' , :5 :5 timing (8-bit bus, three-state access, no wait states) 674 table a.6 instruction execution cycle instruction 123456789 add.b #xx:8,rd r:w next add.b rs,rd r:w next add.w #xx:16,rd r:w 2nd r:w next add.w rs,rd r:w next add.l #xx:32,erd r:w 2nd r:w 3rd r:w next add.l ers,erd r:w next adds #1/2/4,erd r:w next addx #xx:8,rd r:w next addx rs,rd r:w next and.b #xx:8,rd r:w next and.b rs,rd r:w next and.w #xx:16,rd r:w 2nd r:w next and.w rs,rd r:w next and.l #xx:32,erd r:w 2nd r:w 3rd r:w next and.l ers,erd r:w 2nd r:w next andc #xx:8,ccr r:w next andc #xx:8,exr r:w 2nd r:w next band #xx:3,rd r:w next band #xx:3,@erd r:w 2nd r:b ea r:w:m next band #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next band #xx:3, @aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next band #xx:3, @aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bra d:8 (bt d:8) r:w next r:w ea brn d:8 (bf d:8) r:w next r:w ea bhi d:8 r:w next r:w ea bls d:8 r:w next r:w ea bcc d:8 (bhs d:8) r:w next r:w ea bcs d:8 (blo d:8) r:w next r:w ea bne d:8 r:w next r:w ea beq d:8 r:w next r:w ea bvc d:8 r:w next r:w ea bvs d:8 r:w next r:w ea bpl d:8 r:w next r:w ea 675 table a.6 instruction execution cycle (cont) instruction 123456789 bmi d:8 r:w next r:w ea bge d:8 r:w next r:w ea blt d:8 r:w next r:w ea bgt d:8 r:w next r:w ea ble d:8 r:w next r:w ea bra d:16 (bt d:16) r:w 2nd internal operation, 1 state r:w ea brn d:16 (bf d:16) r:w 2nd internal operation, 1 state r:w ea bhi d:16 r:w 2nd internal operation, 1 state r:w ea bls d:16 r:w 2nd internal operation, 1 state r:w ea bcc d:16 (bhs d:16) r:w 2nd internal operation, 1 state r:w ea bcs d:16 (blo d:16) r:w 2nd internal operation, 1 state r:w ea bne d:16 r:w 2nd internal operation, 1 state r:w ea beq d:16 r:w 2nd internal operation, 1 state r:w ea bvc d:16 r:w 2nd internal operation, 1 state r:w ea bvs d:16 r:w 2nd internal operation, 1 state r:w ea bpl d:16 r:w 2nd internal operation, 1 state r:w ea bmi d:16 r:w 2nd internal operation, 1 state r:w ea bge d:16 r:w 2nd internal operation, 1 state r:w ea 676 table a.6 instruction execution cycle (cont) instruction 123456789 blt d:16 r:w 2nd internal operation, 1 state r:w ea bgt d:16 r:w 2nd internal operation, 1 state r:w ea ble d:16 r:w 2nd internal operation, 1 state r:w ea bclr #xx:3,rd r:w next bclr #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr#xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr#xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bclr rn,rd r:w next bclr rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea biand #xx:3,rd r:w next biand #xx:3, @erd r:w 2nd r:b ea r:w:m next biand #xx:3, @aa:8 r:w 2nd r:b ea r:w:m next biand #xx:3, @aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next biand #xx:3, @aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bild #xx:3,rd r:w next bild #xx:3,@erd r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:16 r:w 2nd r:w 3rd r:b: ea r:w:m next 677 table a.6 instruction execution cycle (cont) instruction 123456789 bild #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bior #xx:3,rd r:w next bior #xx:3,@erd r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bior #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bist #xx:3,rd r:w next bist #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bixor #xx:3,rd r:w next bixor #xx:3, @erd r:w 2nd r:b ea r:w:m next bixor #xx:3, @aa:8 r:w 2nd r:b ea r:w:m next bixor #xx:3, @aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bixor #xx:3, @aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bld #xx:3,rd r:w next bld #xx:3,@erd r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bld #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bnot #xx:3,rd r:w next bnot #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea 678 table a.6 instruction execution cycle (cont) instruction 123456789 bnot #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3, @aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot #xx:3, @aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bnot rn,rd r:w next bnot rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bor #xx:3,rd r:w next bor #xx:3,@erd r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w next bset #xx:3,rd r:w next bset #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3, @aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset #xx:3, @aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bset rn,rd r:w next bset rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea 679 table a.6 instruction execution cycle (cont) instruction 123456789 bsr d:8 advanced r:w next r:w ea w:w:m stack (h) w:w stack (l) bsr d:16 advanced r:w 2nd internal operation, 1 state r:w ea w:w:m stack (h) w:w stack (l) bst #xx:3,rd r:w next bst #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea btst #xx:3,rd r:w next btst #xx:3,@erd r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next btst #xx:3, @aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst #xx:3, @aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next btst rn,rd r:w next btst rn,@erd r:w 2nd r:b ea r:w:m next btst rn,@aa:8 r:w 2nd r:b ea r:w:m next btst rn,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bxor #xx:3,rd r:w next bxor #xx:3,@erd r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bxor #xx:3, @aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bxor #xx:3, @aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next clrmac cannot be used in the h8s/2128 series and h8s/2124 series 680 table a.6 instruction execution cycle (cont) instruction 123456789 cmp.b #xx:8,rd r:w next cmp.b rs,rd r:w next cmp.w #xx:16,rd r:w 2nd r:w next cmp.w rs,rd r:w next cmp.l #xx:32,erd r:w 2nd r:w 3rd r:w next cmp.l ers,erd r:w next daa rd r:w next das rd r:w next dec.b rd r:w next dec.w #1/2,rd r:w next dec.l #1/2,erd r:w next divxs.b rs,rd r:w 2nd r:w next internal operation, 11 states divxs.w rs,erd r:w 2nd r:w next internal operation, 19 states divxu.b rs,rd r:w next internal operation, 11 states divxu.w rs,erd r:w next internal operation, 19 states eepmov.b r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next eepmov.w r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next exts.w rd r:w next ? repeated n times * 2 ? exts.l erd r:w next extu.w rd r:w next extu.l erd r:w next inc.b rd r:w next inc.w #1/2,rd r:w next inc.l #1/2,erd r:w next jmp @ern r:w next r:w ea jmp @aa:24 r:w 2nd internal operation, 1 state r:w ea jmp @@aa:8 advanced r:w next r:w:m aa:8 r:w aa:8 internal operation, 1 state r:w ea jsr @ern advanced r:w next r:w ea w:w:m stack (h) w:w stack (l) jsr @aa:24 advanced r:w 2nd internal operation, 1 state r:w ea w:w:m stack (h) w:w stack (l) jsr @@aa:8 advanced r:w next r:w:m aa:8 r:w aa:8 w:w:m stack (h) w:w stack (l) r:w ea 681 table a.6 instruction execution cycle (cont) instruction 123456789 ldc #xx:8,ccr r:w next ldc #xx:8,exr r:w 2nd r:w next ldc rs,ccr r:w next ldc rs,exr r:w next ldc @ers,ccr r:w 2nd r:w next r:w ea ldc @ers,exr r:w 2nd r:w next r:w ea ldc@(d:16,ers), ccr r:w 2nd r:w 3rd r:w next r:w ea ldc@(d:16,ers), exr r:w 2nd r:w 3rd r:w next r:w ea ldc@(d:32,ers), ccr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc@(d:32,ers), exr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @ers+,ccr r:w 2nd r:w next internal operation, 1 state r:w ea ldc @ers+,exr r:w 2nd r:w next internal operation, 1 state r:w ea ldc @aa:16,ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:16,exr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:32,ccr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldc @aa:32,exr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldm.l @sp+, (ern-ern+1) r:w 2nd r:w:m next internal operation, 1 state r:w:m stack (h) * 3 r:w stack (l) * 3 ldm.l @sp+, (ern-ern+2) r:w 2nd r:w:m next internal operation, 1 state r:w:m stack (h) * 3 r:w stack (l) * 3 ldm.l @sp+, (ern-ern+3) r:w 2nd r:w:m next internal operation, 1 state r:w:m stack (h) * 3 r:w stack (l) * 3 ldmac ers,mach cannot be used in the h8s/2128 series and h8s/2124 series ldmac ers,macl mac @ern+, @erm+ mov.b #xx:8,rd r:w next mov.b rs,rd r:w next mov.b @ers,rd r:w next r:b ea mov.b @(d:16,ers),rd r:w 2nd r:w next r:b ea 682 table a.6 instruction execution cycle (cont) instruction 123456789 mov.b @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:b ea mov.b @ers+,rd r:w next internal operation, 1 state r:b ea mov.b @aa:8,rd r:w next r:b ea mov.b @aa:16,rd r:w 2nd r:w next r:b ea mov.b @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.b rs,@erd r:w next w:b ea mov.b rs, @(d:16,erd) r:w 2nd r:w next w:b ea mov.b rs, @(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:b ea mov.b rs,@-erd r:w next internal operation, 1 state w:b ea mov.b rs,@aa:8 r:w next w:b ea mov.b rs,@aa:16 r:w 2nd r:w next w:b ea mov.b rs,@aa:32 r:w 2nd r:w 3rd r:w next w:b ea mov.w #xx:16,rd r:w 2nd r:w next mov.w rs,rd r:w next mov.w @ers,rd r:w next r:w ea mov.w @(d:16,ers),rd r:w 2nd r:w next r:w ea mov.w @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:w ea mov.w @ers+,rd r:w next internal operation, 1 state r:w ea mov.w @aa:16,rd r:w 2nd r:w next r:w ea mov.w @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.w rs,@erd r:w next w:w ea mov.w rs, @(d:16,erd) r:w 2nd r:w next w:w ea mov.w rs, @(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:w ea mov.w rs,@-erd r:w next internal operation, 1 state w:w ea mov.w rs,@aa:16 r:w 2nd r:w next w:w ea mov.w rs,@aa:32 r:w 2nd r:w 3rd r:w next w:w ea 683 table a.6 instruction execution cycle (cont) instruction 123456789 mov.l #xx:32,erd r:w 2nd r:w 3rd r:w next mov.l ers,erd r:w next mov.l @ers,erd r:w 2nd r:w:m next r:w:m ea r:w ea+2 mov.l @(d:16,ers),erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @(d:32,ers),erd r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next r:w:m ea r:w ea+2 mov.l @ers+, erd r:w 2nd r:w:m next internal operation, 1 state r:w:m ea r:w ea+2 mov.l @aa:16, erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @aa:32, erd r:w 2nd r:w:m 3rd r:w 4th r:w next r:w:m ea r:w ea+2 mov.l ers,@erd r:w 2nd r:w:m next w:w:m ea w:w ea+2 mov.l ers, @(d:16,erd) r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers, @(d:32,erd) r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next w:w:m ea w:w ea+2 mov.l ers,@-erd r:w 2nd r:w:m next internal operation, 1 state w:w:m ea w:w ea+2 mov.l ers, @aa:16 r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers, @aa:32 r:w 2nd r:w:m 3rd r:w 4th r:w next w:w:m ea w:w ea+2 movfpe @aa:16,rd cannot be used in the h8s/2128 series and h8s/2124 series movtpe rs,@aa:16 mulxs.b rs,rd r:w 2nd r:w next internal operation, 11 states mulxs.w rs,erd r:w 2nd r:w next internal operation, 19 states mulxu.b rs,rd r:w next internal operation, 11 states mulxu.w rs,erd r:w next internal operation, 19 states neg.b rd r:w next neg.w rd r:w next neg.l erd r:w next nop r:w next not.b rd r:w next not.w rd r:w next 684 table a.6 instruction execution cycle (cont) instruction 123456789 not.l erd r:w next or.b #xx:8,rd r:w next or.b rs,rd r:w next or.w #xx:16,rd r:w 2nd r:w next or.w rs,rd r:w next or.l #xx:32,erd r:w 2nd r:w 3rd r:w next or.l ers,erd r:w 2nd r:w next orc #xx:8,ccr r:w next orc #xx:8,exr r:w 2nd r:w next pop.w rn r:w next internal operation, 1 state r:w ea pop.l ern r:w 2nd r:w:m next internal operation, 1 state r:w:m ea r:w ea+2 push.w rn r:w next internal operation, 1 state w:w ea push.l ern r:w 2nd r:w:m next internal operation, 1 state w:w:m ea w:w ea+2 rotl.b rd r:w next rotl.b #2,rd r:w next rotl.w rd r:w next rotl.w #2,rd r:w next rotl.l erd r:w next rotl.l #2,erd r:w next rotr.b rd r:w next rotr.b #2,rd r:w next rotr.w rd r:w next rotr.w #2,rd r:w next rotr.l erd r:w next rotr.l #2,erd r:w next rotxl.b rd r:w next rotxl.b #2,rd r:w next rotxl.w rd r:w next rotxl.w #2,rd r:w next rotxl.l erd r:w next 685 table a.6 instruction execution cycle (cont) instruction 123456789 rotxl.l #2,erd r:w next rotxr.b rd r:w next rotxr.b #2,rd r:w next rotxr.w rd r:w next rotxr.w #2,rd r:w next rotxr.l erd r:w next rotxr.l #2,erd r:w next rte r:w next r:w stack (exr) r:w stack (h) r:w stack (l) internal operation, 1 state r:w * 4 rts advanced r:w next r:w:m stack (h) r:w stack (l) internal operation, 1 state r:w * 4 shal.b rd r:w next shal.b #2,rd r:w next shal.w rd r:w next shal.w #2,rd r:w next shal.l erd r:w next shal.l #2,erd r:w next shar.b rd r:w next shar.b #2,rd r:w next shar.w rd r:w next shar.w #2,rd r:w next shar.l erd r:w next shar.l #2,erd r:w next shll.b rd r:w next shll.b #2,rd r:w next shll.w rd r:w next shll.w #2,rd r:w next shll.l erd r:w next shll.l #2,erd r:w next shlr.b rd r:w next shlr.b #2,rd r:w next shlr.w rd r:w next shlr.w #2,rd r:w next shlr.l erd r:w next shlr.l #2,erd r:w next 686 table a.6 instruction execution cycle (cont) instruction 123456789 sleep r:w next internal operation :m stc ccr,rd r:w next stc exr,rd r:w next stc ccr,@erd r:w 2nd r:w next w:w ea stc exr,@erd r:w 2nd r:w next w:w ea stc ccr, @(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc exr, @(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc ccr, @(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc exr, @(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc ccr,@-erd r:w 2nd r:w next internal operation, 1 state w:w ea stc exr,@-erd r:w 2nd r:w next internal operation, 1 state w:w ea stc ccr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc exr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stc exr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stm.l (ern-ern+1),@-sp r:w 2nd r:w:m next internal operation, 1 state w:w:m stack (h) * 3 w:w stack (l) * 3 stm.l (ern-ern+2),@-sp r:w 2nd r:w:m next internal operation, 1 state w:w:m stack (h) * 3 w:w stack (l) * 3 stm.l (ern-ern+3),@-sp r:w 2nd r:w:m next internal operation, 1 state w:w:m stack (h) * 3 w:w stack (l) * 3 stmac mach,erd cannot be used in the h8s/2128 series and h8s/2124 series stmac macl,erd sub.b rs,rd r:w next sub.w #xx:16,rd r:w 2nd r:w next sub.w rs,rd r:w next sub.l #xx:32,erd r:w 2nd r:w 3rd r:w next sub.l ers,erd r:w next 687 table a.6 instruction execution cycle (cont) instruction 123456789 subs #1/2/4,erd r:w next subx #xx:8,rd r:w next subx rs,rd r:w next tas @erd r:w 2nd r:w next r:b:m ea w:b ea trapa #x:2 advanced r:w next internal operation, 1 state w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, 1 state r:w * 7 xor.b #xx8,rd r:w next xor.b rs,rd r:w next xor.w #xx:16,rd r:w 2nd r:w next xor.w rs,rd r:w next xor.l #xx:32,erd r:w 2nd r:w 3rd r:w next xor.l ers,erd r:w 2nd r:w next xorc #xx:8,ccr r:w next xorc #xx:8,exr r:w 2nd r:w next reset excep- tion handling advanced r:w:m vec r:w vec+2 internal operation, 1 state r:w * 5 interrupt excep- tion handling advanced r:w * 6 internal operation, 1 state w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, 1 state r:w * 7 notes: 1. eas is the contents of er5. ead is the contents of er6. 2. eas is the contents of er5. ead is the contents of er6. both registers are incremented by 1 after execution of the instruction. n is the initial value of r4l or r4. if n = 0, these bus cycles are not executed. 3. repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. start address after return. 5. start address of the program. 6. prefetch address, equal to two plus the pc value pushed onto the stack. in recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. start address of the interrupt-handling routine. 688 689 appendix b internal i/o registers b.1 addresses address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ec00 mra sm1 sm0 dm1 dm0 md1 md0 dts sz dtc 16/32 * to sar h'efff mrb chne disel dar cra crb h'fee4 kbcomp ire ircks2 ircks1 ircks0 kbade kbch2 kbch1 kbch0 expansion a/d 8 h'fee6 ddcswr swe sw ie if clr3 clr2 clr1 clr0 iic0 8 h'fee8 icra icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 interrupt 8 h'fee9 icrb icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 controller h'feea icrc icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 h'feeb isr irq2f irq1f irq0f h'feec iscrh h'feed iscrl irq2scb irq2sca irq1scb irq1sca irq0scb irq0sca h'feee dtcera dtcea7 dtcea6 dtcea5 dtcea4 dtcea3 dtcea2 dtcea1 dtcea0 dtc 8 h'feef dtcerb dtceb7 dtceb6 dtceb5 dtceb4 dtceb3 dtceb2 dtceb1 dtceb0 h'fef0 dtcerc dtcec7 dtcec6 dtcec5 dtcec4 dtcec3 dtcec2 dtcec1 dtcec0 h'fef1 dtcerd dtced7 dtced6 dtced5 dtced4 dtced3 dtced2 dtced1 dtced0 h'fef2 dtcere dtcee7 dtcee6 dtcee5 dtcee4 dtcee3 dtcee2 dtcee1 dtcee0 h'fef3 dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 h'fef4 abrkcr cmf bie interrupt 8 h'fef5 bara a23 a22 a21 a20 a19 a18 a17 a16 controller h'fef6 barb a15 a14 a13 a12 a11 a10 a9 a8 h'fef7 barc a7 a6 a5 a4 a3 a2 a1 690 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ff80 flmcr1 fwe swe ev pv e p flash 8 h'ff81 flmcr2 fler esu psu h'ff82 pcsr pwckb pwcka pwm 8 ebr1 eb9 eb8 flash 8 h'ff83 ebr2 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ff84 sbycr ssby sts2 sts1 sts0 sck2 sck1 sck0 system 8 h'ff85 lpwrcr dton lson nesel excle h'ff86 mstpcrh mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 h'ff87 mstpcrl mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 h'ff88 smr1 c/ $ chr pe o/ ( stop mp cks1 cks0 sci1 8 iccr1 ice ieic mst trs acke bbsy iric scp iic1 h'ff89 brr1 sci1 8 icsr1 estp stop irtr aasx al aas adz ackb iic1 h'ff8a scr1 tie rie te re mpie teie cke1 cke0 sci1 8 h'ff8b tdr1 h'ff8c ssr1 tdre rdrf orer fer per tend mpb mpbt h'ff8d rdr1 h'ff8e scmr1 sdir sinv smif icdr1 icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 iic1 8 sarx1 svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx h'ff8f icmr1 mls wait cks2 cks1 cks0 bc2 bc1 bc0 sar1 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs h'ff90 tier iciae icibe icice icide ociae ocibe ovie frt 16 h'ff91 tcsr icfa icfb icfc icfd ocfa ocfb ovf cclra h'ff92 frch h'ff93 frcl h'ff94 ocrah ocrbh h'ff95 ocral ocrbl h'ff96 tcr iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 h'ff97 tocr icrdms ocrams icrs ocrs oea oeb olvla olvlb h'ff98 icrah ocrarh 691 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ff99 icral frt 16 ocrarl h'ff9a icrbh ocrafh h'ff9b icrbl ocrafl h'ff9c icrch ocrdmh 0 0 0 0 0 0 0 0 h'ff9d icrcl ocrdml h'ff9e icrdh h'ff9f icrdl h'ffa0 dadrah da13 da12 da11 da10 da9 da8 da7 da6 pwmx 8 dacr test pwme oeb oea os cks h'ffa1 dadral da5 da4 da3 da2 da1 da0 cfs h'ffa6 dadrbh da13 da12 da11 da10 da9 da8 da7 da6 dacnth h'ffa7 dadrbl da5 da4 da3 da2 da1 da0 cfs regs dacntl regs h'ffa8 tcsr0 ovf wt/ ,7 tme rsts rst/ 10, cks2 cks1 cks0 wdt0 16 tcnt0 (write) h'ffa9 tcnt0 (read) h'ffac p1pcr p17pcr p16pcr p15pcr p14pcr p13pcr p12pcr p11pcr p10pcr ports 8 h'ffad p2pcr p27pcr p26pcr p25pcr p24pcr p23pcr p22pcr p21pcr p20pcr h'ffae p3pcr p37pcr p36pcr p35pcr p34pcr p33pcr p32pcr p31pcr p30pcr h'ffb0 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr h'ffb1 p2ddr p27ddr p26ddr p25ddr p24ddr p23ddr p22ddr p21ddr p20ddr h'ffb2 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr h'ffb3 p2dr p27dr p26dr p25dr p24dr p23dr p22dr p21dr p20dr h'ffb4 p3ddr p37ddr p36ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr h'ffb5 p4ddr p47ddr p46ddr p45ddr p44ddr p43ddr p42ddr p41ddr p40ddr h'ffb6 p3dr p37dr p36dr p35dr p34dr p33dr p32dr p31dr p30dr h'ffb7 p4dr p47dr p46dr p45dr p44dr p43dr p42dr p41dr p40dr h'ffb8 p5ddr p52ddr p51ddr p50ddr h'ffb9 p6ddr p67ddr p66ddr p65ddr p64ddr p63ddr p62ddr p61ddr p60ddr h'ffba p5dr p52dr p51dr p50dr 692 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ffbb p6dr p67dr p66dr p65dr p64dr p63dr p62dr p61dr p60dr ports 8 h'ffbe p7pin p77pin p76pin p75pin p74pin p73pin p72pin p71pin p70pin h'ffc2 ier irq2e irq1e irq0e interrupt controller 8 h'ffc3 stcr iics iicx1 iicx0 iice flshe icks1 icks0 system 8 h'ffc4 syscr cs2e iose intm1 intm0 xrst nmieg hie rame h'ffc5 mdcr expe mds1 mds0 h'ffc6 bcr icis1 icis0 brstrm brsts1 brsts0 ios1 ios0 bus 8 h'ffc7 wscr rams ram0 abw ast wms1 wms0 wc1 wc0 controller h'ffc8 tcr0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr0, 16 h'ffc9 tcr1 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr1 h'ffca tcsr0 cmfb cmfa ovf adte os3 os2 os1 os0 h'ffcb tcsr1 cmfb cmfa ovf os3 os2 os1 os0 h'ffcc tcora0 h'ffcd tcora1 h'ffce tcorb0 h'ffcf tcorb1 h'ffd0 tcnt0 h'ffd1 tcnt1 h'ffd2 pwoerb oe15 oe14 oe13 oe12 oe11 oe10 oe9 oe8 pwm 8 h'ffd3 pwoera oe7 oe6 oe5 oe4 oe3 oe2 oe1 oe0 h'ffd4 pwdprb os15 os14 os13 os12 os11 os10 os9 os8 h'ffd5 pwdpra os7 os6 os5 os4 os3 os2 os1 os0 h'ffd6 pwsl pwcke pwcks rs3 rs2 rs1 rs0 h'ffd7 pwdr0 to pwdr15 h'ffd8 smr0 c/ $ chr pe o/ ( stop mp cks1 cks0 sci0 8 iccr0 ice ieic mst trs acke bbsy iric scp iic0 h'ffd9 brr0 sci0 icsr0 estp stop irtr aasx al aas adz ackb iic0 h'ffda scr0 tie rie te re mpie teie cke1 cke0 sci0 h'ffdb tdr0 h'ffdc ssr0 tdre rdrf orer fer per tend mpb mpbt h'ffdd rdr0 h'ffde scmr0 sdir sinv smif icdr0 icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 iic0 sarx0 svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx 693 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name bus width h'ffdf icmr0 mls wait cks2 cks1 cks0 bc2 bc1 bc0 iic0 8 sar0 sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs h'ffe0 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d 8 h'ffe1 addral ad1 ad0 h'ffe2 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffe3 addrbl ad1 ad0 h'ffe4 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffe5 addrcl ad1 ad0 h'ffe6 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffe7 addrdl ad1 ad0 h'ffe8 adcsr adf adie adst scan cks ch2 ch1 ch0 h'ffe9 adcr trgs1 trgs0 h'ffea tcsr1 ovf wt/ ,7 tme pss rst/ 10, cks2 cks1 cks0 wdt1 16 tcnt1 (write) h'ffeb tcnt1 (read) h'fff0 tcrx cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmrx 8 tcry cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmry h'fff1 tcsrx cmfb cmfa ovf icf os3 os2 os1 os0 tmrx tcsry cmfb cmfa ovf icie os3 os2 os1 os0 tmry h'fff2 ticrr tmrx tcoray tmry h'fff3 ticrf tmrx tcorby tmry h'fff4 tcntx tmrx tcnty tmry h'fff5 tcorc tmrx tisr is tmry h'fff6 tcorax tmrx h'fff7 tcorbx h'fffc tconri simod1 simod0 scone icst hfinv vfinv hiinv viinv timer 8 h'fffd tconro hoe voe cloe cboe hoinv voinv cloinv cboinv connection h'fffe tconrs tmrx/y isgene homod1 homod0 vomod1 vomod0 clmod1 clmod0 h'ffff sedgr vedg hedg cedg hfedg vfedg preqf ihi ivi 694 b.2 register selection conditions lower address register name h8s/2128 series register selection conditions h8s/2124 series register selection conditions module name h'ec00 to h'efff mra sar mrb rame = 1 in syscr dtc dar cra crb h'fee4 kbcomp no conditions no conditions expansion a/d h'fee6 ddcswr mstp4 = 0 iic0 h'fee8 icra no conditions no conditions interrupt h'fee9 icrb controller h'feea icrc h'feeb isr h'feec iscrh h'feed iscrl h'feee dtcera no conditions dtc h'feef dtcerb h'fef0 dtcerc h'fef1 dtcerd h'fef2 dtcere h'fef3 dtvecr h'fef4 abrkcr no conditions no conditions interrupt h'fef5 bara controller h'fef6 barb h'fef7 barc h'ff80 flmcr1 flshe = 1 in stcr flshe = 1 in stcr flash h'ff81 flmcr2 memory h'ff82 pcsr flshe = 0 in stcr flshe = 0 in stcr pwm ebr1 flshe = 1 in stcr flshe = 1 in stcr flash memory h'ff83 ebr2 flshe = 1 in stcr flshe = 1 in stcr flash memory h'ff84 sbycr flshe = 0 in stcr flshe = 0 in stcr system h'ff85 lpwrcr h'ff86 mstpcrh h'ff87 mstpcrl 695 lower address register name h8s/2128 series register selection conditions h8s/2124 series register selection conditions module name h'ff88 smr1 mstp6=0, iice=0 in stcr mstp6=0, iice=0 in stcr sci1 iccr1 mstp3=0, iice=1 in stcr iic1 h'ff89 brr1 mstp6=0, iice=0 in stcr mstp6=0, iice=0 in stcr sci1 icsr1 mstp3=0, iice=1 in stcr iic1 h'ff8a scr1 mstp6=0 mstp6=0 sci1 h'ff8b tdr1 h'ff8c ssr1 h'ff8d rdr1 h'ff8e scmr1 mstp6=0, iice=0 in stcr mstp6=0, iice=0 in stcr icdr1 mstp3=0, iice=1 in stcr ice=1 in iccr1 iic1 sarx1 ice = 0 in iccr1 h'ff8f icmr1 ice = 1 in iccr1 sar1 ice = 0 in iccr1 h'ff90 tier mstp13 = 0 mstp13 = 0 frt h'ff91 tcsr h'ff92 frch h'ff93 frcl h'ff94 ocrah ocrbh h'ff95 ocral ocrbl h'ff96 tcr h'ff97 tocr h'ff98 icrah ocrarh h'ff99 icral ocrarl h'ff9a icrbh ocrafh h'ff9b icrbl ocrafl h'ff9c icrch ocrdmh h'ff9d icrcl ocrdml 696 lower address register name h8s/2128 series register selection conditions h8s/2124 series register selection conditions module name h'ff9e icrdh mstp13 = 0 mstp13 = 0 frt h'ff9f icrdl h'ffa0 dadrah mstp11 = 0, iice = 1 in stcr regs = 0 in dacnt/ dadrb pwmx dacr regs = 1 in dacnt/ dadrb h'ffa1 dadral mstp11 = 0, iice = 1 in stcr regs = 0 in dacnt/ dadrb pwmx h'ffa6 dadrbh mstp11 = 0, iice = 1 in stcr regs = 0 in dacnt/ dadrb dacnth regs = 1 in dacnt/ dadrb h'ffa7 dadrbl regs = 0 in dacnt/ dadrb dacntl regs = 1 in dacnt/ dadrb h'ffa8 tcsr0 no conditions no conditions wdt0 tcnt0 (write) h'ffa9 tcnt0 (read) h'ffac p1pcr no conditions no conditions ports h'ffad p2pcr h'ffae p3pcr h'ffb0 p1ddr h'ffb1 p2ddr h'ffb2 p1dr h'ffb3 p2dr h'ffb4 p3ddr h'ffb5 p4ddr h'ffb6 p3dr h'ffb7 p4dr h'ffb8 p5ddr h'ffb9 p6ddr h'ffba p5dr h'ffbb p6dr 697 lower address register name h8s/2128 series register selection conditions h8s/2124 series register selection conditions module name h'ffbe p7pin no conditions no conditions ports h'ffc2 ier no conditions no conditions interrupt controller h'ffc3 stcr no conditions no conditions system h'ffc4 syscr h'ffc5 mdcr h'ffc6 bcr bus h'ffc7 wscr controller h'ffc8 tcr0 mstp12 = 0 mstp12 = 0 tmr0, h'ffc9 tcr1 tmr1 h'ffca tcsr0 h'ffcb tcsr1 h'ffcc tcora0 h'ffcd tcora1 h'ffce tcorb0 h'ffcf tcorb1 h'ffd0 tcnt0 h'ffd1 tcnt1 h'ffd2 pwoerb no conditions pwm h'ffd3 pwoera h'ffd4 pwdprb h'ffd5 pwdpra h'ffd6 pwsl mstp11 = 0 h'ffd7 pwdr0 to 15 h'ffd8 smr0 mstp7 = 0, iice = 0 in stcr mstp7 = 0, iice = 0 in stcr sci0 iccr0 mstp4 = 0, iice = 1 in stcr iic0 h'ffd9 brr0 mstp7 = 0, iice = 0 in stcr mstp7 = 0, iice = 0 in stcr sci0 icsr0 mstp4 = 0, iice = 1 in stcr iic0 h'ffda scr0 mstp7 = 0 mstp7 = 0 sci0 h'ffdb tdr0 h'ffdc ssr0 h'ffdd rdr0 h'ffde scmr0 mstp7 = 0, iice = 0 in stcr mstp7 = 0, iice = 0 in stcr icdr0 mstp4 = 0, iice = 1 in stcr ice = 1 in iccr0 iic0 sarx0 ice = 0 in iccr0 698 lower address register name h8s/2128 series register selection conditions h8s/2124 series register selection conditions module name h'ffdf icmr0 mstp4 = 0, iice = 1 in stcr ice = 1 in iccr0 iic0 sar0 ice = 0 in iccr0 h'ffe0 addrah mstp9 = 0 mstp9 = 0 a/d h'ffe1 addral h'ffe2 addrbh h'ffe3 addrbl h'ffe4 addrch h'ffe5 addrcl h'ffe6 addrdh h'ffe7 addrdl h'ffe8 adcsr h'ffe9 adcr h'ffea tcsr1 no conditions no conditions wdt1 tcnt1 (write) h'ffeb tcnt1 (read) h'fff0 tcrx mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs tmrx tcry tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmry h'fff1 tcsrx mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs tmrx tcsry tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmry h'fff2 ticrr mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs tmrx tcoray tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmry h'fff3 ticrf mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs tmrx tcorby tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmry h'fff4 tcntx mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs tmrx tcnty tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmry h'fff5 tcorc mstp8 = 0, hie = 0 in syscr tmrx/y = 0 in tconrs tmrx tisr tmrx/y = 1 in tconrs mstp8 = 0, hie = 0 in syscr tmry 699 lower address register name h8s/2128 series register selection conditions h8s/2124 series register selection conditions module name h'fff6 tcorax mstp8 = 0, hie = 0 in syscr tmrx/y = 0 tmrx h'fff7 tcorbx in tconrs h'fffc tconri mstp8 = 0, hie = 0 in syscr timer h'fffd tconro connection h'fffe tconrs h'ffff sedgr 700 b.3 functions dacr?/a control register h'fffa d/a converter register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes (? indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 ? 1 3 ? 1 0 ? 1 2 ? 1 1 ? 1 d/a enabled daoe1 0 1 conversion result dae * 0 1 0 1 * daoe0 0 1 0 1 channel 0 and 1 d/a conversion disabled channel 0 d/a conversion enabled channel 1 d/a conversion disabled channel 0 and 1 d/a conversion enabled channel 0 d/a conversion disabled channel 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled channel 0 and 1 d/a conversion enabled d/a output enable 0 0 analog output da0 disabled 1 channel 0 d/a conversion enabled. analog output da0 enabled d/a output enable 1 0 analog output da1 disabled 1 channel 1 d/a conversion enabled. analog output da1 enabled 701 mradtc mode register a h'ec00Ch'efff dtc 7 sm1 undefined 6 sm0 undefined 5 dm1 undefined 4 dm0 undefined 3 md1 undefined 0 sz undefined 2 md0 undefined 1 dts undefined bit initial value read/write dtc data transfer size 0 byte-size transfer 1 word-size transfer dtc transfer mode select 0 destination side is repeat area or block area 1 source side is repeat area or block area dtc mode 0 normal mode repeat mode 0 1 1 block transfer mode 0 1 destination address mode 0 dar is fixed dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 0 1 dar is decremented after a transfer (by ? when sz = 0; by ? when sz = 1) 1 source address mode 0 sar is fixed sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 0 1 sar is decremented after a transfer (by ? when sz = 0; by ? when sz = 1) 1 702 mrbdtc mode register b h'ec00Ch'efff dtc 7 chne undefined 6 disel undefined 5 ? undefined 4 ? undefined 3 ? undefined 0 ? undefined 2 ? undefined 1 ? undefined bit initial value read/write dtc interrupt select 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 1 after a data transfer ends, the cpu interrupt is enabled dtc chain transfer enable 0 end of dtc data transfer 1 dtc chain transfer sardtc source address register h'ec00C h'efff dtc 23 unde- fined bit initial value read/write 22 unde- fined 21 unde- fined 20 unde- fined 19 unde- fined 4 unde- fined 3 unde- fined 2 unde- fined 1 unde- fined 0 unde- fined - - - - - - - - - - - - specifies dtc transfer data source address dardtc destination address register h'ec00Ch'efff dtc 23 unde- fined bit initial value read/write 22 unde- fined 21 unde- fined 20 unde- fined 19 unde- fined 4 unde- fined 3 unde- fined 2 unde- fined 1 unde- fined 0 unde- fined - - - - - - - - - - - - specifies dtc transfer data destination address 703 cradtc transfer count register a h'ec00C h'efff dtc 15 unde- fined bit initial value read/write 14 unde- fined 13 unde- fined 12 unde- fined 11 unde- fined 10 unde- fined 9 unde- fined 8 unde- fined 7 unde- fined 6 unde- fined 5 unde- fined 4 unde- fined 3 unde- fined 2 unde- fined 1 unde- fined 0 unde- fined crah cral specifies the number of dtc data transfers crbdtc transfer count register b h'ec00C h'efff dtc 15 unde- fined bit initial value read/write 14 unde- fined 13 unde- fined 12 unde- fined 11 unde- fined 10 unde- fined 9 unde- fined 8 unde- fined 7 unde- fined 6 unde- fined 5 unde- fined 4 unde- fined 3 unde- fined 2 unde- fined 1 unde- fined 0 unde- fined specifies the number of dtc block data transfers 704 kbcompkeyboard comparator control register h'fee4 comp 7 ire 0 r/w 6 ircks2 0 r/w 5 ircks1 0 r/w 4 ircks0 0 r/w 3 kbade 0 r/w 0 kbch0 0 r/w 2 kbch2 0 r/w 1 kbch1 0 r/w bit initial value read/write an6 cin0 cin1 cin2 cin3 cin4 cin5 cin6 cin7 keyboard comparator control reserved bits bit 3 kbade 0 1 a/d converter channel 6 input an7 undefined a/d converter channel 7 input bit 3 kbch2 ? 0 1 bit 3 kbch1 ? 0 1 0 1 bit 3 kbch0 ? 0 1 0 1 0 1 0 1 705 ddcswrddc switch register h'fee6 iic0 7 swe 0 r/w 6 sw 0 r/w 5 ie 0 r/w 4 if 0 r/(w) * 1 3 clr3 1 w * 2 0 clr0 1 w * 2 2 clr2 1 w * 2 1 clr1 1 w * 2 bit initial value read/write ddc mode switch interrupt flag 0 no interrupt is requested when automatic format switching is executed [clearing condition] when 0 is written in if after reading if = 1 1 an interrupt is requested when automatic format switching is executed [setting condition] when a falling edge is detected on the scl pin when swe = 1 ddc mode switch interrupt enable bit 0 interrupt when automatic format switching is executed is disabled 1 interrupt when automatic format switching is executed is enabled ddc mode switch 0 iic channel 0 is used with the i 2 c bus format [clearing conditions] ? when 0 is written by software ? when a falling edge is detected on the scl pin when swe = 1 1 iic channel 0 is used in formatless mode [setting condition] when 1 is written in sw after reading sw = 0 ddc mode switch enable 0 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is disabled 1 automatic switching of iic channel 0 from formatless mode to i 2 c bus format is enabled notes: 1. only 0 can be written, to clear the flag. 2. always read as 1. iic clear bits bit 3 clr3 0 1 description setting prohibited setting prohibited iic0 internal latch cleared iic1 internal latch cleared iic0 and iic1 internal latches cleared invalid setting bit 2 clr2 0 1 bit 1 clr1 ? 0 1 bit 0 clr0 ? 0 1 0 1 706 icrainterrupt control register a h'fee8 interrupt controller icrbinterrupt control register b h'fee9 interrupt controller icrcinterrupt control register c h'feea interrupt controller 7 icr7 0 r/w 6 icr6 0 r/w 5 icr5 0 r/w 4 icr4 0 r/w 3 icr3 0 r/w 0 icr0 0 r/w 2 icr2 0 r/w 1 icr1 0 r/w bit initial value read/write interrupt control level 0 corresponding interrupt source is control level 0 (non-priority) 1 corresponding interrupt source is control level 1 (priority) correspondence between interrupt sources and icr settings register bits 76543210 icra irq0 irq1 irq2 dtc watchdog timer 0 watchdog timer 1 icrb a/d converter free- running timer ? 8-bit timer channel 0 8-bit timer channel 1 8-bit timer channels x, y icrc sci channel 0 sci channel 1 iic channel 0 (option) iic channel 1 (option) 707 isrirq status register h'feeb interrupt controller 7 ? 0 r/(w) * 6 ? 0 r/(w) * 5 ? 0 r/(w) * 4 ? 0 r/(w) * 3 ? 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value read/write irq2 to irq0 flags 0 [clearing conditions] ? when 0 is written in irqnf after reading irqnf = 1 ? when interrupt exception handling is executed while low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed while falling, rising, or both-edge detection is set (irqnscb = 1 or irqnsca = 1) 1 [setting conditions] ? when irqn input goes low while low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input while falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input while rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input while both-edge detection is set (irqnscb = irqnsca = 1) note: * only 0 can be written, to clear the flag. (n = 2 to 0) 708 iscrhirq sense control register h h'feec interrupt controller iscrlirq sense control register l h'feed interrupt controller 15 ? 0 r/w 14 ? 0 r/w 13 ? 0 r/w 12 ? 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write iscrh 7 0 r/w 6 ? 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value read/write iscrl reserved irq2 to irq0 sense control a and b description iscrl bits 5? irq2scb? irq0scb irq2sca? irq0sca 0 1 0 1 0 1 interrupt request generated by low level of irq2 irq0 input interrupt request generated by falling edge of irq2 irq0 input interrupt request generated by rising edge of irq2 irq0 input interrupt request generated by rising and falling edges of irq2 irq0 input 709 dtcerdtc enable register h'ffee to h'fff2 dtc 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value read/write dtc activation enable 0 dtc activation by interrupt is disabled [clearing conditions] ? when data transfer ends while the disel bit is 1 ? when the specified number of transfers are completed 1 dtc activation by interrupt is enabled [maintenance condition] when the disel bit is 0 and the specified number of transfers have not been completed dtvecrdtc vector register h'fef3 dtc 7 swdte 0 r/(w) * 6 dtvec6 0 r/w 5 dtvec5 0 r/w 4 dtvec4 0 r/w 3 dtvec3 0 r/w 0 dtvec0 0 r/w 2 dtvec2 0 r/w 1 dtvec1 0 r/w bit initial value read/write note: * sets vector number for dtc software activation dtc software activation enable 0 dtc software activation is disabled [clearing condition] when the disel bit is 0 and the specified number of transfers have not been completed 1 dtc software activation is enabled [maintenance conditions] ? when data transfer ends while the disel bit is 1 ? when the specified number of transfers are completed ? during data transfer activated by software a value of 1 can always be written to the swdte bit, but 0 can only be written after 1 is read. 710 abrkcraddress break control register h'fef4 interrupt controller 7 cmf 0 r/w 6 ? 0 5 ? 0 4 ? 0 3 ? 0 0 bie 0 r/w 2 ? 0 1 ? 0 bit initial value read/write break interrupt enable 0 address break disabled 1 address break enabled condition match flag 0 [clearing condition] when address break interrupt exception handling is executed 1 [setting condition] when address set by bara?arc is prefetched while bie = 1 711 barabreak address register a h'fef5 interrupt controller barbbreak address register b h'fef6 interrupt controller barcbreak address register c h'fef7 interrupt controller 7 a23 0 r/w 6 a22 0 r/w 5 a21 0 r/w 4 a20 0 r/w 3 a19 0 r/w 0 a16 0 r/w 2 a18 0 r/w 1 a17 0 r/w bit bara initial value read/write 7 a15 0 r/w 6 a14 0 r/w 5 a13 0 r/w 4 a12 0 r/w 3 a11 0 r/w 0 a8 0 r/w 2 a10 0 r/w 1 a9 0 r/w bit barb initial value read/write 7 a7 0 r/w 6 a6 0 r/w 5 a5 0 r/w 4 a4 0 r/w 3 a3 0 r/w 0 ? 0 2 a2 0 r/w 1 a1 0 r/w bit barc initial value read/write specifies address (bits 23?6) at which address break is to be generated specifies address (bits 15?) at which address break is to be generated specifies address (bits 7?) at which address break is to be generated 712 flmcr1flash memory control register 1 h'ff80 flash memory 7 fwe 1 r 6 swe 0 r/w 5 ? 0 4 ? 0 3 ev 0 r/w 0 p 0 r/w 2 pv 0 r/w 1 e 0 r/w bit initial value read/write program 0 program mode cleared 1 transition to program mode [setting condition] when swe = 1, and psu = 1 erase 0 erase mode cleared 1 transition to erase mode [setting condition] when swe = 1, and esu = 1 program-verify 0 program-verify mode cleared 1 transition to program-verify mode [setting condition] when swe = 1 erase-verify 0 erase-verify mode cleared 1 transition to erase-verify mode [setting condition] when swe = 1 software write enable 0 writes disabled 1 writes enabled reserved 713 flmcr2flash memory control register 2 h'ff81 flash memory 7 fler 0 r 6 ? 0 5 ? 0 4 ? 0 3 ? 0 0 psu 0 r/w 2 ? 0 1 esu 0 r/w bit initial value read/write program setup bit 0 program setup cleared 1 program setup [setting condition] when swe = 1 erase setup bit 0 erase setup cleared 1 erase setup [setting condition] when swe = 1 flash memory error 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 19.8.3, error protection 714 pcsrperipheral clock select register h'ff82 pwm 7 ? 0 6 ? 0 5 ? 0 4 ? 0 3 ? 0 0 ? 0 2 pwckb 0 r/w 1 pwcka 0 r/w bit initial value read/write pwm clock select pwsl pcsr bit 7 pwcke 0 1 bit 6 pwcks ? 0 1 bit 2 pwckb ? ? 0 1 bit 1 pwcka ? ? 0 1 0 1 clock input disabled ?(system clock) selected ?2 selected ?4 selected ?8 selected ?16 selected description 715 ebr1erase block register 1 h'ff82 flash memory ebr2erase block register 2 h'ff83 flash memory 7 ? 0 6 ? 0 5 ? 0 4 ? 0 3 ? 0 0 eb8 0 r/w * 2 ? 0 1 eb9 0 r/w * bit initial value read/write 7 eb7 0 r/w * 6 eb6 0 r/w 5 eb5 0 r/w 4 eb4 0 r/w 3 eb3 0 r/w 0 eb0 0 r/w 2 eb2 0 r/w 1 eb1 0 r/w bit initial value read/write block (size) 128-kbyte versions erase blocks eb0 (1 kbyte) eb1 (1 kbyte) eb2 (1 kbyte) eb3 (1 kbyte) eb4 (28 kbytes) eb5 (16 kbytes) eb6 (8 kbytes) eb7 (8 kbytes) eb8 (32 kbytes) eb9 (32 kbytes) addresses h'(00)0000?'(00)03ff h'(00)4000?'(00)07ff h'(00)8000?'(00)0bff h'(00)c000?'(00)0fff h'(00)1000?'(00)7fff h'(00)8000?'(00)bfff h'(00)c000?'(00)dfff h'00e000?'00ffff h'010000?'017fff h'018000?'01ffff note: * in normal mode, a read will return 0, and writes are invalid. 716 sbycrstandby control register h'ff84 system 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ? 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value read/write 0 1 0 1 0 1 0 1 0 1 bus master is in high-speed mode medium-speed clock = ?2 medium-speed clock = ?4 medium-speed clock = ?8 medium-speed clock = ?16 medium-speed clock = ?32 ? 0 1 system clock select 2 to 0 0 1 0 1 0 1 0 1 0 1 0 1 standby time = 8192 states standby time = 16384 states standby time = 32768 states standby time = 65536 states standby time = 131072 states standby time = 262144 states reserved standby time = 16 states * 0 1 standby timer select 2 to 0 software standby note: * this setting must not be used in the flash memory version. 0 transition to sleep mode on execution of sleep instruction in high-speed mode or medium-speed mode transition to subsleep mode on execution of sleep instruction in subactive mode 1 transition to software standby mode, subactive mode, or watch mode on execution of sleep instruction in high-speed mode or medium-speed mode transition to watch mode or high-speed mode on execution of sleep instruction in subactive mode 717 lpwrcrlow-power control register h'ff85 system 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 excle 0 r/w 3 ? 0 0 ? 0 2 ? 0 1 ? 0 bit initial value read/write subclock input enable 0 subclock input from excl pin disabled 1 subclock input from excl pin enabled noise elimination sampling frequency select 0 sampling at ?divided by 32 1 sampling at ?divided by 4 low-speed on flag 0 transition to sleep mode, software standby mode, or watch mode * on execution of sleep instruction in high-speed mode or medium-speed mode ? transition to watch mode, or direct transition to high-speed mode, on execution of sleep instruction in subactive mode ? transition to high-speed mode after watch mode is cleared 1 transition to watch mode or subactive mode * on execution of sleep instruction in high-speed mode ? transition to subsleep mode or watch mode on execution of sleep instruction in subactive mode ? transition to subactive mode after watch mode is cleared direct transfer on flag 0 transition to sleep mode, software standby mode, or watch mode * on execution of sleep instruction in high-speed mode or medium-speed mode ? transition to subsleep mode or watch mode on execution of sleep instruction in subactive mode 1 direct transition to subactive mode * , or transition to sleep mode or software standby mode, on execution of sleep instruction in high-speed mode or medium-speed mode ? direct transition to high-speed mode, or transition to subsleep mode, on execution of sleep instruction in subactive mode note: * when a transition is made to watch mode or subactive mode, high-speed mode must be set. note: * when a transition is made to watch mode or subactive mode, high-speed mode must be set. 718 mstpcrhmodule stop control register h h'ff86 system mstpcrlmodule stop control register l h'ff87 system 7 mstp15 0 r/w bit initial value read/write 6 mstp14 0 r/w 5 mstp13 1 r/w 4 mstp12 1 r/w 3 mstp11 1 r/w 2 mstp10 1 r/w 1 mstp9 1 r/w 0 mstp8 1 r/w 7 mstp7 1 r/w 6 mstp6 1 r/w 5 mstp5 1 r/w 4 mstp4 1 r/w 3 mstp3 1 r/w 2 mstp2 1 r/w 1 mstp1 1 r/w 0 mstp0 1 r/w mstpcrh mstpcrl module stop 0 module stop mode cleared 1 module stop mode set mstp15 mstp14 * mstp13 mstp12 mstp11 * mstp10 * mstp9 mstp8 mstp7 mstp6 * mstp5 * mstp4 * mstp3 * mstp2 * mstp1 * mstp0 * ? data transfer controller (dtc) 16-bit free-running timer (frt) 8-bit timers (tmr0, tmr1) 8-bit pwm timer (pwm), 14-bit pwm timer (pwmx) ? a/d converter 8-bit timers (tmrx, tmry), timer connection serial communication interface 0 (sci0) serial communication interface 1 (sci1) ? i 2 c bus interface (iic) channel 0 (option) i 2 c bus interface (iic) channel 1 (option) ? ? ? mstpcrh mstpcrl register bit module the correspondence between mstpcr bits and on-chip supporting modules is shown below. note: bits 10, 5, 2, 1, and 0 can be read and written but do not affect operation. * must be set to 1 in the h8s/2124 series. 719 smr1serial mode register 1 smr0serial mode register 0 h'ff88 h'ffd8 sci1 sci0 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 1 and 0 0 clock ?4 clock ?16 clock ?64 clock 0 1 10 1 stop bit length 0 1 stop bit 2 stop bits 1 multiprocessor mode 0 multiprocessor function disabled 1 multiprocessor format selected parity mode 0 even parity odd parity 1 parity enable 0 parity bit addition and checking disabled parity bit addition and checking enabled 1 character length 0 8-bit data 7-bit data * 1 note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and the choice of lsb-first or msb-first mode is not available. communication mode 0 asynchronous mode synchronous mode 1 720 iccr1i 2 c bus control register 1 h'ff88 iic1 iccr0i 2 c bus control register 0 h'ffd8 iic0 7 ice 0 r/w 6 ieic 0 r/w 5 mst 0 r/w 4 trs 0 r/w 3 acke 0 r/w 0 scp 1 w 2 bbsy 0 r/w 1 iric 0 r/(w) * bit initial value read/write start condition/stop condition prohibit 0 writing issues a start or stop condition, in combination with the bbsy flag 1 reading always returns a value of 1; writing is ignored i 2 c bus interface interrupt request flag 0 waiting for transfer, or transfer in progress 1 interrupt requested note: for the clearing and setting conditions, see section 16.2.5, i 2 c bus control register (iccr). bus busy 0 bus is free [clearing condition] when a stop condition is detected 1 bus is busy [setting condition] when a start condition is detected acknowledge mode select 0 acknowledge bit is ignored and transfer is performed continuously 1 when acknowledge bit is 1, continuous transfer is discontinued master/slave select (mst), transmit/receive select (trs) 0 slave receive mode slave transmit mode master receive mode master transmit mode 0 1 10 1 i 2 c bus interface interrupt enable 0 interrupt requests disabled 1 interrupt requests enabled note: for details, see section 16.2.5, i 2 c bus control register (iccr). i 2 c bus interface enable 0 module is non-operational (scl/sda pin has port function) sar and sarx can be accessed 1 module is enabled for transfer operations (sc/sda pin in bus drive state) icmr and icdr can be accessed note: * only 0 can be written, to clear the flag. 721 brr1bit rate register 1 brr0bit rate register 0 h'ff89 h'ffd9 sci1 sci0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write sets the serial transmit/receive bit rate 722 icsr1i 2 c bus status register 1 h'ff89 iic1 icsr0i 2 c bus status register 0 h'ffd9 iic0 7 estp 0 r/(w) * 1 6 stop 0 r/(w) * 1 5 irtr 0 r/(w) * 1 4 aasx 0 r/(w) * 1 3 al 0 r/(w) * 1 0 ackb 0 r/w 2 aas 0 r/(w) * 1 1 adz 0 r/(w) * 1 bit initial value read/write acknowledge bit 0 receive mode: 0 is output at acknowledge output timing transmit mode: indicates that the receiving device has acknowledged the data (0 value) 1 receive mode: 1 is output at acknowledge output timing transmit mode: indicates that the receiving device has not acknowledged the data (1 value) notes: general call address recognition flag * 2 0 general call address not recognized 1 general call address recognized slave address recognition flag * 2 0 slave address or general call address not recognized 1 slave address or general call address recognized arbitration lost flag * 2 0 bus arbitration won 1 bus arbitration lost second slave address recognition flag * 2 0 second slave address not recognized 1 second slave address recognized i 2 c bus interface continuous transmission/reception interrupt request flag * 2 0 waiting for transfer, or transfer in progress 1 continuous transfer state normal stop condition detection flag * 2 0 no normal stop condition 1 in i 2 c bus format slave mode: normal stop condition detected in other modes: no meaning error stop condition detection flag * 2 0 no error stop condition 1 in i 2 c bus format slave mode: error stop condition detected in other modes: no meaning 1. only 0 can be written, to clear the flag. 2. for the clearing and setting conditions, see section 16.2.6, i 2 c bus status register (icsr). 723 scr1serial control register 1 scr0serial control register 0 h'ff8a h'ffda sci1 sci0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value read/write clock enable 1 and 0 0 asynchronous mode synchronous mode 0 1 asynchronous mode 0 synchronous mode 1 1 asynchronous mode 0 synchronous mode 1 asynchronous mode 0 synchronous mode 1 internal clock/sck pin functions as i/o port internal clock/sck pin functions as serial clock output internal clock/sck pin functions as clock output internal clock/sck pin functions as serial clock output external clock/sck pin functions as clock input external clock/sck pin functions as serial clock input external clock/sck pin functions as clock input external clock/sck pin functions as serial clock input transmit end interrupt enable 0 transmit end interrupt (tei) request disabled 1 transmit end interrupt (tei) request enabled multiprocessor interrupt enable 0 multiprocessor interrupts disabled (normal reception performed) [clearing conditions] ? when the mpie bit is cleared to 0 ? when data with mpb = 1 is received 1 multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received receive enable 0 reception disabled 1 reception enabled transmit enable 0 transmission disabled 1 transmission enabled receive interrupt enable 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled transmit interrupt enable 0 transmit data empty interrupt (txi) request disabled 1 transmit data empty interrupt (txi) request enabled 724 rdr1receive data register 1 rdr0receive data register 0 h'ff8d h'ffdd sci1 sci0 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write stores serial receive data tdr1transmit data register 1 tdr0transmit data register 0 h'ff8b h'ffdb sci1 sci0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write stores serial transmit data 725 ssr1serial status register 1 ssr0serial status register 0 h'ff8c h'ffdc sci1 sci0 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value read/write multiprocessor bit transfer 0 data with a 0 multiprocessor bit is transmitted 1 data with a 1 multiprocessor bit is transmitted note: * only 0 can be written, to clear the flag. multiprocessor bit 0 [clearing condition] when data with a 0 multiprocessor bit is received 1 [setting condition] when data with a 1 multiprocessor bit is received transmit end 0 [clearing conditions] ? when 0 is written in tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 [clearing condition] when 0 is written in per after reading per = 1 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr framing error 0 [clearing condition] when 0 is written in fer after reading fer = 1 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 overrun error 0 [clearing condition] when 0 is written in orer after reading orer = 1 1 [setting condition] when the next serial reception is completed while rdrf = 1 receive data register full 0 [clearing conditions] ? when 0 is written in rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt and reads data from rdr 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 [clearing conditions] ? when 0 is written in tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written in tdr 726 scmr1serial interface mode register 1 scmr0serial interface mode register 0 h'ff8e h'ffde sci1 sci0 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 ? 1 bit initial value read/write serial communication interface mode select 0 normal sci mode 1 setting prohibited data invert 0 tdr contents are transmitted as they are tdr contents are stored in rdr as they are 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form data transfer direction 0 tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first 727 icdr1i 2 c bus data register 1 h'ff8e iic1 icdr0i 2 c bus data register 0 h'ffde iic0 7 icdr7 ? r/w 6 icdr6 ? r/w 5 icdr5 ? r/w 4 icdr4 ? r/w 3 icdr3 ? r/w 0 icdr0 ? r/w 2 icdr2 ? r/w 1 icdr1 ? r/w bit initial value read/write 7 icdrr7 ? r 6 icdrr6 ? r 5 icdrr5 ? r 4 icdrr4 ? r 3 icdrr3 ? r 0 icdrr0 ? r 2 icdrr2 ? r 1 icdrr1 ? r bit initial value read/write icdrr icdrs 7 icdrs7 ? 6 icdrs6 ? 5 icdrs5 ? 4 icdrs4 ? 3 icdrs3 ? 0 icdrs0 ? 2 icdrs2 ? 1 icdrs1 ? bit initial value read/write icdrt 7 icdrt7 ? w 6 icdrt6 ? w 5 icdrt5 ? w 4 icdrt4 ? w 3 icdrt3 ? w 0 icdrt0 ? w 2 icdrt2 ? w 1 icdrt1 ? w bit initial value read/write tdre, rdrf (internal flags) ? rdrf 0 ? tdre 0 bit initial value read/write note: for details, see section 16.2.1, i 2 c bus data register (icdr). 728 sarx1second slave address register 1 h'ff8e iic1 sar1slave address register 1 h'ff8f iic1 sarx0second slave address register 0 h'ffde iic0 sar0slave address register 0 h'ffdf iic0 7 sva6 0 r/w 6 sva5 0 r/w 5 sva4 0 r/w 4 sva3 0 r/w 3 sva2 0 r/w 0 fs 0 r/w 2 sva1 0 r/w 1 sva0 0 r/w bit initial value read/write sar sarx slave address format select second slave address 7 svax6 0 r/w 6 svax5 0 r/w 5 svax4 0 r/w 4 svax3 0 r/w 3 svax2 0 r/w 0 fsx 1 r/w 2 svax1 0 r/w 1 svax0 0 r/w bit initial value read/write note: * format select ddcswr bit 6 sw sar bit 0 fs sarx bit 0 fsx operating mode i 2 c bus format ? sar and sarx slave addresses recognized 0 00 i 2 c bus format ? sar slave address recognized ? sarx slave address ignored i 2 c bus format ? sar slave address ignored ? sarx slave address recognized synchronous serial format ? sar and sarx slave addresses ignored formatless mode (start/stop conditions not detected) ? acknowledge bit present formatless mode * (start/stop conditions not detected) ? no acknowledge bit 1 10 1 100 1 10 1 do not select this mode when automatic switching to the i 2 c bus format is performed by means of a ddcswr setting. 729 icmr1i 2 c bus mode register 1 h'ff8f iic1 icmr0i 2 c bus mode register 0 h'ffdf iic0 7 mls 0 r/w 6 wait 0 r/w 5 cks2 0 r/w 4 cks1 0 r/w 3 cks0 0 r/w 0 bc0 0 r/w 2 bc2 0 r/w 1 bc1 0 r/w bit initial value read/write bit counter bc2 bc1 0 1 0 1 0 1 bc0 0 1 0 1 0 1 0 1 note: * do not set this bit to 1 when using the i 2 c bus format. synchronous serial format 8 1 2 3 4 5 6 7 i 2 c bus format 9 2 3 4 5 6 7 8 transfer clock select cks2 cks1 0 1 0 1 0 1 0 1 0 1 0 1 cks0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 iicx 0 1 clock ?28 ?40 ?48 ?64 ?80 ?100 ?112 ?128 ?56 ?80 ?96 ?128 ?160 ?200 ?224 ?256 wait insertion bit 0 data and acknowledge transferred consecutively 1 wait inserted between data and acknowledge msb-first/lsb-first select * 0 msb-first 1 lsb-first 730 tiertimer interrupt enable register h'ff90 frt 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w 3 ociae 0 r/w 0 ? 1 2 ocibe 0 r/w 1 ovie 0 r/w bit initial value read/write input capture interrupt a enable 0 icfa interrupt request (icia) is disabled 1 icfa interrupt request (icia) is enabled input capture interrupt b enable 0 icfb interrupt request (icib) is disabled 1 icfb interrupt request (icib) is enabled input capture interrupt c enable 0 icfc interrupt request (icic) is disabled 1 icfc interrupt request (icic) is enabled input capture interrupt d enable 0 icfd interrupt request (icid) is disabled 1 icfd interrupt request (icid) is enabled output compare interrupt a enable 0 ocfa interrupt request (ocia) is disabled 1 ocfa interrupt request (ocia) is enabled output compare interrupt b enable 0 ocfb interrupt request (ocib) is disabled 1 ocfb interrupt request (ocib) is enabled timer overflow interrupt enable 0 ovf interrupt request (fovi) is disabled 1 ovf interrupt request (fovi) is enabled 731 tcsrtimer control/status register h'ff91 frt 7 icfa 0 r/(w) * 6 icfb 0 r/(w) * 5 icfc 0 r/(w) * 4 icfd 0 r/(w) * 3 ocfa 0 r/(w) * 0 cclra 0 r/w 2 ocfb 0 r/(w) * 1 ovf 0 r/(w) * bit initial value read/write input capture flag a note: * only 0 can be written in bits 7 to 1, to clear the flags. 0 [clearing condition] when 0 is written in icfa after reading icfa = 1 1 [setting condition] when an input capture signal causes the frc value to be transferred to icra input capture flag b 0 [clearing condition] when 0 is written in icfb after reading icfb = 1 1 [setting condition] when an input capture signal causes the frc value to be transferred to icrb input capture flag c 0 [clearing condition] when 0 is written in icfc after reading icfc = 1 1 [setting condition] when an input capture signal is generated input capture flag d 0 [clearing condition] when 0 is written in icfd after reading icfd = 1 1 [setting condition] when an input capture signal is generated counter clear a 0 frc clearing is disabled 1 frc is cleared at compare match a timer overflow 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when the frc value overflows from h'ffff to h'0000 output compare flag b 0 [clearing condition] when 0 is written in ocfb after reading ocfb = 1 1 [setting condition] when frc = ocrb output compare flag a 0 [clearing condition] when 0 is written in ocfa after reading ocfa = 1 1 [setting condition] when frc = ocra 732 frcfree-running counter h'ff92 frt 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w count value ocra/ocrboutput compare register a/b h'ff94 frt 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w constantly compared with frc value; ocf is set when ocr = frc 733 tcrtimer control register h'ff96 frt 7 iedga 0 r/w 6 iedgb 0 r/w 5 iedgc 0 r/w 4 iedgd 0 r/w 3 bufea 0 r/w 0 cks0 0 r/w 2 bufeb 0 r/w 1 cks1 0 r/w bit initial value read/write input edge select a 0 capture at falling edge of input capture input a capture at rising edge of input capture input a 1 input edge select b 0 capture at falling edge of input capture input b capture at rising edge of input capture input b 1 input edge select c 0 capture at falling edge of input capture input c capture at rising edge of input capture input c 1 input edge select d 0 capture at falling edge of input capture input d capture at rising edge of input capture input d 1 buffer enable a 0 icrc is not used as icra buffer register icrc is used as icra buffer register 1 buffer enable b 0 icrd is not used as icrb buffer register 1 clock select 0 internal clock: counting on ?2 0 1 internal clock: counting on ?8 internal clock: counting on ?32 external clock: counting on rising edge 0 1 1 icrd is used as icrb buffer register 734 tocrtimer output compare control register h'ff97 frt 7 icrdms 0 r/w 6 ocrams 0 r/w 5 icrs 0 r/w 4 ocrs 0 r/w 3 oea 0 r/w 0 olvlb 0 r/w 2 oeb 0 r/w 1 olvla 0 r/w bit initial value read/write output level b 0 0 output at compare match b 1 1 output at compare match b output level a 0 0 output at compare match a 1 1 output at compare match a output enable b 0 output compare b output disabled 1 output compare b output enabled output enable a 0 output compare a output disabled 1 output compare a output enabled output compare register select 0 ocra register selected 1 ocrb register selected input capture register select 0 icra, icrb, and icrc registers selected 1 ocrar, ocraf, and ocrdm registers selected output compare a mode select 0 ocra set to normal operating mode 1 ocra set to operating mode using ocrar and ocraf input capture d mode select 0 icrd set to normal operating mode 1 icrd set to operating mode using ocrdm 735 ocraroutput compare register ar h'ff98 frt ocrafoutput compare register af h'ff9a frt 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w used for ocra operation when ocrams = 1 in tocr (for details, see section 11.2.4, output compare registers ar and af (ocrar, ocraf).) ocrdmoutput compare register dm h'ff9c frt 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 8 0 r 10 0 r 9 0 r bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w used for icrd operation when icrdms = 1 in tocr (for details, see section 11.2.5, output compare register dm (ocrdm).) icrainput capture register a h'ff98 frt icrbinput capture register b h'ff9a frt icrcinput capture register c h'ff9c frt icrdinput capture register d h'ff9e frt 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 8 0 r 10 0 r 9 0 r bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r stores frc value when input capture signal is input (icrc and icrd can be used for buffer operation. for details, see section 11.2.3, input capture registers a to d (icra to icrd).) 736 dadrahpwm (d/a) data register ah h'ffa0 pwmx dadralpwm (d/a) data register al h'ffa1 pwmx dadrbhpwm (d/a) data register bh h'ffa6 pwmx dadrblpwm (d/a) data register bl h'ffa7 pwmx 15 13 da13 1 r/w 14 12 da12 1 r/w 13 11 da11 1 r/w 12 10 da10 1 r/w 11 9 da9 1 r/w 8 6 da6 1 r/w 10 8 da8 1 r/w 9 7 da7 1 r/w bit (cpu) bit (data) dadra initial value read/write 7 5 da5 1 r/w 6 4 da4 1 r/w 5 3 da3 1 r/w 4 2 da2 1 r/w 3 1 da1 1 r/w 0 ? ? 1 2 0 da0 1 r/w 1 ? cfs 1 r/w dadrh dadrl da13 1 r/w da12 1 r/w da11 1 r/w da10 1 r/w da9 1 r/w da6 1 r/w da8 1 r/w da7 1 r/w dadrb initial value read/write da5 1 r/w da4 1 r/w da3 1 r/w da2 1 r/w da1 1 r/w regs 1 r/w da0 1 r/w cfs 1 r/w register select (dadrb only) 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed carrier frequency select 0 operates on basic cycle = resolution (t) 64 dadr value range is h'0401 to h'fffd 1 operates on basic cycle = resolution (t) 256 dadr value range is h'0103 to h'ffff d/a conversion data 737 dacrpwm (d/a) control register h'ffa0 pwmx 7 test 0 r/w 6 pwme 0 r/w 5 ? 1 4 ? 1 3 oeb 0 r/w 0 cks 0 r/w 2 oea 0 r/w 1 os 0 r/w bit initial value read/write clock select 0 operates at resolution (t) = system clock cycle (t cyc ) 1 operates at resolution (t) = system clock cycle (t cyc ) 2 output select 0 pwm direct output 1 pwm inverted output output enable a 0 pwm (d/a) channel a output (pwx0 output pin) disabled 1 pwm (d/a) channel a output (pwx0 output pin) enabled output enable b 0 pwm (d/a) channel b output (pwx1 output pin) disabled 1 pwm (d/a) channel b output (pwx1 output pin) enabled pwm enable 0 dacnt operates as 14-bit up-counter 1 stop at dacnt = h'0003 test mode 0 pwm (d/a) in user state, normal operation 1 pwm (d/a) in test state, correct conversion results unobtainable 738 dacnthpwm (d/a) counter h h'ffa6 pwmx dacntlpwm (d/a) counter l h'ffa7 pwmx 15 7 0 r/w 14 6 0 r/w 13 5 0 r/w 12 4 0 r/w 11 3 0 r/w 8 0 0 r/w 10 2 0 r/w 9 1 0 r/w bit (cpu) bit (counter) initial value read/write 7 8 0 r/w 6 9 0 r/w 5 10 0 r/w 4 11 0 r/w 3 12 0 r/w 0 ? regs 1 r/w 2 13 0 r/w 1 ? ? 1 dacnth dacntl up-counter register select 0 dadra and dadrb can be accessed 1 dacr and dacnt can be accessed 739 tcsr0timer control/status register 0 h'ffa8 wdt0 7 ovf 0 r/(w) * 6 wt/ it 0 r/w 5 tme 0 r/w 4 rsts 0 r/w 3 rst/ nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 2 to 0 cks2 0 1 ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 cks1 0 1 0 1 cks0 0 1 0 1 0 1 0 1 note: * only 0 can be written, to clear the flag. clock reset or nmi 0 nmi interrupt requested 1 internal reset requested timer enable 0 tcnt is initialized to h'00 and halted 1 tcnt counts reserved timer mode select 0 interval timer mode: interval timer interrupt request (wovi) sent to cpu when tcnt overflows 1 watchdog timer mode: reset or nmi interrupt request sent to cpu when tcnt overflows overflow flag 0 [clearing conditions] ? when 0 is written in the tme bit ? when 0 is written in ovf after reading tcsr when ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 when internal reset request is selected in watchdog timer mode, ovf is cleared automatically by an internal reset after being set 740 tcnt0timer counter 0 h'ffa8 (w), h'ffa9 (r) wdt0 tcnt1timer counter 1 h'ffea (w), h'ffeb (r) wdt1 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write up-counter p1pcrport 1 mos pull-up control register h'ffac port 1 7 p17pcr 0 r/w 6 p16pcr 0 r/w 5 p15pcr 0 r/w 4 p14pcr 0 r/w 3 p13pcr 0 r/w 0 p10pcr 0 r/w 2 p12pcr 0 r/w 1 p11pcr 0 r/w bit initial value read/write control of port 1 built-in mos input pull-ups p2pcrport 2 mos pull-up control register h'ffad port 2 7 p27pcr 0 r/w 6 p26pcr 0 r/w 5 p25pcr 0 r/w 4 p24pcr 0 r/w 3 p23pcr 0 r/w 0 p20pcr 0 r/w 2 p22pcr 0 r/w 1 p21pcr 0 r/w bit initial value read/write control of port 2 built-in mos input pull-ups p3pcrport 3 mos pull-up control register h'ffae port 3 7 p37pcr 0 r/w 6 p36pcr 0 r/w 5 p35pcr 0 r/w 4 p34pcr 0 r/w 3 p33pcr 0 r/w 0 p30pcr 0 r/w 2 p32pcr 0 r/w 1 p31pcr 0 r/w bit initial value read/write control of port 3 built-in mos input pull-ups 741 p1ddrport 1 data direction register h'ffb0 port 1 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value read/write specification of input or output for port 1 pins p2ddrport 2 data direction register h'ffb1 port 2 7 p27ddr 0 w 6 p26ddr 0 w 5 p25ddr 0 w 4 p24ddr 0 w 3 p23ddr 0 w 0 p20ddr 0 w 2 p22ddr 0 w 1 p21ddr 0 w bit initial value read/write specification of input or output for port 2 pins p1drport 1 data register h'ffb2 port 1 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit initial value read/write stores output data for port 1 pins p2drport 2 data register h'ffb3 port 2 7 p27dr 0 r/w 6 p26dr 0 r/w 5 p25dr 0 r/w 4 p24dr 0 r/w 3 p23dr 0 r/w 0 p20dr 0 r/w 2 p22dr 0 r/w 1 p21dr 0 r/w bit initial value read/write stores output data for port 2 pins 742 p3ddrport 3 data direction register h'ffb4 port 3 7 p37ddr 0 w 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w bit initial value read/write specification of input or output for port 3 pins p4ddrport 4 data direction register h'ffb5 port 4 7 p47ddr 0 w 0 w 6 p46ddr 1 w 0 w 5 p45ddr 0 w 0 w 4 p44ddr 0 w 0 w 3 p43ddr 0 w 0 w 0 p40ddr 0 w 0 w 2 p42ddr 0 w 0 w 1 p41ddr 0 w 0 w bit mode 1 initial value read/write modes 2 and 3 initial value read/write specification of input or output for port 4 pins p3drport 3 data register h'ffb6 port 3 7 p37dr 0 r/w 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit initial value read/write stores output data for port 3 pins p4drport 4 data register h'ffb7 port 4 7 p47dr 0 r/w 6 p46dr * r 5 p45dr 0 r/w 4 p44dr 0 r/w 3 p43dr 0 r/w 0 p40dr 0 r/w 2 p42dr 0 r/w 1 p41dr 0 r/w bit initial value read/write note: * determined by state of pin p46. stores output data for port 4 pins 743 p5ddrport 5 data direction register h'ffb8 port 5 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 p50ddr 0 w 2 p52ddr 0 w 1 p51ddr 0 w bit initial value read/write specification of input or output for port 5 pins p6ddrport 6 data direction register h'ffb9 port 6 7 p67ddr 0 w 6 p66ddr 0 w 5 p65ddr 0 w 4 p64ddr 0 w 3 p63ddr 0 w 0 p60ddr 0 w 2 p62ddr 0 w 1 p61ddr 0 w bit initial value read/write specification of input or output for port 6 pins p5drport 5 data register h'ffba port 5 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 p50dr 0 r/w 2 p52dr 0 r/w 1 p51dr 0 r/w bit initial value read/write stores output data for port 5 pins p6drport 6 data register h'ffbb port 6 7 p67dr 0 r/w 6 p66dr 0 r/w 5 p65dr 0 r/w 4 p64dr 0 r/w 3 p63dr 0 r/w 0 p60dr 0 r/w 2 p62dr 0 r/w 1 p61dr 0 r/w bit initial value read/write stores output data for port 6 pins 744 p7pinport 7 input data register h'ffbe port 7 7 p77pin * r 6 p76pin * r 5 p75pin * r 4 p74pin * r 3 p73pin * r 0 p70pin * r 2 p72pin * r 1 p71pin * r bit initial value read/write note: * determined by state of pins p77 to p70. port 7 pin states ierirq enable register h'ffc2 interrupt controller 7 ? 1 r 6 ? 1 r 5 ? 1 r 4 ? 1 r 3 ? 1 r 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value read/write irq2 to irq0 enable 0 irqn interrupt disabled 1 irqn interrupt enabled (n = 0 to 2) 745 stcrserial timer control register h'ffc3 system 7 iics 0 r/w 6 iicx1 0 r/w 5 iicx0 0 r/w 4 iice 0 r/w 3 flshe 0 r/w 0 icks0 0 r/w 2 ? 0 r/w 1 icks1 0 r/w bit initial value read/write notes: 1. 2. internal clock source select * 1 reserved flash memory control register enable 0 flash memory control register not selected 1 flash memory control register selected i 2 c master enable 0 cpu access to sci0 control registers is disabled 1 cpu access to i 2 c bus interface data, pwmx data register and control registers is enabled i 2 c transfer rate select 1 and 0 * 2 reserved used for 8-bit timer input clock selection. for details, see section 12.2.4, timer control register (tcr). used for i 2 c bus interface transfer clock selection. for details, see section 16.2.4, i 2 c bus mode register (icmr). 746 syscrsystem control register h'ffc4 system 7 cs2e 0 r/w 6 iose 0 r/w 5 intm1 0 r 4 intm0 0 r/w 3 xrst 1 r 0 rame 1 r/w 2 nmieg 0 r/w 1 hie 0 r/w bit initial value read/write ram enable 0 on-chip ram is disabled 1 on-chip ram is enabled host interface enable 0 access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers is disabled 1 access to 8-bit timer (channel x and y) data registers and control registers, and timer connection control registers is enabled nmi edge select 0 falling edge 1 rising edge external reset 0 reset generated by watchdog timer overflow 1 reset generated by an external reset interrupt control mode select 0 interrupt control mode 0 interrupt control mode 1 0 1 reserved ios enable 0 as / ios is address strobe pin (low output in external area access) 1 as / ios is i/o strobe pin (low output when accessing specified address from h'(ff)f000 to h(ff)fe4f) 747 mdcrmode control register h'ffc5 system 7 expe * r/w * 6 ? 0 5 ? 0 4 ? 0 3 ? 0 0 mds0 * r 2 ? 0 1 mds1 * r bit initial value read/write expanded mode enable 0 single-chip mode selected 1 expanded mode selected note: * determined by pins md1 and md0. current mode pin operating mode 748 bcrbus control register h'ffc6 bus controller 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 ios0 1 r/w 2 ? 1 r/w 1 ios1 1 r/w bit initial value read/write ios select ios1 addresses for which as / ios pin output goes low when iose = 1 0 low in accesses to addresses h'(ff)f000 to h'(ff)f03f ios0 0 low in accesses to addresses h'(ff)f000 to h'(ff)f0ff 1 1 low in accesses to addresses h'(ff)f000 to h'(ff)f3ff 0 low in accesses to addresses h'(ff)f000 to h'(ff)fe4f 1 burst cycle select 0 0 max. 4 words in burst access 1 max. 8 words in burst access burst cycle select 1 0 burst cycle comprises 1 state 1 burst cycle comprises 2 states burst rom enable 0 basic bus interface 1 burst rom interface idle cycle insert 0 0 idle cycle not inserted in case of successive external read and external write cycles 1 idle cycle inserted in case of successive external read and external write cycles reserved 749 wscrwait state control register h'ffc7 bus controller 7 rams 0 r/w 6 ram0 0 r/w 5 abw 1 r/w 4 ast 1 r/w 3 wms1 0 r/w 0 wc0 1 r/w 2 wms0 0 r/w 1 wc1 1 r/w bit initial value read/write reserved wait count 1 and 0 0 no programmable waits inserted 0 1 programmable wait state inserted in external memory space access 1 1 2 programmable wait states inserted in external memory space access 0 3 programmable wait states inserted in external memory space access 1 wait mode select 1 and 0 0 programmable wait mode 0 wait disabled mode 1 1 pin wait mode 0 pin auto-wait mode 1 access state control 0 external memory space designated as 2-state access space wait state insertion in external memory space access is disabled 1 external memory space designated as 3-state access space wait state insertion in external memory space access is enabled bus width control 0 external memory space designated as 16-bit access space 1 external memory space designated as 8-bit access space 750 tcr0timer control register 0 h'ffc8 tmr0 tcr1timer control register 1 h'ffc9 tmr1 tcrxtimer control register x h'fff0 tmrx tcrytimer control register y h'fff0 tmry 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 2 to 0 channel bit 2 bit 1 bit 0 cks2 0 1 x y all 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 cks1 cks0 description clock input disabled internal clock: counting at falling edge of ?8 internal clock: counting at falling edge of ?2 internal clock: counting at falling edge of ?64 internal clock: counting at falling edge of ?32 internal clock: counting at falling edge of ?1024 internal clock: counting at falling edge of ?256 counting at tcnt1 overflow signal * 2 clock input disabled internal clock: counting at falling edge of ?8 internal clock: counting at falling edge of ?2 internal clock: counting at falling edge of ?64 internal clock: counting at falling edge of ?128 internal clock: counting at falling edge of ?1024 internal clock: counting at falling edge of ?2048 count at tcnt0 compare match a * 2 clock input disabled internal clock: counting on ? internal clock: counting at falling edge of ?2 internal clock: counting at falling edge of ?4 clock input disabled clock input disabled internal clock: counting at falling edge of ?4 internal clock: counting at falling edge of ?256 internal clock: counting at falling edge of ?2048 clock input disabled external clock: counting at rising edge external clock: counting at falling edge external clock: counting at both rising and falling edges * 1 * 1 * 1 * 1 * 1 * 1 notes: 1. 2. selected by icks1 and icks0 in stcr. for details, see section 12.2.4, timer control register (tcr). if the clock input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare match signal, no incrementing clock is generated. do not use this setting. counter clear 1 and 0 0 clear is disabled clear by compare match a 0 1 1 clear by compare match b 0 clear by rising edge of external reset input 1 timer overflow interrupt enable 0 ovf interrupt request (ovi) is disabled 1 ovf interrupt request (ovi) is enabled compare match interrupt enable a 0 cmfa interrupt request (cmia) is disabled 1 cmfa interrupt request (cmia) is enabled compare match interrupt enable b 0 cmfb interrupt request (cmib) is disabled 1 cmfb interrupt request (cmib) is enabled 751 tcsr0timer control/status register 0 h'ffca tmr0 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write tcsr0 output select 1 and 0 0 no change at compare match a 0 0 output at compare match a 1 1 1 output at compare match a 0 output inverted at compare match a (toggle output) 1 note: output select 3 and 2 0 no change at compare match b 0 0 output at compare match b 1 1 1 output at compare match b 0 output inverted at compare match b (toggle output) 1 a/d trigger enable 0 a/d converter start requests by compare match a are disabled 1 a/d converter start requests by compare match a are enabled timer overflow flag 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 compare match flag a 0 [clearing conditions] ? when 0 is written in cmfa after reading cmfa = 1 ? when the dtc is activated by a cmia interrupt 1 [setting condition] when tcnt = tcora compare match flag b 0 [clearing conditions] ? when 0 is written in cmfb after reading cmfb = 1 ? when the dtc is activated by a cmib interrupt 1 [setting condition] when tcnt = tcorb * only 0 can be written in bits 7 to 5, to clear the flags. 752 tcsr1timer control/status register 1 h'ffcb tmr1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 ? 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write output select 1 and 0 0 no change at compare match a 0 0 output at compare match a 1 1 1 output at compare match a 0 output inverted at compare match a (toggle output) 1 output select 3 and 2 0 no change at compare match b 0 0 output at compare match b 1 1 1 output at compare match b 0 output inverted at compare match b (toggle output) 1 timer overflow flag 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 compare match flag a 0 [clearing conditions] ? when 0 is written in cmfa after reading cmfa = 1 ? when the dtc is activated by a cmia interrupt 1 [setting condition] when tcnt = tcora compare match flag b 0 [clearing conditions] ? when 0 is written in cmfb after reading cmfb = 1 ? when the dtc is activated by a cmib interrupt 1 [setting condition] when tcnt = tcorb note: * only 0 can be written in bits 7 to 5, to clear the flags. 753 tcora0time constant register a0 h'ffcc tmr0 tcora1time constant register a1 h'ffcd tmr1 tcorb0time constant register b0 h'ffce tmr0 tcorb1time constant register b1 h'ffcf tmr1 tcoraytime constant register ay h'fff2 tmry tcorbytime constant register by h'fff3 tmry tcorctime constant register c h'fff5 tmrx tcoraxtime constant register ax h'fff6 tmrx tcorbxtime constant register bx h'fff7 tmrx 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write 15 1 r/w bit initial value read/write 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcorb0 tcora1 tcorb1 compare match flag (cmf) is set when tcor and tcnt values match compare match flag (cmf) is set when tcor and tcnt values match 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value read/write compare match c signal is generated when sum of tcorc and ticr contents match tcnt value tcorax, tcoray tcorbx, tcorby tcorc 754 tcnt0timer counter 0 h'ffd0 tmr0 tcnt1timer counter 1 h'ffd1 tmr1 tcntxtimer counter x h'fff4 tmrx tcntytimer counter y h'fff4 tmry 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write up-counter 15 0 r/w bit initial value read/write 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 tcnt1 up-counter tcntx, tcnty 755 pwoerapwm output enable register a h'ffd3 pwm pwoerbpwm output enable register b h'ffd2 pwm 7 oe7 0 r/w 6 oe6 0 r/w 5 oe5 0 r/w 4 oe4 0 r/w 3 oe3 0 r/w 0 oe0 0 r/w 2 oe2 0 r/w 1 oe1 0 r/w bit pwoera initial value read/write 7 oe15 0 r/w 6 oe14 0 r/w 5 oe13 0 r/w 4 oe12 0 r/w 3 oe11 0 r/w switching between pwm output and port output 0 oe8 0 r/w 2 oe10 0 r/w 1 oe9 0 r/w bit pwoerb initial value read/write 0 1 0 1 0 1 port input port input port output or pwm 256/256 output pwm output (0 to 255/256 output) ddr oe description pwdprapwm data polarity register a h'ffd5 pwm pwdprbpwm data polarity register b h'ffd4 pwm 7 os7 0 r/w 6 os6 0 r/w 5 os5 0 r/w 4 os4 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit pwdpra initial value read/write 7 os15 0 r/w 6 os14 0 r/w 5 os13 0 r/w 4 os12 0 r/w 3 os11 0 r/w 0 os8 0 r/w 2 os10 0 r/w 1 os9 0 r/w bit pwdprb initial value read/write pwm output polarity control 0 pwm direct output (pwdr value corresponds to high width of output) 1 pwm inverted output (pwdr value corresponds to low width of output) 756 pwslpwm register select h'ffd6 pwm 7 pwcke 0 r/w 6 pwcks 0 r/w 5 ? 1 4 ? 1 3 rs3 0 r/w 0 rs0 0 r/w 2 rs2 0 r/w 1 rs1 0 r/w bit initial value read/write 0 1 pwdr0 selected pwdr1 selected pwdr2 selected pwdr3 selected pwdr4 selected pwdr5 selected pwdr6 selected pwdr7 selected pwdr8 selected pwdr9 selected pwdr10 selected pwdr11 selected pwdr12 selected pwdr13 selected pwdr14 selected pwdr15 selected register select 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pwm clock enable, pwm clock select clock input disabled ?(system clock) selected ?2 selected ?4 selected ?8 selected ?16 selected pwsl pcsr bit 2 pwckb ? ? 0 1 bit 1 pwcka ? ? 0 1 0 1 bit 7 pwcke 0 1 bit 6 pwcks ? 0 1 description 757 pwdr0 to pwdr15pwm data registers h'ffd7 pwm 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w specifies duty factor of basic output pulse and number of additional pulses 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write addraha/d data register ah h'ffe0 a/d converter addrala/d data register al h'ffe1 a/d converter addrbha/d data register bh h'ffe2 a/d converter addrbla/d data register bl h'ffe3 a/d converter addrcha/d data register ch h'ffe4 a/d converter addrcla/d data register cl h'ffe5 a/d converter addrdha/d data register dh h'ffe6 a/d converter addrdla/d data register dl h'ffe7 a/d converter 14 ad8 0 r 12 ad6 0 r 10 ad4 0 r 8 ad2 0 r 6 ad0 0 r 0 ? 0 r 4 ? 0 r 2 ? 0 r 15 ad9 0 r 13 ad7 0 r 11 ad5 0 r 9 ad3 0 r 7 ad1 0 r 1 ? 0 r 5 ? 0 r 3 ? 0 r bit initial value read/write addrh stores a/d data correspondence between analog input channels and addr registers addrl addra addrb addrc addrd group 0 an0 an1 an2 an3 group 1 an4 an5 an6 or cin0?in7 an7 analog input channel a/d data register 758 adcsra/d control/status register h'ffe8 a/d converter 7 adf 0 r/(w) 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w * bit initial value read/write channel select 0 1 0 1 0 1 0 1 0 1 0 1 an0 an1 an2 an3 an4 an5 an6 or cin0? an7 description an0 an0, an1 an0, an1, an2 an0, an1, an2, an3 an4 an4, an5 an4, an5, an6 or cin0? an4, an5, an6 or cin0?, an7 group selection ch1 ch0 single mode scan mode ch2 0 1 note: * only 0 can be written, to clear the flag. channel selection clock select 0 conversion time = 266 states (max.) 1 conversion time = 134 states (max.) scan mode 0 single mode 1 scan mode a/d interrupt enable 0 a/d conversion end interrupt (adi) request disabled 1 a/d conversion end interrupt (adi) request enabled a/d end flag 0 [clearing conditions] ? when 0 is written to adf after reading adf = 1 ? when the dtc is activated by an adi interrupt, and addr is read 1 [setting conditions] ? single mode: when a/d conversion ends ? scan mode: when a/d conversion ends for all specified channels a/d start 0 a/d conversion stopped 1 single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends ? scan mode: a/d conversion is started. conversion continues consecutively on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode 759 adcra/d control register h'ffe9 a/d converter 7 trgs1 0 r/w 6 trgs0 0 r/w 5 ? 1 4 ? 1 3 ? 1 0 ? 1 2 ? 1 1 ? 1 bit initial value read/write timer trigger select 0 a/d conversion start by external trigger is disabled a/d conversion start by external trigger is disabled a/d conversion start by external trigger (8-bit timer) is enabled a/d conversion start by external trigger pin is enabled 0 1 10 1 760 tcsr1timer control/status register 1 h'ffea wdt1 7 ovf 0 r/(w) * 1 6 wt/ it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/ nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write clock select 2 to 0 pss 0 1 clock csk2 0 1 0 1 csk1 0 1 0 1 0 1 0 1 csk0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 notes: 1. 2. ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 ?ub/2 ?ub/4 ?ub/8 ?ub/16 ?ub/32 ?ub/64 ?ub/128 ?ub/256 reset or nmi 0 nmi interrupt requested 1 internal reset requested prescaler select * 2 0 tcnt counts on a ?based prescaler (psm) scaled clock 1 tcnt counts on a ?ub-based prescaler (pss) scaled clock timer enable 0 tcnt is initialized to h'00 and halted 1 tcnt counts timer mode select 0 interval timer mode: interval timer interrupt request (wovi) sent to cpu when tcnt overflows 1 watchdog timer mode: reset or nmi interrupt request sent to cpu when tcnt overflows overflow flag 0 [clearing conditions] ? when 0 is written in the tme bit ? when 0 is written in ovf after reading tcsr when ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 when internal reset request is selected in watchdog timer mode, ovf is cleared automatically by an internal reset after being set only 0 can be written, to clear the flag. for operation control when a transition is made to power-down mode, see section 21.2.3, timer control/status register (tcsr). 761 tcsrxtimer control/status register x h'fff1 tmrx 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 icf 0 r/(w) * 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write output select 1 and 0 0 no change at compare match a 0 0 output at compare match a 1 1 1 output at compare match a 0 output inverted at compare match a (toggle output) 1 note: output select 3 and 2 0 no change at compare match b 0 0 output at compare match b 1 1 1 output at compare match b 0 output inverted at compare match b (toggle output) 1 input capture flag 0 [clearing condition] when 0 is written in icf after reading icf = 1 1 [setting condition] when a rising edge followed by a falling edge is detected in the external reset signal after the icst bit is set to 1 in tconri timer overflow flag 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 compare match flag a 0 [clearing conditions] ? when 0 is written in cmfa after reading cmfa = 1 ? when the dtc is activated by a cmia interrupt 1 [setting condition] when tcnt = tcora compare match flag b 0 [clearing conditions] ? when 0 is written in cmfb after reading cmfb = 1 ? when the dtc is activated by a cmib interrupt 1 [setting condition] when tcnt = tcorb * only 0 can be written in bits 7 to 4, to clear the flags. 762 tcsrytimer control/status register y h'fff1 tmry 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 icie 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value read/write output select 1 and 0 0 no change at compare match a 0 0 output at compare match a 1 1 1 output at compare match a 0 output inverted at compare match a (toggle output) 1 note: output select 3 and 2 0 no change at compare match b 0 0 output at compare match b 1 1 1 output at compare match b 0 output inverted at compare match b (toggle output) 1 input capture interrupt enable 0 icf interrupt request (icix) is disabled 1 icf interrupt request (icix) is enabled timer overflow flag 0 [clearing condition] when 0 is written in ovf after reading ovf = 1 1 [setting condition] when tcnt overflows from h'ff to h'00 compare match flag a 0 [clearing conditions] ? when 0 is written in cmfa after reading cmfa = 1 ? when the dtc is activated by a cmia interrupt 1 [setting condition] when tcnt = tcora compare match flag b 0 [clearing conditions] ? when 0 is written in cmfb after reading cmfb = 1 ? when the dtc is activated by a cmib interrupt 1 [setting condition] when tcnt = tcorb * only 0 can be written in bits 7 to 5, to clear the flags. 763 ticrrinput capture register r h'fff2 tmrx ticrfinput capture register f h'fff3 tmrx 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value read/write stores tcnt value at fall of external trigger input tisrtimer input select register h'fff5 tmry 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 is 0 r/w 2 ? 1 1 ? 1 bit initial value read/write input select 0 1 ivg signal is selected (h8s/2128 series) external clock/reset input is disabled (h8s/2124 series) vsync1/tmiy (tmciy/tmriy) is selected 764 tconritimer connection register i h'fffc timer connection bit initial value read/write 7 simod1 0 r/w 6 simod0 0 r/w 5 scone 0 r/w 4 icst 0 r/w 3 hfinv 0 r/w 0 viinv 0 r/w 2 vfinv 0 r/w 1 hiinv 0 r/w input synchronization mode select 1 and 0 0 1 no signal s-on-g mode composite mode separate mode 0 1 0 1 simod1 mode hfbacki input csynci input hsynci input hsynci input ihi signal vfbacki input pdc input pdc input vsynci input ivi signal simod0 synchronization signal connection enable 0 1 ftia input normal connection scone ftia ftib ftic ftid tmci1 tmri1 mode ftib input ftic input tmci1 input tmri1 input ftid input ivi signal synchronization signal connec- tion mode tmo1 signal vfbacki input ihi signal ivi inverse signal ihi signal input synchronization signal inversion 0 the vsynci pin state is used directly as the vsynci input 1 the vsynci pin state is inverted before use as the vsynci input input synchronization signal inversion 0 the hsynci and csynci pin states are used directly as the hsynci and csynci inputs 1 the hsynci and csynci pin states are inverted before use as the hsynci and csynci inputs input synchronization signal inversion 0 the vfbacki pin state is used directly as the vfbacki input 1 the vfbacki pin state is inverted before use as the vfbacki input input capture start bit 0 the ticrr and ticrf input capture functions are stopped [clearing condition] when a rising edge followed by a falling edge is detected on tmrix 1 the ticrr and ticrf input capture functions are operating (waiting for detection of a rising edge followed by a falling edge on tmrix) [setting condition] when 1 is written in icst after reading icst = 0 input synchronization signal inversion 0 the hfbacki pin state is used directly as the hfbacki input 1 the hfbacki pin state is inverted before use as the hfbacki input 765 tconrotimer connection register o h'fffd timer connection bit initial value read/write 7 hoe 0 r/w 6 voe 0 r/w 5 cloe 0 r/w 4 cboe 0 r/w 3 hoinv 0 r/w 0 cboinv 0 r/w 2 voinv 0 r/w 1 cloinv 0 r/w output synchronization signal inversion 0 the cblank signal is used directly as the cblank output 1 the cblank signal is inverted before use as the cblank output output synchronization signal inversion 0 the clo signal (cl1, cl2, cl3, or cl4 signal) is used directly as the clampo output 1 the clo signal (cl1, cl2, cl3, or cl4 signal) is inverted before use as the clampo output output synchronization signal inversion 0 the ivo signal is used directly as the vsynco output 1 the ivo signal is inverted before use as the vsynco output output synchronization signal inversion 0 the iho signal is used directly as the hsynco output 1 the iho signal is inverted before use as the hsynco output output enable 0 the p27/a15/pw15/cblank pin functions as the p27/a15/pw15 pin 1 in mode 1 (expanded mode with on-chip rom disabled): the p27/a15/ pw15/cblank pin functions as the a15 pin in modes 2 and 3 (expanded modes with on-chip rom enabled): the p27/ a15/pw15/cblank pin functions as the cblank pin output enable 0 the p64/ftic/cin4/clampo pin functions as the p64/ftic/cin4 pin 1 the p64/ftic/cin4/clampo pin functions as the clampo pin output enable 0 the p61/ftoa/cin1/vsynco pin functions as the p61/ftoa/cin1 pin 1 the p61/ftoa/cin1/vsynco pin functions as the vsynco pin output enable 0 the p67/tmo1/tmox/cin7/hsynco pin functions as the p67/tmo1/tmox/cin7 pin 1 the p67/tmo1/tmox/cin7/hsynco pin functions as the hsynco pin 766 tconrstimer connection register s h'fffe timer connection 7 tmrx/y 0 r/w 6 isgene 0 r/w 5 homod1 0 r/w 4 homod0 0 r/w 3 vomod1 0 r/w 0 clmod0 0 r/w 2 vomod0 0 r/w 1 clmod1 0 r/w bit initial value read/write clamp waveform mode select 1 and 0 clmod1 clmod0 0 1 0 1 0 1 0 1 0 1 0 1 description the cl1 signal is selected the cl2 signal is selected the cl3 signal is selected the cl4 signal is selected isgene 0 1 vertical synchronization output mode select 1 and 0 vomod1 vomod0 0 1 0 1 0 1 0 1 0 1 0 1 description isgene 0 1 horizontal synchronization output mode select 1 and 0 homod1 homod0 0 1 0 1 0 1 0 1 0 1 0 1 description the ihi signal (without 2fh modification) is selected the ihi signal (with 2fh modification) is selected the cli signal is selected the ihg signal is selected isgene 0 1 the ivi signal (without fall modification or ihi synchronization) is selected the ivi signal (without fall modification, with ihi synchronization) is selected the ivi signal (with fall modification, without ihi synchronization) is selected the ivi signal (with fall modification and ihi synchronization) is selected the ivg signal is selected internal synchronization signal select 8-bit timer access select 0 the tmrx registers are accessed at addresses h'fff0 to h'fff5 1 the tmry registers are accessed at addresses h'fff0 to h'fff5 767 sedgredge sense register h'ffff timer connection bit initial value read/write 7 vedg 0 r/(w) 6 hedg 0 r/(w) 5 cedg 0 r/(w) 4 hfedg 0 r/(w) 3 vfedg 0 r/(w) 0 ivi * 2 r 2 preqf 0 r/(w) 1 ihi * 2 r * 1 * 1 * 1 * 1 * 1 * 1 ivi signal level 0 the ivi signal is low 1 the ivi signal is high notes: 1. 2. ihi signal level 0 the ihi signal is low 1 the ihi signal is high pre-equalization flag 0 [clearing condition] when 0 is written in preqf after reading preqf = 1 1 [setting condition] when an ihi signal 2fh modification condition is detected vfbacki edge 0 [clearing condition] when 0 is written in vfedg after reading vfedg = 1 1 [setting condition] when a rising edge is detected on the vfbacki pin hfbacki edge 0 [clearing condition] when 0 is written in hfedg after reading hfedg = 1 1 [setting condition] when a rising edge is detected on the hfbacki pin csynci edge 0 [clearing condition] when 0 is written in cedg after reading cedg = 1 1 [setting condition] when a rising edge is detected on the csynci pin hsynci edge 0 [clearing condition] when 0 is written in hedg after reading hedg = 1 1 [setting condition] when a rising edge is detected on the hsynci pin vsynci edge 0 [clearing condition] when 0 is written in vedg after reading vedg = 1 1 [setting condition] when a rising edge is detected on the vsynci pin only 0 can be written, to clear the flags. the initial value is undefined since it depends on the pin states. 768 769 appendix c i/o port block diagrams c.1 port 1 block diagram r qd d p1npcr c reset reset r qd p1ndr c reset wp1p r q p1nddr c wp1d wp1 internal data bus internal address bus 8-bit pwm pwm output enable 14-bit pwm pwx0, pwx1 output output enable pwm output p1n rp1p rp1 mode 2, 3 mode 1 hardware standby mode 1 expe wp1p: write to p1pcr wp1d: write to p1ddr wp1: write to port 1 rp1p: read p1pcr rp1: read port 1 n = 0 or 1 figure c.1 port 1 block diagram (pins p10 and p11) 770 r qd d p1npcr c reset r qd p1ndr c reset wp1p r q p1nddr c reset wp1d wp1 internal data bus internal address bus 8-bit pwm pwm output enable pwm output p1n rp1p rp1 mode 2, 3 mode 1 expe wp1p: write to p1pcr wp1d: write to p1ddr wp1: write to port 1 rp1p: read p1pcr rp1: read port 1 n = 2 to 7 hardware standby mode 1 figure c.2 port 1 block diagram (pins p12 to p17) 771 c.2 port 2 block diagrams r r qd d p2npcr c reset r qd p2ndr c reset wp2p q p2nddr c reset wp2d wp2 8-bit pwm pwm output enable pwm output p2n rp2p rp2 mode 2, 3 mode 1 expe wp2p: write to p2pcr wp2d: write to p2ddr wp2: write to port 2 rp2p: read p2pcr rp2: read port 2 n = 0 to 2 internal data bus internal address bus hardware standby mode 1 figure c.3 port 2 block diagram (pins p20 to p22) 772 r qd d p23pcr c reset r qd p23dr c reset wp2p r q p23ddr c reset wp2d wp2 8-bit pwm pwm output enable pwm output iic1 sda1 output transmit enable rp2p rp2 mode 2, 3 mode 1 hardware standby expe wp2p: write to p2pcr wp2d: write to p2ddr wp2: write to port 2 rp2p: read p2pcr rp2: read port 2 notes: 1. output enable signal 2. open-drain control signal internal data bus internal address bus p23 sda1 input * 1 * 2 hardware standby mode 1 figure c.4 port 2 block diagram (pin 23) 773 r qd d p24pcr c reset r qd p24dr c reset wp2p r q p24ddr c reset wp2d wp2 8-bit pwm pwm output enable pwm output iic1 scl1 output transmit enable rp2p rp2 mode 2, 3 expe iose mode 1 wp2p: write to p2pcr wp2d: write to p2ddr wp2: write to port 2 rp2p: read p2pcr rp2: read port 2 notes: 1. output enable signal 2. open-drain control signal internal data bus internal address bus p24 scl1 input * 1 * 2 hardware standby mode 1 figure c.5 port 2 block diagram (pin 24) 774 r qd d p25pcr c reset r qd c reset wp2p r q p25ddr p25dr c reset wp2d wp2 8-bit pwm pwm output enable pwm output sci1 output enable serial transmit data rp2p rp2 mode 2, 3 expe mode 1 wp2p : write to p2pcr wp2d : write to p2ddr wp2 : write to port 2 rp2p : read p2pcr rp2 : read port 2 internal data bus internal address bus p2n hardware standby mode 1 figure c.6 port 2 block diagram (pin p25) 775 r qd d p26pcr c reset reset wp2p r q p26ddr c reset wp2d wp2 8-bit pwm pwm output enable pwm output sci1 input enable serial receive data rp2p rp2 mode 2, 3 expe mode 1 wp2p : write to p2pcr wp2d : write to p2ddr wp2 : write to port 2 rp2p : read p2pcr rp2 : read port 2 internal data bus internal address bus p2n hardware standby mode 1 r qd c p26dr figure c.7 port 2 block diagram (pin p26) 776 r qd d p27pcr c reset r qd p27dr c reset wp2p r q p27ddr c reset wp2d mode 2, 3 wp2 8-bit pwm pwm output enable pwm output timer connection cblank cblank output enable sci1 input enable clock output output enable clock input p27 rp2p rp2 mode 2, 3 expe iose mode 1 wp2p: write to p2pcr wp2d: write to p2ddr wp2: write to port 2 rp2p: read p2pcr rp2: read port 2 internal data bus internal address bus hardware standby mode 1 figure c.8 port 2 block diagram (pin p27) 777 c.3 port 3 block diagram r qd d p3npcr c reset r qd p3ndr c reset wp3p r q p3nddr c reset wp3d wp3 p3n rp3p rp3 mode 2, 3 mode 1 hardware standby expe wp3p: write to p3pcr wp3d: write to p3ddr wp3: write to port 3 rp3p: read p3pcr rp3: read port 3 n = 0 to 7 external address read internal data bus figure c.9 port 3 block diagram 778 c.4 port 4 block diagrams d r qd p40dr c reset r q p40ddr c reset wp4d wp4 a/d converter external trigger input p40 rp4 wp4d: write to p4ddr wp4: write to port 4 rp4: read port 4 irq2 input irq2 enable internal data bus figure c.10 port 4 block diagram (pin p40) 779 d r qd p4ndr c reset r q p4nddr c reset wp4d wp4 irq1 input irq0 input irq1 enable irq0 enable p4n rp4 wp4d: write to p4ddr wp4: write to port 4 rp4: read port 4 n = 1 or 2 internal data bus figure c.11 port 4 block diagram (pins p41, p42) 780 d r qd p4ndr c reset r q p4nddr c reset wp4d mode 2, 3 expe expe wp4 bus controller rd output wr output as/ios output p4n rp4 wp4d: write to p4ddr wp4: write to port 4 rp4: read port 4 n = 3 to 5 internal data bus figure c.12 port 4 block diagram (pins p43 to p45) 781 d r s q p46ddr c reset mode 1 wp4d subclock input ?output subclock input enable p46 wp4d: write to p4ddr rp4: read port 4 rp4 internal data bus hardware standby figure c.13 port 4 block diagram (pin p46) 782 d r qd p47dr c reset r q p47ddr c reset wp4d expe wp4 iic0 sda0 input sda0 output transmit enable bus controller input enable wait input p47 rp4 wp4d: write to p4ddr wp4: write to port 4 rp4: read port 4 notes: 1. output enable signal 2. open drain control signal * 1 * 2 internal data bus figure c.14 port 4 block diagram (pin p47) 783 c.5 port 5 block diagrams d r qd p50dr c reset r q p50ddr c reset wp5d wp5 sci0 serial transmit data output enable p50 rp5 wp5d: write to p5ddr wp5: write to port 5 rp5: read port 5 internal data bus figure c.15 port 5 block diagram (pin p50) 784 d r qd p51dr c reset r q p51ddr c reset wp5d wp5 sci0 input enable serial receive data p51 rp5 wp5d: write to p5ddr wp5: write to port 5 rp5: read port 5 internal data bus figure c.16 port 5 block diagram (pin p51) 785 d r qd p52dr c reset r q p52ddr c reset wp5d * 1 * 2 wp5 sci0 input enable clock output scl0 output scl0 input transmit enable output enable clock input iic0 p52 rp5 wp5d: write to p5ddr wp5: write to port 5 rp5: read port 5 notes: 1. output enable signal 2. open drain control signal internal data bus figure c.17 port 5 block diagram (pin p52) 786 c.6 port 6 block diagrams d r qd p6ndr c reset r q p6nddr c reset wp6d wp6 16-bit frt ftci input ftia input ftib input ftid input a/d converter analog input timer connection 8-bit timers y, x hfbacki input, tmix input, vsynci input, tmiy input, vfbacki input p6n rp6 wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 n = 0, 2, 3, 5 hardware standby internal data bus figure c.18 port 6 block diagram (pins p60, p62, p63, p65) 787 d r qd p61dr c reset r q p61ddr c reset wp6d wp6 16-bit frt ftoa output output enable timer connection vsynco output output enable a/d converter analog input p61 rp6 wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 hardware standby internal data bus figure c.19 port 6 block diagram (pin p61) 788 d r qd p64dr c reset r q p64ddr c reset wp6d wp6 timer connection clampo output output enable a/d converter analog input 16-bit frt ftic input p64 rp6 wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 hardware standby internal data bus figure c.20 port 6 block diagram (pin p64) 789 d r qd p66dr c reset r q p66ddr c reset wp6d wp6 16-bit frt ftob output output enable a/d converter analog input p66 rp6 wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 hardware standby internal data bus figure c.21 port 6 block diagram (pin p66) 790 d r qd p67dr c reset r q p67ddr c reset wp6d wp6 8-bit timer x tmox output output enable a/d converter analog input p67 rp6 wp6d: write to p6ddr wp6: write to port 6 rp6: read port 6 hardware standby internal data bus figure c.22 port 6 block diagram (pin p67) 791 c.7 port 7 block diagrams a/d converter analog input p7n rp7: read port 7 n = 0 to 7 rp7 internal data bus figure c.23 port 7 block diagram (pins p70 to p77) 792 769 appendix d pin states d.1 port states in each processing state table d.1 i/o port states in each processing state port name pin name mcu operating mode reset hardware standby mode software standby mode watch mode sleep mode sub- sleep mode subactive mode program execution state port 1 1 l t keep * keep * keep * keep * a7 to a0 a7 to a0 a7 to a0 2, 3 (expe = 1) t address output/ input port address output/ input port 2, 3 (expe = 0) i/o port i/o port port 2 1 l t keep * keep * keep * keep * a15 to a8 a15 to a8 a15 to a8 2, 3 (expe = 1) t address output/ input port address output/ input port 2, 3 (expe = 0) i/o port i/o port port 3 1 t t t t t t d7 to d0 d7 to d0 d7 to d0 2, 3 (expe = 1) 2, 3 (expe = 0) keep keep keep keep i/o port i/o port port 47 1 t t t/keep t/keep t/keep t/keep :$,7 / :$,7 / :$,7 2, 3 (expe = 1) i/o port i/o port 2, 3 (expe = 0) keep keep keep keep i/o port i/o port port 46 ? excl 1 clock output t [ddr = 1] h [ddr = 0] t excl input [ddr = 1] clock output excl input excl input clock output/ excl input/ input port 2, 3 (expe = 1) t [ddr = 0] t 2, 3 (expe = 0) port 45 to 43 1 h t h h h h $6 , :5 , 5' $6 , :5 , 5' $6 , :5 , 5' 2, 3 (expe = 1) t 2, 3 (expe = 0) keep keep keep keep i/o port i/o port port 42 to 40 1 t t keep keep keep keep i/o port i/o port 2, 3 (expe = 1) 2, 3 (expe = 0) port 5 1 t t keep keep keep keep i/o port i/o port 2, 3 (expe = 1) 2, 3 (expe = 0) 770 table d.1 i/o port states in each processing state (cont) port name pin name mcu operating mode reset hardware standby mode software standby mode watch mode sleep mode sub- sleep mode subactive mode program execution state port 6 1 t t keep keep keep keep i/o port i/o port 2, 3 (expe = 1) 2, 3 (expe = 0) port 7 1 t t t t t t input port input port 2, 3 (expe = 1) 2, 3 (expe = 0) legend: h: high l: low t: high-impedance state keep: input ports are in the high-impedance state (when ddr = 0 and pcr = 1, mos input pull- ups remain on). output ports maintain their previous state. depending on the pins, the on-chip supporting modules may be initialized and the i/o port function determined by ddr and dr used. ddr: data direction register note: * in the case of address output, the last address accessed is retained. 771 appendix e timing of transition to and recovery from hardware standby mode e.1 timing of transition to hardware standby mode (1) to retain ram contents with the rame bit set to 1 in syscr, drive the 5(6 signal low 10 system clock cycles before the 67%< signal goes low, as shown in figure e.1. 5(6 must remain low until 67%< signal goes low (minimum delay from 67%< low to 5(6 high: 0 ns). stby res t 2 3 0 ns t 1 3 10t cyc figure e.1 timing of transition to hardware standby mode (2) to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained, 5(6 does not have to be driven low as in (1). e.2 timing of recovery from hardware standby mode drive the 5(6 signal low at least 100 ns before 67%< goes high to execute a reset. stby res t osc t 3 100 ns figure e.2 timing of recovery from hardware standby mode 772 773 appendix f product code lineup table f.1 h8s/2128 series and h8s/2124 series product code lineup preliminary product type product code mark code package (hitachi package code) notes h8s/2128 series h8s/2128 mask rom version standard product (5 v version, 4 v version, hd6432128 hd6432128( *** )ps 64-pin shrink dip (dp-64s) in planning stage 3 v version) hd6432128 (***) fa 64-pin qfp (fp-64a) hd6432128 (***) tf 80-pin tqfp (tfp-80c) version with on-chip i 2 c bus interface hd6432128w hd6432128w (***) ps 64-pin shrink dip (dp-64s) (5 v version, 4 v version, 3 v version) hd6432128w (***) fa 64-pin qfp (fp-64a) hd6432128w (***) tf 80-pin tqfp (tfp-80c) f-ztat version standard product (5 v/4 v version) hd64f2128 HD64F2128PS20 64-pin shrink dip (dp-64s) under development hd64f2128fa20 64-pin qfp (fp-64a) hd64f2128tf20 80-pin tqfp (tfp-80c) low-voltage version (3 v version) hd64f2128v hd64f2128vps10 64-pin shrink dip (dp-64s) under development hd64f2128vfa10 64-pin qfp (fp-64a) hd64f2128vtf10 80-pin tqfp (tfp-80c) h8s/2127 mask rom version standard product (5 v version, 4 v version, hd6432127r hd6432127r (***) ps 64-pin shrink dip (dp-64s) under development 3 v version) hd6432127r (***) fa 64-pin qfp (fp-64a) hd6432127r (***) tf 80-pin tqfp (tfp-80c) version with on-chip i 2 c bus interface hd6432127rw hd6432127rw (***) ps64-pin shrink dip (dp-64s) (5 v version, 4 v version, 3 v version) hd6432127rw (***) fa64-pin qfp (fp-64a) hd6432127rw (***) tf 80-pin tqfp (tfp-80c) 774 table f.1 h8s/2128 series and h8s/2124 series product code lineup (cont) preliminary product type product code mark code package (hitachi package code) notes h8s/2128 series h8s/2126 mask rom version standard product (5 v version, 4 v version, hd6432126r hd6432126r( *** )ps 64-pin shrink dip (dp-64s) under development 3 v version) hd6432126r (***) fa 64-pin qfp (fp-64a) hd6432126r (***) tf 80-pin tqfp (tfp-80c) version with on-chip i 2 c bus interface hd6432126rw hd6432126rw (***) ps 64-pin shrink dip (dp-64s) (5 v version, 4 v version, 3 v version) hd6432126rw (***) fa 64-pin qfp (fp-64a) hd6432126rw (***) tf 80-pin tqfp (tfp-80c) h8s/2124 series h8s/2124 mask rom version standard product (5 v version, 4 v version, hd6432124 hd6432124 (***) ps 64-pin shrink dip (dp-64s) in planning stage 3 v version) hd6432124 (***) fa 64-pin qfp (fp-64a) hd6432124 (***) tf 80-pin tqfp (tfp-80c) h8s/2123 mask rom version standard product (5 v version, 4 v version, hd6432123 hd6432123 (***) ps 64-pin shrink dip (dp-64s) in planning stage 3 v version) hd6432123 (***) fa 64-pin qfp (fp-64a) hd6432123 (***) tf 80-pin tqfp (tfp-80c) h8s/2122 mask rom version standard product (5 v version, 4 v version, hd6432122 hd6432122 (***) ps 64-pin shrink dip (dp-64s) 3 v version) hd6432122 (***) fa 64-pin qfp (fp-64a) hd6432122 (***) tf 80-pin tqfp (tfp-80c) h8s/2120 mask rom version standard product (5 v version, 4 v version, hd6432120 hd6432120 (***) ps 64-pin shrink dip (dp-64s) 3 v version) hd6432120 (***) fa 64-pin qfp (fp-64a) hd6432120 (***) tf 80-pin tqfp (tfp-80c) note: ( *** ) is the rom code. the f-ztat version of the h8s/2128 has an on-chip i 2 c bus interface as standard. the f-ztat 5 v/4 v version supports the operating ranges of the 5 v version and the 4 v version. the operating range of the f-ztat low-voltage version will be decided later. the above table includes products in the planning stage or under development. information on the status of individual products can be obtained from hitachis sales offices. 775 appendix g package dimensions figures g.1, g.2 and g.3 show the package dimensions of the h8s/2128 series and h8s/2124 series. unit: mm 0.25 + 0.11 ?0.05 0 ?15 1.78 0.25 0.48 0.10 0.51 min 2.54 min 5.08 max 19.05 57.6 58.5 max 1.0 1 33 32 64 17.0 18.6 max 1.46 max *dimension including the plating thickness base material dimension figure g.1 package dimensions (dp-64s) 776 unit: mm *dimension including the plating thickness base material dimension 0.10 0.15 m 17.2 0.3 48 33 49 64 1 16 32 17 17.2 ?.3 0.35 0.06 0.8 3.05 max 14 2.70 0 ?8 1.6 0.8 0.3 *0.17 0.05 0.10 +0.15 ?.10 1.0 *0.37 0.08 0.15 0.04 figure g.2 package dimensions (fp-64a) 777 unit: mm *dimension including the plating thickness base material dimension 0.10 m 0.10 0.5 0.1 0 ?8 1.20 max 14.0 0.2 0.5 12 14.0 0.2 60 41 120 80 61 21 40 *0.17 0.05 1.0 *0.22 0.05 0.10 0.10 1.00 1.25 0.20 0.04 0.15 0.04 figure g.3 package dimensions (tfp-80c) |
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