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ac 97 soundmax ? codec ad1981bl rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . ac 97 2.3 c o mpatible features s/pdif output, 20-bit data for m at, supporting 48 kh z an d 44. 1 kh z sample r a tes integrated ster eo headphone amplifier variable s a mple rate a u dio external audio power-down control >90 db dynami c range stereo full -dup lex codec 20-bit pcm da c 3 analog line- l evel stereo inputs for line -in, aux, and cd mono line-level phone input dual mic input with built-in programmable preamplifier high qua l ity c d input with gr ound sense mono output for speakerphone or internal s p eaker power management support 48-lea d lqfp package, pb-fre e avai lable enhanced features stereo mic preamplifier supp ort built-in digit a l equali zer f u nction for optimized speaker sound full- duplex var i able sample r a tes from 704 0 hz to 48 kh z with 1 hz reso l u tio n jack sense pins for au tomatic ou tpu t switching software-programmed v re f o ut ou tpu t for biasing microphone and external power amplifier low power 3.3 v operation for analog and di gital supplies multiple codec configuration options func tio n a l block di agram a m mic1 mic2 phone_in cd_l cd_gnd cd_r aux_l aux_r line_in_l mic preamp mono_out hp_out_l hp mz line_out_l mz line_out_r hp_out_r hp g = gain a = attenuation m = mute z = high z ga pcm front dac rate m m pcm l/r adc rate re co rd sel ec t o r g line_in_r codec core eapd pll xtl_out xtl_in spdif spdif tx id 0 id 1 re s e t ad c an d da c sl o t lo gic sync bit_clk sdata_out sdata_in e q co re s t o rag e js0 js1 eapd ad1981bl g g 2cmi c mi x a m a a a m m ga m ga m ga m ga m ga m ga m ga m ga m m ga m m eq b ypa ss eq g g m g m g ms analog mixing control logic ac '97 control registers v refout v ref b ypa ss 16-bit - ? adc 16-bit - ? adc 16-bit - ? adc 16-bit - ? adc 20-bit - ? dac 20-bit - ? dac cd diff amp 04321-001 voltage reference ac ' 9 7 i n t e r f ac e ou t p u t sel ec t o r fi g u r e 1 .
ad1981bl rev. a | page 2 of 32 table of contents specifications ..................................................................................... 3 test conditions ............................................................................. 3 general specifications ................................................................. 3 power-down states ...................................................................... 5 timing parameters ....................................................................... 5 absolute maximum ratings ............................................................ 9 environmental conditions .......................................................... 9 pin configuration and function descriptions ........................... 10 indexed control registers ............................................................. 12 control register details ................................................................ 13 reset register .............................................................................. 13 master volume register ............................................................. 13 headphone volume register .................................................... 14 mono volume register .............................................................. 15 phone volume register .............................................................. 15 mic volume register ................................................................. 16 line-in volume register ............................................................ 16 cd volume register ................................................................... 17 aux volume register ................................................................ 17 pcm-out volume register ....................................................... 18 record select control register ................................................. 19 record gain register ................................................................. 19 general-purpose register ......................................................... 20 power-down control/status register ..................................... 21 extended audio id register ..................................................... 22 extended audio status and control register ......................... 22 pcm front dac rate register ................................................. 23 pcm adc rate register ........................................................... 23 spdif control register ............................................................. 24 eq control register ................................................................... 24 eq data register ........................................................................ 26 mixer adc, input gain register ............................................. 26 jack sense/audio interrupt/status register ............................ 27 serial configuration register ................................................... 29 miscellaneous control bit register ......................................... 29 vendor id registers ................................................................... 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 1/05rev. 0 to rev. a updated format..................................................................universal changes to ordering guide .......................................................... 32 1/04revision 0: initial version
ad1981bl rev. a | page 3 of 32 specifications test conditions standard test conditions, unless otherwise noted. table 1. parameter test condition temperature 25c digital supply (dv dd ) 3.3 v analog supply (av dd ) 3.3 v sample rate (f s ) 48 khz input signal 1008 hz analog output pass band 20 hz to 20 khz dac calibrated ?3 db attenuation relative to full scale 0 db input 10 k? output load (line_out) 32 ? output load (hp_out) adc calibrated 0 db gain input ?3.0 db relative to full scale general specifications table 2. parameter min typ max unit analog input input voltage (rms values assume sine wave input) line_in, aux, cd, phone_in 0.707 v rms 2.0 v p-p mic_in with 20 db gain 0.0707 v rms 0.2 v p-p mic_in with 0 db gain 1.707 v rms 2.0 v p-p input i mpedanc e 1 20 k? input capacitance 1 5 7.5 pf master volume step size (0 db to ?46.5 db): line_out_l, line_out_r 1.5 db output attenuation range 1 46.5 db step size (0 db to ?46.5 db): mono_out 1.5 db output attenuation range 1 46.5 db step size (0 db to ?46.5 db): hp_out_r, hp_out_l 1.5 db output attenuation range span 1 46.5 db mute attenuation of 0 db fundamental 1 80 db programmable gain amplifieradc step size (0 db to 22.5 db) 1.5 db pga gain range 22.5 db analog mixerinput gain/amplifiers/attenuators signal-to-noise ratio (snr) cd to line_out 90 db other to line_out 1 90 db
ad1981bl rev. a | page 4 of 32 parameter min typ max unit step size (+12 db to ?34.5 db) (all steps tested): mic_in, line_in, cd, aux, phone_in, dac 1.5 db input gain/attenuation range: mic_in, line_in, cd, aux, phone_in, dac 46.5 db digital decimation and interpolation filters 1 pass band 0 0.4 f s hz pass-band ripple 0.09 db transition band 0.4 f s 0.6 f s hz stop band 0.6 f s hz stop-band rejection ?74 db group delay 16/f s sec group delay variation over pass band 0 s analog-to-digital converters resolution 16 bits total harmonic distortion (thd) ?87 db dynamic range (?60 db input thd + n referenced to full scale, a-weighted) 78 83 db signal-to-intermodulation distortion 1 ccif method) 85 db adc crosstalk 1 line inputs (input l, ground r, read r; input r, ground l, read l) ?80 db line_in to other ?100 ?80 db gain error 2 (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error 1 5 mv digital-to-analog converters resolution 20 bits total harmonic distortion (thd) line_out ?88 db total harmonic distortion (thd) hp_out ?81 db dynamic range (?60 db input thd + n referenced to full scale, a-weighted) 82 87.5 db signal-to-intermodulation distortion 1 (ccif method) ?100 db gain error 2 (output fs voltage relative to nominal output fs voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.7 db dac crosstalk 1 (input l, zero r, measure r_out; input r, zero l, measure l_out) ?80 db analog output full-scale output voltage; line_o ut and mono_out 0.707 v rms 2.0 v p-p output impedance 1 800 ? external load impedance 1 10 k? output capacitance 1 15 pf external load capacitance 1 100 pf full-scale output voltage; hp_out (0 db gain) 1 v rms external load impedance 1 32 ? v ref 1 1.12 1.225 v v refout 2.25 v v refout current drive 5 ma mute click (muted output minus unmuted midscale dac output) 5 mv static digital specifications high level input voltage (v ih ): digital inputs 0.65 dv dd v low level input voltage (v il ) 0.35 dv dd v high level output voltage (v oh ), i oh = 2 ma 0.9 dv dd v
ad1981bl rev. a | page 5 of 32 parameter min typ max unit low level output voltage (v ol ), i ol = 2 ma 0.1 dv dd v input leakage current ?10 +10 a output leakage current ?10 +10 a power supply power supply range (av dd and dv dd ) 3.0 3.47 v power dissipation 2.87 mw analog supply current3.3 v (av dd ) 39 ma digital supply current3.3 v (dv dd ) 48 ma power supply rejection (100 mv p-p signal at 1 khz) 1 (at both analog and digital supply pins, both adcs and dacs) 40 db clock specifications 1 input clock frequency 24.576 mhz recommended clock duty cycle 40 50 60 % 1 guaranteed but not tested. 2 measurements reflect main adc. power-down states values presented with v refout not loaded. table 3. parameter set bits dv dd typ av dd typ unit fully active no bits value 47.76 38.9 ma adc pr0 40.1 34.39 ma dac pr1 32.8 26.3 ma adc + dac pr1, pr0 13.2 20.55 ma mixer pr2 47.7 19.39 ma adc + mixer pr2, pr0 40 14.86 ma dac + mixer pr2, pr1 32.77 6.39 ma adc + dac + mixer pr2, pr1, pr0 13.9 1.15 ma standby pr5, pr4, pr3, pr2, pr1, pr0 0 0 ma headphone standby pr6 47.7 32 ma timing parameters guaranteed over operating temperature range. table 4. parameter symbol min typ max unit reset active low pulse width t rst_low 1.0 ms reset inactive to bit_clk start-up delay t rst2clk 162.8 ns sync active high pulse width t sync_high 1.3 s sync low pulse width t sync_low 19.5 s sync inactive to bit_clk start-up delay t sync2clk 162.8 ns bit_clk frequency 12.288 mhz bit_clk frequency accuracy 1 ppm bit_clk period t clk_period 81.4 ns bit_clk output jitter 1 , , 2 3 750 2000 ps bit_clk high pulse width t clk_high 32.56 42 48.84 ns bit_clk low pulse width t clk_low 32.56 38 ns sync frequency 48.0 khz
ad1981bl r e v. a | pa ge 6 o f 3 2 parameter symbol min typ max unit sync period t sy n c _ p eriod 20.8 ms setup to falling edge of bit_clk t set u p 5 2.5 ns hold from falling edge of bi t_c l k t hold 5 ns bit_clk rise ti me t riseclk 2 4 6 ns bit_clk fall time t f a llclk 2 4 6 ns sync rise time t risesy n c 2 4 6 ns sync fall t ime t f a llsy n c 2 4 6 ns sdata_in rise time t ri sedi n 2 4 6 ns sdata_in fall time t f a lldin 2 4 6 ns sdata_out rise time t ri sedou t 2 4 6 ns sdata_out fal l time t f a lldou t 2 4 6 ns end of slot 2 to bit_clk, sdata _ in low t s2_pdow n 0 1.0 ms setup to trailing edge of reset (applies to sync, sdata_out) t set u p2rst 15 ns rising edge of reset to high z delay t of f 25 ns propagation de l a y 15 ns reset rise time 50 ns output valid de lay from rising edge of bit_clk to sdi valid 15 ns 1 guarante e d but not te s t e d . 2 output jitte r is d i rectl y de pe nd e nt o n crys tal input jitte r. 3 m a ximum jitter s p ecif ication is for noncrys tal oper ation onl y. c r ys tal op eration maximum is much l o w e r. 04321-002 r ese t bit_clk sdata_in t rst_low t rst2clk t tri2actv t tri2actv f i g u re 2. cold r e s e t ti mi ng (cod ec is s u p p ly i n g t h e bi t_c l k s i g n a l ) 04321-003 sync bit_clk t sync_high t sync2clk f i gure 3. w a rm r e s e t t i m i ng
ad1981bl r e v. a | pa ge 7 o f 3 2 04321-004 bit_clk sync t clk_low t clk_high t clk_period t sync_low t sync_high t sync_period fi g u r e 4 . c l o c k t i m i n g 04321-005 bit_clk sync sdata_in sdata_out t fallclk t fallsync t falldin t falldout t riseclk t risesync t risedin t risedout f i gure 5 . s i gnal r i se a n d f a ll t i m e s 04321-006 bit_clk sync sdata_in sdata_out bit_clk not to scale slot 1 slot 2 write to 0x20 data pr4 t s2_pdown f i gure 6. a c -link l o w p o w e r m o de t i ming
ad1981bl r e v. a | pa ge 8 o f 3 2 04321-007 t setup t hold t co v il v ih v oh v ol bit_clk s data_ou t sdata_in sync f i gure 7. a c -link l o w p o w e r m o de t i ming , sy nc and bi t_ clk chop p e d 04321-008 t setup2rst t off re s e t sdata_out sdata_in, bit_clk, eapd, spdif_out and digital i/o high z fi g u r e 8 . a t e t e s t m o d e
ad1981bl r e v. a | pa ge 9 o f 3 2 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 5. p a r a m e t e r r a t i n g power supplie s digital (dv dd ) ? 0.3 v to +3.6 v analog (av dd ) ? 0.3 v to +6.0 v input current ( e x c ept supply pins) 10 ma signals pin s digital input voltage ? 0.3 v to dv dd + 0.3 v analog input voltage ? 0.3 v to av dd + 0.3 v ambient temperature range (operating) 0c to 70c s t r e s s es g r e a t e r t h a n t h os e lis t e d under a b s o l u te m a xi m u m r a tin g s m a y ca use pe rm a n en t d a ma g e t o t h e devi ce . t h is i s a st re ss r a t i n g on l y ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . environme n t a l c o n d i t io ns a m b i en t t e m p era t ur e r a ti n g (l q f p p a c k a g e ) t ca se = c a s e t e m p er a t ur e i n c pd = p o w e r dissi p a t ion in w ja th er mal res i s t an ce ( j u n c t ion t o a m b i en t) jc th e r m a l r e si s t a n c e ( j un cti o n t o c a se ) table 6. therm a l resistance package ja jc lqfp 50.1c/w 17.8c/w esd (electrostatic discharge) se nsit ive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test eq ui pment and can discharge wi thout detection. although this product features proprietary esd protection circ uitry, permane n t dama ge may occur on devices subj ected to high energy electrostatic discharges. theref ore, pr oper esd prec a utions are recomm ended to avoid perfor mance degrada - tion or los s of functional ity.
ad1981bl rev. a | page 10 of 32 pin conf iguration and fu nction descriptions 04321-009 nc = no connect spd if ea pd id1 id0 av ss 3 av dd 3 nc hp _ o ut_ r av ss 2 hp _ o ut_ l av dd 2 mono_ o ut ph on e_in aux _ l aux _ r js1 js0 cd_ l cd_ gnd_ re f cd_ r mi c1 mi c2 line _ i n_ l line _ i n_ r 1 2 3 4 5 6 7 8 9 10 11 12 dv dd 1 xtl_in xtl_out dv ss 1 sdata_out bit_clk dv ss 2 sdata_in dv dd 2 sync reset nc line_out_r line_out_l av dd 4 av ss 4 afilt4 afilt3 afilt2 afilt1 v refout v ref av ss 1 av dd 1 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 ad1981bl top view (not to scale) f i g u re 9. 48-l e ad l qfp pin conf ig u r at ion ta ble 7. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic i/o description digital i/o 2 xtl_in i crystal input (24 . 576 mhz) or external clock inpu t. 3 xtl_out o crystal output. 5 sdata_out i ac-link serial d a ta output, ad1 981bl da ta input stream. 6 bit_clk o/i ac-link bit cloc k output (12.288 mhz) or bit cl ock input, if secondary mode selected. 8 sdata_in o ac-link serial d a ta input, ad19 81bl data output stream. 10 sync i ac-link frame sync. 11 reset i ac-link reset, ad1981bl master hardware reset. 48 spdif o s/pdif output. chip selec ts 1 45 id0 i chip select inpu t 0 (ac t ive low). this pin ca n also be used as th e chain input fro m a secondary code c. 46 id1 i chip select inpu t 1 (ac t ive low). jack sense an d eapd 17 js0 i jack sense 0 input. 16 js1 i jack sense 1 input. 47 eapd o external amp p o wer-down control. analog i/o 13 phone_in i phone input. mo no input from telepho n y subs ystem speaker p h one or h a ndse t. 14 aux_l i auxiliary input left channel. 15 aux_r i aux i liary input r i ght channel. 18 cd_l i cd audio lef t c h annel. 19 cd_gnd_ref i cd audio analog grou nd refer e nce for differential cd input. 20 cd_ r i cd audio righ t channe l. 21 mic1 i microphon e 1 input (mono) or left cha nnel wh e n 2-channe l m o d e selected (stereo mic).
ad1981bl rev. a | page 11 of 32 pin no. mnemonic i/o description 22 mic2 i microphone 2 input (mono) or right cha nnel when 2-channel mode selected (stereo mic). 23 line_in_l i line-in left channel. 24 line_in_r i line-in right channel. 35 line_out_l o line-out (front) left channel. 36 line_out_r o line-out (front) right channel. 37 mono_out o monaural output to telephony su bsystem speaker phone. 39 hp_out_l o headphone left-channel output. 41 hp_out_r o headphone right-channel output. filter/reference 2 27 v ref o voltage reference filter. 28 v refout o voltage reference output 5 ma drive (i ntended for mic bias and power amp bias). 29 afilt1 o antialiasing filter capacitoradc right channel. 30 afilt2 o antialiasing filter capacitoradc left channel. 31 afilt3 o antialiasing filter capacitormixer adc right channel. 32 afilt4 o antialiasing filter capacitormixer adc left channel. power and ground signals 1 dv dd 1 i digital v dd , 3.3 v. 4 dv ss 1 i digital gnd. 7 dv ss 2 i digital gnd. 9 dv dd 2 i digital v dd , 3.3 v. 25 av dd 1 i analog v dd , 3.3 v. 26 av ss 1 i analog gnd. 38 av dd 2 i analog v dd , 3.3 v. 40 av ss 2 i analog gnd. 43 av dd 3 i analog v dd , 3.3 v. 44 av ss 3 i analog gnd. 34 av dd 4 i analog v dd , 3.3 v. 33 av ss 4 i analog gnd. no connects 12 nc no connect. 42 nc no connect. 1 these pins can also be used to select an external clock. see table 44. 2 these signals are connected to resistors, capacitors, or specific voltages.
ad1981bl rev. a | page 12 of 32 indexed control registers table 8. reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x00 reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0x0090 0x02 master volume mm x x lmv4 lmv3 lmv2 lmv1 lmv0 rm 1 x x rmv4 rmv3 rmv2 rmv1 rmv0 0x8000 0x04 headphone volume hpm x x lhv4 lhv3 lhv2 lhv1 lhv0 rm 1 x x rhv4 rhv3 rhv2 rhv1 rhv0 0x8000 0x06 mono volume mvm x x x x x x x x x x mv4 mv3 mv2 mv1 mv0 0x8000 0x0c phone volume phm x x x x x x x x x x phv4 phv3 phv2 phv1 phv0 0x8008 0x0e mic volume mcm x x x x x x x x m20 x mcv4 mcv3 mcv2 mcv1 mcv0 0x8008 0x10 line-in volume lvm x x llv4 llv3 llv2 llv1 llv0 rm 1 x x rlv4 rlv3 rlv2 rlv1 rlv0 0x8808 0x12 cd volume cvm x x lcv4 lcv3 lcv2 lcv1 lcv0 rm 1 x x rcv4 rcv3 rcv2 rcv1 rcv0 0x8808 0x16 aux volume am x x lav4 lav3 lav2 lav1 lav0 rm 1 x x rav4 rav3 rav2 rav1 rav0 0x8808 0x18 pcm-out volume om x x lov4 lov3 lov2 lov1 lov0 rm 1 x x rov4 rov3 rov2 rov1 rov0 0x8808 0x1a record select x x x x x ls2 ls1 ls0 x x x x x rs2 rs1 rs0 0x0000 0x1c record gain im x x x lim3 lim2 lim1 lim0 rm 1 x x x rim3 rim2 rim1 rim0 0x8000 0x20 general- purpose x x x x x x mix ms lpbk x x x x x x x 0x0000 0x26 power-down ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 0x000x 0x28 extd audio id idc1 idc0 x x revc1 revc0 amap x x x dsa1 dsa0 x spdif x vras 0xx605 0x2a extd audio stat/ctrl vforce x x x x spcv x x x x spsa1 spsa0 x spdif x vra 0x0000 0x2c pcm front dac rate srf15 srf14 srf13 srf12 sr f11 srf10 srf9 srf8 srf7 srf6 srf5 srf4 srf3 srf2 srf1 srf0 0xbb80 0x32 pcm l/r adc rate sra15 sra14 sra13 sra12 sr a11 sra10 sra9 sra8 sra7 sra6 sra5 sra4 sra3 sra2 sra1 sra0 0xbb80 0x3a spdif control v x spsr1 spsr0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy /aud pro 0x2000 0x60 eq ctrl eqm mad lben x x x x x x sym chs bca5 bca4 bca3 bca2 bca1 bca0 0x8080 0x62 eq data cfd15 cfd14 cfd13 cfd12 cfd11 cfd10 cfd9 cfd8 cfd7 cfd6 cfd5 cfd4 cfd3 cfd2 cfd1 cfd0 0x0000 0x64 mixer adc, volume mxm x x x lmg3 lmg2 lmg1 lmg0 rm 1 x x x rmg3 rmg2 rmg1 rmg0 0x8000 0x72 jack sense x x x js mt2 js mt1 js mt0 js1 eqb js0 eqb js1 tmr js0 tmr js1 md js0 md js1 st js0 st js1 int js0 int 0x0000 0x74 serial config slot 16 regm 2 regm 1 regm 0 x x x chen x x x ints x spal spdz splnk 0x7001 0x76 misc control bit dacz x msplt lodis dam x fmxe x mad pd 2cmic x mad st vrefh vrefd mbg1 mbg0 0x0000 0x7c vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 0x4144 0x7e vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 re v7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 0x5374 all registers are not shown. bits co ntaining an x are assumed to be reserved. odd register addresses are aliased to the next lower even address. reserved registers should not be written. zeros should be written to reserved bits. 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, the rm bit has no effect.
ad1981bl rev. a | page 13 of 32 control register details reset register index 0x00 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x00 reset x se4 se3 se2 se 1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0x0090 x is a wild card, and has no effect on the value. writing any value to this register performs a register reset that causes all registers to revert to their default values (ex cept 0x74, which forces the serial configuration). reading this register returns the id code of the part and a code for the type of 3d stereo enhancement. id[9:0] identify capability. the id decodes the capabiliti es of ad1981bl based on the functions listed in table 9. table 9. id bits bit function ad1981b id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 1 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 0 id7 20-bit dac resolution 1 id8 18-bit adc resolution 0 id9 20-bit adc resolution 0 master volume register index 0x02 this register controls the line_out volume controls for both stereo channels and the mute bit. each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 db each. because ac 97 defines 6-bit volume registers, to maintain compatibil ity whenever the d5 or d13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic . on readback, all lower five bits read 1s whenever these bits are set to 1. refer to table 12 for examples. reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x02 master volume mm x x lmv4 lmv3 lmv2 lmv1 lmv0 rm 1 x x rmv4 rmv3 rm v2 rmv1 rmv0 0x8000 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. all registers are not shown, and bits containing an x are assumed to be reserved. table 10. bit mnemonic function rmv [4:0] right master volume control the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. rm right-channel mute once enabled by the msplt bit in register 0x76, th is bit mutes the right channel separately from the mm bit. otherwise, this bit always reads 0 and has no effect when set to 1. lmv [4:0] left master volume control the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. mm master volume mute when this bit is set to 1, both the left and right channels are muted, unless the msplt bit in register 0x76 is set to 1, in which case this mute bit affects only the left channel.
ad1981bl rev. a | page 14 of 32 headphone volume register index 0x04 this register controls the headphone volume controls for both stereo channels and the mute bit. each volume subregister contain s five bits, generating 32 volume levels with 31 steps of 1.5 db each. be cause ac 97 defines 6-bit volume registers, to maintain comp atibility, whenever the d5 or d13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic . on readback, all lower five bits read 1s whenever these bits are set to 1. refer to table 12 for examples. reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x04 headphone volume hpm x x lhv4 lhv3 lhv2 lhv1 lhv0 rm 1 x x rhv4 rhv3 rh v2 rhv1 rhv0 0x8000 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. all registers are not shown, and bits containing an x are assumed to be reserved. table 11. bit mnemonic function rhv [4:0] right headphone volume control the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. rm right-channel mute once enabled by the msplt bit in register 0x76, th is bit mutes the right channel separately from the hpm bit. otherwise, this bit always read s 0 and has no effect when set to 1. lhv [4:0] left headphone volume control the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. hpm headphone volume mute when this bit is set to 1, both the left and right channels are muted, unless the msplt bit in register 0x76 is set to 1, in which case this mute bit affects only the left channel. table 12. volume settings for master and headphone reg. 0x76 control bits master volume (0x02) and headphone volume (0x04) left-channel volume d [13:8] right-channel volume d [5:0] msplt 1 d15 write readback function d7 1 write readback function 0 0 00 0000 00 0000 0 db gain x 00 0000 00 0000 0 db gain 0 0 00 1111 00 1111 ?22.5 db gain x 00 1111 00 1111 ?22.5 db gain 0 0 01 1111 01 1111 ?46.5 db gain x 01 1111 01 1111 ?46.5 db gain 0 0 1x xxxx 01 1111 ?46.5 db gain x 1x xxxx 01 1111 ?46.5 db gain 0 1 xx xxxx xx xxxx ? db gain, muted x xx xxxx xx xxxx ? db gain, muted 1 0 1x xxxx 01 1111 ?46.5 db gain 1 xx xxxx xx xxxx ? db gain, right only muted 1 1 xx xxxx xx xxxx ? db gain, left only muted 0 xx xxxx xx xxxx ?46.5 db gain 1 1 xx xxxx xx xxxx ? db gain, left muted 1 xx xxxx xx xxxx ? db gain, right muted 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. x is a wild card, and has no effect on the value.
ad1981bl rev. a | page 15 of 32 mono volume register index 0x06 this register controls the mono output volume and mute bit. th e volume register contains five bits, generating 32 volume levels with 31 steps of 1.5 db each. because ac 97 defines 6-bit volume regist ers, to maintain compatibility, whenever the d5 bit is set t o 1, their respective lower five volume bits are automatically set to 1 by the codec logic. on readback, all lower five bits read 1s whene ver this bit is set to 1. refer to table 14 for examples. reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x06 mono volume mvm x x x x x x x x x x mv4 mv3 mv2 mv1 mv0 0x8000 all registers are not shown, and bits containing an x are assumed to be reserved. table 13. bit mnemonic function mv [4:0] mono volume control the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. mvm mono volume mute when this bit is set to 1, the channel is muted. table 14. volume settings for mono control bits d [4:0] for mono (0x06) d15 write readback function 0 0 0000 0 0000 0 db gain 0 0 1111 0 1111 ?22.5 db gain 0 1 1111 1 1111 ?46.5 db gain 1 x xxxx x xxxx ? db gain, muted an x is a wild card, and has no effect on the value. phone volume register index 0x0c reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x0c phone volume phm x x x x x x x x x x phv4 phv3 phv2 phv1 phv0 0x8008 all registers are not shown, and bits containing an x are assumed to be reserved. refer to table 17 for examples. table 15. bit mnemonic function phv [4:0] phone volume allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 db each. the lsb represents 1.5 db, and the gain range is +12 db to ?34.5 db. the default value is 0 db, with the mute bit enabled. phm phone mute when this bit is set to 1, the phone channel is muted. all registers are not shown, and bits containing an x are assumed to be reserved. refer to table 17 for examples.
ad1981bl rev. a | page 16 of 32 mic volume register index 0x0e reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x0e mic volume mcm x x x x x x x x m20 x mcv4 mcv3 mcv2 mcv1 mcv0 0x8008 all registers are not shown, and bits containing an x are assumed to be reserved. refer to table 17 for examples. table 16. bit mnemonic function mcv [4:0] mic volume gain allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 db each. the lsb represents 1.5 db, and the gain rang e is +12 db to ?34.5 db. the default value is 0 db, with the mute bit enabled. m20 mic gain boost this bit allows setting additional mic gain to increase the microphon e sensitivity. the nominal gain boost by default is 20 db; however, bits d0 and d1 (mbg [1:0]) on the mis cellaneous control bits register (0x76) allow changing the gain boos t to 10 db or 30 db, if necessary. 0 = disabled; gain = 0 db 1 = enabled; default gain = 20 db (see register 0x76, bits d0, d1) mcm mic mute when this bit is set to 1, the mic channel is muted. table 17. volume settings for phone and mic control bits d [4:0] phone (0x0c) and mic (0x0e) d15 write readback function 0 0 0000 0 0000 12 db gain 0 0 1000 0 1000 0 db gain 0 1 1111 1 1111 ?34.5 db gain 1 x xxxx x xxxx ? db gain, muted x is a wild card, and has no effect on the value. line-in volume register index 0x10 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x10 line-in volume lvm x x llv4 llv3 llv2 llv1 llv0 rm 1 x x rlv4 rlv3 rlv2 rlv1 rlv0 0x8808 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. all registers are not shown, and bits containing an x are assumed to be reserved. refer to ta for examples. ble 22 table 18. bit mnemonic function rlv [4:0] line-in volume right allows setting the line-in right-channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to ?34.5 db. the default value is 0 db, mute enabled. rm right-channel mute once enabled by the msplt bit in register 0x76, th is bit mutes the right channel separately from the lm bit. otherwise, this bit always read s 0 and has no effect when set to 1. llv [4:0] line-in volume left allows setting the line-in left-channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to ?34.5 db. the default value is 0 db, mute enabled. lvm line-in mute when this bit is set to 1, both the left and right channels are muted, unless the msplt bit in register 0x76 is set to 1, in which case this mute bit affects only the left channel.
ad1981bl rev. a | page 17 of 32 cd volume register index 0x12 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x12 cd volume cvm x x lcv4 lcv3 lcv2 lcv1 lcv0 rm 1 x x rcv4 rcv3 rcv2 rcv1 rcv0 0x8808 1 f or ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. all registers are not shown, and bits containing an x are assumed to be reserved. refer to table 22 for examples. table 19. bit mnemonic function rcv [4:0] right cd volume allows setting the cd right-channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the gain range is +12 db to ?34.5 db. the default value is 0 db, mute enabled. rm right-channel mute once enabled by the msplt bit in register 0x76, th is bit mutes the right channel separately from the cvm bit. otherwise, this bit always read s 0 and has no affect when set to 1. lcv [4:0] left cd volume allows setting the cd left-channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the gain range is +12 db to ?34.5 db. the default value is 0 db, mute enabled. cvm cd volume mute when this bit is set to 1, both the left and right channels are muted, unless the msplt bit in register 0x76 is set to 1, in which case this mute bit affects only the left channel. aux volume register index 0x16 reg no. name d15 d14 d13 d12 d11 d1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x16 aux volume am x x lav4 lav3 lav2 lav1 lav0 rm 1 x x rav4 rav3 ra v2 rav1 rav0 0x8808 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. all registers are not shown, and bits containing an x are assumed to be reserved. refer to ta for examples. ble 22 table 20. bit mnemonic function rav [4:0] right aux volume allows setting the aux right-channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the gain range is +12 db to ?34.5 db. the default value is 0 db, mute enabled. rm right-channel mute once enabled by the msplt bit in register 0x76, th is bit mutes the right channel separately from the am bit. otherwise, this bit always read s 0 and has no affect when set to 1. lav [4:0] left aux volume allows setting the aux left-channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the gain range is +12 db to ?34.5 db. the default value is 0 db, mute enabled. am aux volume mute when this bit is set to 1, both the left and right channels are muted, unless the msplt bit in register 0x76 is set to 1, in which case this mute bit affects only the left channel.
ad1981bl rev. a | page 18 of 32 pcm-out volume register index 0x18 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x18 pcm-out volume om x x lov4 lov3 lov2 lov1 lov0 rm 1 x x rov4 rov3 rov2 rov1 rov0 0x8808 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. all registers are not shown, and bits containing an x are assumed to be reserved. refer to ta for examples. ble 22 table 21. bit mnemonic function rov [4:0] right pcm-out volume allows setting the pcm right-channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to ?34.5 db. the default value is 0 db, mute enabled. rm right-channel mute once enabled by the msplt bit in register 0x76, this bit mutes the right channel separately from the om bit. otherwise, this bit always re ads 0 and has no effect when set to 1. lov [4:0] left pcm-out volume allows setting the pcm left-channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to ?34.5 db. the default value is 0 db, mute enabled. om pcm-out volume mute when this bit is set to 1, both the left and right channels are muted unless the msplt bit in register 0x76 is set to 1, in which case this mute bit affects only the left channel. table 22. volume settings for line-in, cd volume, aux, and pcm-out control bits reg. 0x76 line-in (0x10), cd (0x12), aux (0x16), and pcm-out (0x18) left-channel volume d [12:8] right-channel volume d [4:0] msplt 1 d15 write readback function d7 1 write readback function 0 0 0 0000 0 0000 12 db gain x 0 0000 0 0000 12 db gain 0 0 0 1000 0 1000 0 db gain x 0 1000 0 1000 0 db gain 0 0 1 1111 1 1111 +34.5 db gain x 1 1111 1 1111 ?34.5 db gain 0 1 x xxxx x xxxx ? db gain, muted x x xxxx x xxxx ? db gain, muted 1 0 1 1111 1 1111 ?34.5 db gain 1 x xxxx x xxxx ? db gain, right only muted 1 1 x xxxx x xxxx ? db gain, left only muted 0 1 1111 1 1111 ?34.5 db gain 1 1 x xxxx x xxxx ? db gain, left muted 1 x xxxx x xxxx ? db gain, right muted 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. x is a wild card, and has no effect on the value.
ad1981bl rev. a | page 19 of 32 record select control register index 0x1a reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x1a record select x x x x x ls2 ls 1 ls0 x x x x x rs2 rs1 rs0 0x0000 used to select the record source independ ently for right and left. th e default value is 0x0000, wh ich corresponds to mic in. refer to table 24 for examples. all registers are not shown, and bits containing an x are assumed to be reserved. table 23. bit function rs [2:0] right record select ls [2:0] left record select table 24. settings for record select control ls [10:8] left record source rs [2:0] right record source 000 mic 000 mic 001 cd_l 001 cd_r 010 muted 010 muted 011 aux_l 011 aux_r 100 line_in_l 100 line_in_r 101 stereo mix (l) 101 stereo mix (r) 110 mono mix 110 mono mix 111 phone_in 111 phone_in record gain register index 0x1c reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x1c record gain im x x x lim3 lim2 lim1 lim0 rm 1 x x x rim3 rim2 rim1 rim0 0x8000 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. all registers are not shown, and bits containing an x are assumed to be reserved. refer to table 24 for examples. table 25. bit mnemonic function rim [3:0] right input mixer gain control each lsb represents 1.5 db, 0000 = 0 db, an d the gain range is 0 db to 22.5 db. rm right-channel mute once enabled by the msplt bit in register 0x76, th is bit mutes the right channel separately from the im bit. otherwise, this bit always read s 0 and has no affect when set to 1. lim [3:0] left input mixer gain control each lsb represents 1.5 db, 0000 = 0 db, an d the gain range is 0 db to 22.5 db. im input mute when this bit is set to 1, both the left and right channels are muted, unless the msplt bit in register 0x76 is set to 1, in which case this mute bit affects only the left channel.
ad1981bl rev. a | page 20 of 32 table 26. settings for record gain register reg. 0x76 control bits record gain (1channel) left-channel input mixer d [11:8] right-channel input mixer d [3:0] msplt 1 d15 write readback function d7 1 write readback function 0 0 1111 1111 22.5 db gain x 1111 1111 22.5 db gain 0 0 0000 0000 0 db gain x 0000 0000 0 db gain 0 1 xxxx xxxx ? db gain, muted x xxxx xxxx ? db gain, muted 1 0 1111 1111 22.5 db gain 1 xxxx xxxx ? db gain, right only muted 1 1 xxxx xxxx ? db gain, left only muted 0 1111 1111 22.5 db gain 1 1 xxxx xxxx ? db gain, left muted 1 xxxx xxxx ? db gain, right muted 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. x is a wild card, and has no effect on the value. general-purpose register index 0x20 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x20 general-purpose x x x x x x mix ms lpbk x x x x x x x 0x0000 this register should be read before writing to generate a mask for only the bit(s) that need to be changed. all registers are not shown, and bits containing an x are assumed to be reserved. table 27. bit mnemonic function lpbk loopback control adc/dac digital loopback mode. 0 = no loopback (default). 1 = loopback pcm digital data from adc output to dac. ms mic select selects mono mic input. 0 = select mic1. 1 = select mic2. see the 2cmic bit in register 0x76 to enable stereo microphone recording. mix mono output select sele cts mono output audio source. 0 = mixer mono output (reset default). 1 = mic1 channel.
ad1981bl rev. a | page 21 of 32 power-down control/status register index 0x26 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x26 power-down ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 0x000x the ready bits are read-only; writing to ref, anl, dac, adc has no effect. these bits indicate the status for the ad1981bl s ubsections. if the bit is a 1, that subsection is ready. ready is defined as the subsection able to perform in its nominal state. all registers are not shown, and bits containing an x are assumed to be reserved. table 28. bit mnemonic function adc adc sections ready to transmit data. dac dac sections ready to accept data. anl analog amplifiers, atte nuators, and mixers ready. ref voltage references, v ref and v refout , up to nominal level. pr [6:0] codec power- down modes the first three bits are to be used individually rather than in comb ination with each other. pr3 can be used in combination with pr2 or by itself. the mixer and reference cannot be powered down via pr3 unless the adcs and dacs are also powered down. nothing else can be powered up until the reference is powered up. pr5 has no effect unless all adcs, dacs, and the ac-link are powered down. the refere nce and the mixer can be either powered up or powered down, but all power-up sequences must be al lowed to run to completi on before pr5 and pr4 are both set. in multiple codec systems, the master codecs pr5 and pr4 bits control the slave codec. pr5 is also effective in the slave codec, if the masters pr5 bit is clear, but the pr4 bit has no e ffect except to enable or disable pr5. eapd external audio power-down control controls the state of the eapd pin. eapd = 0 sets the eapd pin low, enabling an external power amplifie r (reset default). eapd = 1 sets the eapd pin high, shutting the external power amplifier off. table 29. power-down state set bits pr [6:0] adcs and input mux power-down pr0 [000 0001] dacs power-down pr1 [000 0010] analog mixer power-down (v ref and v refout on) pr1, pr2 [000 0101] analog mixer power-down (v ref and v refout off) pr0, pr1, pr3 [000 1011] ac-link interface power-down pr4 [001 0000] internal clocks disabled pr 0, pr1, pr4, pr5 [011 0011] adc and dac power-down pr0, pr1 [000 0011] v ref standby mode pr0, pr1, pr2, pr4, pr5 [011 0111] total power-down pr0, pr1, pr2, pr3, pr4, pr5, pr6 [111 1111] headphone amp power-in standby pr6 [100 0000]
ad1981bl rev. a | page 22 of 32 extended audio id register index 0x28 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x28 extd audio id idc1 idc0 x x revc1 revc0 amap x x x dsa1 dsa0 x spdif x vras 0xx605 the extended audio id register identifies which extended audio features are supported. a nonzero extended audio id value ind icates that one or more of the extended audio features are supported. all registers are not shown, and bits containing an x are assumed to be reserved. table 30. bit mnemonic function vras variable rate pcm audio support (read-only) this bit returns a 1 when read to indicates that the variable rate pcm audio is supported. spdif spdif support (read-only) this bit returns a 1 when read to indicates that the spdif transmitter is supported (iec958). this bit is also used to validate that the spdif transmitter output is enabled. the spdif bit can be set high only if the spdif pin (pin 48) is pulled down at power-up, enabling the codec transmitter logic. if the spdif pin is floating or pulled high at power-up, the transmitter logic is disabled; therefore, this bit returns a low, indicating that the sp dif transmitter is not available. this bit must always be read back to verify that the spdi f transmitter is actually enabled. dsa [1:0] dac slot assignments (read/write) reset default = 00. 00 dacs 1, 2 = 3 and 4. 01 dacs 1, 2 = 7 and 8. 10 dacs 1, 2 = 6 and 9. 11 reserved. amap slot dac mappings based on codec id (read-only) this bit returns a 1 when read to indicate th at slot/dac mappings based on the codec id are supported. revc [1:0] ac 97 revision compliance revc [1:0] = 01 indicates that the codec is ac 97 revisi on 2.2-compliant (read-only). idc [1:0] indicates codec configuration (read-only) 00 = primary. 01, 10, 11 = secondary. extended audio status and control register index 0x2a reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x2a extd audio stat/ctrl vforce x x x x spcv x x x x spsa1 spsa0 x spdif x vra 0x0000 the extended audio status and control register is a read/write register that provides status and control of the extended audio features. all registers are not shown, and bits containing an x are assumed to be reserved. table 31. bit mnemonic function vra variable rate audio (read/write) vra = 0 sets the fixed sample rate audio to 48 khz (reset default). vra = 1 enables variable rate audio mode (enables sample rate registers and slotreq signaling). spdif spdif transmitter subsystem enable/disable bit (read/write) spdif = 1 enables the spdif transmitter. spdif = 0 disables the sp dif transmitter (default). this bit is also used to validate that the spdif transmitter output is enabled. the spdif bit can be set high only if the spdif pin (pin 48) is pulled down at power-up, enabling the codec transmitter logic. if the spdif pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit returns a low, indicating that the spdif trans mitter is not available. this bit must always be read back to verify th at the spdif transmitter is enabled. spsa [1:0] spdif slot assignment bits (read/write) these bits control the spdif slot assignment an d respective defaults, depending on the codec id configuration.
ad1981bl rev. a | page 23 of 32 bit mnemonic function spcv spdif configuration valid (read-only) this bit indicates the status of the spdif tr ansmitter subsystem, enabling the driver to determine if the currently programmed spdif config uration is supported. spcv is always valid, independent of the spdif enable bit status. spcv = 0 indicates that the current spdif config uration (spsa, spsr, dac slot rate, drs) is not valid (not supported). spcv = 1 indicates that the current spdif configur ation (spsa, spsr, dac slot rate, drs) is valid (supported). vforce validity force bit (reset default = 0) when asserted, this bit forces the spdif stream validity flag (bit 28 within each spdif l/r subframe) to be controlled by the v bit (d15) in register 0x3a (spdif control register). vforce = 0 and v = 0; the validity bit is ma naged by the codec error detection logic. vforce = 0 and v = 1; the validity bit is forced high, indicating the subframe data is invalid. vforce = 1 and v = 0; the validity bit is forced low, indicating the subframe data is valid. vforce = 1 and v = 1; the validity bit is forced hi gh, indicating the subframe data is invalid. table 32. ac 97 2.2 amap-compliant default spdif slot assignments codec id function spsa = 00 spsa = 01 spsa = 10 spsa = 11 00 2-channel primary w/spdif 3 and 4 7 and 8 (default) 6 and 9 10 and 11 00 4-channel primary w/spdif 3 and 4 7 and 8 6 and 9 (default) 10 and 11 00 6-channel primary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11 (default) 01 +2-channel secondary w/spdif 3 an d 4 7 and 8 6 and 9 (default) 01 +4-channel secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11 (default) 10 +2-channel secondary w/spdif 3 an d 4 7 and 8 6 and 9 (default) 10 +4-channel secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11 (default) 11 +2-channel secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11 (default) pcm front dac rate register index 0x2c reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x2c pcm front dac rate srf15 srf14 srf13 srf12 srf11 srf10 srf9 srf8 srf7 srf6 srf5 srf4 srf3 srf2 srf1 srf0 0xbb80 this read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in hz. table 33. bit mnemonic function srf [15:0] sample rate the sampling frequency range is from 7 khz (0x1b58) to 48 khz (0xbb80) in 1 hz increments. if 0 is written to vra, the sample rate is reset to 48 khz. pcm adc rate register index 0x32 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x32 pcm l/r adc rate sra15 sra14 sra13 sra12 sra11 sra10 sra9 sra8 sra7 sra6 sra5 sra4 sra3 sra2 sra1 sra0 0xbb80 this read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in hz. table 34. bit mnemonic function sra [15:0] sample rate the sampling frequency range is from 7 khz (0x1b58) to 48 khz (0xbb80) in 1 hz increments. if 0 is written to vra, the sample rate is reset to 48 khz.
ad1981bl rev. a | page 24 of 32 spdif control register index 0x3a reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x3a spdif control v x spsr1 spsr0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy aud pro 0x2000 register 0x3a is a read/write register that controls spdif functionality and manages bit fiel ds propagated as channel status (or subframe in the v case). with the exception of v, this register should be written to only when the spdif transmitter is disabled (spdif bit in register 0x2a is 0 ). this ensures that control and status information start up correctly at the beginning of spdif transmission. table 35. bit mnemonic function pro professional 1 = professional use of channel status. 0 = consumer. aud nonaudio 1 = data is non-pcm format. 0 = data is pcm format. copy copyright 1 = copyright is asserted. 0 = copyright is not asserted. pre pre-emphasis 1 = filter pre-emphasis is 50 s/15 s. 0 = pre-emphasis is none. cc [6:0] category code programmed accordin g to iec standards, or as appropriate. l generation level programmed according to iec standards, or as appropriate. spsr [1:0] spdif transmit sample rate spsr [1:0] = 00: transmit sample rate is 44.1 khz. spsr [1:0] = 01: reserved. spsr [1:0] = 10: transmit sample rate is 48 khz (reset default). spsr [1:0] = 11: not supported. v validity this bit affects the validity flag (bit 28 transmitted in each spdif l/r subframe) and enables the spdif transmitter to maintain connection du ring error or mute conditions. v = 1: each spdif subframe (l + r) has bit 28 set to 1. this tags both samples as invalid. v = 0: each spdif subframe (l + r) has bit 28 set to 0 for valid data and 1 for invalid data (error condition). when v = 0, asserting the vforce bit (d15) in regist er 0x2a (extd audio stat/ctrl) forces the validity flag low, marking both samples as valid. eq control register index 0x60 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x60 eq ctrl eqm mad lben x x x x x x sym chs bca5 bca4 bca3 bca2 bca1 bca0 0x8080 register 0x60 is a read/write register that controls the equalizer functionality and data setup. this register contains the biquad and coefficient address pointer, which is used in conjunction with the eq data register (0x78) to set up the equalizer coefficients. the reset default disables the eq ualizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels. all registers are not shown, and bits containing an x are assumed to be reserved. table 36. bit mnemonic function bca [5:0] biquad and coefficient address pointer biquad 0 coef a0 bca[5:0] = 011011 biquad 0 coef a1 bca[5:0] = 011010 biquad 0 coef a2 bca[5:0] = 011001 biquad 0 coef b1 bca[5:0] = 011101 biquad 0 coef b2 bca[5:0] = 011100 biquad 1 coef a0 bca[5:0] = 100000 biquad 1 coef a1 bca[5:0] = 011111
ad1981bl rev. a | page 25 of 32 bit mnemonic function biquad 1 coef a2 bca[5:0] = 011110 biquad 1 coef b1 bca[5:0] = 100010 biquad 1 coef b2 bca[5:0] = 100001 biquad 2 coef a0 bca[5:0] = 100101 biquad 2 coef a1 bca[5:0] = 100100 biquad 2 coef a2 bca[5:0] = 100011 biquad 2 coef b1 bca[5:0] = 100111 biquad 2 coef b2 bca[5:0] = 100110 biquad 3 coef a0 bca[5:0] = 101010 biquad 3 coef a1 bca[5:0] = 101001 biquad 3 coef a2 bca[5:0] = 101000 biquad 3 coef b1 bca[5:0] = 101100 biquad 3 coef b2 bca[5:0] = 101011 biquad 4 coef a0 bca[5:0] = 101111 biquad 4 coef a1 bca[5:0] = 101110 biquad 4 coef a2 bca[5:0] = 101101 biquad 4 coef b1 bca[5:0] = 110001 biquad 4 coef b2 bca[5:0] = 110000 biquad 5 coef a0 bca[5:0] = 110100 biquad 5 coef a1 bca[5:0] = 110011 biquad 5 coef a2 bca[5:0] = 110010 biquad 5 coef b1 bca[5:0] = 110110 biquad 5 coef b2 bca[5:0] = 110101 biquad 6 coef a0 bca[5:0] = 111001 biquad 6 coef a1 bca[5:0] = 111000 biquad 6 coef a2 bca[5:0] = 110111 biquad 6 coef b1 bca[5:0] = 111011 biquad 6 coef b2 bca[5:0] = 111010 chs channel select chs = 0 selects the left-channel coefficients data block. chs = 1 selects the right-channel coefficients data block. sym symmetry when set to 1, this bit indicate s that the left- and right-channel coefficients are equal. this shortens the coefficients setup sequence, because only the left-channel coefficients need to be addressed and set up. the right- channel coefficients are fetched from the left-channel memory. mad lben mixer adc loopback enable enables mixer adc data to be summed into the pcm stream. 0 = no loopback allowed (default). 1 = enable loopback. eqm equalizer mute when set to 1, this bit disables the equalizer function (allows all data to pass through). the reset default sets this bit to 1, disa bling the equalizer function until the biquad coefficients can be properly set.
ad1981bl rev. a | page 26 of 32 eq data register index 0x62 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x62 eq data cfd15 cfd14 cfd13 cfd12 cfd11 cfd10 cfd9 cfd8 cfd7 cfd6 cfd5 cfd4 cfd3 cfd2 cfd1 cfd0 0x0000 this read/write register is used to transfer eq biquad coe fficients into memory. the register data is transferred to, or ret rieved from, the address pointed to by the bca bits in the eq cntrl register (0x60). data is written to memory only if the eqm bit (register 0x60, bit 15) is asserted. table 37. bit mnemonic function cfd [15:0] coefficient data the biquad coefficients are fixed-point format valu es with 16 bits of resolution. the cfd15 bit is the msb, and the cfd0 bit is the lsb. mixer adc, input gain register index 0x64 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x64 mixer adc, volume mxm x x x lmg3 lmg2 lmg1 lmg0 rm 1 x x x rmg3 rmg2 rmg1 rmg0 0x8000 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. all registers are not shown, and bits containing an x are assumed to be reserved. refer to table 39 for examples. table 38. bit mnemonic function rmg [3:0] right mixer gain control this register controls the gain into the mixer ad c from 0 db to a maximum gain of 22.5 db. the least significant bit represents 1.5 db. rm right-channel mute once enabled by the msplt bit in register 0x76, this bit mutes the right channel separately from the mxm bit. otherwise, this bit always re ads 0 and has no affect when set to 1. lmg [3:0] left mixer gain control this register controls the gain into the mixer ad c, from 0 db to a maximum gain of 22.5 db. the least significant bit represents 1.5 db. mxm mixer gain register mute 0 = unmuted. 1 = muted (reset default). table 39. settings for mixer adc, input gain reg. 0x76 control bits mixer adc, input gain (0x64) left-channel mixer gain d [11:8] right-channel mixer gain d [3:0] msplt 1 d15 write readback function d7 1 write readback function 0 0 1111 1111 22.5 db gain x 1111 1111 22.5 db gain 0 0 0000 0000 0 db gain x 0000 0000 0 db gain 0 1 xxxx xxxx ? db gain, muted x xxxx xxxx ? db gain, muted 1 0 1111 1111 22.5 db gain 1 xxxx xxxx ? db gain, right only muted 1 1 xxxx xxxx ? db gain, left only muted 0 1111 1111 22.5 db gain 1 1 xxxx xxxx ? db gain, left muted 1 xxxx xxxx ? db gain, right muted 1 for ac 97 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 0x76. the msplt bit enables separat e mute bits for the left and right channels. if msplt is not set, the rm bit has no effect. x is a wild card, and has no effect on the value.
ad1981bl rev. a | page 27 of 32 jack sense/audio interrupt/status register index 0x72 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x72 jack sense x x x js mt2 js mt1 js mt0 js1 eqb js0 eqb js1 tmr js0 tmr js1 md js0 md js1 st js0 st js1 int js0 int 0x0000 all register bits are read/write except for js0st and js1st, which are read-only. all registers are not shown, and bits containing an x are assumed to be reserved. table 40. bit mnemonic function js0int js0 interrupt this bit indicates that pin js0 has generated an interrupt. this bit remains set until the software services the js0 interrupt, that is, js0 isr sh ould clear this bit by writing a 0 to it. the interrupt to the system is an or combination of this bit and js1int. the actual interrupt implementation is selected by the ints bit (register 0x76). it is also possible to generate a software system interrupt by writing a 1 to this bit. js1int js1 interrupt this bit indicates that pin js1 has generated an interrupt. this bit remains set until the software services the js1 interrupt, that is, js1 isr should cl ear this bit by writing a 0 to it. see the js0int description for details. js0st js0 state this bit always repor ts the logic state of the js0 pin. js1st js1 state this bit always repor ts the logic state of the js1 pin. js0md js0 mode this bit selects th e operation mode for the js0 pin. 0 = jack sense mode (default). 1 = interrupt mode. js1md js1 mode this bit selects th e operation mode for the js1 pin. 0 = jack sense mode (default). 1 = interrupt mode. js0tmr js0 timer enable if this bit is set to 1, js0 must be high for >278 ms to be recognized. js1tmr js1 timer enable if this bit is set to 1, js1 must be high for >278 ms to be recognized. js0eqb js0 eq bypass enable this bit enables js0 to control the eq bypass. when this bit is set to 1, js0 = 1 causes the eq to be bypassed. js1eqb js1 eq bypass enable this bit enables js1 to control the eq bypass. when this bit is set to 1, js1 = 1 causes the eq to be bypassed. jsmt [2:0] js mute enable selector these three bits select and enable the ja ck sense muting action (see table 41).
ad1981bl rev. a | page 28 of 32 table 41. jack sense mute selectjsmt [2:0] ref js1 headphone js0 line_out jsmt2 jsmt1 jsmt0 hp_out line_out mono_out notes 0 out (0) out (0) 0 0 0 active active active js0 and js1 ignored. 1 out (0) in (1) 0 0 0 active active active 2 in (1) out (0) 0 0 0 active active active 3 in (1) in (1) 0 0 0 active active active 4 out (0) out (0) 0 0 1 fmute fmute active js0 no mute action; js1 mutes line_out. 5 out (0) in (1) 0 0 1 fmute active active 6 in (1) out (0) 0 0 1 active fmute active 7 in (1) in (1) 0 0 1 active fmute active 8 out (0) out (0) 0 1 0 fmute fmute active js0 no mute action; js1 mutes mono and line-out. 9 out (0) in (1) 0 1 0 fmute active active 10 in (1) out (0) 0 1 0 active fmute fmute 11 in (1) in (1) 0 1 0 active fmute fmute 12 out (0) out (0) 0 1 1 ** ** ** ** reserved. 13 out (0) in (1) 0 1 1 ** ** ** 14 in (1) out (0) 0 1 1 ** ** ** 15 in (1) in (1) 0 1 1 ** ** ** 16 out (0) out (0) 1 0 0 fmute fmute active js0 mutes mono; js1 no mute action. 17 out (0) in (1) 1 0 0 fmute active fmute 18 in (1) out (0) 1 0 0 active fmute active 19 in (1) in (1) 1 0 0 active active fmute 20 out (0) out (0) 1 0 1 fmute fmute active js0 mutes mono; js1 mutes line-out. 21 out (0) in (1) 1 0 1 fmute active fmute 22 in (1) out (0) 1 0 1 active fmute active 23 in (1) in (1) 1 0 1 active fmute fmute 24 out (0) out (0) 1 1 0 fmute fmute active js0 mutes mono; js1 mutes mono and line-out. 25 out (0) in (1) 1 1 0 fmute active fmute 26 in (1) out (0) 1 1 0 active fmute fmute 27 in (1) in (1) 1 1 0 active fmute fmute 28 out (0) out (0) 1 1 1 ** ** ** ** reserved. 29 out (0) in (1) 1 1 1 ** ** ** 30 in (1) out (0) 1 1 1 ** ** ** 31 in (1) in (1) 1 1 1 ** ** ** fmute = output is forced to mute independent of the respective volume register setting. active = output is not muted, and its status is dependent on the respective volume register setting. out = nothing plugged into the jack and, therefore, the js status is low (via the load resistor pull-down). in = jack has plug inserted and, therefore, the js status is high (via the codec js internal pull-up).
ad1981bl rev. a | page 29 of 32 serial configuration register index 0x74 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x74 serial config slot16 regm2 regm1 regm 0 x x x chen x x x ints x spal spdz splnk 0x7001 this register is not reset when the reset register (register 0x00) is written. all registers are not shown, and bits containing an x are assumed to be reserved. table 42. bit mnemonic function splnk spdif link this bit enables the spdif to link with the dac for data requests. 0 = spdif and dac are not linked. 1 = spdif and dac are linked and receive th e same data requests (reset default). spdz spdif dacz 0 = repeat last sample out of th e spdif stream if fifo underruns (reset default). 1 = forces midscale sample out the sp dif stream if fifo underruns. spal spdif adc loop- around 0 = spdif transmitter is connected to the ac-link stream (reset default). 1 = spdif transmitter is connected to th e digital adc stream, not the ac-link. ints interrupt mode select this bit sele cts the js interrupt implementation path. 0 = bit 0 slot 12 (modem interrupt). 1 = slot 6 valid bit (mic adc interrupt). chen chain enable this bit enables chaining of a slave codec sdata_in stream into the id0 pin (pin 45). 0 = disable chaining (reset default). 1 = enable chaining into id0 pin. regm0 master codec register mask regm1 slave 1 codec register mask regm2 slave 2 codec register mask slot16 enable 16-bit slot mode slot 16 makes all ac-link slots 16 bits in length, fo rmatted into 16 slots. this is a preferred mode for dsp serial port interfacing. miscellaneous control bit register index 0x76 reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x76 misc control bit dacz x msplt lodis dam x fmxe x madpd 2cmic x madst vrefh vrefd mbg1 mbg0 0x0000 all registers are not shown, and bits containing an x are assumed to be reserved. table 43. bit mnemonic function mbg [1:0] mic boost gain change register these two bits allow changing the mic pr eamp gain from the nominal 20 db gain. this gain setting takes effect only while bit d6 (m20) on the mic volume register (0x0e) is set to 1; otherwise, the mic boost block has a gain of 0 db. 00 = 20 db gain (reset default). 01 = 10 db gain. 10 = 30 db gain. 11 = reserved.
ad1981bl rev. a | page 30 of 32 bit mnemonic function vrefd v refout disable this bit disables v refout , placing it into high z out mode. this bit overrides the vrefh bit selection. 0 = v refout pin is driven by the intern al reference (reset default). 1 = v refout pin is placed into high z out mode. vrefh v refout high 0 = v refout pin is set to 2.25 v output (reset default). 1 = v refout pin is set to 2.25 v output (is set to 3.7 v only if avdd = 5 v). madst mixer adc status bit this bit indicates status of the mixer digitizing adc (l eft and right channels). 0 = mixer adc not ready. 1 = mixer adc ready. 2cmic 2-channel mic select this bit enables simultaneous re cording from mic1 and mic2 inp uts for applications that use a stereo microphone array. this register works in conjunction with the ms bit in register 0x20. 0 = mic1 or mic2 (determined by the ms bit) is routed to the record selectors left and right mic channels, as well as to the mixer (reset default). 1 = mic1 is routed to the record selectors le ft mic channel and mic2 is routed to the record selectors right mic channel. in this mode, the ms bit should be set low, and mic1 can still be enabled into the mixer. madpd mixer adc power-down this bit controls power-down for mixer digitizing adc. 0 = mixer adc is powered on (default). 1 = mixer adc is powered down. fmxe front dac into mixer enable this bit controls the front (main) dac to mixer mute switches. 0 = front dac outputs are allowed to sum into the mixer (reset default). 1 = front dac outputs are muted into the mixer (blocked). dam digital audio mode pcm dac outputs bypass the analog mixer and are sent directly to the codec output. lodis line_out disable this bit disables the line_out pins (l/r), placin g them into high z mode so that the assigned output audio jack can be shared for the input function (or other function). 0 = line_out pins have normal audi o drive capability (reset default). 1 = line_out pins are placed into high z mode. msplt mute split this bit allows separate mute control bits for th e master, headphone, line_in, cd, aux, and pcm volume control registers as well as for the record gain register. 0 = both left- and right-channel mutes are controlled by bit 15 in the respective registers (reset default). 1 = bit 15 affects only the left-channel mute, an d bit 7 affects only the right-channel mute. dacz dac zero-fill this bit determines dac data fill under starved conditions. 0 = dac data is repeated when dacs are starved for data (reset default). 1 = dac is zero-filled when dacs are starved for data.
ad1981bl rev. a | page 31 of 32 vendor id registers index 0x7cC0x7e reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x7c vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 0x4144 s[7:0] this register is ascii encoded to a. f[7:0] this register is ascii encoded to d. reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0x7e vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 re v6 rev5 rev4 rev3 rev2 rev1 rev0 0x5374 t[7:0] this register is ascii encoded to s. rev[7:0] vendor-specific revision number: the ad1981bl assigns 0x74 to this field. table 44. codec id and external clock selection id1 id0 codec id codec clocking source 1 1 (00) primary 24.576 mhz loca l crystal or external into xtl_in. 1 0 (01) secondary 12.288 mhz external into bit_clk. 0 1 (00) primary 48.000 mhz external into xtl_in. 0 0 (00) primary 14.31818 mhz external into xtl_in. internally, the id pins have weak pull-ups and are inverted.
ad1981bl rev. a | page 32 of 32 outline dimensions compliant to jedec standards ms-026bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3. 5 0 0.15 0.05 f i g u re 10. 4 8 -l ead l o w p r of i l e q u ad f l at p a ckag e [l qf p ] (st - 48) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ad1981bljst 0c to 70c 48-lead low pr ofile quad flat package [lqfp] st-48 ad1981bljst-r eel 0c to 70c 48-lead low pr ofile quad flat package [lqfp] st-48 ad1981bljstz 1 0c to 70c 48-lead low profil e quad flat package [lqfp] st-48 ad1981bljstz-reel 1 0c to 70c 48-lead low profil e quad flat package [lqfp] st-48 1 z = pb-free part. th e ad1981bljstz i s a lead- f ree environ m entally fri e ndly pr oduct. it is manufac tured u s in g the most up-to-dat e material s and proces ses . the coating on the leads of each device is 100% p ure tin electroplate. the device i s suitab le for lead-fr ee ap plicat ions and can withstand surface- mount soldering at up to 255c (5 c). in a d di t i on , i t i s ba ckwa rd com p a t i b le wi t h con v en ti on a l t i n - l ea d s o l d e r i n g proces se s. th i s m e a n s t h a t t h e el e c t r opla t e d tin co ating can be so ld e r e d with tin - lead solder pastes at reflow temperatures of 220c to 235c. ? 2005 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04321C0C 1/05(a)

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