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1 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram features electronic designs incorporated ? one research drive ? westborough, ma 01581 usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com 1 meg x 16 bit cmos dynamic random access memory ? access times: 60 and 70ns ? edo cycle time 25 and 30ns ? single +3.3v (10%) supply operation ? 1024 cycles/16ms refresh ? ras - only, cas-before-ras,and hidden refresh capability ? low operating power dissipation ? low standby power ? common i/o ? all inputs/outputs ttl compatible package style ? 44/50 pin plastic tsop ? 42 pin plastic soj 1 megabit x 16 dynamic ram 3.3v, extended data out edi's ruggedized plastic 1mx16 dram allows the user to capitalize on the cost advantage of using a plastic compo- nent while not sacrificing all of the reliability available in a full military device. extended temperature testing is performed with the test patterns developed for use on edi's fully compliant drams. edi fully characterizes devices to determine the proper test patterns for testing at temperature extremes. this is critical because the operating characteristics of device change when it is operated beyond the commercial temperature range. using commercial test methods will not guarantee a device that operates reliably in the field at temperature extremes. users of edi's ruggedized plastic benefit from edi's extensive experience in characterizing drams for use in military systems. the x16 width of the memory allows the user to build a cost effective x64 wide main memory array for the power pc microprocessor. the wider memory width provides for a higher memory bandwidth required by today's systems. pin configurations pin names a?-a9 address inputs casl\ and cash\ column address strobe ras\ row address strobe w\ write control input g\ output enable dq1-dq16 data inputs/outputs vcc power (+5v10%) vss ground nc no connection vcc dq1 dq2 dq3 dq4 vcc dq5 dq6 dq7 dq8 nc vss dq16 dq15 dq14 dq13 vss dq12 dq11 dq10 dq9 nc nc nc w\ ras\ nc nc a0 a1 a2 a3 vcc nc casl\ cash\ g\ a9 a8 a7 a6 a5 a4 vss 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 vcc dq1 dq2 dq3 dq4 vcc dq5 dq6 dq7 dq8 nc nc w\ ras\ nc nc a0 a1 a2 a3 vcc vss a4 a5 a6 a7 a8 a9 g\ cash\ casl\ nc dq9 dq10 dq11 dq12 vss dq13 dq14 dq15 dq16 vss 1 2 3 4 5 6 7 8 9 42 pin 44/50 pin 1 50 26 25
2 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram absolute maximum ratings* recommended dc operating conditions electrical characteristics parameter sym conditions min typ max units average supply current from vcc icc1 ras\, cas\ cycling 170 ma operating (notes 3, 4) trc = twc = min, output open supply current from vcc icc2 ras\ = cas\ = w\=vih, outputs open 2 ma standby icc5 ras\ = cas\ =w\? vcc-0.2, outputs open 1 ma average supply current from vcc icc3 ras\,cas\ address cycling 150 ma refreshing (note 3) trc = min, outputs open average supply current from vcc icc4 ras\ = vil, cas\ = cycling 120 ma edo page mode (notes 3, 4) tpc = min, outputs open average supply current from vcc icc6 cas\ before ras\ refresh cycling 160 ma ras\ only refresh mode (note 3) cas\ before ras\ refresh mode (note 3) trc = min, outputs open input current iil 0v - vin - 6.5v -2 10 a all other input pins = 0v off-state output current ioz q floating 0v- v out - 5.5v -10 2 a output high voltage voh ioh = -2.0ma 2.4 vcc v output low voltage vol iol= 2.2ma 0 0.4 v (vcc = 5.0v 10%) note 2. voltage on any pin relative to vss -1.0v to 5.5v operating temperature ta (ambient) industrial -40c to +85c military -55c to +125c storage temperature -65c to +125c power dissipation 1 watt output current 50 ma *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note 1 parameter sym min typ max units supply voltage vcc 3.0 3.3 3.6 v supply voltage vss 0 0 0 v input high voltage vih 2 -- 5.5 v input low voltage vil -1.0 -- 0.8 v notes: 1. all voltage values are with respect to vss. block diagram notes: 2. current flowing into an ic is positive, out is negative. 3. icc1(av), icc3(av), icc4(av), and icc6 are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4. icc1(av), and icc4(av) are dependent on output loading. specified values are obtained with the output open. control clocks refresh timer refresh control refresh counter row address buffer col. address buffer row decoder memory array 1024x1024x16 cells column decoder data in buffer data out buffer sense amps & io ras cas w a0-a9 dq1 t o dq16 g casl cash g
3 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram capacitance (f=1.0mhz, vin=vcc or vss) parameter sym test conditions min typ max unit address input capacitance ca vi = vss 5 pf input capacitance (d) cd f = 1mhz 7 pf input capacitance (cas\,w\, ras\) cc, cw, cr vi = 25mvrms 7 pf output capacitance (q) cq vo = vss, f = 1mhz, vi = 25mvrms 7 pf input conditions for each mode the edi4161mev provides, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g.extended data out, ras\-only refresh, and delayed write. the input conditions for each are shown below. act = active vld = valid nac= non-active apd = applied dnc= don't care opn = open inputs input/output operation ras\ cas\ w\ g\ row column d q address address read* act act nac act apd apd opn vld early write* act act act dnc apd apd vld opn read-modify-write* act act act act apd apd vld vld ras\ -only refresh act nac dnc dnc apd dnc dnc opn hidden refresh act act dnc act apd dnc opn vld cas\ before ras\ refresh act act nac dnc dnc dnc dnc opn standby nac dnc dnc dnc dnc dnc dnc opn *extended data out mode identical.
4 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram timing requirements read, write, read-modify-write, refresh, and fast page mode cycles 60ns 70ns parameter sym min max min max unit notes random read or write cycle time trc 105 125 ns read-modify-write cycletime trwc 145 170 ns access time from cas\ tcac 15 20 ns 3,4,5 access time from ras\ trac 60 70 ns 3,4,10 access time from column address taa 30 35 ns 3,10 cas to output in low-z tclz 0 0 ns 6 output buffer turn-off delay toff 3 15 3 15 ns 6,14 transition time tt 2 50 2 50 ns 2 ras\ precharge time trp 40 50 ns ras\ low pulse width tras 60 10,000 70 10,000 ns ras\ hold time after cas\ low trsh 13 15 ns cas\ hold time after ras\ low tcsh 50 55 ns cas\ low pulse width tcas 12 10,000 13 10,000 ns ras\ to cas\ delay time trcd 14 45 14 50 ns 4 column address delay from ras\ low trad 12 30 12 35 ns 10 delay cas\ high to ras\ low tcrp 5 5 ns row address set up time tasr 0 0 ns row address hold time trah 10 10 ns column address set up time tasc 0 0 ns column address hold time tcah 10 12 ns column address hold time referenced ras tar 45 50 ns column address to ras\ setup tral 30 35 ns read set up time before cas\ low trcs 0 0 ns read hold time after cas\ high trch 0 0 ns 8 read hold time after ras\ high trrh 0 0 ns 8 write hold time after cas\ low twch 10 12 ns write command hold time referenced to ras twcr 45 55 ns write pulse width twp 10 12 ns ras\ hold time after write low trwl 15 15 ns cas\ hold time after write low tcwl 15 15 ns data set up time tds 0 0 ns 9 data hold time after cas\ low tdh 10 12 ns 9 data hold time referenced to ras tdhr 45 55 ns refresh cycle tref 16 16 ms write setup time before cas\ low twcs 0 0 ns 7 cas\ low to w\ low delay tcwd 35 40 ns 7 ras\ low to w\ low delay trwd 80 90 ns 7 column address setup to cas high tach 15 15 ns g low to output valid toe 15 20 ns 13 cas low to dout tcoh 3 3 ns ras low to w low twrh 10 10 ns write high to ras low twrp 10 10 ns address to w\ low delay tawd 55 60 ns 7 (vcc=3.3v10%) note 1,2,5,11,12
5 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram write cycle, early and delayed write (vcc = 5.0v10%) notes 1,2,5,11,12 60ns 70ns parameter sym min max min max unit notes cas\ setup for cas\ before ras\ refresh tcsr 5 5 ns cas\ hold for cas\ before ras\ refresh tchr 10 12 ns precharge to cas\ active trpc 5 5 ns access time from cas\ precharge tcpa 35 40 ns 3 edo page cycle time tpc 25 30 ns edo page read-modify-write cycle time tprwc75 85 ns cas precharge time (edo cycle) tcp 10 10 ns ras pulse width (edo cycle) trasp 60 125k 70 125k ns ras hold time from cas precharge trhcp 35 40 ns output disable time after g\ high tod 0 15 0 15 ns 6 write low to next g\ low toeh 12 12 ns g low to cas high setup time toes 5 5 ns g high hold from cas high toehc 10 10 ns oe high pulse width toep 10 10 ns g setup prior to ras during tord 0 0 ns hidden refresh cycle g delay from w twhz 0 13 0 15 ns w pulse to disable at cas high twpz 10 12 ns notes: 1. an initial pause of 100s is required after power-up followed by any 8 ror or cbr cycles before proper device operation is a chieved, and must be repeated whenever tref is exceeded. 2. vih(min) and vil(max) are reference levels for measuring timing of input signals. transition times are measured between vih (min) and vil(max) and are assumed to be 3ns for all inputs. 3. measured with a load equivalent to 2 ttl loads and 100pf. 4. operation within the trcd (max) limit insures that trac (max) can be met. trcd (max) is specified as a reference point only . if trcd is greater than the specified trcd(max) limit, then access time is controlled exclusively by tcac. 5. assumes that trcd>trcd (max) 6. this parameter defines the time at which the output achieves the open circuit condition and is not referenced to voh or vol . 7. twcs, trwd, tcwd and tawd are non restrictive operating parameters. they are included in the data sheet as electric characte ristics only. if twcs?twcs(min), the cycle is an early write and the data output will remain high impedance for the duration of the cycle. if tcwd?tcwd(min), trwd>t rwd(min) and tawd>tawd(min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. either trch or trrh must be satisfied for a read cycle. 9. these parameters are referenced to the cas leading edge in early write cycles and to the w leading edge in read-modify-write cycles. 10. operation within the trad(max) limit insures that trac(max) can be met. trad (max) is specified as a reference point only. if trad is greater than the specified trad(max) limit, then access time is controlled by taa. 11. 1024 (1k ref.) cycles of burst refresh must be executed within 16ms before and after self refresh, in order to meet refresh specification. 12. tar, twcr, and tdhr are referenced to trad (max). 13. if oe is tied permanently low, late write or read-modify-write operations are not permissible and should not be attempted. additionally, we must be pulsed during cas high time in order to place i/o buffers in high z. 14. toff (max) defines the time at which the output achieves the open circuit conditions, and is not referenced to voh or vol. it is referenced from the rising edge of ras or cas, whichever occurs last.
6 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram read cycle g a0-a9 w notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. 2. toff is referenced from rising edge of ras or cas, whichever occurs last.
7 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram write cycle, early write read write cycle late write and read-modify-write cycles notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. a0-a9 w dq g a0-a9 w dq g t rcs
8 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. g a0-a9 v ih v il ras edo-page-mode early write cycle notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. a0-a9 w dq g w dq edo-page-mode read cycle t rp
9 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram edo-page-mode read-write cycle edo-page-mode read-early-write cycle w dq a0-a9 g a0-a9 g notes: 1. tpc is for late write cycles only 2. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. w dq
10 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram read cycle with we controlled disable a0-a9 w g notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. ras- only refresh cycle a0-a9 w notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams.
11 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram cbr refresh cycle hidden refresh cycle w a0-a9 g (w=high, g=low) note 1 notes: 1. although w is a "don't care" at ras time during an access cycle (read or write), the system designer should implement w high for twrp and twrh. the design implementation will facilitate compatibility with future edo drams. notes: 1. a hidden refresh may also be performed after a write cycle. in this case, we = low and oe = high note 1 (a0-a9 and g=don't care)
12 edi4161mev-rp rev. 1 4/98 eco#10179 edi4161mev-rp 1meg x16 edo dram package no. 420 42 pin plastic soj package no. 371 44/50 pin plastic tsop electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 ordering information package description military (-55c to +125c) part no. speed (ns) package no. edi4161mev60sm 60 371 edi4161mev70sm 70 371 edi4161mev60mm 60 420 edi4161mev70mm 70 420 industrial (-40c to +85c) part no. speed (ns) package no. edi4161mev60si 60 371 edi4161mev70si 70 371 EDI4161MEV60MI 60 420 edi4161mev70mi 70 420 .006 .002 .024 .016 .008 .005 .830 .820 .471 .455 .047 max. .0315 typ .018 .012 see detail a .405 .395 .445 .435 20x.050 (1.000 ref.) .050 typ. .020 .015 .025 min. .370 nom. .405 .395 1.080 1.070 .148 max.

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