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hm51w4265c series 262,144-word 16-bit dynamic random access memory ade-203-477b (z) rev. 2.0 jul. 10, 1997 description the hitachi hm51w4265c series is a cmos dynamic ram organized as 262,144-word 16-bit. hm51w4265c series has realized higher density, higher performance and various functions by employing 0.8 m m cmos process technology and some new cmos circuit design technologies. the hm51w4265c series offers extended data out (edo) page mode as a high speed access mode. it is packaged in standard 44-pin plastic tsopii. features single 3.3 v supply: 3.3 v 0.15 v (hm51w4265c-6r) 3.3 v 0.3 v (hm51w4265c-6r) access time: 60 ns/70 ns/80 ns (max) power dissipation ? active mode: 576 mw/552 mw/468 mw/396 mw (max) ? standby mode: 6.9 mw (max) (hm51w4265c-6r) 7.2 mw (max) (hm51w4265c-6/7/8) 0.69 mw (max)(l-version) (hm51w4265cl-6r) 0.72 mw (max) (l-version) (hm51w4265cl-6/7/8) edo page mode capability refresh cycles ? 512 refresh cycles: 8 ms 128 ms (l-version) 3 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? self refresh 2 cas -byte control battery backup operation (l-version)
hm51w4265c series 2 ordering information type no. access time package hm51w4265ctt-6 hm51w4265ctt-6r hm51w4265ctt-7 hm51w4265ctt-8 60 ns 60 ns 70 ns 80 ns 400-mil 44-pin plastic tsopii (ttp-44/40db) hm51w4265cltt-6 hm51w4265cltt-6r hm51w4265cltt-7 HM51W4265CLTT-8 60 ns 60 ns 70 ns 80 ns
hm51w4265c series 3 pin arrangement hm51w4265ctt/clttseries (top view) v i/o0 i/o1 i/o2 i/o3 v i/o4 i/o5 i/o6 i/o7 nc nc we ras nc a0 a1 a2 a3 v cc cc cc v i/o15 i/o14 i/o13 i/o12 v i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a8 a7 a6 a5 a4 v ss ss ss 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 pin description pin name function a0 to a8 address input - row address a0 to a8 - column address a0 to a8 - refresh address a0 to a8 i/o0 to i/o15 data input/output ras row address strobe ucas , lcas column address strobe we read/write enable oe output enable v cc power supply v ss ground nc no connection
hm51w4265c series 4 block diagram 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder 128 k memory array mat 128 k memory array mat i/o bus & column decoder row decoder row decoder peripheral circuit address a0-a8 oe ras ucas we lcas selector selector selector selector selector selector selector selector selector selector selector selector selector selector selector selector i/o 1 i/o 14 i/o 2 i/o 13 i/o 3 i/o 12 i/o 4 i/o 11 i/o 5 i/o 10 i/o 6 i/o 9 i/o 15 i/o 0 i/o 7 i/o 8 i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer i/o buffer
hm51w4265c series 5 operation table the hm51w4265c series has the following 11 operation modes. 1. read cycle 2. early write cycle 3. delayed write cycle 4. read-modify-write cycle 5. ras -only refresh cycle 6. cas -before- ras refresh cycle 7. self refresh cycle 8. edo page mode read cycle 9. edo page mode early write cycle 10. edo page mode delayed write cycle 11. edo page mode read-modify-write cycle inputs ras lcas ucas we oe output operation h h h d d open standby h l l h l valid standby l l l h l valid read cycle llll* 2 d open early write cycle llll* 2 h undefined delayed write cycle l l l h to l l to h valid read-modify-write cycle l h h d d open ras -only refresh cycle h to l h l d d open cas -before- ras refresh cycle l h self refresh cycle ll l h to l h to l h l valid edo page mode read cycle l h to l h to l l* 2 d open edo page mode early write cycle l h to l h to l l* 2 h undefined edo page mode delayed write cycle l h to l h to l h to l l to h valid edo page mode read-modify-write cycle l l l h h open read cycle (output disabled) notes: 1. h: high(inactive) l: low(active) d: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) 2. t wcs 3 0 ns: early write cycle t wcs < 0 ns: delayed write cycle 3. mode is determined by the or function of the ucas and lcas . (mode is set by the earliest of ucas and lcas active edge and reset by the latest of ucas and lcas inactive edge.) however write operation and output high-z control are done independently by each ucas , lcas . ex. if ras = h to l, lcas = l, ucas = h, then cas -before- ras refresh cycle is selected.
hm51w4265c series 6 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t - 0.5 to +4.6 v supply voltage relative to v ss v cc - 0.5 to +4.6 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg - 55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit notes supply voltage v ss 00 0 v2 v cc (hm51w4265c-6r) 3.15 3.3 3.45 v 1, 2 v cc (hm51w4265c-6/7/8) 3.0 3.3 3.6 v 1, 2 input high voltage v ih 2.0 ? v cc + 0.3 v 1 input low voltage v il - 0.3 ? 0.8 v 1 notes: 1. all voltage referred to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hm51w4265c series 7 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.15 v, v ss = 0 v) (hm51w4265c-6r)* 5 (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hm51w4265c-6/7/8) * 5 hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit test conditions operating current* 1, * 2 i cc1 ? 120 ? 110 ? 95 ma ras , ucas , lcas cycling t rc = min standby current i cc2 ? 2 ? 2 ? 2 ma ttl interface ras , ucas , lcas = v ih dout = high-z ? 1 ? 1 ? 1 ma cmos interface ras , ucas , lcas we , oe 3 v cc - 0.2 v dout = high-z standby current (l-version) i cc2 ? 200 ? 200 ? 200 m a cmos interface ras , ucas , lcas , we , oe 3 v cc - 0.2 v dout = high-z ras -only refresh current* 2 i cc3 ? 120 ? 105 ? 92 ma t rc = min standby current* 1 i cc5 ? 5 ? 5 ? 5ma ras = v ih , ucas , lcas = v il dout = enable cas -before- ras refresh current* 2 i cc6 ? 120 ? 105 ? 92 ma t rc = min edo page mode current* 1, * 3 i cc4 ? 160 ? 130 ? 110 ma t hpc = min battery backup current* 4 (standby with cbr refresh) (l-version) i cc10 ? 200 ? 200 ? 200 m a standby: cmos interface dout = high-z cbr refresh: t rc = 250 m s t ras 1 m s, ucas , lcas = v il we , oe = v ih self-refresh mode current i cc11 ? 1 ? 1 ? 1 ma cmos interface ras , ucas , lcas 0.2 v dout = high-z self-refresh mode current (l-version) i cc11 ? 200 ? 200 ? 200 m a cmos interface ras , ucas , lcas 0.2 v dout = high-z input leakage current i li - 10 10 - 10 10 - 10 10 m a 0 v vin 4.6 v output leakage current i lo - 10 10 - 10 10 - 10 10 m a 0 v vout 4.6 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = - 2 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition.
hm51w4265c series 8 2. address can be changed once or less while ras = v il . 3. address can be changed once or less within one edo page cycle. 4. v ih 3 v cc - 0.2 v, 0 v il 0.2 v, address can be changed once or less while ras = v il . 5. all the v cc pins should be supplied with the same voltage. and all the v ss pins should be supplied with the same voltage. capacitance (ta = +25 c, v cc = 3.3 v 0.15 v) (hm51w4265c-6r) (ta = +25 c, v cc = 3.3 v 0.3 v) (hm51w4265c-6/7/8) parameter symbol typ max unit notes input capacitance (address) c i1 ? 5pf1 input capacitance (clocks) c i2 ? 7pf1 output capacitance (data-in, data-out) c i/o ? 10 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ucas and lcas = v ih to disable dout. ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.15 v, v ss = 0 v) (hm51w4265c-6r)* 1, * 14, * 15, * 17, * 18 (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hm51w4265c-6/7/8)* 1, * 14, * 15, * 17, * 18 test conditions input rise and fall time: 2 ns input levels: v il = 0 v, v ih = 3.0 v input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load: 1 ttl gate + c l (50 pf) (including scope and jig)
hm51w4265c series 9 read, write, read-modify-write and refresh cycles (common parameters) hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit notes random read or write cycle time t rc 104 ? 124 ? 144 ? ns ras precharge time t rp 40 ? 50 ? 60 ? ns ras pulse width t ras 60 10000 70 10000 80 10000 ns 27 cas pulse width t cas 10 10000 13 10000 15 10000 ns 28 row address setup time t asr 0 ? 0 ? 0 ? ns row address hold time t rah 10 ? 10 ? 10 ? ns column address setup time t asc 0 ? 0 ? 0 ? ns 19 column address hold time t cah 10 ? 13 ? 15 ? ns 19 ras to cas delay time t rcd 20 45 20 50 20 60 ns 8 ras to column address delay time t rad 15 30 15 35 15 40 ns 9 ras hold time t rsh 15 ? 18 ? 20 ? ns cas hold time t csh 48 ? 58 ? 68 ? ns 29 cas to ras precharge time t crp 10 ? 10 ? 10 ? ns 20 oe to din delay time t odd 15 ? 18 ? 20 ? ns oe delay time from din t dzo 0 ? 0 ? 0 ? ns cas setup time from din t dzc 0 ? 0 ? 0 ? ns transition time (rise and fall) t t 250250250ns7 refresh period t ref ? 8 ? 8 ? 8ms refresh period (l-version) t ref ? 128 ? 128 ? 128 ms
hm51w4265c series 10 read cycle hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit notes access time from ras t rac ? 60 ? 70 ? 80 ns 2, 3 access time from cas t cac ? 15 ? 20 ? 20 ns 3, 4, 13 access time from address t aa ? 30 ? 35 ? 40 ns 3, 5, 13 access time from oe t oac ? 15 ? 20 ? 20 ns 3, 23 read command setup time t rcs 0 ? 0 ? 0 ? ns 19 read command hold time to cas t rch 0 ? 0 ? 0 ? ns 16, 20 read command hold time to ras t rrh 0 ? 0 ? 0 ? ns 16 column address to ras lead time t ral 30 ? 35 ? 40 ? ns column address to cas lead time t cal 18 ? 23 ? 28 ? ns output buffer turn-off time t off1 ? 15 ? 15 ? 15 ns 6, 25 output buffer turn-off time to oe t off2 ? 15 ? 15 ? 15 ns 6 cas to din delay time t cdd 15 ? 18 ? 20 ? ns ras to din delay time t rdd 15 ? 18 ? 20 ? ns we to din delay time t wdd 15 ? 18 ? 20 ? ns oe pulse width t oep 15 ? 20 ? 20 ? ns 23 turn-off to ras t ofr ? 15 ? 15 ? 15 ns 6, 25 turn-off to we t wez ? 15 ? 15 ? 15 ns 6 output data hold time t oh 5 ? 5 ? 5 ? ns 25 output data hold time from ras t ohr 5 ? 5 ? 5 ? ns 25 read command hold time from ras t rchr 60 ? 70 ? 80 ? ns read command hold time from cas t rchc 15 ? 18 ? 20 ? ns read command hold time from column address t rcha 30 ? 35 ? 40 ? ns
hm51w4265c series 11 write cycle hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit notes write command setup time t wcs 0 ? 0 ? 0 ? ns 10, 19 write command hold time t wch 10 ? 13 ? 15 ? ns 19 write command pulse width t wp 10 ? 10 ? 10 ? ns write command to ras lead time t rwl 10 ? 13 ? 15 ? ns write command to cas lead time t cwl 10 ? 13 ? 15 ? ns 21 data-in setup time t ds 0 ? 0 ? 0 ? ns 11, 21 data-in hold time t dh 10 ? 13 ? 15 ? ns 11, 21 read-modify-write cycle hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 133 ? 159 ? 183 ? ns ras to we delay time t rwd 77 ? 90 ? 102 ? ns 10 cas to we delay time t cwd 32 ? 38 ? 42 ? ns 10 column address to we delay time t awd 47 ? 55 ? 62 ? ns 10 oe hold time from we t oeh 15 ? 18 ? 20 ? ns refresh cycle hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 ? 10 ? 10 ? ns 19 cas hold time (cbr refresh cycle) t chr 10 ? 10 ? 10 ? ns 20 ras precharge to cas hold time t rpc 10 ? 10 ? 10 ? ns 19 cas precharge time in normal mode t cpn 10 ? 13 ? 15 ? ns 22
hm51w4265c series 12 edo page mode cycle hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit notes edo page mode cycle time t hpc 25 ? 30 ? 35 ? ns 24 edo page mode cas precharge time t cp 10 ? 13 ? 15 ? ns 22 edo page mode ras pulse width t rasc ? 100000 ? 100000 ? 100000 ns 12 access time from cas precharge t acp ? 35 ? 40 ? 45 ns 3, 13, 20 ras hold time from cas precharge t rhcp 35 ? 40 ? 45 ? ns output data hold time from cas low t doh 3 ? 3 ? 3 ? ns 26 cas hold time referred oe t col 10 ? 13 ? 20 ? ns cas to oe setup time t cop 5 ? 5 ? 5 ? ns read command hold time from cas precharge t rchp 35 ? 40 ? 45 ? ns edo page mode read-modify-write cycle hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit notes edo page mode read-modify-write cycle time t hpcm 66 ? 77 ? 86 ? ns edo page mode read-modify-write cycle cas precharge to we delay time t cpw 52 ? 60 ? 67 ? ns 10, 20
hm51w4265c series 13 self refresh mode hm51w4265c -6/6r -7 -8 parameter symbol min max min max min max unit notes ras pulse width (self refresh) t rass 100 ? 100 ? 100 ?m s 30, 31, 32, 33 ras precharge time (self refresh) t rps 110 ? 130 ? 150 ? ns cas hold time (self refresh) t chs - 50 ?- 50 ?- 50 ? ns 21 notes: 1. ac measurements assume t t = 2 ns. 2. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 3. measured with a load circuit equivalent to 1 ttl loads and 50 pf. (v oh = 2.0 v, v ol = 0.8 v) 4. assumes that t rcd 3 t rcd (max) and t rad t rad (max). 5. assumes that t rcd t rcd (max) and t rad 3 t rad (max). 6. t off1 (max), t off2 (max), t ofr (max) and t wez (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only, if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 9. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only, if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 10. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only: if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. these parameters are referred to cas leading edge in an early write cycle and to we leading edge in a delayed write or a read-modify-write cycle. 12. t rasc defines ras pulse width in edo mode cycles. 13. access time is determined by the longest among t aa , t cac and t acp . 14. an initial pause of 100 m s is required after power up followed by a minimum of eight initialization cycles ( ras -only refresh cycle or cas -before- ras refresh cycle). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles is required. 15. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 16. either t rch or t rrh must be satisfied for a read cycle. 17. when both ucas and lcas go low at the same time, all 16-bit data are written into the device. ucas and lcas cannot be staggered within the same write/read cycles. 18. all the v cc and v ss pins shall be supplied with the same voltages. 19. t asc , t cah , t rcs , t wcs , t wch , t csr and t rpc are determined by the earlier falling edge of ucas or lcas . 20. t crp , t chr , t acp , t cpw and t rch are determined by the later rising edge of ucas or lcas . 21. t cwl , t dh , t ds and t chs should be satisfied by both ucas and lcas . 22. t cpn and t cp are determined by the time that both ucas and lcas are high.
hm51w4265c series 14 23. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 24. t hpc (min) can be achieved during a series of edo page mode early write cycles or edo page mode read cycles. if both write and read operation are mixed in a edo page mode ras cycle (edo page mode mix cycle (1), (2)), minimum value of cas cycle t hpc (t cas + t cp + 2t t ) becomes greater than the specified t hpc (min) value. 25. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off1 . 26. t doh defines the time at which the output level satisfied the output timing reference levels. measured with the test conditions. 27. t ras (min) = t rwd (min) + t rwl (min) + t t in read-modify-write cycle. 28. t cas (min) = t cwd (min) + t cwl (min) + t t in read-modify-write cycle. 29. t csh (min) can be achieved when t rcd t csh (min) - t cas (min). 30. please do not use t rass timing, 10 m s t rass 100 m s. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass 3 100 m s, then ras precharge time should use t rps instead of t rp . 31. if you use distributed cbr refresh mode with 15.6 m s interval in normal read/write cycle, cbr refresh should be executed within 15.6 m s immediately after exiting from and before entering into self refresh mode. 32. if you use ras only refresh or cbr burst refresh mode in normal read/write cycle, 512 cycles of distributed cbr refresh with 15.6 m s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 33. repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 34. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm51w4265c series 15 notes concerning 2 cas control please do not separate the ucas / lcas operation timing intentionally. however skew between ucas / lcas are allowed under the following conditions. 1. each of the ucas / lcas should satisfy the timing specifications individually. 2. different operation mode for upper/lower byte is not allowed; such as following. ras ucas lcas we delayed write early write 3. closely separated upper/lower byte control is not allowed. however when the condition (t cp t ul ) is satisfied, edo page mode can be performed. ras ucas lcas t ul 4. byte control operation by remaining ucas or lcas high is guaranteed.
hm51w4265c series 16 timing waveforms * 34 read cycle ras ucas lcas address we dout oe din t rc t ras t rp t crp t rcd t rsh t cas t t t rad t ral t asc t cah t asr row column t rah t rcs t rrh t dzc high-z dout t dzo t odd t rac t oep t aa t cac t off1 t csh t cdd t off2 t oac t cal t rdd t ofr t wdd t wez t rchr t rcha t oh t ohr t rch t rchc
hm51w4265c series 17 early write cycle ras address we din dout t ras t rp t rc t csh t crp t rcd t rsh t cas t t t cah t asc t rah t asr row column t wcs t ds t dh din high-z t wch ucas lcas
hm51w4265c series 18 delayed write cycle address ucas lcas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t odd t oeh t off2 din invalid dout* * high-z * do not enable dout during delayed write cycle.
hm51w4265c series 19 read-modify-write cycle address ras din dout oe we ucas lcas t rwc t ras t rp t crp t cas t rcd t t t rad t asr tt asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t odd t t oep t cac t aa t oac t rac t off2 oeh rah dout
hm51w4265c series 20 ras -only refresh cycle ucas lcas ras address t rc t ras t rp t t t crp t rpc t crp t asr t rah row high-z dout
hm51w4265c series 21 cas -before- ras refresh cycle ras address dout t rc t rc t rp t ras t rp t ras t rp t rpc t t t cpn t csr t chr t cpn t csr t rpc t chr t crp t off1 high-z ucas lcas
hm51w4265c series 22 edo page mode read cycle (t hpc minimum cycle operation) we din oe dout address ucas lcas ras t rasc t rhcp t rp t t t csh t rcd t cas t cp t cas t hpc t rsh t cp t cas t crp t ral t cah t asc t t asc t t rad t asr t rah t t rrh t rch t cdd t wez t high-z t t aa t t acp t t rac t aa t cac t cac t cac dout 3 dout 2 dout 1 row column 3 cah cah rcs asc t dzc t off1 t off2 t oac t dzo column 2 column 1 t rchp t rchc t rcha t oh t ohr t doh t doh t ofr acp aa t cal t cal t cal odd
hm51w4265c series 23 edo page mode read cycle (high-z control by we and oe ) din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t off2 t off1 t oh t ohr t t col t t acp t aa t cac t cac t oac t aa t rac t aa t cac t acp t t oac t off2 t aa t cac t t rasc cop t rp t cas t cas t cas t csh t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wdd t ral t cal t cal t cal row dout 2 dout 4 acp dout 1 t cas t rcs t t rcs dout 3 t doh t rhcp t hpc t cal t oac t wez dzo t odd dout 2 off2 rch t rchr t rchp t rchc t rcha t rchc asc
hm51w4265c series 24 edo page mode early write cycle (t hpc minimum cycle operation) ras ucas lcas address we din dout t rasc t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah row t wcs t wcs t wcs t wch t wch t wch t ds t dh t ds t dh t ds t dh din din din high-z column column column
hm51w4265c series 25 edo page mode delayed write cycle din we address ras dout ucas lcas t rasc t rp t t t csh t hpc t rsh t cas t rcd t cp t cas t cp t cas t crp t asr t rah t asc t t asc t cah t asc t cah row column t t rcs tt wp t cwl t cwl t t t t ds t t ds t dh din din din t rwl t rcs wp cah t rcs wp cwl dh ds dh oe t odd t oeh high-z column column
hm51w4265c series 26 edo page mode read-modify-write cycle din dout address ras t rasc t t cp t hpcm t t t rcd t t cp t rad t asr t asc t t t rah t t cah t t cpw t t cpw t cwl t rwd t awd t awd t awd t cwd t t cwd t cwd t rcs t wp t t wp t ds t t dh t t ds t dzc t dh t odd t dh t t dzo t oeh t oeh t oeh t aa t t off2 din din din t rp t rwl t oac t odd t off2 t t odd t dzo t off2 t t t dzo aa t we ucas lcas oe dout dout dout t cah t ds column column column row rac cwl acp wp cwl t crp asc acp t asc rcs high-z high-z oac t dzc dzc rcs oac t cas t cas t cas aa t t oep t oep t oep cah cac cac high-z cac
hm51w4265c series 27 edo page mode mix cycle (1) * 24 din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t off2 t off1 t oh t t cac t aa t cac t t t aa t oac t t rasc t rp t cas t cas t cas crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t cah t ral t cal t cal t cal row dout 2 dout 4 acp t cas t wcs dout 3 t doh t wp t wch t wdd t wez t ds t dh t ds t dh din 3 din 1 t cal t oac t odd t cac t asc t cpw t awd off2 acp aa t acp rchp t dzo t rchc t rcha t t csh t asc
hm51w4265c series 28 edo page mode mix cycle (2) * 24 din oe dout we address ras ucas lcas t cp t cp t cp t t t rch t rrh t cdd t rdd high-z t ofr t off2 t off1 t oh t acp t aa t cac t aa t cac t off2 t aa t oac t t rasc t rp t cas t cas t cas t csh crp t t asr t rah column 1 column 2 column 3 column 4 t asc t cah t asc t cah t cah t asc t cah t ral t cal t cal t cal row dout 1 dout 4 acp t cas dout 3 t wdd t wez t ds t dh t ds t din 3 din 2 t cal t oac t t cac t asc t wcs t rch t rcs t wch t rac t odd t dzo t oac t off2 dh odd t rchr t cpw t wp t cwl t rchp t rchc t rcha t dzo
hm51w4265c series 29 self refresh cycle* 30, 31, 32, 33 ras address dout t rp t rass t rps t rpc t t t cpn t csr t chs t crp t off1 high-z ucas lcas
hm51w4265c series 30 package dimensions hm51w4265ctt/cltt series (ttp-44/40db) unit: mm hitachi code jedec code eiaj code weight (reference value) ttp-44/40db mo-133ba sc-504-8c 0.43 g 0.13 m 0.10 0.80 44 23 122 18.41 18.81 max 0.27 0.07 1.20 max 10.16 11.76 0.20 0 ?5 0.145 0.05 1.005 max 10 13 32 35 2.40 0.13 0.05 0.50 0.10 0.68 0.80 0.25 0.05 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
hm51w4265c series 31 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein.1 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm51w4265c series 32 revision record rev. date contents of modification drawn by approved by 0.0 dec. 1, 1995 initial issue t. oono s. suzuki 1.0 jul. 31, 1996 addition of hm51w4265c-6 series ac characteristics change of note 25, 34 addition of note 30 notes concerning 2 cas control addition of note 4 timing waveforms deletion of notes about undefined pins. early write cycle. edo pagemode early write cycle. cas -before- ras refresh cycle. ras - only refresh cycle. self refresh cycle. m. tsunozaki s. suzuki 2.0 jul. 10, 1997 correct errors dc characteristics test conditions of i cc1 , i cc5 : ucas or ... to ucas , ... addition of note 5 ac characteristics correct numbers on tables t rps max: 130/130/130 ns to 110/130/150 ns notes concerning 2 cas control addition of description timing waveforms change order of waveforms cas -before- ras refresh cycle read-modify-write cycle

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