altera corporation 1 sonet sts-1 framer megacore function (STS1FRM) june 2001; ver. 1.01 data sheet a-ds-ipSTS1FRM-1.01 features performs synchronous optical network (sonet) framing and transmission convergence (tc) processes transport overhead (toh) and path overhead (poh) supports a data rate of up to 51.84 megabits per second (mbps) easy-to-use megawizard ? plug-in generates megacore ? variants quartus ? ii software and opencore ? feature allow place-and-route, and static timing analysis of designs prior to licensing secure register transfer level (rtl) simulation models allow simulation with user design in third-party simulators optimized for the altera ? apex tm 20ke device architecture typical applications figure 1 shows the STS1FRM interfacing with two other altera megacore variants to achieve atm transport over sonet. figure 1. typical application notes: (1) pif?processor interface block (2) the cp155 runs at 51.84 mhz. other possible applications include: atm switches digital cross-connection (dcc) systems routers multiplexers s e rializer deserializer clock data recovery sonet sts-1 framer (STS1FRM) atm cell processor 155 mbps (cp155)(2) utopia interface (utopia2sl) utopia level 2 bus external cpu pif (1) midbus atlantic cpu bus airbus apex 20k boundary txclk rxclk line interface circuit
2 altera corporation sonet sts-1 framer megacore function (STS1FRM) data sheet the STS1FRM complies with all applicable standards, including: ? american national standards institute (ansi), synchronous optical network (sonet) ?basic description including multiplex structure, rates, and formats, ansi t1-105? 1995 . ? american national standards institute (ansi), synchronous optical network (sonet) ?payload mappings, ansi t1-105.02? 1995 . ?telcordia, synchronous optical network (sonet) transport systems: common generic criteria, gr-253-core, issue 3, september 2000. ?telcordia, synchronous optical network (sonet) transport systems: common generic criteria issue list report, gr-253-ilr, issue 3a, october 2000. functional description the STS1FRM operates in full-duplex mode, and comprises four blocks, as illustrated in figure 2 . the following list of functions is based on a full-feature STS1FRM. see table 2 for all possible options. transport overhead receiver (rxtoh) ?inputs raw sonet data ? descrambles the data ? performs frame alignment ? performs error checking ? maintains counters and buffers ? captures the toh bytes for processing by software, and parameterized hardware extraction path overhead receiver (rxpoh_0) ? processes the pointer ? performs error checking ? maintains counters and buffers ? captures the poh bytes for processing by software, and parameterized hardware extraction ? outputs payload data transport overhead transmitter (txtoh) ? generates the pointer (normal, positive stuff, negative stuff, or new data flag (ndf) selected by software) ? allows the flexible insertion of the toh by software, or by parameterized hardware ? generates parity bytes ? maintains counters and buffers ? scrambles the data ? outputs raw sonet data
altera corporation 3 sonet sts-1 framer megacore function (STS1FRM) data sheet path overhead transmitter (txpoh_0) ? inputs payload data ? allows the flexible insertion of the poh by software, or by parameterized hardware ? generates parity bytes ? maintains counters and buffers interfaces & protocols two interfaces support the STS1FRM: the middle interface (midbus), and the access to internal registers (airbus) interface. midbus the midbus interface is a simple synchronous full-duplex data path bus. the STS1FRM midbus runs at 6.48 mhz over a single byte lane in each direction. in the receive (rx) direction, data is transferred from the midbus master (rxpoh_0) to the slave. in the transmit (tx) direction, data is transferred from the slave to the master (txpoh_0). in each direction, rx and tx, the midbus can carry eight bits per clock cycle. it includes midbus receive data ( mrxdat_0[7:0]) and midbus receive enable (mrxena_0) lines to indicate valid data transfers in the rx direction, and midbus transmit data ( mtxdat_0[7:0]) and midbus data enable (mtxena_0) lines to indicate valid data requests in the tx direction. airbus the airbus interface provides access to internal registers using a simple synchronous internal bus protocol. this consists of separate read data ( rdata[31:0] ) and write data ( wdata[31:0] ) buses, a data transfer acknowledge ( dtack ) signal, and a block select ( sel ) signal. an address ( addr[11:2] ) bus and read ( read ) signal indicate the location and type of access within the block. the rdata buses and dtack signals can be merged from multiple blocks using a simple or function. the dtack signal is sustained until the block sel is removed (four-way handshaking), meaning the airbus can cross clock domain boundaries. in the STS1FRM the airbus has a data width of 32 bits. more detailed information on the midbus, and airbus is available from the altera web site at http://www.altera.com/ipmegastore .
4 altera corporation sonet sts-1 framer megacore function (STS1FRM) data sheet figure 2. block diagram i/o signals the following is a port list for the STS1FRM. the signal direction is indicated by (i) for input, or (o) for output. rx clock domain signals: rxclk (i), rxclk_en (i), rxreset_n (i); sonet signals: srxdat[7:0] (i), srxval (i), srxfr (i); maintenance signals: align_data[7:0] (o), lopc (i), los (o), lof (o), sef (o); hardware serial toh extract signals: rxtohclk (o), rxtoh (o), rxtohval (o), rxtohfp (o), rxsdcc (o), rxsdccval (o), rxldcc (o), rxldccval (o), rxe1f1e2 (o), rxe1f1e2val (o), rxe1f1e2fp (o); hardware serial poh extract signals: rxpohclk_0 (o), rxpoh_0 (o), rxpohval_0 (o), rxpohfp_0 (o); midbus signals: mrxdat_0[7:0] (o), mrxena_0 (o), mrxval_0 (o), mrxffp_0 (o), mrxefp_0 (o), mrxfoh_0 (o), mrxeoh_0 (o). airbus signals: sel (i), read (i), addr[11:2] (i), rdata[31:0] (o), wdata[31:0] (i), dtack (o), irq (o) . txtohclk txtoh txtohen txtohfp txtohrdy txsdcc txsdccrdy txldcc txldccrdy txe1f1e2 txe1f1e2fp txe1f1e2rdy rxtohclk rxtoh rxtohval rxtohfp rxsdcc rxsdccval rxldcc rxldccval rxe1f1e2 rxe1f1e2val rxe1f1e2fp mrxefp_0 mrxffp_0 mrxval_0 mrxena_0 mrxdat_0[7:0] rxpohfp_0 rxpohval_0 rxpoh_0 rxpohclk_0 mrxfoh_0 mrxeoh_0 mtxdat_0[7:0] mtxena_0 mtxval_0 mtxffp_0 mtxefp_0 mtxfoh_0 mtxeoh_0 midbus sonet airbus irq dtack rdata[31:0] wdata[31:0] addr[11:2] read sel toh extract poh extract toh insert poh insert txtoh txpoh_0 rxtoh rxpoh_0 txpohrdy_0 txpohfp_0 txpohen_0 txpoh_0 txpohclk_0 align_data[7:0] srxdat[7:0] srxva l srxfr rxclk lopc los lof se f stxdat[7:0] stxval stxfp txclk rxclk_ e n rxreset_n txclk_en txreset_n stxfr rxclk domain txclk domain sonet
altera corporation 5 sonet sts-1 framer megacore function (STS1FRM) data sheet tx clock domain signals: txclk (i), txclk_en (i), txreset_n (i); sonet signals: stxdat[7:0] (o), stxval (o), stxfr (i), stxfp (o); hardware serial toh insert signals: txtohclk (o), txtoh (i), txtohen (i), txtohfp (o), txtohrdy (o), txsdcc (i), txsdccrdy (o) , txldcc (i), txldccrdy (o), txe1f1e2 (i), txe1f1e2fp (o), txe1f1e2rdy (o); hardware serial poh insert signals: txpohclk_0 (o), txpoh_0 (i), txpohen_0 (i), txpohfp_0 (o), txpohrdy_0 (o); midbus signals: mtxdat_0[7:0] (i), mtxena_0 (o), mtxval_0 (o) mtxffp_0 (o), mtxefp_0 (o), mtxfoh_0 (o), mtxeoh_0 (o) . performance table 1 shows the required speed and estimated gate count of the STS1FRM in an apex 20ke device. note: (1) the numbers for the logic elements (les) and embedded system blocks (esbs) are approximate as of may 25, 2001. they reflect the range from the basic to the full feature variant. generating variants table 2 shows the optional features available to generate all variants. note: (1) the numbers for the les and esbs are approximate as of may 25, 2001. users are strongly advised to run the megawizard plug-in and the quartus ii software to see exact numbers for each STS1FRM variant. table 1. performance note (1) les esbs frequency (mhz) 4,169 ? 6,843 1 ? 11 6.48 required to support 51.84 mbps table 2. optional features note (1) options parameters choices les esbs basic configuration ?? 4,169 1 serial insertion/extraction of toh and poh bytes soh y/n 619 0 64-byte insert, extract, and expect buffers automatic monitoring of extracted section trace j0 (transport overhead) j0b y/n 305 3 64-byte insert, extract, and expect buffers automatic monitoring of extracted path trace j1 (path overhead) j1b y/n 284 3 bit error rate monitoring with one second window bm1s y/n 1,495 4
sonet sts-1 framer megacore function (STS1FRM) data sheet 6 altera corporation altera, apex, apex 20k, megacore, megawizard, opencore, quartus, and quartus ii are trademarks and/or service marks of altera corporation in the united states and other countries. altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document. altera products are protected under numerous u.s. and foreign patents and pending applications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products to current specifications in accordance with altera?s standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. copyright ? 2001 altera corporation. all rights reserved. 101 innovation drive san jose, ca 95134 (408) 544-7000 http://www.altera.com applications hotline: (800) 800-epld customer marketing: (408) 544-7104 literature services: lit_req@altera.com licensing a license is not required to perform the following trial operations using your own custom logic: instantiation place-and-route static timing analysis simulation on a third-party simulator only when you are ready to generate programming files, do you need to obtain licenses through your local altera sales representative. all current variants use a single license with ordering code: plsm-STS1FRM. deliverables the following elements are provided with the STS1FRM package: data sheet user guide midbus and airbus interface functional specifications megawizard plug-in ? encrypted gate level netlist ? place-and-route constraints (where necessary) ? secure rtl simulation model demo testbench access to problem reporting system
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