16-bit latched transceivers sccs059b - august 1994 - revised september 2001 data sheet acquired from cypress semiconductor corporation. data sheet modi?d to remove devices not offered. cy74fct16543t cy74fct162543t CY74FCT162H543T copyright 2001, texas instruments incorporated features ? off supports partial-power-down mode operation edge-rate control circuitry for signi?antly improved noise characteristics typical output skew < 250 ps esd > 2000v tssop (19.6-mil pitch) and ssop (25-mil pitch) packages industrial temperature range of ? 40?c to +85?c ? cc = 5v 10% cy74fct16543t features: 64 ma sink current, 32 ma source current typical v olp (ground bounce) <1.0v at v cc = 5v, t a = 25?c cy74fct162543t features: balanced 24 ma output drivers reduced system switching noise typical v olp (ground bounce) <0.6v at v cc = 5v, t a = 25?c CY74FCT162H543T features: bus hold retains last active state eliminates the need for external pull-up or pull-down resistors functional description the cy74fct16543t and cy74fct162543t are 16-bit, high-speed, low power latched transceivers that are organized as two independent 8-bit d-type latched transceivers containing two sets of eight d-type latches with separate latch enable ( leab, leab) and output enable ( oeab, oeab) controls for each set to permit independent control of inputting and outputting in either direction of data flow. for data flow from a to b, for example, the a-to-b input enable ( ceab) must be low in order to enter data from a or to take data from b as indicated in the truth table. with caeb low, a low signal on the a-to-b latch enable ( leab) makes the a-to-b latches transparent; a subsequent low-to-high transition of the leab signal puts the a latches in the storage mode and their outputs no longer change with the a inputs. with ceab and oeab both low, the three-state b output buffers are active and reflect the data present at the output of the a latches. control of data from b to a is similar, but uses ceab, leab, and oeab inputs flow-through pinout and small shrink packaging and in simplifying board design. this device is fully speci?d for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current back?w through the device when it is powered down. the cy74fct16543t is ideally suited for driving high-capacitance loads and low-impedance backplanes. the cy74fct162543t has 24-ma balanced output drivers with current limiting resistors in the outputs. this reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. the cy74fct162543t is ideal for driving transmission lines. the CY74FCT162H543T is a 24-ma balanced output part that has ?us hold on the data inputs. the device retains the input s last state whenever the input goes to high impedance. this eliminates the need for pull-up/down resistors and prevents ?ating inputs.
cy74fct16543t cy74fct162543t CY74FCT162H543T 2 maximum ratings [3, 4] (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature .....................com? ? 55 c to +125 c ambient temperature with power applied .................................com? ? 55 c to +125 c dc input voltage .................................................? 0.5v to +7.0v dc output voltage ..............................................? 0.5v to +7.0v dc output current (maximum sink current/pin) ........................... ? 60 to +120 ma power dissipation .......................................................... 1.0w static discharge voltage............................................>2001v (per mil-std-883, method 3015) logic block diagrams pin configuration 1 oeab ssop/tssop top view gnd v cc fct16543t -1 fct16543t-2 to 7 other channels d c 1 b 1 1 oeba 1 a 1 1 ceba 1 leab 1 oeab 1 leba 1 ceab d c d c 2 b 1 2 oeba 2 a 1 2 ceba 2 oeab 2 leba 2 ceab 1 leab 1 ceab 1 a 1 v cc gnd 2 leab 1 a 2 1 a 3 1 a 5 1 a 4 1 a 6 1 a 7 1 a 8 gnd 2 a 1 2 a 2 2 a 3 2 a 4 2 a 5 2 a 6 2 a 7 2 a 8 gnd 2 oeab 2 ceab 2 leab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 oeba gnd v cc 1 leba 1 ceba 1 b 1 v cc gnd 1 b 2 1 b 3 1 b 5 1 b 4 1 b 6 1 b 7 1 b 8 gnd 2 b 1 2 b 2 2 b 3 2 b 4 2 b 6 2 b 7 2 b 8 gnd 2 oeba 2 ceba 2 leba 2 b 5 d c fct16543t-3 to 7 other channels pin description name description oeab a-to-b output enable input (active low) oeba b-to-a output enable input (active low) ceab a-to-b enable input (active low) ceba b-to-a enable input (active low) leab a-to-b latch enable input (active low) leba b-to-a latch enable input (active low) a a-to-b data inputs or b-to-a three-state outputs [9] b b-to-a data inputs or a-to-b three-state outputs [9] function table [1] inputs latch status output buffers ceab leab oeab a to b b h x x storing high z x h x storing x x x h x high z l l l transparent current a inputs l h l storing previous a inputs [2] operating range range ambient temperature v cc industrial ? 40 c to +85 c 5v 10%
cy74fct16543t cy74fct162543t CY74FCT162H543T 3 electrical characteristics over the operating range parameter description test conditions min. typ. [5] max. unit v ih input high voltage 2.0 v v il input low voltage 0.8 v v h input hysteresis [6] 100 mv v ik input clamp diode voltage v cc =min., i in = ? 18 ma ? 0.7 ? 1.2 v i ih input high current v cc =max., v i =v cc 1 a i il input low current v cc =max., v i =gnd 1 a i ozh high impedance output cur- rent (three-state output pins) v cc =max., v out =2.7v 1 a i ozl high impedance output cur- rent (three-state output pins) v cc =max., v out =0.5v 1 a i os short circuit current [7] v cc =max., v out =gnd ? 80 ? 140 ? 200 ma i o output drive current [7] v cc =max., v out =2.5v ? 50 ? 180 ma i off power-off disable v cc =0v, v out 4.5v [8] 1 a notes: 1. a-to-b data ?w shown; b-to-a ?w control is the same, except using ceba, leba, and oeba. 2. data prior to leab low-to-high transition h = high voltage level. l = low voltage level. x = don? care. z = high impedance. 3. operation beyond the limits set forth may impair the useful life of the device. unless otherwise noted, these limits are over the operating free-air temperature range. 4. unused inputs must always be connected to an appropriate logic voltage level, preferably either v cc or ground. 5. typical values are at v cc = 5.0v, t a = +25?c ambient. 6. this parameter is speci?d but not tested. 7. not more than one output should be shorted at a time. duration of short should not exceed one second. the use of high-speed test apparatus and/or sampl e and hold techniques are preferable in order to minimize internal chip heating and more accurately re?ct operational values. ot herwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. in any sequence of param eter tests, i os tests should be performed last. 8. tested at +25?c. 9. on the 74fct162h543t, these pins have bus hold.
cy74fct16543t cy74fct162543t CY74FCT162H543T 4 output drive characteristics for cy74fct16543t parameter description test conditions min. typ. [5] max. unit v oh output high voltage v cc =min., i oh = ? 3 ma 2.5 3.5 v v cc =min., i oh = ? 15 ma 2.4 3.5 v cc =min., i oh = ? 32 ma 2.0 3.0 v ol output low voltage v cc =min., i ol =64 ma 0.2 0.55 v output drive characteristics for cy74fct162543t, CY74FCT162H543T parameter description test conditions min. typ. [5] max. unit i odl output low current [7] v cc =5v, v in =v ih or v il , v out =1.5v 60 115 150 ma i odh output high current [7] v cc =5v, v in =v ih or v il , v out =1.5v ? 60 ? 115 ? 150 ma v oh output high voltage v cc =min., i oh = ? 24 ma 2.4 3.3 v v ol output low voltage v cc =min., i ol =24 ma 0.3 0.55 v capacitance [6] (t a = +25?c, f = 1.0 mhz) parameter description test conditions typ. [5] max. unit c in input capacitance v in = 0v 4.5 6.0 pf c out output capacitance v out = 0v 5.5 8.0 pf power supply characteristics parameter description test conditions typ. [5] max. unit i cc quiescent power supply current v cc =max. v in 0.2v, v in v cc ? 0.2v 5 500 a ? i cc quiescent power supply current (ttl inputs high) v cc =max. v in =3.4v [10] 0.5 1.5 ma i ccd dynamic power supply current [11] v cc =max., one input toggling, 50% duty cycle, outputs open, oe=gnd v in =v cc or v in =gnd 60 100 a/mhz i c total power supply current [12] v cc =max., f 1 =10 mhz, 50% duty cycle, outputs open, one bit toggling, oe=gnd v in =v cc or v in =gnd 0.6 1.5 ma v in =3.4v or v in =gnd 0.9 2.3 ma v cc =max., f 1 =2.5 mhz, 50% duty cycle, outputs open, sixteen bits toggling, oe=gnd v in =v cc or v in =gnd 2.4 4.5 [13] ma v in =3.4v or v in =gnd 6.4 16.5 [13] ma notes: 10. per ttl driven input (v in =3.4v); all other inputs at v cc or gnd. 11. this parameter is not directly testable, but is derived for use in total power supply calculations. 12. i c =i quiescent + i inputs + i dynamic i c =i cc + ? i cc d h n t +i ccd (f 0 /2 + f 1 n 1 ) i cc = quiescent current with cmos input levels ? i cc = power supply current for a ttl high input (v in =3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f 0 = clock frequency for registered devices, otherwise zero f 1 = input signal frequency n 1 = number of inputs changing at f 1 all currents are in milliamps and all frequencies are in megahertz. 13. values for these conditions are examples of the i cc formula. these limits are speci?d but not tested.
cy74fct16543t cy74fct162543t CY74FCT162H543T 5 switching characteristics over the operating range [14] cy74fct16543t cy74fct162543t cy74fct16543at cy74fct162543at fig. no. [15] parameter description min. max. min. max. unit t plh t phl propagation delay transparent mode a to b or b to a 1.5 8.5 1.5 6.5 ns 1, 3 t plh t phl propagation delay leba to a, leab to b 1.5 12.5 1.5 8.0 ns 1, 5 t pzh t pzl output enable time oeba or oeab to a or b ceba or ceab to a or b 1.5 12.0 1.5 9.0 ns 1, 7, 8 t phz t plz output disable time oeba or oeab to a or b ceba or ceab to a or b 1.5 9.0 1.5 7.5 ns 1, 7, 8 t su set-up time high or low a or b to leab or leba 2.0 2.0 ns 4 t h hold time high or low a or b to leab or leba 2.0 2.0 ns 4 t w leba or leab pulse width low 4.0 4.0 ns 5 t sk(o) output skew [16] 0.5 0.5 ns cy74fct16543ct cy74fct162543ct cy74fct162h543ct fig. no. [15] parameter description min. max. unit t plh t phl propagation delay transparent mode a to b or b to a 1.5 5.1 ns 1, 3 t plh t phl propagation delay leba to a, leab to b 1.5 5.6 ns 1, 5 t pzh t pzl output enable time oeba or oeab to a or b ceba or ceab to a or b 1.5 7.8 ns 1, 7, 8 t phz t plz output disable time oeba or oeab to a or b ceba or ceab to a or b 1.5 6.5 ns 1, 7, 8 t su set-up time high or low a or b to leab or leba 2.0 ns 4 t h hold time high or low a or b to leab or leba 2.0 ns 4 t w leba or leab pulse width low 4.0 ns 5 t sk(o) output skew [16] 0.5 ns notes: 14. minimum limits are speci?d but not tested on propagation delays. 15. see ?arameter measurement information?in the general information section. 16. skew between any two outputs of the same package switching in the same directional. this parameter is ensured by design.
cy74fct16543t cy74fct162543t CY74FCT162H543T 6 ordering information CY74FCT162H543T ordering information cy74fct16543 speed (ns) ordering code package name package type operating range 5.1 cy74fct16543ctpvc/pvct o56 56-lead (300-mil) ssop industrial 6.5 cy74fct16543atpact z56 56-lead (240-mil) tssop industrial 8.5 cy74fct16543tpvc/pvct o56 56-lead (300-mil) ssop industrial ordering information cy74fct162543 speed (ns) ordering code package name package type operating range 5.1 74fct162543ctpact z56 56-lead (240-mil) tssop industrial cy74fct162543ctpvc o56 56-lead (300-mil) ssop 74fct162543ctpvct o56 56-lead (300-mil) ssop 6.5 74fct162543atpact z56 56-lead (240-mil) tssop industrial 8.5 cy74fct162543tpvc/pvct o56 56-lead (300-mil) ssop industrial speed (ns) ordering code package name package type operating range 5.1 74fct162h543ctpact z56 56-lead (240-mil) tssop industrial
cy74fct16543t cy74fct162543t CY74FCT162H543T 7 package diagrams 56-lead shrunk small outline package o56 56-lead thin shrunk small outline package z56
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