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32k/64kx18 low voltage deep sync fifos cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 november 20, 2000 features ? 3.3v operation for low power consumption and easy integration into low-voltage systems high-speed, low-power, first-in first-out (fifo) memories 8k x 18 (cy7c4255v) 16k x 18 (cy7c4265v) 32k x 18 (cy7c4275v) 64k x 18 (cy7c4285v) 0.35 micron cmos for optimum speed/power high-speed 100-mhz operation (10-ns read/write cycle times) low power ? i cc = 30 ma ? i sb = 4 ma fully asynchronous and simultaneous read and write operation empty, full, half full, and programmable almost empty and almost full status flags retransmit function output enable (oe ) pin independent read and write enable pins supports free-running 50% duty cycle clock inputs width expansion capability depth expansion capability 64-pin 10x10 stqfp pin-compatible density upgrade to cy7c42x5v-asc families pin-compatible 3.3v solutions for cy7c4255/65/75/85 functional description the cy7c4255/65/75/85v are high-speed, low-power, first-in first-out (fifo) memories with clocked read and write interfac- es. all are 18 bits wide and are pin/functionally compatible to the cy7c42x5v synchronous fifo family. the cy7c4255/65/75/85v can be cascaded to increase fifo depth. programmable features include almost full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multipro- cessor interfaces, and communications buffering. these fifos have 18-bit input and output ports that are con- trolled by separate clock and enable signals. the input port is controlled by a free-running clock (wclk) and a write enable pin (wen ). when wen is asserted, data is written into the fifo on the rising edge of the wclk signal. while wen is held active, data is continu- ally written into the fifo on each cycle. the output port is controlled in a similar manner by a free-running read clock (rclk) and a read enable pin (ren ). in addition, the cy7c 4255/65/75/85v have an output enable pin (oe ). the read and write clocks may be tied togeth- er for single-clock operation or the two clocks may be run indepen- dently for asynchronous read/write applications. clock frequencies up to 67 mhz are achievable. retransmit and synchronous almost full/almost empty flag features are available on these devices. depth expansion is possible using the cascade input (wxi , rxi ), cascade output (wxo , rxo ), and first load (fl ) pins. the wxo and rxo pins are connected to the wxi and rxi pins of the next device, and the wxo and rxo pins of the last device should be connected to the wxi and rxi pins of the first device. the fl pin of the first device is tied to v ss and the fl pin of all the remaining devic- es should be tied to v cc . q 0? 17 4275v?1 three-st ate output register read control flag logic write control write pointer read pointer reset logic expansion logic input register flag program register d 0? 17 ren rclk ff ef pae wen wclk rs fl /rt wxi oe paf wxo /hf rxi rxo smode logic block diagram high density dual-port ram array 8kx9 32kx9 16kx9 64kx9
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 2 functional description (continued) the cy7c4255/65/75/85v provides five status pins. these pins are decoded to determine one of five states: empty, al- most empty, half full, almost full, and full (see ta b l e 2 ). the half full flag shares the wxo pin. this flag is valid in the stand-alone and width-expansion configurations. in the depth expansion, this pin provides the expansion out (wxo ) informa- tion that is used to signal the next fifo when it will be acti- vated. the empty and full flags are synchronous, i.e., they change state relative to either the read clock (rclk) or the write clock (wclk). when entering or exiting the empty states, the flag is updated exclusively by the rclk. the flag denoting full states is updated exclusively by wclk. the synchronous flag archi- tecture guarantees that the flags will remain valid from one clock cycle to the next. the almost empty/almost full flags become synchronous if the v cc /smode is tied to v ss . all configurations are fabricated using an advanced 0.35 cmos technology. input esd protection is greater than 2001v, and latch-up is prevented by the use of guard rings. pin configuration ef stqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 q 15 gnd q 16 q 17 gnd v cc rs oe ld ren rclk gnd d 17 d 16 pae wclk wen wxi v cc paf rxi ff xo /hf rxo q 0 q 1 gnd q 2 q 3 q 14 q 13 gnd q 12 q 11 v cc q 10 q 9 gnd q 8 q 7 q 6 q 5 gnd q 4 v cc v cc /smode fl /rt 4275v ? 3 cy7c4255v cy7c4265v cy7c4275v cy7c4285v selection guide 7c4255/65/75/85v-10 7c4255/65/75/85v-15 7c4255/65/75/85v-25 maximum frequency (mhz) 100 66.7 40 maximum access time (ns) 8 10 15 minimum cycle time (ns) 10 15 25 minimum data or enable set-up (ns) 3.5 4 6 minimum data or enable hold (ns) 0 0 1 maximum flag delay (ns) 8 10 15 active power supply current (i cc1 ) (ma) commercial 30 30 30 industrial 35 cy7c4255v cy7c4265v cy7c4275v cy7c4285v density 8k x 18 16k x 18 32k x 18 64k x 18 package 64-pin 10x10 tqfp 64-pin 10x10 tqfp 64-pin 10x10 tqfp 64-pin 10x10 tqfp
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 3 pin definitions signal name description i/o function d 0 ? 17 data inputs i data inputs for an 18-bit bus. q 0 ? 17 data outputs o data outputs for an 18-bit bus. wen write enable i enables the wclk input. ren read enable i enables the rclk input. wclk write clock i the rising edge clocks data into the fifo when wen is low and the fifo is not full. when ld is asserted, wclk writes data into the programmable flag-offset register. rclk read clock i the rising edge clocks data out of the fifo when ren is low and the fifo is not empty. when ld is asserted, rclk reads data out of the programmable flag- offset register. wxo /hf write expansion out/half full flag o dual-mode pin: single device or width expansion ? half full status flag. cascaded ? write expansion out signal, connected to wxi of next device. ef empty flag o when ef is low, the fifo is empty. ef is synchronized to rclk. ff full flag o when ff is low, the fifo is full. ff is synchronized to wclk. pa e programmable almost empty o when pae is low, the fifo is almost empty based on the almost-empty offset value programmed into the fifo. pae is asynchronous when v cc /smode is tied to v cc ; it is synchronized to rclk when v cc /smode is tied to v ss . pa f programmable almost full o when paf is low, the fifo is almost full based on the almost full offset value programmed into the fifo. paf is asynchronous when v cc /smode is tied to v cc ; it is synchronized to wclk when v cc /smode is tied to v ss . ld load i when ld is low, d 0 ? 17 (q 0 ? 17 ) are written (read) into (from) the programmable- flag-offset register. fl /rt first load/ retransmit i dual-mode pin: cascaded ? the first device in the daisy chain will have fl tied to v ss ; all other devices will have fl tied to v cc . in standard mode or width expansion, fl is tied to v ss on all devices. not cascaded ? tied to v ss . retransmit function is also available in stand-alone mode by strobing rt. wxi write expansion input i cascaded ? connected to wxo of previous device. not cascaded ? tied to v ss . rxi read expansion input i cascaded ? connected to rxo of previous device. not cascaded ? tied to v ss . rxo read expansion output o cascaded ? connected to rxi of next device. rs reset i resets device to empty condition. a reset is required before an initial read or write operation after power-up. oe output enable i when oe is low, the fifo ? s data outputs drive the bus to which they are con- nected. if oe is high, the fifo ? s outputs are in high z (high-impedance) state. v cc /smode synchronous almost empty/ almost full flags i dual-mode pin: asynchronous almost empty/almost full flags ? tied to v cc . synchronous almost empty/almost full flags ? tied to v ss . (almost empty synchronized to rclk, almost full synchronized to wclk.)
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 4 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................ ? 65 c to +150 c ambient temperature with power applied ............................................ ? 55 c to +125 c supply voltage to ground potential ......... ? 0.5v to v cc +0.5v dc voltage applied to outputs in high z state ......................................... ? 0.5v to v cc +0.5v dc input voltage ..........................................? 0.5v to v cc +0.5v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................... >2001v (per mil ? std ? 883, method 3015) latch-up current..................................................... >200 ma notes: 1. t a is the ? instant on ? case temperature. 2. v cc range for commercial -10 ns is 3.3v 150mv. 3. see the last page of this specification for group a subgroup testing information. 4. the v ih and v il specifications apply for all inputs except wxi , rxi . the wxi , rxi pin is not a ttl input. it is connected to either rxo , wxo of the previous device or v ss . 5. input signals switch from 0v to 3v with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 mhz, while data inputs switch at 10 mhz. outputs are unloaded. 6. all inputs = v cc ? 0.2v, except rclk and wclk (which are at frequency = 0 mhz), and fl /rt which is at v ss . all outputs are unloaded. 7. tested initially and after any design changes that may affect these parameters. operating range range ambient temperature v cc [2] commercial 0 c to +70 c 3.3v 300 mv industrial [1] ? 40 c to +85 c 3.3v 300 mv electrical characteristics over the operating range [3] 7c4255/65/75/ 85v-10 7c4255/65/75/ 85v-15 7c4255/65/75/ 85v-25 parameter description test conditions min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 1.0 ma v cc = 3.0v. i oh = ? 2.0 ma 2.4 2.4 2.4 v v ol output low volt- age v cc = min.,i ol = 4.0 ma v cc = 3.0v.,i ol = 8.0 ma 0.4 0.4 0.4 v v ih [4] input high voltage 2.0 v cc 2.0 v cc 2.0 v cc v v il [4] input low voltage ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 v i ix input leakage current v cc = max. ? 10 +10 ? 10 +10 ? 10 +10 a i ozl i ozh output off, high z current oe > v ih , v ss < v o < v cc ? 10 +10 ? 10 +10 ? 10 +10 a i cc1 [5] active power supply current com ? l 30 30 30 ma ind 35 ma i sb [6] average standby current com ? l 4 4 4 ma ind 4 ma capacitance [7] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 5 pf c out output capacitance 7 pf
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 5 ac test loads and waveforms (-15 -25) [8, 9] ac test loads and waveforms (-10) 3.0v 3.3v output r1=330 ? r2=510 ? c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 2.0v equivalent to: th venin equivalent 4275v ? 4 200 ? all input pulses 4287v ? 5 3.0v gnd 90% 10% 90% 10% 3ns 3 ns all input pulses 4275v ? 6 i/o 50 ? v cc /2 z0=50 ? 4275v ? 7 switching characteristics over the operating range 7c4255/65/75/85v -10 7c4255/65/75/85v -15 7c4255/65/75/85v -25 parameter description min. max. min. max. min. max. unit t s clock cycle frequency 100 66.7 40 mhz t a data access time 2 8 2 10 2 15 ns t clk clock cycle time 10 15 25 ns t clkh clock high time 4.5 6 10 ns t clkl clock low time 4.5 6 10 ns t ds data set-up time 3.5 4 6 ns t dh data hold time 0 0 1 ns t ens enable set-up time 3.5 4 6 ns t enh enable hold time 0 0 1 ns t rs reset pulse width [10] 10 15 25 ns t rsr reset recovery time 8 10 15 ns t rsf reset to flag and output time 10 15 25 ns t prt retransmit pulse width 60 60 60 ns t rtr retransmit recovery time 90 90 90 ns t olz output enable to output in low z [11] 0 0 0 ns t oe output enable to output valid 3 7 3 10 3 12 ns notes: 8. c l = 30 pf for all ac parameters except for t ohz . 9. c l = 5 pf for t ohz . 10. pulse widths less than minimum values are not allowed. 11. values guaranteed by design, not currently tested.
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 6 t ohz output enable to output in high z [11] 3 7 3 8 3 12 ns t wff write clock to full flag 8 10 15 ns t ref read clock to empty flag 8 10 15 ns t pa fa s y n c h clock to programmable almost-full flag [12] (asynchronous mode, v cc /smode tied to v cc ) 15 16 20 ns t pafsynch clock to programmable almost-full flag (synchronous mode, v cc /smode tied to v ss ) 8 10 15 ns t paeasynch clock to programmable almost-empty flag [12] (asynchronous mode, v cc /smode tied to v cc ) 15 16 20 ns t paesynch clock to programmable almost-full flag (synchronous mode, v cc /smode tied to v ss ) 8 10 15 ns t hf clock to half-full flag 12 16 20 ns t xo clock to expansion out 6 10 15 ns t xi expansion in pulse width 4.5 6.5 10 ns t xis expansion in set-up time 4 5 10 ns t skew1 skew time between read clock and write clock for full flag 5 6 10 ns t skew2 skew time between read clock and write clock for empty flag 5 6 10 ns t skew3 skew time between read clock and write clock for programmable almost empty and programmable almost full flags (synchronous mode only) 10 15 18 ns note: 12. t pafa sy n ch , t pa e a s y n c h , after program register write will not be valid until 5 ns + t pa f ( e ) . switching characteristics over the operating range (continued) 7c4255/65/75/85v -10 7c4255/65/75/85v -15 7c4255/65/75/85v -25 parameter description min. max. min. max. min. max. unit
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 7 switching waveforms notes: 13. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. 14. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. it the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ef may not change state until the next rclk rising edge. write cycle timing t clkh t clkl no operation t ds t skew1 t ens wen t clk t dh t wff t wff t enh wclk d 0 ? d 17 ff ren rclk 4275v ? 8 [13] read cycle timing t clkh t clkl no operation t skew2 wen t clk t ohz t ref t ref rclk q 0 ? q 17 ef ren wclk oe t oe t ens t olz t a t enh valid data 4275v ? 9 [14]
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 8 notes: 15. the clocks (rclk, wclk) can be free-running during reset. 16. after reset, the outputs will be low if oe = 0 and three-state if oe = 1. 17. when t skew2 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew2 < minimum specification, t frl (maximum) = either 2*t clk + t skew2 or t clk + t skew2 . the latency timing applies only at the empty boundary (ef = low). 18. the first word is always available the cycle after ef goes high. switching waveforms (continued) reset timing t rs t rsr q 0 ? q 17 rs t rsf t rsf t rsf oe =1 oe =0 ren ,wen, ld ef ,pae ff ,paf , hf 4275v ? 10 [15] [16] d 0 (firstvalid write) first data word latency after reset with simultaneous read and write t skew2 wen wclk q 0 ? q 17 ef ren oe t oe t ens t olz t ds rclk t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 d 0 ? d 17 4275v ? 11 t a [17] [18]
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 9 switching waveforms (continued) d1 d0 t ens t skew2 empty flag timing wen wclk q 0 ? q 17 ef ren oe t ds t enh rclk t ref t a t frl d 0 ? d 17 d0 t skew2 t frl t ref t ds t ens t enh 4275v ? 12 t ref [17] [17] next data read data write no write data in output register full flag timing ff wclk q 0 ? q 17 ren oe rclk t a d 0 ? d 17 data read t skew1 t ds t ens t enh wen t wff t a t skew1 t ens t enh t wff data write no write t wff low 4275v ? 13 [13] [13]
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 10 note: 19. pae is offset = n. number of data words into fifo already = n. switching waveforms (continued) t enh half-full flag timing wen wclk hf ren rclk t clkh t hf t ens half full + 1 or more t clkl t ens half full or less half full or less t hf 4275v ? 14 t enh programmable almost empty flag timing wen wclk pae ren rclk t clkh t pae t ens n + 1 words in fifo t clkl t ens t pae n words in fifo 4275v ? 15 [19]
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 11 notes: 20. pae offset ? n. 21. t skew3 is the minimum time between a rising wclk and a rising rclk edge for pae to change state during that clock cycle. if the time between the edge of wclk and the rising rclk is less than t skew3 , then pae may not change state until the next rclk. 22. if a read is performed on this rising edge of the read clock, there will be empty + (n ? 1) words in the fifo when pae goes low. 23. paf offset = m. number of data words written into fifo already = 8192 ? (m + 1) for the cy7c4255v, 16384 ? (m + 1) for the cy7c4265v, 32768 ? (m + 1) for the cy7c4275v, and 65536 ? (m + 1) for the cy7c4285v. 24. paf is offset = m. 25. 8192 ? m words in cy7c4255v, 16384 ? m words in cy7c4265v, 32768 ? m words in cy7c4275v, and 65536 ? m words in cy7c4285v. 26. 8192 ? (m + 1) words in cy7c4255v, 16384 ? (m + 1) words in cy7c4265v, 32768 ? (m + 1) words in cy7c4275v, and 65536 ? (m + 1) words in cy7c4285v. switching waveforms (continued) note t enh programmable almost empty flag timing (applies only in smode (smode is low)) wclk pae rclk t clkh t ens t clkl t ens t pae synch n + 1 words in fifo 4275v ? 16 t enh t ens t pae synch ren wen t skew3 note [21] 20 22 note t enh programmable almost full flag timing wen wclk paf ren rclk t clkh t paf t ens t clkl t ens t paf 4275v ? 17 full ? m words in fifo full ? (m+1) words in fifo [26] [25] 23 [24]
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 12 notes: 27. if a write is performed on this rising edge of the write clock, there will be full ? (m ? 1) words of the fifo when paf goes low. 28. t skew3 is the minimum time between a rising rclk and a rising wclk edge for paf to change state during that clock cycle. if the time between the edge of rclk and the rising edge of wclk is less than t skew3 , then paf may not change state until the next wclk rising edge. switching waveforms (continued) note t enh programmable almost full flag timing (applies only in smode (smode is low)) wclk paf rclk t clkh t ens full ? m words in fifo t clkl t ens full ? m + 1 words in fifo 4275v ? 18 t enh t ens t paf ren wen t skew3 t paf synch 27 [25] [28] t enh write programmable registers ld wclk t clkh t ens t clkl pae offset d 0 ? d 17 wen t ens paf offset pae offset t clk d 0 ? d 11 t ds t dh 4275v ? 19
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 13 notes: 29. write to last physical location. 30. read from last physical location. switching waveforms (continued) t enh read programmable registers ld rclk t clkh t ens t clkl pae offset q 0 ? q 17 wen t ens paf offset pae offset t clk unknown t a 4275v ? 20 write expansion out timing wen wclk wxo t clkh t ens t xo t xo 4275v ? 21 note 29 note 30 read expansion out timing ren wclk rxo t clkh t ens t xo t xo 4275v ? 22 note 30 write expansion in timing wclk wxi t xi t xis 4275v ? 23
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 14 notes: 31. clocks are free-running in this case. 32. the flags may change state during retransmit as a result of the offset of the read and write pointers, but flags will be val id at t rtr . 33. for the synchronous pae and paf flags (smode), an appropriate clock cycle is necessary after t rtr to update these flags. switching waveforms (continued) read expansion in timing rclk rxi t xi t xis 4275v ? 24 retransmit timing ren /wen fl /rt t prt t rtr 4275v ? 25 ef /ff and all async flags hf /pae /paf [31, 32, 33]
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 15 architecture the cy7c4255/65/75/85v consists of an array of 8k/16k/32k/64k words of 18 bits each (implemented by a dual-port array of sram cells), a read pointer, a write pointer, control signals (rclk, wclk, ren , wen , rs ), and flags (ef , pa e , hf , paf , ff ). the cy7c4255/65/75/85v also includes the control signals wxi , rxi , wxo , rxo for depth expansion. resetting the fifo upon power-up, the fifo must be reset with a reset (rs ) cycle. this causes the fifo to enter the empty condition sig- nified by ef being low. all data outputs go low after the falling edge of rs only if oe is asserted. in order for the fifo to reset to its default state, the user must not read or write while rs is low. fifo operation when the wen signal is active (low), data present on the d 0 ? 17 pins is written into the fifo on each rising edge of the wclk signal. similarly, when the ren signal is active low, data in the fifo memory will be presented on the q 0 ? 17 out- puts. new data will be presented on each rising edge of rclk while ren is active low and oe is low. ren must set up t ens before rclk for it to be a valid read function. wen must occur t ens before wclk for it to be a valid write function. an output enable (oe ) pin is provided to three-state the q 0 ? 17 outputs when oe is deasserted. when oe is enabled (low), data in the output register will be available to the q 0 ? 17 outputs after t oe . if devices are cascaded, the oe function will only output data on the fifo that is read enabled. the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and under flow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0 ? 17 outputs even after additional reads occur. programming the cy7c4255/65/75/85v devices contain two 16-bit offset registers. data present on d 0 ? 15 during a program write will determine the distance from empty (full) that the almost emp- ty (almost full) flags become active. if the user elects not to program the fifo ? s flags, the default offset values are used (see ta b l e 2 ). when the load ld pin is set low and wen is set low, data on the inputs d 0 ? 15 is written into the empty offset register on the first low-to-high transition of the write clock (wclk). when the ld pin and wen are held low then data is written into the full offset register on the second low- to-high transition of the write clock (wclk). the third transi- tion of the write clock (wclk) again writes to the empty offset register (see ta b l e 1 ). writing all offset registers does not have to occur at one time. one or two offset registers can be written and then, by bringing the ld pin high, the fifo is returned to normal read/write operation. when the ld pin is set low, and wen is low, the next offset register in sequence is written. the contents of the offset registers can be read on the output lines when the ld pin is set low and ren is set low; then, data can be read on the low-to-high transition of the read clock (rclk). flag operation the cy7c4255/65/75/85v devices provide five flag pins to in- dicate the condition of the fifo contents. empty and full are synchronous. pae and paf are synchronous if v cc /smode is tied to v ss . full flag the full flag (ff ) will go low when device is full. write op- erations are inhibited whenever ff is low regardless of the state of wen . ff is synchronized to wclk, i.e., it is exclusive- ly updated by each rising edge of wclk. empty flag the empty flag (ef ) will go low when the device is empty. read operations are inhibited whenever ef is low, regard- less of the state of ren . ef is synchronized to rclk, i.e., it is exclusively updated by each rising edge of rclk. programmable almost empty/almost full flag the cy7c4255/65/75/85v features programmable almost empty and almost full flags. each flag can be programmed (described in the programming section) a specific distance from the corresponding boundary flags (empty or full). when the fifo contains the number of words or fewer for which the flags have been programmed, the paf or pae will be asserted, signifying that the fifo is either almost full or almost empty. see ta b l e 2 for a description of programmable flags. when the smode pin is tied low, the paf flag signal transi- tion is caused by the rising edge of the write clock and the pae flag transition is caused by the rising edge of the read clock. note: 34. the same selection sequence applies to reading from the registers. ren is enabled and read is performed on the low-to-high transition of rclk. table 1. write offset register ld wen wclk [34] selection 0 0 writing to offset registers: empty offset full offset 0 1 no operation 1 0 write into fifo 1 1 no operation
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 16 retransmit the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. the retransmit (rt) input is active in the stand-alone and width expansion modes. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred and at least one word has been read since the last rs cycle. a high pulse on rt resets the internal read pointer to the first physical location of the fifo. wclk and rclk may be free running but must be disabled during and t rtr after the retransmit pulse. with every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. data written to the fifo after activation of rt are transmitted also. the full depth of the fifo can be repeatedly retransmitted. width expansion configuration the cy7c4255/65/75/85v can be expanded in width to pro- vide word widths greater than 18 in increments of 18. during width expansion mode all control line inputs are common and all flags are available. empty (full) flags should be created by anding the empty (full) flags of every fifo; the pae and paf flags can be detected from any one device. this technique will avoid reading data from, or writing data to the fifo that is ? staggered ? by one clock cycle due to the variations in skew between rclk and wclk. figure 1 demonstrates a 36-word width by using two cy7c4255/65/75/85vs. table 2. flag truth table number of words in fifo ff pa f hf pa e ef 7c4255v ? 8k x 18 7c4265v ? 16k x 18 7c4275v ? 32k x 18 7c4285v ? 64k x 18 0 0 0 0 h h h l l 1 to n [35] 1 to n [35] 1 to n [35] 1 to n [35] h h h l h (n+1) to 4096 (n+1) to 8192 (n+1) to 16384 (n+1) to 32768 h h h h h 4097 to (8192 ? (m+1)) 8193 to (16384 ? (m+1)) 16385 to (32768 ? (m+1)) 32769 to (65536 ? (m+1)) h h l h h (8192 ? m) [36] to 8192 (16384 ? m) [36] to 16384 (32768 ? m) [36] to 32767 (65536 ? m) [36] to 65535 h l l h h 8192 16384 32768 65536 l l l h h figure 1. block diagram of 8k/16k/32k/64k x 18 low-voltage synchronous fifo memory used in a width expansion configuration notes: 35. n = empty offset (default values: cy7c4255/65/75/85v n = 127). 36. m = full offset (default values: cy7c4255/65/75/85v n = 127). 4275v ? 24 ff ff ef ef write clock (wclk) write enable (wen ) load (ld ) programmable(pae ) half full flag (hf ) full flag (ff ) 7c4255v 7c4265v 18 36 data in (d) reset (rs) 18 reset (rs) read clock (rclk) read enable (ren ) output enable (oe ) programmable (paf ) empty flag (ef ) 18 data out (q) 18 36 first load (fl ) write expansion in (wxi ) read expansion in (rxi ) 7c4275v 7c4285v 7c4255v 7c4265v 7c4275v 7c4285v
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 17 depth expansion configuration (with programmable flags) the cy7c4255/65/75/85v can easily be adapted to applica- tions requiring more than 8k/16k/32k/64k words of buffering. figure 2 shows depth expansion using three cy7c4255/65/ 75/85vs. maximum depth is limited only by signal loading. fol- low these steps: 1. the first device must be designated by grounding the first load (fl ) control input. 2. all other devices must have fl in the high state. 3. the write expansion out (wxo ) pin of each device must be tied to the write expansion in (wxi ) pin of the next device. 4. the read expansion out (rxo ) pin of each device must be tied to the read expansion in (rxi ) pin of the next device. 5. all load (ld ) pins are tied together. 6. the half-full flag (hf ) is not available in the depth expan- sion configuration. 7. ef , ff , pae , and paf are created with composite flags by oring together these respective flags for monitoring. the composite pae and paf flags are not precise. figure 2. block diagram of 8k/16k/32k/64k x 18 low-voltage synchronous fifo memory with programmable flags used in depth expansion configuration 4275v ? 25 write clock (wclk) write enable (wen ) reset (rs ) load (ld ) ff paf paf ff ef pae pae ef wxi rxi first load (fl ) read clock (rclk) read enable (ren ) output enable (oe ) wxo rxo paf ff ef pae wxi rxi wxo rxo v cc fl paf ff ef pae wxi rxi wxo rxo 7c4255v 7c4265v v cc fl data in (d) data out (q) 7c4275v 7c4285v 7c4255v 7c4265v 7c4275v 7c4285v 7c4255v 7c4265v 7c4275v 7c4285v
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v 18 document #: 38-00654-c ordering information 8kx18 low-voltage deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4255v ? 10asc a64 64-lead 10x10 thin quad flatpack commercial 15 cy7c4255v ? 15asc a64 64-lead 10x10 thin quad flatpack commercial 25 cy7c4255v ? 25asc a64 64-lead 10x10 thin quad flatpack commercial 16kx18 low-voltage deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4265v ? 10asc a64 64-lead 10x10 thin quad flatpack commercial 15 cy7c4265v ? 15asc a64 64-lead 10x10 thin quad flatpack commercial 25 cy7c4265v ? 25asc a64 64-lead 10x10 thin quad flatpack commercial 32kx18 low-voltage deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4275v ? 10asc a64 64-lead 10x10 thin quad flatpack commercial 15 cy7c4275v ? 15asc a64 64-lead 10x10 thin quad flatpack commercial 64kx18 low-voltage deep sync fifo speed (ns) ordering code package name package type operating range 10 cy7c4285v ? 10asc a64 64-lead 10x10 thin quad flatpack commercial 15 cy7c4285v ? 15asi a64 64-lead 10x10 thin quad flatpack industrial 25 cy7c4285v ? 25asc a64 64-lead 10x10 thin quad flatpack commercial
cy7c4255v/cy7c4265v cy7c4275v/cy7c4285v ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams 64-pin thin plastic quad flat pack (10 x 10 x 1.4 mm) a64 51-85051-a

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