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isplsi 2064/a in-system programmable high density pld 2064_09 1 use isplsi 2064e for new designs features ? enhancements ? isplsi 2064a is fully form and function compatible to the isplsi 2064, with identical timing specifcations and packaging ? isplsi 2064a is built on an advanced 0.35 micron e 2 cmos ? technology ? high density programmable logic ? 2000 pld gates ? 64 i/o pins, four dedicated inputs ? 64 registers ? high speed global interconnect ? wide input gating for fast counters, state machines, address decoders, etc. ? small logic block size for random logic ? high performance e 2 cmos ? technology ? f max = 125 mhz maximum operating frequency ? t pd = 7.5 ns propagation delay ? ttl compatible inputs and outputs ? electrically erasable and reprogrammable ? non-volatile ? 100% tested at time of manufacture ? unused product term shutdown saves power ? in-system programmable ? in-system programmable (isp?) 5v only ? increased manufacturing yields, reduced time-to- market and improved product quality ? reprogram soldered devices for faster prototyping ? offers the ease of use and fast system speed of plds with the density and flexibility of field programmable gate arrays ? complete programmable device can combine glue logic and structured designs ? enhanced pin locking capability ? three dedicated clock input pins ? synchronous and asynchronous clocks ? programmable output slew rate control to minimize switching noise ? flexible pin placement ? optimized global routing pool provides global interconnectivity fu description the isplsi 2064 and 2064a are high density program- mable logic devices. the devices contain 64 registers, 64 universal i/o pins, four dedicated input pins, three dedicated clock input pins, two dedicated global oe input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the 2064 and 2064a feature 5v in-system programmability and in-system diagnostic capabilities. the isplsi 2064 and 2064a offer non-volatile reprogrammability of the logic, as well as the intercon- nect, to provide truly reconfigurable systems. the basic unit of logic on these devices is the generic logic block (glb). the glbs are labeled a0, a1?b7 (figure 1). there are a total of 16 glbs in the isplsi 2064 and 2064a devices. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. functional block diagram global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) b3 b2 b1 b0 input bus output routing pool (orp) a2 glb logic array dq dq dq dq a4 a5 a6 a7 input bus output routing pool (orp) b7 b6 b5 b4 input bus output routing pool (orp) 0139bisp/2064 copyright ? 2002 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com january 2002
2 specifications isplsi 2064/a use isplsi 2064e for new designs functional block diagram figure 1. isplsi 2064/a functional block diagram sdo/in 2 global routing pool (grp) a0 a1 a3 input bus output routing pool (orp) b3 b2 b1 b0 input bus output routing pool (orp) a2 clk 0 clk 1 clk 2 goe 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 sdi/in 0 mode/in 1 i/o 4 i/o 5 ispen reset 0139b(1)isp/2064 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 input bus output routing pool (orp) i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 y0 y1 y2 i/o 31 output routing pool (orp) megablock input bus a4 a5 a6 a7 b7 b6 b5 b4 goe 1 sclk/in 3 generic logic blocks (glbs) the devices also have 64 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. eight glbs, 32 i/o cells, two dedicated inputs and two orps are connected together to make a megablock (figure 1). the outputs of the eight glbs are connected to a set of 32 universal i/o cells by two orps. each isplsi 2064 and 2064a device contains two megablocks. the grp has as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2064 and 2064a devices are se- lected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock.
3 specifications isplsi 2064/a use isplsi 2064e for new designs absolute maximum ratings 1 supply voltage v cc ................................................... -0.5 to +7.0v input voltage applied .............................. -2.5 to v cc +1.0v off-state output voltage applied ........... -2.5 to v cc +1.0v storage temperature ..................................... -65 to 150 c case temp. with power applied .................... -55 to 125 c max. junction temp. (t j ) with power applied ............ 150 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating condition t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2 - 0005/2064 v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 4.75 4.5 2.0 0 5.25 5.5 v cc +1 0.8 v v v v commercial industrial table 2-0008/2064 parameter data retention minimum maximum units erase/reprogram cycles 20 10000 ? ? years cycles data retention specifications capacitance (ta=25 c, f=1.0 mhz) c symbol table 2-0006/2064 c parameter i/o capacitance 9 units typical test conditions 1 2 8 dedicated input capacitance pf pf v = 5.0v, v = 2.0v v = 5.0v, v = 2.0v cc cc i/o in c clock capacitance 15 3 pf v = 5.0v, v = 2.0v cc y
4 specifications isplsi 2064/a use isplsi 2064e for new designs output load conditions (see figure 2) figure 2. test load + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. dc electrical characteristics over recommended operating conditions input pulse levels table 2-0003/2064 input rise and fall time 10% to 90% input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. -125 others 2 ns 3 ns test condition r1 r2 cl a 470 ? 390 ? 35pf b 390 ? 35pf 470 ? 390 ? 35pf active high active low c 470 ? 390 ? 5pf 390 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004/2064 switching test conditions v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using four 16-bit counters. 3. typical values are at v = 5v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/2064 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current ispen input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 3.5v v v 0v v v (max.) 0v v v 0v v v v = 5v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in cc in il in il cc out clock il ih condition min. typ. max. units 3 ? 2.4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 95 95 0.4 ? 10 -10 -150 -150 -200 175 ? v v a a a a ma ma ma cc a out cc cc commercial industrial
5 specifications isplsi 2064/a use isplsi 2064e for new designs external timing parameters over recommended operating conditions t pd1 units -100 min. test cond. 1. unless noted otherwise, all parameters use the grp, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2 - 0030b/2064-130 1 4 3 1 tsu2 + tco1 ( ) -80 min. max. max. description # 2 parameter a1 data propagation delay, 4pt bypass, orp bypass ? 10.0 ? 15.0 ns t pd2 a2 data propagation delay ? ? ns f max a3 clock frequency with internal feedback 100 ? 81.0 ? mhz f max (ext.) ? 4 clock frequency with external feedback ? ? mhz f max (tog.) ? 5 clock frequency, max. toggle ? ? mhz t su1 ? 6 glb reg. setup time before clock, 4 pt bypass ? ? ns t co1 a7 glb reg. clock to output delay, orp bypass ? ? ns t h1 ? 8 glb reg. hold time after clock, 4 pt bypass 0.0 ? ns t su2 ? 9 glb reg. setup time before clock 8.0 ? ns t co2 ? 10 glb reg. clock to output delay ? ? ns t h2 ? 11 glb reg. hold time after clock 0.0 ? ns t r1 a1 2 ext. reset pin to output delay ? ? ns t rw1 ? 13 ext. reset pulse duration 6.5 ? ns t ptoeen b1 4 product term oe, enable ? ? ns t ptoedis c1 5 product term oe, disable ? ? ns t goeen b1 6 global oe, enable ? ? ns t goedis c1 7 global oe, disable ? ? ns t wh ? 18 external synchronous clock pulse duration, high 4.5 ? ? ns t wl ? 19 external synchronous clock pulse duration, low 4.5 ? ? ns 77.0 111 6.5 5.0 ? ? 6.0 ? 13.5 ? 15.0 15.0 9.0 9.0 13.0 57.0 100 9.0 0.0 11.0 0.0 10.0 5.0 5.0 18.5 6.5 8.0 17.0 18.0 18.0 12.0 12.0 -125 min. ? 7.5 ? 125 ? ? ? ? ? 0.0 6.0 ? 0.0 ? 5.0 ? ? ? ? 4.0 ? 4.0 ? 100 125 5.0 4.0 ? ? 4.5 ? 10.0 ? 12.0 12.0 7.0 7.0 10.0 max.
6 specifications isplsi 2064/a use isplsi 2064e for new designs internal timing parameters 1 over recommended operating conditions ? ? ? ? ? ? ? ? ? 1.2 4.0 ? ? ? ? 4.1 ? ? ? ? ? ? ? 2.7 2.7 ? 0.2 1.5 1.3 4.5 5.0 5.7 6.0 6.5 0.5 ? ? 0.2 1.1 4.8 7.3 5.6 0.8 0.3 1.2 10.0 3.2 3.2 3.8 2.3 2.3 6.9 -125 -80 max. min. max. min. max. min. ? ? ? ? ? ? ? ? ? 0.8 3.0 ? ? ? ? 3.3 ? ? ? ? ? ? ? 2.3 2.3 ? ? ? ? ? ? ? ? ? ? 1.4 6.0 ? ? ? ? 5.6 ? ? ? ? ? ? ? 3.6 3.6 ? -100 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 input buffer delay dedicated input delay grp delay 4 product term bypass comb. path delay 4 product term bypass reg. path delay 1 product term/xor path delay 20 product term/xor path delay xor adjacent path delay 3 glb register bypass delay glb register setup time before clock glb register hold time after clock glb register clock to output delay glb register reset to output delay glb product term reset to register delay glb product term output enable to i/o cell delay glb product term clock delay orp delay orp bypass delay output buffer delay output slew limited delay adder i/o cell oe to output enabled i/o cell oe to output disabled global output enable clock delay, y0 to global glb clock line (ref. clock) clock delay, y1 or y2 to global glb clock line global reset to glb 1.8 4.4 2.6 8.1 6.8 8.0 8.8 9.8 1.3 ? ? 0.4 1.6 8.6 9.0 10.2 2.0 0.5 2.0 10.0 4.6 4.6 7.4 3.6 3.6 11.4 t io t din t grp t 4ptbp t 4ptbp t 1ptxor t 20ptxor t xoradj t gbp t gsu t gh t gco t gro t ptre t ptoe t ptck t orp t orpbp t ob t sl t oen t odis t goe t gy0 t gy1/2 t gr units # 2 inputs grp description glb parameter orp outputs 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns table 2- 0036c/2064-130 0.5 2.2 1.7 5.8 5.8 6.8 7.3 8.0 0.5 ? ? 0.3 1.3 6.1 8.6 7.1 1.4 0.4 1.6 10.0 4.2 4.2 4.8 2.7 2.7 9.2 clocks global reset
7 specifications isplsi 2064/a use isplsi 2064e for new designs isplsi 2064/a timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 reset ded. in #21 #20 #28 #29, 30, 31, 32 #38, 39 goe 0,1 #42 #40, 41 0491/2064 #22 comb 4 pt bypass #23 #37 #45 derivations of t su, t h and t co from the product term clock 1 = = = = t su logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3) 3.5 ns = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0) 2.6 ns = = = = t co clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2) 9.4 ns table 2- 0042a-2064 note: calculations are based upon timing specifications for the isplsi 2064/a-125l.
8 specifications isplsi 2064/a use isplsi 2064e for new designs power consumption power consumption in the isplsi 2064 and 2064a de- vices depends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 4 shows the relationship between power and operating speed. figure 4. typical device power consumption vs fmax 80 100 120 120406 080 100 120 140 f max (mhz) i cc (ma) notes: configuration of four 16-bit counters typical current at 5v, 25 c isplsi 2064/a 110 90 0127a/2064a i cc can be estimated for the isplsi 2064/a using the following equation: i cc (ma) = 38 + (# of pts * 0.33) + (# of nets * max freq * 0.007) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 70 130 140 150 160
9 specifications isplsi 2064/a use isplsi 2064e for new designs pin description i/o 0 - i/o 3 i/o 4 - i/o 7 i/o 8 - i/o 11 i/o 12 - i/o 15 i/o 16 - i/o 19 i/o 20 - i/o 23 i/o 24 - i/o 27 i/o 28 - i/o 31 i/o 32 - i/o 35 i/o 36 - i/o 39 i/o 40 - i/o 43 i/o 44 - i/o 47 i/o 48 - i/o 51 i/o 52 - i/o 55 i/o 56 - i/o 59 i/o 60 - i/o 63 name description 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. pins have dual function capability. table 2-0002a-08isp/2064 plcc pin numbers input ? dedicated in-system programming enable pin. this pin is brought low to enable the programming mode. when low, the mode, sdi, sdo and sclk controls become active. input ? this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in 0 also is used as one of the two control pins for the isp state machine. when ispen is high, it functions as a dedicated pin input. input ? this pin performs two functions. when ispen is logic low, it functions as a pin to control the operation of the isp state machine. when ispen is high, it functions as a dedicated input pin. output/input ? this pin performs two functions. when ispen is logic low, it functions as an output pin to read serial shift register data. when ispen is high, it functions as a dedicated input pin. input ? this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. when ispen is high, it functions as a dedicated input pin. no connect nc 1 vcc 21, 65 gnd 1, sdo/in 2 2 44 mode/ in 1 2 42 sdi/ in 0 2 25 ispen 23 reset 24 sclk/in 3 2 61 22, 43, 64 y0, y1, y2 20, 66, goe 0, goe 1 67, 84 63 input/output pins ? these are the general purpose i/o pins used by the logic array. global output enable input pins. dedicated clock input. this clock input is connected to one of the clock inputs of all the glbs in the device. active low (0) reset pin which resets all registers in the device. ground (gnd) vcc 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 2, 19, 62 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18
10 specifications isplsi 2064/a use isplsi 2064e for new designs pin description 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. pins have dual function capability. gnd 13, 38, 63, 88 vcc 12, 64 ground (gnd) v cc input ? dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk controls become active. input ? this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in 0 also is used as one of the two control pins for the isp state machine. when ispen is high, it functions as a dedicated input pin. input ? this pin performs two functions. when ispen is logic low, it functions as a pin to control the operation of the isp state machine. when ispen is high, it functions as a dedicated input pin. output/input ? this pin performs two functions. when ispen is logic low, it functions as an output pin to read serial shift register data. when ispen is high, it functions as a dedicated input pin. input ? this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. when ispen is high, it functions as a dedicated input pin. no connect. ispen 14 sdi/in 0 2 16 mode/in 1 2 37 sdo/in 2 2 39 sclk/in 3 2 60 nc 1 1, 2, 10, 24, 25, 26, 27, 49, 50, 51, 52, 61, 74, 75, 76, 77, 89, 99, 100 description tqfp pin numbers name input/output pins - these are the general purpose i/o pins used by the logic array. i/o 0 - i/o 3 17, 18, 19, 20, i/o 4 - i/o 7 21, 22, 23, 28, i/o 8 - i/o 11 29, 30, 31, 32, i/o 12 - i/o 15 33, 34, 35, 36, i/o 16 - i/o 19 40, 41, 42, 43, i/o 20 - i/o 23 44, 45, 46, 47, i/o 24 - i/o 27 48, 53, 54, 55, i/o 28 - i/o 31 56, 57, 58, 59, i/o 32 - i/o 35 67, 68, 69, 70, i/o 36 - i/o 39 71, 72, 73, 78, i/o 40 - i/o 43 79, 80, 81, 82, i/o 44 - i/o 47 83, 84, 85, 86, i/o 48 - i/o 51 90, 91, 92, 93, i/o 52 - i/o 55 94, 95, 96, 97, i/o 56 - i/o 59 98, 3, 4, 5, i/o 60 - i/o 63 6, 7, 8, 9 goe 0, goe 1 66, 87 global output enable input pins. dedicated clock input. this clock input is connected to one of the clock inputs of all of the glbs on the device. active low (0) reset pin which resets all of the registers in the device. y0, y1, y2 11, 65, 62 reset 15 table 2-0002-2064b.eps
11 specifications isplsi 2064/a use isplsi 2064e for new designs pin configuration isplsi 2064/a 84-pin plcc pinout diagram i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 goe 0 y1 vcc gnd y2 nc 1 sclk/in 3 2 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 1 nc y0 vcc gnd ispen reset 2 sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 nc 1 gnd goe 1 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 2 mode/in 1 gnd 2 sdo/in 2 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 isplsi 2064/a top view 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. pins have dual function capability. 0123a/2064
12 specifications isplsi 2064/a use isplsi 2064e for new designs pin configuration isplsi 2064/a 100-pin tqfp pinout diagram 1 nc 1 nc i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 1 nc y0 vcc gnd ispen reset 2 sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 1 nc 1 nc nc 1 nc 1 i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 goe 0 y1 vcc gnd y2 nc 1 sclk/in 3 2 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 nc 1 nc 1 nc 1 nc 1 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 nc 1 gnd goe 1 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 nc 1 nc 1 1 nc 1 nc i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 2 mode/in 1 gnd 2 sdo/in 2 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 1 nc 1 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 58 isplsi 2064/a top view 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. pins have dual function ca p abilit y . 0766a-2064-isp
13 specifications isplsi 2064/a use isplsi 2064e for new designs part number description 81 81 84-pin plcc 15 15 isplsi 2064a-80lj84 100-pin tqfp isplsi 2064a-80lt100 table 2-0041a/2064a family f max (mhz) 125 125 100 ordering number package 84-pin plcc 100-pin tqfp t pd (ns) 7.5 7.5 10 isplsi isplsi 2064a-125lj84 isplsi 2064a-125lt100 84-pin plcc isplsi 2064a-100lj84 100 100-pin tqfp 10 isplsi 2064a-100lt100 commercial 81 81 84-pin plcc 15 15 isplsi 2064-80lj 100-pin tqfp isplsi 2064-80lt 125 125 100 84-pin plcc 100-pin tqfp 7.5 7.5 10 isplsi 2064-125lj isplsi 2064-125lt 84-pin plcc isplsi 2064-100lj 100 100-pin tqfp 10 isplsi 2064-100lt table 2-0041b/2064a family f max (mhz) 81 81 ordering number package 84-pin plcc 100-pin tqfp t pd (ns) 15 15 isplsi isplsi 2064a-80lj84i isplsi 2064a-80lt100i industrial 81 81 84-pin plcc 100-pin tqfp 15 15 isplsi 2064-80lji isplsi 2064-80lti device number isplsi xxxxx xxx x x grade blank = commercial i = industrial x speed 125 = 125 mhz f max 100 = 100 mhz f max 80 = 81 mhz f max power l = low package j = plcc t = tqfp ? device family 2064 2064a 0212/2064/a isplsi 2064/a ordering information

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