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philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 2 1995 sep 26 853-1735 15806 description the abt22v10 is a versatile pal ? device fabricated with the philips bicmos process known as qubic. the qubic process produces a very high speed device (7.5ns worst case) which has excellent noise characteristics. the ground bounce, with 9 outputs switching and the 10th held low is less than 0.8v (see page 12). the abt22v10 is designed so the outputs can never display a metastable state due to set up and hold time violations. if set up and hold times are violated, the outputs will not glitch or display a metastable state (the propagation delays may, however, be extended). the abt22v10 uses the familiar and/or logic array structure, which allows direct implementation of sum-of-product equations. this device has a programmable and array which drives a fixed or array. the and array is programmed to create custom product terms while the fixed or array sums selected terms at the output. the or sum of the products feeds the aoutput macro cello (omc), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. in other words, the architecture provides maximum design flexibility by allowing the output macro cell to be configured by the user. this device is pin and jedec file compatible with industry standard 22v10 and can be used in all standard applications where speed is to be maximized. features ? ultra fast 7.5ns t pd and 6ns t co ? high output drive; 48ma = i ol (complete specification, page 3) ? metastable immune flip-flops, t = 83ps (complete specification, page 9) ? low ground bounce (<0.8v) ? varied product term distribution with up to 16 product terms per output for complex functions ? programmable output polarity ? power-up reset on all registers ? synchronous preset/asynchronous reset ? programmable on standard pal-type device programmers ? design support provided using snap software development package and other cad tools for plds applications ? dma control ? state machine implementation ? high speed graphics processing ? counters/shift registers ? ssi/msi random logic replacement ? high speed memory decoder pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 n package i0/clk i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 v cc f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 i11 gnd nc nc a package nc i7 clk/ i0 i1 i2 i3 i4 i5 nc i6 i8 i9 i10 gnd i11 f0 f1 f2 f3 f7 f6 f5 f4 f8 f9 v cc a = plastic leaded chip carrier n = plastic dual in-line package (300mil-wide) sp00406 pin label descriptions i1 i11 dedicated input nc not connected f0 f9 macro cell input/output clk/i0 clock input/dedicated input v cc supply voltage gnd ground ordering information description order code drawing number 24-pin plastic dual-in-line package 300mil-wide abt22v107n sot222-1 28-pin plastic leaded chip carrier abt22v107a sot261-3 ? pal is a registered trademark of advanced micro devices, inc.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 3 absolute maximum ratings 1 symbol parameter ratings unit symbol parameter min max unit v cc supply voltage 0.5 +7.0 v dc v in input voltage 1.2 v cc + 0.5 v dc v out output voltage 0.5 v cc + 0.5 v dc i in input currents 30 +30 ma i out output currents +100 ma t stg storage temperature range 65 +150 c note: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. thermal ratings temperature maximum junction 150 c maximum ambient 75 c allowable thermal rise ambient to junction 75 c operating ranges symbol parameter ratings unit symbol parameter min max unit v cc supply voltage +4.75 +5.25 v dc t amb operating free-air temperature 0 +75 c dc electrical characteristics (over operating ranges) symbol parameter test conditions 1 limits unit symbol parameter test conditions 1 min max unit input voltage v il low v cc = min 0.8 v v ih high v cc = max 2.0 v v i clamp v cc = min, i in = 18ma 1.2 v output voltage v cc = min, v in = v ih or v il v ol low i ol = 48ma 0.5 v v oh high i oh = 16 ma 2.4 v input current i il low v cc = max, v in = 0.40v 10 m a i ih high v cc = max, v in = 2.7v 10 m a output current v cc = min v in or v il i ol low v ol = .5 (max) 48 ma i oh high v oh = 2.4 (min) 16 ma v cc = max i ozh output leakage 2 v in = v il or v ih , v out = 2.7v 100 m a i ozl output leakage 2 v in = v il or v ih , v out = 0.4v 100 m a i sc short circuit 3 v out = 0.5 v 30 190 ma i cc v cc supply current v cc = max 185 ma notes: 1. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i ozx or i ix (where x = h or l). 3. no more than one output should be tested at a time. duration of the short-circuit test should not exceed one second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 4 ac electrical characteristics symbol parameter test conditions limits 1 unit symbol parameter test conditions min typ max unit t pd input or feedback to non-registered output 2 , 4 active-low 3.5 7.5 t pd i npu t or f ee db ac k t o non-reg i s t ere d ou t pu t 2 , 4 active-high 3.5 7.5 ns t s setup time from input, feedback or sp to clock 5.5 ns t h hold time 0 ns t co clock to output4, 7 3.0 6.0/6.5 ns t cf clock to feedback 3 2.5 ns t ar asynchronous reset to registered output 10.0 ns t arw asynchronous reset width 7.5 ns t arr asynchronous reset recovery time 5.5 ns t spr synchronous preset recovery time 5.0 ns t wl width of clock low 3.0 ns t wh width of clock high 3.0 ns f max maximum frequency; external feedback 1/(t s + t co ) 4,7 87/83 mhz f max maximum frequency; internal feedback 1/(t s + t cf ) 4 125 mhz t ea input to output enable 5 7.5 ns t er input to output disable 5 7.5 ns capacitance 6 c in input capacitance (pin 1) v in = 2.0v v cc = 5.0v 6 pf c in input capacitance (others) v in = 2.0v t amb = 25 c 6 pf c out output capacitance v out = 2.0v f = 1mhz 8 pf notes: 1. commercial test conditions: r 1 = 300 w , r 2 = 390 w (see test load circuit). 2. t pd is tested with switch s 1 closed and c l = 50pf (including jig capacitance). v ih = 3v, v il = 0v, v t = 1.5v. 3. calculated from measured f max internal. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. for 3-state output; output enable times are tested with c l = 50pf to the 1.5v level, and s 1 is open for high-impedance to high tests and closed for high-impedance to low tests. output disable times are tested with c l = 5pf. high-to-high impedance tests are made to an output voltage of v t = (v oh 0.5v) with s 1 open, and low-to-high impedance tests are made to the v t = (v ol + 0.5v) level with s 1 closed. 6. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 7. for plcc package, t co = 6.0ns; for dip package, t co = 6.5ns test load circuit +5v c l r 1 r 2 s 1 c 2 c 1 note: c 1 and c 2 are to bypass v cc to gnd. v cc gnd ck i n i 0 f 0 f n dut oe inputs sp00369 voltage waveform 90% 10% 2.5ns 2.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00407
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 5 timing characterization the timing characterization represents the average values of a representative sample for each parameter. the data can be used to derate the max ac characterization based upon the specific user design. philips guarantees the max ac characterization specifications. delta t cko vs # of outputs switching (v cc = 5.0v, temp = 25 c, cap = 50pf) 1 0.8 0.6 0.4 0.2 0 12 34 56 78910 1 0.8 0.6 0.4 0.2 0 12 34 56 78910 delta t pd vs # of outputs switching (v cc = 5.0v, temp = 25 c, cap = 50pf) number of outputs switching number of outputs switching delta t cko vs output capacitance (v cc = 5.0v, temp = 25 c, 1 output switching) 1 0 1 2 3 4 5 6 0 100 200 300 400 1 0 1 2 3 4 5 6 0 100 200 300 400 delta t pd vs output capacitance (v cc = 5.0v, temp = 25 c, 1 output switching) rise fall rise fall output capacitance output capacitance delta tcko (ns) delta tpd (ns) delta tpd (ns) delta tcko (ns) sp00408 figure 1. device characterization
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 6 timing characterization the timing characterization represents the average values of a representative sample for each parameter. the data can be used to derate the max ac characterization based upon the specific user design. philips guarantees the max ac characterization specifications. rise fall rise fall normalized t cko vs temperature (v cc = 5.0 v, cap = 50 pf, 1 output switching) 1.1 1.05 1 0.95 0.9 0.85 0.8 50 25 0 25 50 75 100 125 temperature ( c) 1.1 1.05 1 0.95 0.9 0.85 0.8 50 25 0 25 50 75 100 125 temperature ( c) normalized t pd vs temperature (v cc = 5.0 v, cap = 50 pf, 1 output switching) rise fall rise fall 1.1 1.05 1 0.95 0.9 0.85 0.8 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 supply voltage (v) 1.1 1.05 1 0.95 0.9 0.85 0.8 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 supply voltage (v) normalized t cko vs v cc (v cc = 5.0 v, cap = 50 pf, 1 output switching) normalized t pd vs v cc (v cc = 5.0 v, cap = 50 pf, 1 output switching) normalized tcko normalized tpd normalized tpd normalized tcko sp00409 figure 1. device characterization (continued)
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 7 product features metastable immune flip-flops the d-type flip-flops have been designed such that the outputs will not glitch or display an output anomaly if the input set up or hold times are violated. based on a t of 83ps, and sampling the output 8ns after the clock edge, the typical mtbf is 104 years. if the sample is taken 8.5ns after the clock, the mtbf is 43,095 years. (see page 11.) low ground bounce the philips semiconductors bicmos qubic process produces exceptional noise immunity. the typical ground bounce, with 9 outputs simultaneously switching and the 10th output held low, is less than 0.8v. (see page 12.) programmable 3-stage outputs each output has a 3-stage output buffer with 3-state control. a product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. the combinatorial output provides a bidirectional i/o pin, and may be configured as a dedicated input if the buffer is always disabled. programmable output parity the polarity of each macro cell output can be active-high or active-low, either to match output signal needs or to reduce product terms. programmable polarity allows boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. it can also save ademorganizingo efforts. selection is controlled by programmable bit s 0 in the output macro cell, and affects both registered and combinatorial outputs. selection is automatic, based on the design specification and pin definitions. if the pin definition and output equation have the same polarity, the output is programmed to be active-high (s 0 = 1). (see page 15.) preset/reset for initialization, the abt22v10 has additional preset and reset product terms. these terms are connected to all registered outputs. when the synchronous preset (sp) product term is asserted high, the output registers will be loaded with a high on the next low-to-high clock transition. when the asynchronous reset (ar) product term is asserted high, the output registers will be immediately loaded with a low, independent of the clock. note that preset and reset control the flip-flop, not the output pin. the output level is determined by the output polarity selected. (see page 16.) power-up reset all flip-flops power-up to a logic low for predictable system initialization. outputs of the abt22v10 will depend on the programmed output polarity. the v cc rise must be monotonic and the reset delay time is 110 m s maximum. (see page 18.) security fuse after programming and verification, a abt22v10 design can be secured by programming the security fuse link. once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. when the security fuse is programmed, the array will read as if every fuse is programmed. quality and testability the abt22v10 offers a very high level of built-in quality. extra programmable fuses provide a means of verifying performance of all ac and dc parameters. in addition, this verifies programmability and functionality of the device to provide the highest programming and post-programming functional yields. technology the bicmos abt22v10 is fabricated with the philips semiconductors process known as qubic. qubic combines an advanced, state-of-the-art 1.0 m m (drawn feature size) cmos process with an ultra fast bipolar process to achieve superior speed and drive capabilities. qubic incorporates three layers of al/cu interconnects for reduced chip size, and our proven ti-w fuse technology ensures highest programming yields. programming the abt22v10-7 is fully supported by industry standard (jedec compatible) pld cad tools, including philips semiconductors snap design software package. abel ? cupl ? and palasm ? 90 design software packages also support the abt22v10-7 architecture. all packages allow boolean and state equation entry formats, snap, abel and cupl also accept, as input, schematic capture format. programming/software support refer to section 9 (development software) and section 10 (support material) of the1994 pld data handbook for additional information. output register preload the register on the abt22v10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. this feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired sate. in addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. the procedure for preloading follows: 1. raise v cc to 5.0v 0.25v. 2. set pin 2 or 3 to v hh to disable outputs and enable preload. 3. apply the desired value (v ilp /v ihp ) to all registered output pins. leave combinatorial output pins floating. 4. clock pin 1 from v ilp to v ihp . 5. remove v ilp /v ihp from all registered output pins. 6. lower pin 2 or 3 to v ilp . 7. enable the output registers according to the programmed pattern. 8. verify v ol /v oh at all registered output pins. note that the output pin signal will depend on the output polarity. abel is a trademark of data i/o corp. cupl is a trademark of logical devices, inc. palasm is a registered trademark of amd corp.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 8 philips abt features the abt22v10-7 is the first in a complete family of 22v10s targeted to meet the high performance needs of the design community. in addition to the high speed characteristics of the devices, philips has designed the devices with advanced features to ensure high system reliability. the abt22v10-7 is the only programmable device that guarantees metastable immunity while providing high drive and low noise. the abt22v10a55 and abt22v10a7 offer high performance with live insertion capability, as well as high drive and low noise. live insertion refers to the ability of the outputs to remain 3-stated during power supply ramp. this is a key feature for many telecom applications, where boards are inserted into poweredup systems. system integrity is maintained as the device powers up in a well-defined manner. abt22v10-7 abt22v10a5 abt22v10a7 live insertion no yes yes dual verify no yes yes metastability immune no no source drive capability 16ma (v oh = 2.4v) 16ma (v oh = 2.4v) 16ma (v oh = 2.4v) sink drive capability 48ma (v ol = 0.5v) 48ma (v ol = 0.5v) 48ma (v ol = 0.5v) low ground bounce yes yes yes package availability: plastic dual in-line (n) 24-pin not available not available plastic leaded chip carrier (a) 28-pin 28-pin 28-pin pinout standard evolutionary evolutionary
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 9 metastable immune characteristics what is metastable immunity? philips semiconductors uses the term `metastable immune' to describe a combination of two characteristic features. the first is a patented philips circuit that prevents the outputs from glitching, oscillating, or remaining in the linear region under any circumstances, including setup and hold time violations. the second is the flip-flop's inherent ability of resolving the metastable condition. for example, using a non-metastable immune device, a typical metastabel condition could result by running two independent signal genrators (see figure 2) at nearly the same frequency (in this case 10mhz clock and 10.02mhz data). this device-under-test can often be driven into a metastable state. if the q outut is used to trigger a digital scope set to infinite persistence, the q output will build a waveform. dq q cp trigger digital scope input signal generator signal generator sp00410 figure 2. test set-up figure 3 shows that for a non-metastable immune device, the q output can vay in time with respect to the q trigger point. this also implies that the q or q output waveshapes may be distorted. this can be erified on an analog scope with a charge plate crt. of even greater interest are the dots running along the 3.5v volt line in the upper right-hand quadrant. these show that the q output did not change state even though the q output glitched to at least 1.5 volts, the trigger point of the scope. when the device-under-test is a metastable immune part, the waveform will appear as in figure 4. the output will not vary with respect to the q trigger point even when the part is driven into a metastable state. any tendency towards internal metastability is resolved by philips semiconductors patented circuitry. if a metastable event occurs within the flip-flop, the only outward manifestation of the event will be an increased clock-to-q delay. this delay is a function of the metastability characteristics of the device, defined by t and t 0 as described in the design example that follows. since the outputs never glitch, oscillate, or remain in the linear region, the only metastable failure that can propagate further into the system is when the next flip-flop in the system samples the abt22v10-7's outut at recisely the same time it is making a logic transition. by allowing sufficient time for any increased clock-to-q delay, propagation of metastable failures can be avoided. the following design example illustrates this concept.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 10 comparison of metastable immune and non-immune characteristics 4 3 2 1 0 time base = 2.00ns/div trigger level = 1.5 volts trigger slope = positive sa00006 figure 3. non-immune q output triggered by q output, setup and hold times violated 3 2 1 0 time base = 2.00ns/div trigger level = 1.5 volts trigger slope = positive sa00007 figure 4. metastable immune q output triggered by q output, setup and hold times violated
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 11 design example suppose a designer wants to use the abt22v10-7 for synchronizing asynchronous data that is arriving at 10mhz (as measured by a frequency counter), in a 5v system that has a clock frequency of 50mhz, at an ambient temperature of 25 c. she has decided that she would like to sample the output of the abt22v10 8.5ns after the clock edge to ensure that any clock-to-q delays that were the result of the abt22v10 internal metastability resolution circuitry have completed and the outputs have transitioned. the mtbf for this situation can be calculated by using the equation below: mtbf e t t 0 f c f i in this formula, f c is the frequency of the clock, f i is the average input event frequency, and t is the time after the clock pulse that the output is sampled (t > t co ). t 0 and t are derived from tests and can most nearly be defined as follows: t is a function of the rate at which a latch in a metastable state resolves that condition. t 0 is a function of the measurement of the propensity of a latch to enter a metastable state. t 0 is also a normalization constant which is a very stron function of the normal propagation delay of the device. in this situation, the f i will be twice the data frequency, or 20mhz, because input events consist of both low and high transitions. thus, in this case, f c is 50mhz, f i is 20mhz, t is 83ps, t is 8.5ns, and t 0 is 2.2 10 17 seconds. using the above formula, the actual mtbf for this situation is 1.36 10 12 seconds, or 43,095 years for the abt22v10-7. abt22v107 values for t and t 0 t amb = 0 c t amb = 25 c t amb = 70 c v cc t t 0 t t 0 t t 0 5.5v 83ps 8.1 10 18 sec 82ps 7.5 10 18 sec 101ps 3.0 10 12 sec 5.0v 80ps 4.0 10 18 sec 83ps 2.2 10 17 sec 98ps 4.4 10 11 sec 4.5v 85ps 3.4 10 14 sec 91ps 2.5 10 12 sec 106ps 1.1 10 8 sec summary the philips abt22v10-7 has on-chip circuitry that completely eliminates any output glitches, oscillations, or other output anomalies associated with metastable conditions. for outputs that are then used to generate clocks, control signals or other asynchonous data, this represents an unparalled level of reliability in a pld. in addition, a complete set of metastability data is provided, which allows designers the ability to design extremely robust systems where data is synchronously pipelined.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 12 low noise output f9 pin 27 800mv gnd 4v 3v 2v 1v 0v 1v 2v 3v 4v 5.0 ns/division sp00414 figure 5. device characterization ground bounce figure 5 shows the low ground (v olp ) bounce (0.8v) observed on the 10th output of the abt22v10 under the following conditions: 9 remaining outputs switching, each driving 50pf loads, in plcc non-socketed device, at 5.25v, 25 c. similar testing of comparable eecmos 22v10 devices resulted in ground bounce in the 1.5 2.0v range. at philips the utilization of our advanced bicmos process, qubic, enables the production of high performance devices with the lowest output noise to ensure first pass system reliability. quiet your concerns on ground bounce with philips abt22v10-7.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 13 logic diagram note: programmable connection. 1 1 0 0 0 1 0 1 d ar q q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 ar sp 0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 3940 43 0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 3940 43 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk/i0 i1 i2 i3 i4 i5 i6 i7 i10 i8 i9 gnd i11 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 v cc 0 1 9 10 20 21 33 34 48 49 65 66 82 83 97 98 110 111 121 122 130 131 sp00059
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 14 functional diagram output macro cell clk/i0 i1 i11 reset preset f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 programmable and array (44 132) 1 11 8 101214 1616141210 8 sp00060 output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell figure 6. functional diagram functional description the abt22v10 allows the systems engineer to implement the design on-chip, by opening fuse links to configure and and or gates within the device, according to the desired logic function. product terms with all fuses opened assume the logical high state; product terms connected to both true and complement of any single input assume the logical low state. the abt22v10 has 12 inputs and 10 i/o macro cells (figure 6). the macro cell allows one of four potential output configurations, registered output or combinatorial i/o, active-high or active-low (see figure 7). the configuration choice is made according to the user's design specification and corresponding programming of the configuration bits s 0 s 1 . multiplexer controls are connected to ground (0) through a programmable fuse link, selecting the a0o path through the multiplexer. programming the fuse disconnects the control line from gnd and it floats to v cc (1), selecting the a1o path. the device is produced with a fuse link at each input to the and gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. utilizing an easily-implemented programming algorithm, these products can be rapidly programmed to any customized pattern. information on approved programmers can be found in the programmer reference guide. extra test fuses are pre-programmed during manufacturing to ensure extremely high field programming yields, and provide extra test paths to achieve parametric correlation.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 15 output macro cell f 0 1 1 0 0 1 0 0 1 clk 1 ar sp s 1 s 0 s 1 s 0 output configuration 0 = unprogrammed fuse 1 = programmed fuse dq q 0 0 1 1 0 1 0 1 registered/active-low registered/active-high combinatorial/active-low combinatorial/active-high sp00375 figure 7. output macro cell logic diagram f clk ar sp s 0 = 0 s 1 = 0 dq q a. registered/active-low f clk ar sp s 0 = 1 s 1 = 0 dq q b. registered/active-high f s 0 = 0 s 1 = 1 c. combinatorial/active-low d. combinatorial/active-high f s 0 = 1 s 1 = 1 sp00376 figure 8. output macro cell configurations registered output configuration each macro cell of the abt22v10 includes a d-type flip-flop for data storage and synchronization. the flip-flop is loaded on the low-to-high transition of the clock input. in the registered configuration (s 1 = 0), the array feedback is from q of the flip-flop. combinatorial i/o configuration any macro cell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (s 1 = 1). in the combinatorial configuration, the feedback is from the pin. variable input/output pin ratio the abt22v10 has twelve dedicated input lines, and each macro cell output can be an i/o pin. buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. unused input pins should be tied to v cc or gnd.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 16 switching waveforms t s combinatorial output registered output clock to feedback (f max internal) (see path at right) clock width input to output disable/enable asynchronous reset synchronous preset t pd v t v t input or feedback combinatorial output v t v t v t input or feedback clock registered output t s t h t co v t t s + t cf clock logic register clk t s t cf v t t wh clock t wl t er t ea v oh 0.5v v ol + 0.5v input output v t v t v t v t v t t arw t ar t arr clock registered output input asserting asynchronous reset t h v t v t v t v t t spr input asserting synchronous preset clock registered output t co sp00377 clock to feedback notes: 1. v t = 1.5v. 2. input pulse amplitude 0v to 3.0v. 3. input rise and fall times 2.5ns max.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 17 aando array (i, b) i, b p, d code o state inactive 1 code state code state code state true hle p, d i, b i, b p, d i, b i, b p, d i, b i, b i, b complement don't care sp00008 i, b i, b i, b i, b note: 1. this is the initial state. preload set-up symbol parameter limits unit symbol parameter min rec max unit v hh super-level input voltage 9.5 9.5 10 v v ilp low-level input voltage 0 0 0.8 v v ihp high-level input voltage 2.4 5.0 5.5 v t d delay time 100 200 1000 ns t i/o i/o valid after pin 2 or 3 drops from v hh to v ilp 100 ns t d v hh v ihp v oh v ol v ilp v ihp v ilp t i/o pins 2, 3 registered outputs clock t d t d t d t d output register preload waveform data in data out v ilp sp00373
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 18 t wl power-up reset waveform 4v v cc t s t pr power registered active-low output clock sp00066 symbol parameter limits unit symbol parameter min max unit t pr power-up reset time 1 m s t s input or feedback setup time see ac electrical characteristics t wl clock width low s ee ac el ec t r i ca l ch arac t er i s ti cs power-up reset the power-up reset feature ensures that all flip-flops will be reset to low after the device has been powered up. the output state will depend on the programmed pattern. this feature is valuable in simplifying state machine initialization. a timing diagram and parameter table are shown above. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met.
philips semiconductors product specification abt22v10-7 low noise, high drive, metastable immune, pld 1995 sep 26 19 snap resource summary designations clock or or or or or or or or or or output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell clk/i0 i1 i11 reset preset f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 programmable and array (44 132) 1 11 8 101214 1616141210 8 output macro cell f 0 clk 1 ar sp s 1 s 0 dq q olminv dinv10 ninv10 dinv10 ninv10 and ninv10 dinv10 ckv10 outv10 outv10 outv10 outv10 outv10 outv10 outv10 outv10 outv10 outv10 olmdir olmreg dinv10 ninv10 outv10 sp00413

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