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cyis1sm0250-aa cyis1sm0250-aa star250 250k pixel radiation hard cmos ima g e sensor cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05713 rev. *b revised december 12, 2006 features the star250 sensor is a cmos active pixel sensor, designed for application in optical inter-satellite link beam trackers. the star250 is part of broader range of applications such as space-borne systems like sun sensing and star tracking. it features 512 by 512 pixels on a 25 m pitch, on chip fixed pattern noise (fpn) correction, a programmable gain amplifier, and a 10bit adc. flexible operating (multiple windowing, subsampling) is possible by direct addressable x- and y- register. the sensor has an outstanding radiation tolerance that is observed by using proprietary technology modifications and design techniques. two versions of sensors are available, star250 and star250bk7. star250 has a quartz glass lid and air in the cavity. the star250bk7 has a bk7g18 glass lid with anti reflective coating. the cavity is filled with n 2 increasing the temperature operating range. applications ? satellites ? spacecraft monitoring ? nuclear inspection key features parameter typical value optical format 1 inch active pixels 512 x 512 pixel size 25 m shutter type electronic maximum data rate / master clock 8 mhz frame rate up to 30 full frames/s adc resolution 10 bit sensitivity 3340 v.m 2 /w.s dynamic range 74db (5000:1) ktc noise 76 e - dark current 4750 e - /s at rt supply voltage 5v operating temperature 0c - +65c (star250) -40c - +85c (star250bk7) gamma total dose radiation tolerance increase in average dark current < 1 na/cm 2 after 3 mrad image operation with dark signal < 1v/s after 10 mrad demonstrated (co60) proton radiation tolerance 1% of pixels has an increase in dark current > 1 na/cm 2 after 3*10^10 protons at 11.7 mev sel threshold > 80 mev cm 3 mg -1 color filter array mono packaging 84 pin jlcc power consumption < 350 mw key features (continued) parameter typical value [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 2 of 24 specifications general specifications electro-optical specifications overview table 1. general specifications parameter specification remarks pixel architecture 3-transistor active pixel 4 diodes per pixel radiation-tolerant pixel design 4 photodiodes for improved mtf pixel size 25 x 25 m 2 resolution 512 by 512 pixels pixel rate 8 mps shutter type electronic integration time is variable in time, steps equal to the row readout time frame rate 29 full frames/second extended dynamic range double slope programmable gain programmable between x1, x2, x4, x8 selectable through pins g0 and g1 supply voltage vdd 5v operational temperature range 0c - +65c star250 (quartz glass lid, air in cavity) -40c - +85c star250bk7 (bk7g18 glass lid, n 2 in cavity) package 84 pins jlcc table 2. electro-optical specifications parameter specification (all typical) comment detector technology cmos active pixel sensor pixel structure 3-trans istor active pixel 4 diodes per pixel radiation-tolerant pixel design 4 photodiodes for improved mtf photodiode high fill factor photodiode sensitive area format 512 by 512 pixels pixel size 25 x 25 m 2 spectral range 200 - 1000 nm see curves quantum efficiency x fill factor max. 35% above 20% between 450 and 750 nm (note: metal fillfactor (mff) is 63%) full well capacity 311k electrons when output amplifier gain = 1 linear range within + 1% 128k electr ons when output amplifier gain = 1 output signal swing 1.68 v whe n output amplifier gain = 1 conversion gain 5.7 v/e - when output amplifier gain = 1 near dark temporal noise 76 e - dominated by ktc dynamic range 74 db (5000:1) at the analog output [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 3 of 24 fpn (fixed pattern noise) 1 < 0.1% of full well (typical) measured local, on central im age area 50% of pixels, in the dark prnu (photo response non-uniformity) local: 1 = 0.39% of response global: 1 = 1.3% of response measured in central image area 50% of pixels, at qsat/2 average dark current signal 4750 e - /s at rt dsnu (dark signal non uniformity) 3805 e - /s rms at rt, scale linearly with integration time mtf horizontal: 0.36 vertical: 0.39 at 600 nm. optical cross talk 5% (tbc) to nearest neighbor if central pixel is homogeneously illuminated anti-blooming capacity x 1000 to x 100 000 output amplifier gain 1, 2, 4 or 8 controlled by 2 bits windowing x and y 9-bit programmable shift registers indicate upper left pixel of each window electronic shutter range 1: 512 integration time is variable in time steps equal to the row readout time adc 10 bit adc linearity 3.5 counts inl missing codes none adc setup time 310 ns to reach 99% of final value adc delay time 125 ns power dissipation < 350 mw average at 8 mhz pixel rate table 2. electro-optical specifications (continued) parameter specification (all typical) comment [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 4 of 24 spectral response curve figure 1. spectral response curve figure 2. uv region spectral response curve 0 0.05 0.1 0.15 0.2 400 500 600 700 800 900 1000 1100 wavelength [nm] spectral respnse [a/w] qe 0.01 qe 0.05 qe 0.1 qe 0.2 qe 0.3 qe 0.4 star250 uv-measurement 1,00e-04 1,00e-03 1,00e-02 1,00e-01 1,00e+00 200 250 300 350 400 450 500 wavelength [nm] ff * spectral response [a/w] qe 100% qe 10% qe 1% [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 5 of 24 pixel profile figure 3. pixel profile the pixel profile is measured using the 'knife edge' method: the image of a target containing a black to white transition is scanned over a certain pixel with subpixel resolution steps. the image sensors settings and the illumination conditions are adjusted such that the transi tion covers 50% of the output range. the scan is performed both horizontal and vertical. 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 scan distance [mm] relative profile horizontal pixel profile vertica pixel pr ofile ima g inar yp ixel boundaries [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 6 of 24 electrical specifications absolute maximum ratings radiation tolerance figure 4. shows the increase in dark current under total dose irradiation. this curve is meas ured when the radiation is at high dose rate. annealing results in a significant dark current decrease. table 3. absolute maximum ratings star250 characteristics limits units remarks min max any supply voltage -0.5 +7 v voltage on any input terminal -0.5 vdd + 0.5 v operating temperature 0 +60 c storage temperature -10 +60 c sensor soldering temperature na 125 c hand soldering only. the sensor?s temperature during soldering should not exceed this limit. table 4. absolute maximum ratings star250bk7 characteristics limits units remarks min max any supply voltage -0.5 +7 v voltage on any input terminal -0.5 vdd + 0.5 v operating temperature -40 +85 c storage temperature -40 +85 c -40 +120 c maximum 1 hour sensor soldering temperature na 125 c hand soldering only. the sensor?s temperature during soldering should not exceed this limit. table 5. radiation tolerance parameter criterion qualification level gamma total dose radiation tolerance increase in average dark current < 1 na/cm 2 after 3 mrad see graph image operation with dark signal < 1v/s 10 mrad demonstrated (co60) single (test) pixel operation with dark signal < 1v/s 24 mrad demonstrated (co60) proton radiation tolerance 1% of pixels has an increase in dark current > 1 na/cm 2 after 3*10^10 protons at 11.7 mev see graph sel threshold > 80 mev cm 3 mg -1 to be confirmed [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 7 of 24 figure 4. dark current increase figure 5. shows the percentage of pixels with a dark current increase under 11.7 mev radiation with protons. absolute ratings are those values beyond that damage to the device may occur. figure 5. percentage of pixels with dark current increase 0 0,2 0,4 0,6 0,8 1 1,2 1,4 024681012 total ionizing dose [mrad(si)] dark current increase [na/cm 2 ] notes 1. all parameters are characterized for dc cond itions after establishing thermal equilibrium. 2. unused inputs must always be tied to an appropriate logic level, e.g. either vdd or gnd. 3. this device contains circ uitry to protect the inputs against damage due to high static voltages or electric fields. take, nor mal precautions to avoid applying any voltages higher than the maximum rated voltages to this high-impedance circuit. [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 8 of 24 dc operating conditions table 6. dc operating conditions symbol parameter min typ max units vdd_ana analogue supply voltage to imager part 5 v vdd_dig digital supply voltage to imager part 5 v vdd_adc_ana analogue supply voltage to adc 5 v vdd_adc_dig digital supply voltage to adc 5 v vdd_adc_dig_3.3/5 supply voltage of adc output stage 3.3 to 5 v vih logical '1' input voltage 2.3 vdd v vil logical '0' input voltage 0 1 v voh logical '1' output voltage 4.25 4.5 v vol logical '0' output voltage 0.1 1 v vdd_pix pixel array power supply (default 5v, the device is then in "soft reset". in order to avoid the image lag associated with soft reset, reduce this voltage to 3?3.5v "hard reset") 5v vdd_resl reset power supply 5 v [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 9 of 24 sensor architecture figure 6. star250 schematic the base line of the star250 se nsor design consists of an imager with a 512 by 512 array of active pixels at 25 m pitch. the detector contains on-chi p correction for fixed pattern noise (fpn) in the column amplifiers, a programmable gain output amplifier and a 10-bit analog-to-digital converter (adc). through additional preset registers the start position of a window can be programmed to enable fast read out of only part of the detector array. pixel structure the image sensor consists of several building blocks as outlined in figure 6. the central element is a 512 by 512 pixel array with square pixels at 25 m pitch. unlike classical designs, the pixels of this s ensor contain four photodiodes. this configuration enhances the mtf and reduces the prnu. figure 7. shows an electrical diagram of the pixel structure. the four photodiodes are connected in parallel to the reset transistor (t1). transistor t2 co nverts the charge, collected on the photo diode node, to a voltage signal that is connected to the column bus by t3. the reset and the read entrance of the pixel are connected to one of the y shift registers. figure 7. star250 pixel structure y-start registeer-decoder 9 10 d9...d0 clk_adc ain s r column amplifiers 512 512 1024 1024 ld_x x address decoder / shift register rst sig progr. gain amplifier blackref cal g0 g1 sync_yl clk_yl ld_y 9 9 512 y address decoder / shift register pixel array 512 by 512 pixels 512 rst sel col y address decoder / shift register 10-bit adc clk_yr syncyr a8...a0 aout 9 clkx sync_x x-start register t1 t2 t3 read column bus reset [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 10 of 24 shift registers the shift registers are located next to the pixel array and contain as many outputs as t he number of rows in the pixel array. they are designed as "1- hot" registers, (yl and yr shift register) each allowing selection of one row of pixels at a time. a clock pulse moves the pointer one position down the register resulting in the selection of every individual row for either reset or for readout. the spatial offset between the two selected rows determines the integration time. a synchronization pulse to the shift registers loads the va lue from a preset register into the shift register forcing the pointer to a predetermined position. windowing in the vertical (y) direction is achieved by presetting the registers to a row that is not the first row and by clocking out only the required number of rows. column amplifiers all outputs from the pixels in a column are connected in parallel to a column amplifier. this amplifier samples the output voltage and the reset level of the pixel whose row is selected at that moment and presents these voltage levels to the output amplifier. as a result, the pixels are always reset immediately after readout as part of t he sample procedure and the maximum integration time of a pixel is the time between two read cycles. electronic shutter in a linescan integrating imager with electronic shutter, there are two continuous processes of image gathering. the first process resets lines in a progressive scan. at line reset, all the pixels in a line are drained from any photo charges collected since their last reset or readout. after reset, a new exposure cycle starts for that particular line. the second process is the actual readout, which also happens in an equally fast linewise progressive scan. during readout, the photo charges collected since the previous reset are converted into an output voltage. this is then passed on pixel by pixel to the imager's pixel serial output and adc. readout is destructive, meaning the accumulation of charges from successive exposure phases is not possible in the present architecture. the star250 has two y- shift registers; yl and yr. one is used for readout of a line (yl) and the other is used to reset a line (yr). the integration time is equal to the time between the last reset and the readout of that line, see figure 8. the integration time is thus equal to: integration time = (nr. lines * (rbt + pixel period * nr. pixels)) with: ? nr. lines: number of lines between readout and reset (y). ? nr. pixels: number of pixels read out each line (x). ? rbt: row blanking time = 3.2 s (typical). ? pixel period: 1/8 mhz = 125 ns (typical). figure 8. electronic shutter reset line read line x y x y time axis line number reset sequence frame time integration time [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 11 of 24 programmable gain amplifier the signal from the column amplifiers is fed to an output amplifier with four presettable gains (adjustable with pins g0 and g1). the offset correction of this amplifier is done through a black reference procedure. the signal from the output amplifier is externally available on the analog output terminator of the device. analog-to-digital converter the on-chip 10-bit adc is electrically separated from the other circuits of the device. the adc conversion range is set by the voltages on vlow_adc (pin 47) and vhigh_adc (pin 70). make voltages on these pins equal to about 2v on vlow_adc and 4v on vhigh_adc. the voltages are set by connecting vlow with 1.2k ? to gnd and vhigh_adc with 560 ? to vdd. this way, a resistor ladder is created as shown in figure 9. figure 9. adc resistor ladder the internal adc resistance varies according to temperature. the resistance value increases approximately 4.4 ? /c with increasing temperature. if the ad c range is set externally with resistors, the conversion ran ge may vary with temperature. this effect is cancelled out by not making use of resistors but directly applying voltages on vlow_adc and vhigh_adc. timing and readout of the image sensor image readout procedure a preamble or initialization phase is irrelevant. the sensor is read out continuously. the first frame is generally saturated and useless because there is no preceding reset of each pixel. image readout in an infinite uninterrupted loop, follow these steps line-by-line: 1. synchronize the read (yl) and/or reset (yr) registers, in this cases: ? sync_yl - to reinitiate the readout sequence to row position y1 ? sync_yr - to reinitiate the reset pointer to row position y1 for all other lines do not puls e one of these sync_y signals. 2. operate the double sampling column amplifiers with two resets. apply one to reset the line that is currently selected to produce the reset reference level for the double sampling column amplifiers. apply the other reset to another line depending on the required integration time reduction. 3. perform a line readout: reset the x read address shift register to the value in its shadow register (x1). perform a pixel readout operat ion, operating the track/hold and the adc. shift the x read address shift register one position further. shift the y read and reset address shift registers one position further. if either of y read or reset address shift register comes to the end of the pixel array (or the roi), wrap it around to the start position by pulsing sync_yl. readout timing the actual line readout process starts with addressing the line to read. this is done either by initializing the yl pointer with a new value, or by shifting it one position beyond its previous value. (addressing the line has reset, yr is done in an analogous fashion). during the "blanking time", after the new line is addressed on the sens or, the built-in column-parallel double sampling amplifiers are operated. this renders offset-corrected values of the line under readout. after the blanking time the pixels of the row addressed by yl are read by multiplexing all the pixels one by one to the serial output chain. the pixel is selected by the x pointer, and that pointer is either initialized with a new value or an increment of the previous position. the time between row resets and their corresponding row readouts is the effective exposure time (or integration time). this time is proportional to the number of lines (delaylines) between the line currently under reset and the line currently under readout: delaylines = (yr - yl+1). this time is also equal to the delay between the sync_yr pulse and the subsequent sync_yr. the effective integration time tint is calculated as delaylines * line time. the line time itself is a function of four terms: the time to output the desired number of pixels in the line (wframe), and the overhead ("blanking") time that is needed to select an new line and perform the double sampling and reset operations. r adc_vhigh external internal r adc r adc_vlow external pin 70: vhigh_adc pin 47: vlow_adc [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 12 of 24 figure 10. basic readout timing sync_yr is not identical to as sync_yl. sync_yr is used in case of electronic shutter operation. the clk_yr is driven identically as clk_yl, but the sync_yr pulse leads the sync_yl pulse by a certain number of rows. this lead time is the effective integration (electronic shutter ~) time. relative to the row timing, both sync pulses are given at the same time position, once for each frame, but during different rows. sync_yl is pulsed when the first row is read out and sync_yr is pulsed for the electronic shutter to start for this first row. cal is pulsed on the first row too, 2 s later than sync_yl. the minimal idle time is 1.4 s (before starting reading pixels). however, do not read out pixels during the complete row initial- ization process (in between the rising edge on s and the falling edge on l/r). in this case, the total idle time is minimal. this timing assumes that the y start register was loaded in advance, which can occur at any time but before the pulse on sync_yl or sync_yr. t13 t10 t2 t9 t16 t15 t17 t14 t12 t1 t3 t7 t4 t6 t4 t11 t5 t8 time available for read out of row y row blanking time row y-1 sync_yl sync_yr cal row start address ld_y may occur at any moment, persumably once per sequence of frames once per frame clk_yl clk_yr s reset r l/r table 7. readout timing specifications symbol min typ description t1 1.8 s delay between selection of new row by falling edge on clk_yl and falling edge on s. minimal value. normally, clk_yr is low already at the end of the previous sequence. t2 1.8 s delay between selection of new a row by sync_yl and falling edge on s. t3 0.4 s duration of s and r pulse. t4 0.1 s duration of reset pulse. t5 t4 + 40 ns 0.3 s l/r pulse must overlap second reset pulse at both sides. [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 13 of 24 loading the x- and y- start positions the start positions (start addresses) for "roi" (region of interest) are preloaded in the x or y start register. they become effective by the application of the sync_x, sync_yl and/or sync_yr. the start x- or y address must be applied to their common address bus, and the corresponding ld_x or ld_y pin must be pulsed. on each falling edge of clk_x, a new pixel of the same row (line) is accessed. the output stage is in hold when clk_x is low and starts generating a new output after a rising edge on clk_x. the following timing constraints apply: load the x or y start addresses in advance, before the x or y shift registers are preset by a sync pulse. however, if necessary, they can be load just before the sync_x or sync_y pulse as shown in the figure 11. e.g. the x start register can be loaded during the row idle time. the y start register can be loaded during readout of the last row of the previous frame. if the x or y start address does not change for later frames, it does not need to be reloaded in the register. t6 0.8 s delay between falling edge on reset and falling edge on r. t7 20 ns 0.1 s delay between falling edge on s and rising edge on reset. t8 0 1 s delay between falling edge on l/r and falling edge on clk_y. t9 100 ns 1 s duration of cal pulse. the ca l pulse is given once each frame. t10 0 2 s delay between falling edge of sy nc_yl and rising edge of cal pulse. t11 40 ns 0.1 s delay between falling edge on r and rising edge on l/r. t12 0.1 s1 s delay between rising edge of clk_y and falling edge on s. t13 0.5 s pulse width sync_yl / yr t14 0.5 s pulse width clk_yl / yr t15 10 ns address set-up time t16 20 ns load x / y start register value t17 10 ns address stable after load t18 10 ns t19 20 ns sync_x pulse width. sync_x while clk_x is high. t20 10 ns t21 40 ns analogue output is stable during clk_x low. t22 40 ns clk_x pulse width: during this clock phase the analogue output ramps to the next pixel level. t23 125 ns adc digital output stable after falling edge of clk_adc table 7. readout timing specifications (continued) symbol min typ description [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 14 of 24 figure 11. timing for loading the x- and y- register other signals tie select signal to vdd for normal operation. this signal was added for diagnostic reasons and inhibits the pixel array operation when held low. the cal signal sets the output amplifier dc offset level. when this signal is active (high) the pixel array is internally disconnected from the output amplif ier, its gain is set to unity and its input signal is connected to the black_ref input. perform this action at least once for each frame. eos_x, eos_yl and eos_yr produce a pulse when the respective shift register comes at its end. these outputs are used mainly during testing to verify proper operation of the shift registers. test diode and testpixel array are connections to optical test structures that are used for electro optical evaluation. testdiode is a pl ain photodiode with an area of 14x5 pixels. testpixel_array is an array (14x5) of pixels where the photodiodes are connected in parallel. these structures measure the photocu rrent of the diodes directly. testpixel_reset and testpi xel-out are connections to a single pixel that are used for testing. row blanking time time available for read out of row y column start address may occur at any moment in time ld_x t15 t17 t16 t19 t18 t20 t21 t22 pixel 1 pixel 2 pixel 3 t23 pixel 1 pixel 2 adc out clk adc analog output clk_x sync_x [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 15 of 24 pinlist table 8. power supply connections pin pin name pin description 10 vdd_ana analog power supply 5v. 11 vdd_dig digital power supply 5v. 31 vdd_amp power supply of output amplifier 5v. 33 vdd_dig digital power supply 5v. 34 vdd_ana analogue power supply 5v. 49 vdd_resr reset power supply 5v. 50 vdd_dig digital power supply 5v. 53 vdd_adc_ana adc analogue power supply 5v. 66 vdd_adc_ana adc analogue power supply 5v. 67 vdd_adc_dig adc digital power supply 5v. 69 vdd_adc_dig_3.3/5 adc 3.3v power supply for digital output of adc. for interface with 5v external system: connect to vdd_adc_dig. for interface with 3.3 v external system: connect to 3.3v power supply. 52 76 vdd_pix pixel array power supply [d efault: 5v, the device is then in "soft reset". in order to avoid the image lag associated with soft reset, reduce this voltage to 3?3.5 v "hard reset"]. 78 vdd_dig digital power supply 5v. 79 vdd_resl reset power supply 5v. table 9. ground connections pin pin name pin description 9 gnd_ana analog ground. 12 gnd_dig digital ground. 30 gnd_amp ground of output amplifier. 32 gnd_dig digital ground. 35 gnd_ana analog ground. 51 gnd_dig digital ground. 54 gnd_adc_ana adc analog ground. 65 gnd_adc_ana adc analog ground. 68 gnd_adc_dig adc digital ground. 77 gnd_dig digital ground. table 10. digital input signals pin pin name pin description 1 s control signal for column amplifier. apply pulse pattern - see sensor timing diagram. 2 r control signal for column amplifier. apply pulse pattern - see sensor timing diagram. [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 16 of 24 3 reset resets row indicated by left/right shift register. high active (1= reset row). apply pulse pattern - see sensor timing diagram. 4 select selects row indicated by left/right shift register. high active (1=select row). apply 5 v dc for normal operation. 5 l/r use left or right shift register for select and reset. 1 = left / 0 = right - see sensor timing diagram. 6 a0 start address for x- and y- pointers (lsb). 7 a1 start address for x- and y- pointers. 8 a2 start address for x- and y- pointers. 13 a3 start address for x- and y- pointers. 14 a4 start address for x- and y- pointers. 15 a5 start address for x- and y- pointers. 16 a6 start address for x- and y- pointers. 17 a7 start address for x- and y- pointers. 18 a8 start address for x- and y- pointers (msb). 19 ld_y latch address (a0?a8) to y start register (0 = track, 1 = hold). 20 ld_x latch address (a0?a8) to x start register(0 = track, 1 = hold). 21 clk_yl clock yl shift register (shifts on falling edge). 22 sync_yl sets yl shift register to location preloaded in y start register. low active (0=sync). apply sync_yl when clk_yl is high. 24 clk_x clock x shift register (output valid & s when clk_x is low). 25 sync_x sets x shift register to location preloaded in x start register. low active (0=sync). apply sync_x when clk_x is high. after sync_x, apply falling edge on clk_x, and rising edge on clk_x. 27 clk_yr clock yr shift register (shifts on falling edge). 28 sync_yr sets yr shift register to location preloaded in y start register. low active (0=sync). apply sync_yr when clk_yr is high. 36 cal initialize output amplifier. output amplifier will output blackref in unity gain mode when cal is high (1). apply pulse pattern (one pulse per frame) - see sensor timing diagram. 37 g0 select output amplifier gain value: g0 = lsb; g1 = msb. 00 = unity gain; 01 = x2; 10= x4; 11=x8. 38 g1 idem. 71 clk_adc adc clock. adc converts on falling edge. 75 bitinvert 1 = invert output bits. 0 = no inversion of output bits. table 10. digital input signals (continued) pin pin name pin description [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 17 of 24 80 tri_adc tri-state control of digital adc outputs 1 = tri-state; 0 = output table 11. digital output signals pin pin name pin description 23 eos_yl end-of-scan of yl shift register. low first clock period after last row (low active). 26 eos_x end-of-scan of x shift register. low first clock period after last active column (low active). 29 eos_yr end-of-scan of yr shift register. low first clock period after last row (low active). 55 d0 adc output bit (lsb). 56 d1 adc output bit. 57 d2 adc output bit. 58 d3 adc output bit. 59 d4 adc output bit. 60 d5 adc output bit. 61 d6 adc output bit. 62 d7 adc output bit. 63 d8 adc output bit. 64 d9 adc output bit (msb). table 12. analog input signals pin pin name pin description 39 nbiasarr connect with 470 k to vdd and decouple to ground with a 100 nf capacitor. 40 pbias connect with 39 k to ground and decouple to vdd with a 100 nf capacitor for 8 mhz pixel rate. (lower resistor values yield higher maximal pixel rates at the cost of extra power dissipation). 41 nbias_amp output amplifier speed/power control. connect with 51k ? to vdd and decouple with 100 nf to gnd for 8 mhz output rate (lower resistor values yield higher maximal pixel rates at the cost of extra power dissipation). 42 blackref control voltage for output signal offset level. buffered on-chip, the reference level can be generated by a 100k ? resistive divider. connect to +/- 2 v dc for use with on-chip adc. 44 in_adc input, connect to sensor's output. input range is between 2 & 4 v (vlow_adc & vhigh_adc). 45 nbiasana2 connect with 100 k to vdd and decouple to gnd. 46 nbiasana connect with 100 k to vdd and decouple to gnd. 47 70 vlow_adc vhigh_adc low reference and high reference voltages of adc should be about 2 and 4v. the required voltage settings on vlow _adc and vhigh_adc can be approximated by tying vlow_adc with 1.2k ? to gnd and vhigh_adc with 560 ? to vdd. table 10. digital input signals (continued) pin pin name pin description [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 18 of 24 48 g_ab anti-blooming drain control voltage: default: connect to ground. the anti-bl ooming is operational but not maximal. apply 1v dc for improved anti-blooming. 72 pbiasdig2 connect with 100k to gnd and decouple to vdd. 73 pbiasencload connect with 100k to gnd and decouple to vdd. 74 pbiasdig1 connect with 47k to gnd and decouple to vdd. table 13. analog output signals pin pin name pin description 43 out analogue output signal are connected to the analogue input of the adc. table 14. test structures pin pin name pin description 81 testdiode plain photo diode, size: 14 x 25 pixels. must be left open for normal operation. 82 testpix array array of test pixels, connected in parallel (14 x 25 pixels). must be left open for normal operation. 83 testpixel_reset reset input of single test pixel. must be tied to gnd for normal operation. 84 testpixel_out output of single test pixel. must be left open for normal operation. table 12. analog input signals (continued) pin pin name pin description [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 19 of 24 package package with glass note: all dimension in figure 12. are measured in inches. figure 12. star250 package dimensions table 15. package specifications: type jlcc-84 material black alumina ba-914 thermal expansion coefficient 7.6 x 10 -6 /k [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 20 of 24 die alignment figure 13. die alignment the die is aligned manually in the package to a tolerance of 50 m and the alignment is verified after hardening the die adhesive. all dimensions in figure 13 are in mm. die adhesive: 0.08+0.02 window adhesive: 0.08+0.02 glass window: 1.0+/-0.05 die: 0.508+0.01 bonding cavity: 0.508+0.051 die cavity: 0.508+0.051 section a a - drawing not to scale 68 p center of cavity and of fpa center of silicium offset between center of silicium and center of cavity: x: 0 y: 68 p m parallelism in x and y within + 50 p m pin 1 a a [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 21 of 24 window specifications star250 star250bk7 table 16. star250 glass cover specifications: material fused silica dimensions 25 x 25 mm +- 0.2 mm thickness 1 mm +- 0.05 mm anti reflecti ve coating no cavity fill air table 17. star250bk7 glass cover specifications material bk7g18 dimensions 25 x 25 mm +- 0.2 mm thickness 1 mm +- 0.05 mm anti reflecti ve coating yes cavity fill n 2 [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 22 of 24 soldering and handling soldering and handling conditions take special care when soldering image sensors onto a circuit board. prolonged heating at elev ated temperatures may result in deterioration of the performance of the sensor. the following recommendations are made to ensure that sensor performance is not compromised during end users' assembly processes. board assembly the star250 is very sensitive to esd. device placement onto boards should be done in accordance with strict esd controls for class 0, jesd22 human body model, and class a, jesd22 machine model devices. assembly operators need to always wear all designated and approved grounding equipment; grounded wrist straps at esd protected workstations are recommended including the use of ionized blowers. all tools should be esd protected. manual soldering when a soldering iron is used the following conditions should be observed: use a soldering iron with temperat ure control at the tip. the soldering iron tip temperature should not exceed 350c. the soldering period for each pin should be less than five seconds. reflow soldering reflow soldering is not allowed. precautions and cleaning avoid spilling solder flux on the cover glass; bare glass and particularly glass with antirefle ction filters may be harmed by the flux. avoid mechanical or particulate damage to the cover glass. use isopropyl alcohol (ipa) as a solvent for cleaning the image sensor glass lid. when using other solvents, it should be confirm whether the solvent wil l dissolve the package and/or the glass lid. rohs (lead free) compliance this paragraph reports the use of hazardous chemical substances as required by the rohs directive (excluding packing material). information on lead free soldering the product cannot withstand a lead free soldering process. reflow or wave soldering is not allowed. hand soldering only. solder 1 pin on each side of the sensor and let it cool down for at least 1 minute before continuing note: "intentional content" is defined as any material demanding special attention is contained into the inquired product by these cases: 1. a case that the above material is added as a chemical composition into the inquired pr oduct intentionally in order to produce and maintain the required performance and function of the intended product 2. a case that the above material, which is used intentionally in the manufacturing process, is contained in or adhered to the inquired product. the following case is not treated as "intentional content": a case that the above material is contained as an impurity into raw materials or parts of the intended product. the impurity is defined as a substance that c annot be removed industrially, or it is produced at a process like chemical composing or reaction and it cannot be removed technically. table 18. chemical substances in star250 sensor chemical substance any intentional content if there is any intentional content, in which portion is it contained? lead no - cadmium no - mercury no - hexavalent chromium no - pbb (polybrominate d biphenyls) no - pbde (polybrominated diphenyl ethers) no - [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 23 of 24 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. ordering information part numbers evaluation kit for evaluating purposes an star250 evaluation kit is available. the star250 evaluation kit consists of a multifunctional digital board (memory, sequencer and ieee 1394 fire wire interface) and an analog image sensor board. visual basic software (under win 2000 or xp) allows the grabbing and display of images from the sensor. all acquired images can be stored in different file formats (8 or 16-bit). all setting can be adjusted on t he fly to evaluate the sensors specs. default register values can be loaded to start the software in a desired state. please contact us for more information. all products and company names mentioned in this document may be the trademarks of their respective holders fillfactory part number cypress part number package glass lid mono/color star250 cyis1sm0250aa-hqc 84-pin jlcc quartz fused silica mono star250bk7 cyis1sm0250aa-hhc 84-pin jlcc bk7g18 mono evaluation system CYIS1SM0250-EVAL 84-pin jlcc quartz fused silica mono [+] feedback [+] feedback
cyis1sm0250-aa document number: 38-05713 rev. *b page 24 of 24 document history page document title: cyis1sm0250-aa star250 250k pixel radiation hard cmos image sensor document number: 38-05713 rev. ecn no. issue date orig. of change description of change ** 310213 see ecn s il origination *a 603159 see ecn qgs convert ed to framemaker format *b 649360 see ecn fpw title update + package spec label [+] feedback [+] feedback

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