View HMC704LP4E_2677885.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HMC704LP4E v02.0411 8 gh z fractional- n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls - s mt 5 - 1 t ypical a pplications the HMC704LP4E is ideal for: ? microwave point-to-point radios ? base s tations for mobile radio (g s m, pc s , dc s , cdma, wcdma) ? wireless lans, wimax ? communications test equipment ? catv equipment ? automotive f unctional diagram f eatures wide band: dc - 8 ghz rf input, 4 ghz 19-bit prescaler industry leading phase noise & s purious: -112 dbc/hz @ 8 ghz fractional, 50 khz offset figure of merit -230 dbc/hz fractional mode -233 dbc/hz integer mode 100 mhz pfd high pfd rate: 100 mhz 24 lead 4x4 mm s mt package: 16 mm 2 general description the HMC704LP4E has been designed for the best phase noise and lowest spurious content possible in an integrated pll. fabricated in a s ige bicmo s process, this fractional-n pll con sists of a very low noise digital phase detector, vco divider, reference divider and a precision controlled charge pump. ultra low in-close phase noise and low spurious allows wide loop bandwidths for faster fre quency hopping and low micro-phonics. exact frequency mode with 24-bit fractional mod ulator provides the ability to generate fractional frequencies with zero frequency error, an important feature for digital pre-distortion systems. the serial interface offers read back capability and is compatible with a wide variety of protocols.
pll s - s mt 5 - 2 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 1. electrical specifcations vddcp, vppcp = 5v+/-4%; rvdd, avdd, dvdd, vddpd, vccp s = 3.3v +/-10%; agnd = dgnd = 0v parameter conditions min. typ. max. units rf input characteri s tic s [6][7] rf input frequency range [1] dc 8000 mhz prescaler input freq range [1] dc 4000 mhz power range [13] -15 -7 -3 dbm impedance 100 ohms each leg||3pf 100||3 ohms||pf ref input characteri s tic s frequency range (3.3v) [1][8] dc 50 350 mhz power from 50ohm s ource [12] 6 dbm impedance 100||3 ohms||pf ref divider range (14 bit) 1 16,383 pha s e detector rate [1][12] integer mode dc 50 115 mhz fractional mode a dc 50 80 mhz fractional mode b dc 50 100 mhz charge pump output current 20ua s teps 0.02 2.5 ma power s upplie s rvdd, avdd, vccp s , vcchf, vccpd - analog supply all should be equal 3.0 3.3 3.5 v dvdd - digital supply 3.0 3.3 3.5 v vddl s , vppcp charge pump vddl s , vppcp must be equal 4.7 5.0 5.2 v 3.3v - current consumption [9] 38 52 58 ma 5v - current consumption all modes 2 6 7 ma power down current [10] 100 ua bia s reference voltage pin 12. measured with 10gohm meter 1.880 1.920 1.960 v pha s e noi s e flicker figure of merit (fom)[2] -266 dbc/hz floor figure of merit [11] integer hik mode integer normal mode fractional hik mode [3] fractional normal mode [3] -236 -232 -232 -228 -233 -230 -230 -227 -231 -228 -227 -225 dbc/hz dbc/hz dbc/hz dbc/hz flicker noise at f offset pn fick = flicker fom +20log(f vco ) -10log(f offset ) dbc/hz phase noise floor at f vco with f pd pn foor = floor fom + 10log(f pd ) +20log(f vco /f pd ) dbc/hz total phase noise vs f offset , f vco, f pd pn = 10log(10 (pnfick /10) + 10 (pnfoor /10) ) dbc/hz jitter ss b 100hz to 50khz 50 fs s puriou s [4][5] integer boundary s purs @~8ghz offsets less than loop band - width, f pd = 50mhz -60 -52 dbc logic input s
plls - s mt 5 - 3 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com parameter conditions min. typ. max. units vih input high voltage vdd-0.4 v vil input low voltage 0.4 v logic output s voh output high voltage vdd-0.4 v vol output low voltage 0.4 v digital output driver delay s ck to digital output delay 1.7nsec with a 3pf load 0.5ns+0.2ns/pf 8.2ns+0.2ns/pf ns ns rf divider 8ghz integer mode 19 bit , even values only 32 1,048,574 rf divider 4ghz integer mode 19 bit , all values 16 524,287 rf divider 8ghz fractional mode 19 bit , even values only 40 1,048,566 rf divider 4ghz fractional mode 19 bit , all values 20 524,283 [1] frequency is guaranteed across process, voltage and temperature from -40 0 c to 85 0 c. [2] with high charge-pump current, +12dbm 100mhz sine reference [3] fractional fom degrades about 3db/octave for prescaler input frequencies below 2ghz [4] using 50mhz reference with vco tuned to within one loop bandwidth of an integer multiple of the pd frequency. larger offsets produce better results. s ee the s purious performance section for more information. [5] measured with the HMC704LP4E evaluation board. board design and isolation will affect performance. [6] internal divide-by-2 must be enabled for frequencies >4ghz [7] at low rf frequency, rise and fall times should be less than 1ns to maintain performance [8] s lew rate of greater or equal to 0.5ns/v [9] current consumption depends upon operating mode and frequency of the vco [10] reference input disconnected [11] min/max versus temperature and supply, under typical reference & frequencies & rf power levels [12] s lew > 0.5v/ns is recommended , see table 6 for more information [13] operable with reduced spectral performance up to +7 dbm t able 1. electrical specifcations (continued)
pll s - s mt 5 - 4 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t yp ica l pe rfor m anc e c h aract e ri s tic s unless otherwise specifed, plots are measured with a 50 mhz pd rate, vco near 8 ghz. the operating modes in the following plots refer to integer (int), fractional modes a and b, hikcp (hik) or active (act) confgurations. f igure 1. f loor fo m vs. mode and t emp f igure 2. f licker fo m vs. mode and t emp f igure 3. f loor fo m vs. o utput f requency and mode f igure 4. f licker fo m vs. o utput f requency and mode -236 -234 -232 -230 -228 -226 int frac mode a hik int hik frac mode a -40 0 40 80 floor fom temperature (c) -270 -269 -268 -267 -266 -265 -264 -263 int frac mode a hik int hik frac mode a -40 -20 0 20 40 60 80 flicker fom temperature (c) -235 -230 -225 -220 -215 1 2 4 8 int frac mode a frac mode b hik int hik frac mode a hik frac mode b frequency (ghz) floor fom hik frac mode b hik frac int int hik frac mode a frac mode b frac mode a -268 -267 -266 -265 -264 -263 1 2 4 8 int frac mode a frac mode b hik frac mode a hik frac mode b frequency (ghz) flicker fom int hik frac mode a frac mode b frac mode a hik frac mode b
plls - s mt 5 - 5 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com f igure 7. f licker fo m vs. c harge pump c urrent f igure 8. f licker fo m vs. c p voltage, c p c urrent = 2.5m a f igure 9. f licker fo m vs. c p voltage, hikcp + c p c urrent = 6m a f igure 10. f loor fo m vs. c p voltage, c p c urrent = 2.5m a -270 -268 -266 -264 0 1 2 3 4 5 cp voltage (v) flicker fom -230 -228 -226 -224 -222 -220 -218 0 1 2 3 4 5 cp voltage (v) floor fom -270 -265 -260 -255 -250 -245 0 0.5 1 1.5 2 2.5 3 cp current (ma) flicker fom -270 -268 -266 -264 -262 -260 -258 -256 0 1 2 3 4 5 cp voltage (v) flicker fom -234 -232 -230 -228 -226 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 int mode a hik int hik mode a reference power (dbm) floor fom -272 -271 -270 -269 -268 -267 -266 -4 -2 0 2 4 6 8 10 12 int frac mode a hik int hik frac mode a reference power (dbm) flicker fom f igure 5. f loor fo m vs. r eference power and mode f igure 6. f licker fo m vs. r eference power and mode
pll s - s mt 5 - 6 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com f igure 11. f loor fo m vs. c p voltage, hikcp+ c p c urrent = 6m a f igure 12. f loor fo m vs. c p c urrent f igure 14. spur performance vs. f requency o ffset [2] f igure 15. worst c ase i nteger boundary spur n ear 8 ghz f igure 16. worst c ase i nteger boundary spur n ear 4 ghz f igure 13. spur performance vs. f requency o ffset [1] -85 -80 -75 -70 -65 -60 -55 -50 4150 4200 4250 4300 4350 4400 4450 4500 4550 4600 mode a mode b hik mode a hik mode b frequency (mhz) worst spur (dbc) mode a mode b hik mode b hik mode a -234 -232 -230 -228 -226 -224 0 1 2 3 4 5 cp voltage (v) floor fom -230 -225 -220 -215 -210 -205 -200 0 0.5 1 1.5 2 2.5 3 cp current (ma) floor fom -90 -85 -80 -75 -70 -65 -60 -55 -50 1 10 100 1000 worst spur (dbc) frequency offset (khz) -90 -85 -80 -75 -70 -65 -60 -55 1 10 100 1000 worst spur (dbc) frequency offset (khz) -75 -70 -65 -60 -55 -50 8450 8550 8650 8750 8850 8950 mode a mode b hik mode a hik mode b frequency (mhz) worst spur (dbc) mode a hik mode a hik mode b mode b [1] cp current = 2.5 ma, loop filter = 20 khz, phase margin = 78 [2] hi k, cp current = 6 ma, loop filter bw = 45 khz, phase margin = 78
plls - s mt 5 - 7 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com f igure 19. modelled vs. measured phase n oise, f ractional mode [3] f igure 18. modelled vs. measured phase n oise [4] f igure 17. i nteger boundary spur vs. c p o ffset [3] f igure 22. i nteger boundary spurious at 8 ghz + 10 khz vs. rf power [3] -180 -160 -140 -120 -100 -80 100 1000 10 4 10 5 10 6 10 7 10 8 int ff fb act int hik mode a act fb predicted act int predicted hik mode a offset (hz) phase noise (dbc) -234 -233 -232 -231 -230 -229 -228 -227 -24 -21 -18 -15 -12 -9 -6 -3 0 3 hik int hik mode a hik mode b rf power (dbm) floor fom -268 -267.5 -267 -266.5 -266 -24 -21 -18 -15 -12 -9 -6 -3 0 3 hik int hik mode a hik mode b rf power (dbm) flicker fom -75 -70 -65 -60 -55 -50 -15 -12 -9 -6 -3 0 3 5khz 10khz rf power (dbm) spur (dbc) -65 -60 -55 -50 -45 -40 -35 -30 -25 -600 -400 -200 0 200 400 600 mode a mode b hik mode a hik mode b offset current (ua) worst spur (dbc) recommended operating region hik mode b mode b hik mode a mode a f igure 20. f loor fo m n ear 8 ghz vs. rf power and mode -180 -160 -140 -120 -100 -80 100 1000 10 4 10 5 10 6 10 7 10 8 hik int predicted hik int offset (hz) phase noise (dbc) f igure 21. f licker fo m n ear 8 ghz vs. rf power and mode [3] vco near 8.6 ghz, prescalar = vco/2 [4] active fractional a mode (prescalar @ 4 ghz + 5 khz)
pll s - s mt 5 - 8 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 2. pin descriptions pin number function description 1 s di main s erial port data input 2 s ck main s erial port clock input 3 a s en auxiliary s erial port enable output 4 ld_ s do lock detect output or s erial data output or gpo, s electable 5 vcoin complementary input to the rf prescaler. for s ingle ended operation must be decoupled to the ground plane with a ceramic bypass capacitor, typically 100 pf. dc bias of 2.0v is generated internally 6 vcoip input to the rf prescaler. s mall signal input from external vco. dc bias of 2.0v is generated internally. external ac coupling required 7 vcchf power supply pin for the rf s ection. nominal +3.3 v. a decoupling capacitor to the ground plane should be placed as close as possible to this pin. see eval board layout. 8 n/c no connect 9 vccp s power s upply prescaler, nominal +3.3v 10 n/c no connect 11 vccpd power supply for the phase detector, nominal +3.3v 12 bia s external bypass decoupling for precision bias circuits, 1.920v +/-20mv note: bia s ref voltage cannot drive an external load. must be measured with 10gohm meter such as agilent 34410a, normal 10mohm dvm will read erroneously. 13 n/c no connect 14 avdd power supply for analog bias generation, nominal +3.3v 15 vppcp power supply for charge pump, nominal +5v 16 cp charge pump output. 17 vddl s power s upply for charge pump digital section, nominal +5v 18 rvdd ref path supply, nominal +3.3v 19 xrefp reference input 20 a s ck auxiliary s erial port clock output 21 a s d auxiliary s erial port data output 22 dvdd digital supply, nominal +3.3v 23 cen hardware chip enable 24 s en main s erial port latch enable input
plls - s mt 5 - 9 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 3. a bsolute maximum r atings parameter rating avdd or dvdd to gnd -0.3v to +3.6v avdd to dvdd -0.5v to +0.5v vddl s , vppcp -0.3v to +5.2v vcoin, vcoip s ingle ended dc vcchf-0.2v vcoin, vcoip differential dc 5.2v vcoin, vcoip s ingle ended ac 50ohm +7 dbm vcoin, vcoip differential ac 50ohm +13 dbm digital load 1kohm min digital input 1.4v to 1.7v min rise time 20nsec digital input voltage range -0.25 to dvdd+0,5v thermal resistance (jxn to gnd paddle) 25 0 c/w operating temperature range -40 o c to +85 o c s torage temperature range -65 o c to + 125 o c maximum junction temperature +125 o c refow s oldering peak temperature 260 o c time at peak temperature 40sec e s d s ensitivity hbm class 1b s tresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
pll s - s mt 5 - 10 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com o utline drawing t able 4. package i nformation part number package body material lead finish m s l rating package marking [1] HMC704LP4E roh s -compliant low s tress injection molded plastic 100% matte s n m s l1 [2] h704 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260c note s : [1] package body material: low s tre ss injection molded pla s tic s ilica and s ilicon impregnated. [2] lead and ground paddle material: copper alloy. [3] lead and ground paddle plating: 100% matte tin. [4] dimen s ion s are in inche s [millimeter s ]. [5] lead s pacing tolerance i s non-cumulative. [6] pad burr length s hall be 0.15mm max. pad burr height s hall be 0.05mm max. [7] package warp s hall not exceed 0.05mm [8] all ground lead s and ground paddle mu s t be s oldered to pcb rf ground. [9] refer to hittite application note for s ugge s ted pcb land pattern.
plls - s mt 5 - 11 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com evaluation p c b the circuit board used in the application should use rf circuit design techniques. s ignal lines should have 50 ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request. t able 5. evaluation o rder i nformation item contents part number evaluation pcb only HMC704LP4E evaluation pcb 130933-HMC704LP4E evaluation kit HMC704LP4E evaluation pcb u s b interface board 6 u s b a male to u s b b female cable cd rom (contains user manual, evaluation pcb s chematic, evaluation s oftware, hittite pll design s oftware) 129856-HMC704LP4E
pll s - s mt 5 - 12 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com evaluation p c b block diagram evaluation p c b schematic to view evaluation pcb s chematic please visit www.hittite.com and choose HMC704LP4E from s earch by part number pull down menu to view the product splash page.
plls - s mt 5 - 13 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t heory of o peration the pll consists of the following functional blocks: 1. reference path input buffer and r divider 2. vco path input buffer, rf divide-by-2 and multi-modulus n divider 3. fractional modulator 4. phase detector 5. charge pump 6. main s erial port 7. lock detect and register control 8. auxiliary output s erial port 9. power on reset circuit external v co the pll charge pump can operate with the charge pump supply as high as 5.2 volts. the charge pump output at the varactor tuning port, normally can maintain low noise performance to within 500mv of ground or 800mv of the upper supply voltage. high performance low spurious o peration the HMC704LP4E has been designed for the best phase noise and low spurious content possible in an integrated pll. s purious signals in a pll can occur in any mode of operation and can come from a number of sources. f igure of merit n oise f loor and f licker n oise models the phase noise of an ideal phase locked oscillator is dependent upon a number of factors: a. frequency of the vco, and the phase detector b. vco s ensitivity, kvco, vco and reference oscillator phase noise profles c. charge pump current, loop filter and loop bandwidth d. mode of operation: integer, fractional modulator style the contributions of the pll to the output phase noise can be characterized in terms of a figure of merit (fom) for both the pll noise foor and the pll ficker (1/f) noise regions, as follows: figure 23. synthesizer with external vco
pll s - s mt 5 - 14 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com where: p 2 phase noise contribution of the pll (rads 2 /hz) f o frequency of the vco (hz) f pd frequency of the phase detector (hz) f m frequency offset from the carrier (hz) f po figure of merit (fom) for the phase noise foor f p1 figure of merit (fom) for the ficker noise region pll noise floor pll 1/f flicker noise vco 1/f 2 noise vco 1/f 3 noise typical closed loop phase noise log offset frequency (f m ) phase noise (dbc/hz) closed loop bandwidth figure 24. figures of merit noise models for the pll if the free running phase noise of the vco is known, it may also be represented by a fgure of merit for both 1/f 2 , f v2 , and the 1/f 3 , f v3 , regions. the figures of merit are essentially normalized noise parameters for both the pll and vco that can allow quick esti - mates of the performance levels of the pll at the required vco, offset and phase detector fre quency. normally, the pll ic noise dominates inside the closed loop bandwidth of the pll, and the vco dominates outside the loop band - width at offsets far from the carrier. hence a quick estimate of the closed loop performance of the pll can be made by setting the loop bandwidth equal to the frequency where the pll and free running phase noise are equal. the figure of merit is also useful in estimating the noise parameters to be entered into a closed loop design tool such as hittite pll design, which can give a much more accurate estimate of the closed loop phase noise and pll loop flter component values. given an optimum loop design, the approximate closed loop performance is simply given by the minimum of the pll and vco noise contributions. ( ) 0 1 2 2 0 0 2 0 , , d p p p m pd m f f f f f f f f f f = + pll phase noise contribution (eq 1) (eq 2) ( ) 3 2 2 0 2 0 0 2 3 , m m m f f f f f f f f = + vco phase noise contribution
plls - s mt 5 - 15 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com ( ) 2 2 2 min , p = an example of the use of the fom values to make a quick estimate of pll performance: estimate the phase noise of an 8ghz closed loop pll with a 100mhz reference operating in fractional mode b with the vco operating at 8ghz and the vco divide by 2 port driving the pll at 4ghz. assume an hmc509 vco has free running phase noise in the 1/f 2 region at 1mhz offset of -135dbc/hz and phase noise in the 1/f 3 region at 1khz offset of -60dbc/hz. f v1_db = -135 free running vco pn at 1mhz offset +20*log10(1e6) pnoise normalized to 1hz offset -20*log10(8e9) pnoise normalized to 1hz carrier = -213.1 dbc/hz at 1hz vco fom f v3 _db = -60 free running vco pn at 1khz offset +30*log10(1e3) pnoise normalized to 1hz offset -20*log10(8e9) pnoise normalized to 1hz carrier = -168 dbc/hz at 1hz vco flicker fom we can see from figure 3 and figure 4 respectively that the pll fom foor and fom ficker parameters in fractional mode a: fpo_db = -227 dbc/hz at 1hz fp1_db = -266 dbc/hz at 1hz each of the figure of merit equations result in straight lines on a log-frequency plot. we can see in the example below the resulting pll foor at 8ghz = f po_db +20log10(fvco) -10log10(fpd) = -227+198 -80 = -109 dbc/hz pll flicker at 1khz = f p1_db +20log10(fvco)-10log10(fm) = -266 +198-30 = -98 dbc/hz vco at 1mhz = f v1_db +20log10(fvco)-20log10(fm)= -213 +198-120 = -135dbc/hz vco ficker at 1khz = f v3_db +20log10(fvco)-30log10(fm)= -168 +198-90 = -60dbc/hz these four values help to visualize the main contributors to phase noise in the closed loop pll. each falls on a linear line on the log-frequency phase noise plot shown in figure 25 . (eq 3) pll-v co n oise -180 -160 -140 -120 -100 -80 -60 -40 -20 100 1000 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) frequency offset (hz) pll at 1 khz vco at 1 khz pll floor vco at 1 mhz figure 25. example of figure of merit models at 8 ghz
pll s - s mt 5 - 16 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com it should be noted that actual phase noise near the corner frequency of the loop bandwidth is affected by loop parame - ters and one should use a more complete design tool such as hittite pll design for better esti mates of the phase noise performance. noise models for each of the components in hittite pll design can be derived from the fom equations or can be provided by hittite applications engineering. spurious performance i nteger o peration the vco always operates at an integer multiple of the pd frequency in an integer pll. in general spurious signals originating from an integer pll can only occur at multiples of the pd frequency. these unwanted outputs are often sim - ply referred to as reference sidebands. s purs unrelated to the reference frequency must originate from outside sources. external spurious sources can modu - late the vco indirectly through power supplies, ground, or output ports, or bypass the loop flter due to poor isolation of the flter. it can also simply add to the output of the pll. the HMC704LP4E has been designed and tested for ultra-low spurious performance. reference spuri ous levels are typically below -100dbc with a well designed board layout. a regulator with low noise and high power supply rejection, such as the hmc860lp3e, is recommended to minimize external spurious sources. reference spurious levels of below -100dbc require superb board isolation of power supplies, isolation of the vco from the digital switching of the pll and isolation of the vco load from the pll. typical board layout, regulator design, demo boards and application information are available for very low spurious operation. operation with lower levels of isola - tion in the application circuit board, from those rec ommended by hittite, can result in higher spurious levels. of course, if the application environment contains other interfering frequencies unrelated to the pd fre quency, and if the application isolation from the board layout and regulation are insufficient, then the unwanted interfering frequencies will mix with the desired pll output and cause additional spurs. the level of these spurs is dependant upon isolation and supply regulation or rejection (p s rr). f ractional o peration unlike an integer pll, spurious signals in a fractional pll can occur due to the fact that the vco operates at frequen - cies unrelated to the pd frequency. hence intermodulation of the vco and the pd harmonics can cause spurious side - bands. s purious emissions are largest when the vco operates very close to an integer multiple of the pd. when the vco operates exactly at a harmonic of the pd then, no in-close mixing products are present. interference is always present at multiples of the pd frequency, f pd , and the vco frequency, f vco . if the fractional mode of operation is used, the difference, , between the vco frequency and the nearest har monic of the reference, will cre - ate what are referred to as integer boundary spurs. depending upon the mode of operation of the pll, higher order, lower power spurs may also occur at multiples of integer fractions (sub-harmonics) of the pd frequency. that is, frac - tional vco frequencies which are near nf pd + f pd d/m, where n, d and m are all integers and d4 spurs are very small or unmeasurable. the worst case, in fractional mode, is when d=0, and the vco frequency is offset from nf pd by less than the loop band - width. this is the in-band fractional boundary case.
plls - s mt 5 - 17 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com nf pd (n+1)f pd integer boundary f vco integer boundary n = integer d = 0 m = 1 = 1st order < loop bandwidth 1st order integer boundary spur (n+1)f pd f vco integer boundary n = integer d = 1 m = 2 = 2nd order < loop bandwidth 2nd order spur 2 2 integer boundary figure 26. fractional spurious example (n+1/2)f pd (n+1/2)f pd nf pd characterization of the levels and orders of these products is not unlike a mixer spur chart. exact levels of the products are dependent upon isolation of the various pll parts. hittite can offer guidance about expected levels of spurious with our pll and vco application boards. regulators with high power supply rejection ratios (p s rr) are recommended, especially in noisy applications. when operating in fractional mode, charge pump and phase detector linearity is of paramount importance. any non- linearity degrades phase noise and spurious performance. phase detector linearity degrades when the phase error is very small and is operating back and forth between reference lead and vco lead. to mitigate these non-linearities in fractional mode it is critical to operate the phase detector with some fnite phase offset such that either the reference or vco always leads. to provide a fnite phase error, extra current sources can be enabled which provide a constant dc current path to vdd (vco leads always) or ground (reference leads always). these current sources are called charge pump offset and they are controlled via reg 09h . the time offset at the phase detector should be ~2.5ns + 4t ps , where t ps is the rf period at the fractional prescaler input in nanoseconds (ie. after the optional fxed divide by 2). the spe - cifc level of charge pump offset current is determined by this time offset, the comparison frequency and the charge pump current and can be calculated from: operation with charge pump offset infuences the required confguration of the lock detect function. refer to the de - scription of pd window based lock detect later in this document. note that this calculation can be performed for the center frequency of the vco, and does not need refnement for small differences (<25%) in center frequencies. another factor in the spectral performance in fractional mode is the choice of the delta- s igma modulator mode. mode a can offer better in-band spectral performance (inside the loop bandwidth) while mode b offers better out of band per - formance. s ee reg 06h [3:2] for d s m mode selection. finally, all fractional plls cre ate fractional spurs at some level. hittite offers the lowest level fractional spurious in the indus try in an integrated solution. ( ) ( ) 9 required cp offset ( a) = 2.5 10 4 (sec) ( ) ( ) ps comparison cp t f hz i a ? + (eq 4)
pll s - s mt 5 - 18 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com r eference i nput stage the reference buffer provides the path from an external reference source (generally crystal based) to the r divider, and eventually to the phase detector. the buffer has two modes of operation. high gain (recommended below 200mhz), and high frequency, for 200 to 350mhz operation. the buffer is internally dc biased, with 100 ohm internal termina - tion. for 50 ohm match, an external 100 ohm resistance to ground should be added, followed by an ac coupling ca - pacitance (impedance < 1 ohm), then to the xrefp pin of the part. at low frequencies, a relatively square reference is recommended to keep the input slew rate high. at higher frequen - cies, a square or sinusoid can be used. the following table shows the recommended operating regions for different reference frequencies. if operating outside these regions the part will normally still operate, but with degraded perfor - mance. minimum pulse width at the reference buffer input is 2.5ns. for best spur performance when r = 1, the pulse width should be (2.5ns + 8tps), where tps is the period of the vco at the prescaler input. when r > 1 minimum pulse width is 2.5ns. t able 6. r eference sensitivity t able s quare input s inusoidal input frequency (mhz) s lew > 0.5v/ns recommended s wing (vpp) recommended power range (dbm) recommended min max recommended min max < 10 yes 0.6 2.5 x x x 10 yes 0.6 2.5 x x x 25 yes 0.6 2.5 ok 8 15 50 yes 0.6 2.5 yes 6 15 100 yes 0.6 2.5 yes 5 15 150 ok 0.9 2.5 yes 4 12 200 ok 1.2 2.5 yes 3 8 200 to 350 x x x yes 1 5 10 note: for greater than 200mhz operation, use buffer in high frequency mode. reg[8] bit 21 = 1 input referred phase noise of the pll when operating at 50mhz is between -150 and -156dbc/hz at 10khz offset de - pending upon the mode of operation. the input reference signal should be 10db better than this foor to avoid deg - radation of the pll noise contribution. it should be noted that such low levels are only necessary if the pll is the domi - nant noise contributor and these levels are required for the system goals. figure 27. reference path input stage
plls - s mt 5 - 19 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com r ef path r divider the reference path r divider is based on a 14 bit counter and can divide input signals of up to 350mhz input by values from 1 to 16,383 and is controlled by reg 02h [13:0]. the reference divider output may be viewed in test mode on the ld_ s do pin, by setting reg 0fh [4:0] = 9d. rf path the rf path is shown in figure 28 . this path features a low noise 8ghz rf input buffer followed by an 8ghz rf divide- by-2 with a selectable bypass. if the vco input is below 4ghz the rf divide-by-2 should be by-passed for reduced power consumption and improved performance in fractional mode. the rf divide-by-2 is followed by the n divider, a 19 bit divider that can operate in either integer or fractional mode with up to 4ghz inputs. finally the n divider is followed by the phase detector (pd), which has two inputs, the rf path from the vco (v) and the reference path (r) from the crys - tal. the pd can operate at speeds up to 80mhz in fractional mode a, 100mhz in fractional mode b and 115mhz in inte - ger mode. rf i nput stage the rf input stage provides the path from the external vco to the phase detector via the rf or n divider. the rf in - put path is rated to operate up to 8ghz across all conditions. the rf input stage is a differential common emitter stage with internal dc bias, and is protected by e s d diodes as shown in figure 29 . this input is not matched to 50 ohms. a 50 ohm resistor placed across the inputs can be used if desired. in most applications the input is used single-ended into either the vcoip or vcoin pin with the other input connected to ground through a dc blocking capacitor. the preferred input level for best spectral performance is -10dbm nominally. figure 29. rf input stage figure 28. rf path rf buffer /2 or 8ghz 8ghz 4ghz bypass 19 bit /n pd 80mhz/100mhz fractional 115mhz integer v r ref path sel control vcoip vcoin rf divide by 2 n divider phase detector cp up dn cp vppcp charge pump
pll s - s mt 5 - 20 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com rf path n divider the main rf path n divider is capable of divide ratios anywhere between 2 19 -1 (524,287) and 16 . this divider for ex - ample could divide a 4ghz input to a pd frequency anywhere between its maximum output limit of 115mhz to as low as 7.6khz. the n divider output may be viewed in test mode on ld_ s do by set ting reg 0fh [4:0] = 10d. when operating in fractional mode the n divider can change by up to +/-4 from the average value. hence the selected divide ratio in fractional mode is restricted to values between 2 19 -5 (524,283) and 20. if the vco input is above 4ghz then the 8ghz fxed rf divide-by-2 should be used, reg 08h [19] = 1. in this case the total division range is restricted to even numbers over the range 2*(2 19 -5) (1,048,566) to 40. c harge pump and phase detector the phase detector or pd has two inputs, one from the reference path divider and one from the rf path divider. when in lock these two inputs are at the same average frequency and are fxed at a constant aver age phase offset with re - spect to each other. we refer to the frequency of operation of the pd as f pd . most formula related to step size, delta-sig - ma modulation, timers etc., are functions of the operating frequency of the pd, f pd is sometimes referred to as the com - parison frequency of the pd. the pd compares the phase of the rf path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. the out put current varies in a linear fashion over nearly 2 radians (360) of input phase difference. phase detector and c harge pump f unctions phase detector register reg 08h allows manual access to control special phase detector features. reg 0bh [2:0] allows fne tuning of the pd reset path delay. this adjustment can be used to improve perfor mance at very high pd rates. most often this register is set to the recommended value only. reg 06h [5] and [6] enables the pd up and dn outputs respectively. disabling prevents the charge pump from pump - ing up or down respectively and effectively tri-states the charge pump while leaving all other functions operating inter - nally. cp force up reg 08h [9] and cp force dn reg 00h [10] allows the charge pump to be forced up or down respec - tively. this will force the vco to the ends of the tuning range which can be useful for testing of the vco. pd force mid reg 0bh [11] will disable the charge pump current sources and place a voltage source on the loop flter at approximately vppcp/2. if a passive flter is used this will set the vco to the mid-voltage tun ing point which can be useful for testing of the vco. reg 0bh [21:7] control other aspects of the phase detector operation and should be set to recommended values. pll jitter the standard deviation of the arrival time of the vco signal, or the jitter, may be estimated with a simple approximation if we assume that the locked vco has a constant phase noise, ( ) 2 0 f , at offsets less than the loop 3db bandwidth and a 20db per decade roll off at greater offsets. the simple locked vco phase noise approximation is shown on the left of figure 30 .
plls - s mt 5 - 21 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com with this simplifcation the total integrated vco phase noise, 2 , in rads 2 is given by where ( ) 2 0 f is the single sideband phase noise in rads 2 /hz inside the loop bandwidth, and b is the 3db corner frequency of the closed loop pll the integrated phase noise at the phase detector, , is just scaled by n 2 ie. the rms phase jitter of the vco ( ) in rads, is just the square root of the phase noise integral. s ince the simple integral of (eq 5) is just a product of constants, we can easily do the integral in the log domain. for example if the phase noise inside the loop is -110dbc/hz at 10khz offset and the loop band width is 100khz, and the di - vision ratio is 100, then the integrated phase noise at the phase detector, in db, is given by; , or equivalently 95 20 10 ? = = 18urads = 1 milli-degrees rms. while the phase noise reduces by a factor of 20logn after division to the reference, due to the increased period of the pd reference signal, the jitter is constant. the rms jitter from the phase noise is then given by 2 jpn pd pd t t = in this example if the pd reference was 50mhz, t pd = 20nsec, and hence t jpn = 56 femto-sec. pd window based lock detect lock detect enable reg 0bh [3]=1 is a global enable for all lock detect functions. the window based lock detect circuit effectively measures the difference between the arrival of the refer ence and the divided vco signals at the pd. the arrival time difference must consistently be less than the lock detect window length, to declare lock. either signal may arrive frst, only the difference in arrival times is counted. 2 f o ( ) f o b 2 f ( ) r 2 hz ? ? ? ? ? (t) rms figure 30. synthesizer phase noise and jitter (eq 5) ( ) 2 2 0 f b = 2 pd 2 2 2 pd n = v ( ) ( ) 2 2 2 0 10log = -110 + 5 +50 - 40 = -95 dbrads pd db f n = |
pll s - s mt 5 - 22 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a nalog window lock detect the lock detect window may be generated by either an analog circuit or a digital one-shot circuit. clearing reg 07h [6]=0 will result in a fxed, analog, nominal 10nsec window, as shown in figure 31 . the analog window cannot be used if the pd rate is very high, for example near 100mhz, or if the charge pump offset current results in an offset larger than 7nsec. for example a 25mhz pd rate with a 1ma charge pump setting ( reg 09h [6:0]= reg 09h [13:7]= 50d) and a - 400ua offset current reg 09h [20:14]=80d), would have a phase offset of about 400/1000 = 40% of the pd period or about 16nsec. in such an extreme case the divided vco would arrive 16ns after the pd ref erence, and would always arrive outside of the 10nsec lock detect window. in such a case the lock detect circuit would always read unlocked, even though the vco might be locked. the charge pump current, reference period, charge pump offset current, and lock detect win dow are related. digital window lock detect s etting reg 07h [6]=1 will result in a variable length lock detect window based upon the internal digital timer. the one shot timer period is controlled by reg 07h [11:10]. the resulting lock detect window period is then generated by the number of timer periods defned in reg 07h [9:7]. declaration of lock reg 07h [2:0] defnes the number of consecutive counts of the divided vco that must land inside the lock detect win - dow to declare lock. if for example we set reg 07h [2:0] =5 then the vco arrival would have to occur inside the widow 2048 times in a row to be declared locked, which would result in a lock detect flag high. a single occurrence outside of the window will result in an out of lock, i.e. lock detect flag low. once low, the lock detect flag will stay low until the lkd_wincnt_max = 2048 condition is met again. the lock detect flag status is always readable in reg 12h [1]. lock detect status is also output to the ld_ s do pin if reg 0fh [4:0]=1, reg 0fh [6]=1 and reg 0fh [7]=1. clearing reg 0fh [6]=0 will display the lock detect flag on ld_ s do except when a serial port read is requested, in which case the pin reverts temporarily to the s erial data out pin and returns to the lock detect flag after the read is completed. timing of the lock detect function is shown in fig - ure 31 and figure 32 . 50mhz pd vco with jitter lock detect window t window = 10nsec figure 31. normal lock detect window - integer mode, zero offset avg pha se offset ~ 0 avg pha se offset ~ 0 integer mode integer mode pha s e jitter pha s e jitter lock window
plls - s mt 5 - 23 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com lock detect o peration with phase o ffset when operating in fractional mode the linearity of the charge pump and phase detector are much more crit ical than in integer mode. the phase detector linearity degrades when operated with zero phase offset. hence in fractional mode it is necessary to offset the phase of the reference and vco at the phase detector. in such a case, for example with an offset delay, as shown in figure 32 , the vco arrival may always occur after the reference. the lock detect circuit win - dow may need to be adjusted to allow for the delay being used, if the delay is large. vco at pd with frac jitter lock detect window t window ~ +10nsec figure 32. lock detect window - fractional mode with offset ref pha s e arrival fractional mode vco arrival di s tribution at pd pha s e jitter lock window avg vco pha se offset avg pha se offset fractional mode avg vco pha se offset ref pha s e arrival avg pha se offset at pd in integer mode, 0 offset is recommended. in fractional mode, the time offset should be set to ~ 2.5ns + 4tps, where tps is the rf period at the fractional prescaler input (i.e. after the optional fxed divide by 2). refer to the fractional opera - tion section for further details about calculating charge pump offset currents digital lock detect with digital window example typical digital lock detect window widths are shown in table 7 . lock detect windows typically vary +/-10% vs voltage and +/-15% over -40c to +85c. t able 7. t ypical digital lock detect window ld timer speed reg07[11:10] digital lock detect window nominal value +/-25% (nsec) fastest 00 6.5 8.0 11.0 17 29 53 100 195 01 7.0 8.9 12.8 21 36 68 130 255 10 7.1 9.2 13.3 22 38 72 138 272 s lowest 11 7.6 10.2 15.4 26 47 88 172 338 ld timer divider s etting reg07[9:7] 0 1 2 3 4 5 6 7 ld timer divider value 0.5 1 2 4 8 16 32 64 as an example if we operate in fractional mode, with a 50mhz pd, a 2700 mhz vco and a charge pump gain of 2ma ( reg 09h ), based on the previous example, we should set the dc phase offset near 2.5ns+4x370ps =4ns, or 20% of the 20ns reference period. it becomes a larger proportion with increasing f pd . the offset current is therefore 20% x 2ma=400ua. the polarity of the offset should be chosen so that the vco lags the reference for the most consistent results. for non-inverting /inverting loop flter confgurations, we recommend down/up offsets, respectively. reference signal
pll s - s mt 5 - 24 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com given a dc phase offset as described in the above example, when in lock, the divided vco will arrive at the pd about 4nsec after the divided reference. the lock detect window always starts on the arrival of the frst signal at the pd, in this case the reference. the lock detect win dow must be longer than 4ns+4tps and shorter than the period of the pd, in this example, 20nsec. a comfortable solution of 8.9ns with timer speed set at reg 07h [11:10]=1 and timer divider reg 07h [9:7]=1 works well for the example pd frequency and charge pump offset setting. tolerance on the window is +25% at +85c, -25% at -40c. here 8.9ns nominal window may extend by +25% at +85c to 11.1ns, which is fne for a pd period of 20ns. also the minimum window may shrink by 25% to 6.7ns at -40c, which again works well for the dc offset of 4.0ns (worst case instantaneous phase offset of 5.5ns). there is always a good solution for the lock detect window for a given operating point. the user should understand however that one solution does not ft all operating points. if charge pump offset or pd fre quency are changed signif - cantly then the lock detect window may need to be adjusted. c ycle slip prevention ( c sp) when changing frequency and the vco is not yet locked to the reference, the instantaneous frequencies of the two pd inputs are different, and the phase difference of the two inputs at the pd varies rapidly over a range much greater than +/-2 radians. s ince the gain of the pd varies linearly with phase up to +/-2, the gain of a conventional pd will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than 0 radians. the output current from the charge pump will cycle from maximum to minimum even though the vco has not yet reached its fnal frequency. the charge on the loop flter small cap may actually discharge slightly during the low gain portion of the cycle. this can make the vco frequency actually reverse temporarily during locking. this phenomenon is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically. cycle s lipping increases the time to lock to a value much greater than that predicted by normal small signal laplace analysis. the pll pd features an ability to reduce cycle slipping during acquisition. the cycle s lip preven tion (c s p) feature in - creases the pd gain during large phase errors. the specifc phase error that triggers the momentary increase in pd gain is set via reg 0bh [8:7]. ref at pd vco at pd ld window pd period 20ns vco offset 4ns ld window 8.9ns+/-25% +window margin -window margin figure 33. lock detect window example with 50mhz pd and 4ns vco offset
plls - s mt 5 - 25 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com pd polarity reg 0bh [4]=0 sets the phase detector polarity for use with a passive loop flter together with a vco with a positive tuning slope (increasing tuning voltage increases vco frequency). reg 0bh [4]=1 inverts the phase detector polarity. this is most often used if an inverting op-amp is used in an active loop flter together with a vco with a positive tuning slope. c harge pump t ri-state reg 0bh [5]= reg 0bh [6]=0 tri-states the charge pump. this effectively freezes charge on the loop flter and allows the vco to run open loop. c harge pump gain reg 09h [6:0] and reg 09h [13:7] program current gain settings for the charge pump. pump ranges can be set from 0ua to 2.54ma in 20ua steps. charge pump gain affects the loop bandwidth. the product of vco gain (k vco ) and charge pump gain (k cp ) can be held constant for vcos that have a wide ranging k vco by adjusting the charge pump gain. this compensation helps to keep the loop bandwidth constant. in addition to the normal cp current as described above, there is also an extra output source of current that offers im - proved noise performance. hik cp provides an output current that is proportional to the loop flter voltage. this being the case hik cp should only be operated with active op-amp loop flters that defne the voltage as seen by the charge pump pin. with 2.5v as observed at the charge pump pin, the hik cp current is 3.5ma. there are several confgurations that could be used with the hik cp feature. for lowest noise, hik cp could be used with - out the normal charge pump current (the charge pump current would be set to 0). in this case, the loop flter would be designed with 3.5ma as the effective charge pump current. another possible confguration is to operate with both the hik cp and normal charge pump current sources. in this case the effective charge pump current would be 3.5ma + programmed normal charge pump current which could offer a maximum of 6ma. with passive loop flters the voltage seen by the charge pump pin will vary which would cause the hik cp current to vary widely. as such, hik cp should not be used on passive loop flter implementations. a simplifed diagram of the charge pump is shown in figure 34 . the current gain of the pump in amps/radian is equal to the gain setting of this register divided by 2. c harge pump o ffset reg 09h [20:14] controls the charge pump current offsets. reg 09h [21] and reg 09h [22] enable the up and dn offset currents respectively. normally only one is used at a time. as mentioned earlier charge pump offsets affect fractional mode linearity and the lock detect window selection.
pll s - s mt 5 - 26 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com vco path ref path up dn loop filter pd 0-2.54ma figure 34. charge pump gain and offset control - reg09h up 7 7 0-635ua 5uasteps offset up pump gain dn pump gain 20ua s teps 0-2.54ma 20ua s teps dn 0-635ua 5uasteps offset 7 7 f requency t uning the HMC704LP4E fractional-n pll can operate in either integer mode, or 3 different fractional modes. integer mode: delta s igma modulator is disabled., reg 06h [11]=0, reg 06h [7]=1 fractional modes: delta sigma modulator is enabled., reg 06h 11]=1, reg 06h [7]=0 mode a: provides better phase noise performance inside the loop bandwidth, worse outside; mode b : higher phase noise inside the loop bandwidth, better outside; exact frequency mode: must be in mode b. provides zero frequency error; frequency programming and mode control is described below. frequency of vco [ ] 24 2 2 2 d d xtal xtal frac vco frac f f n f n f f r r ? ? ? = + = + ? ? ? ? ? int int where n int integer division ratio, reg 03h , integer mode : an integer number between 16 and 2 19 -1 fractional mode : an integer number between 20 and 2 19 -5 n frac fractional part, a number from 0 to 2 24 -1, reg 04h d divide by 2 for operation > 4ghz, reg 08h [19] = 1, < 4ghz = 0 r reference path division ratio, a number from 1 to 2 14 , reg 02h f xtal frequency of the reference oscillator input f pd pd operating frequency, f xtal /r as an example for fractional operation at 2.3ghz + 2.98hz: f xtal = 50mhz r = 1 f ref = 50mhz n int = 46 n frac = 1 d= 0 6 6 0 24 50 10 50 10 1 2 46 2.3 2.98 1 1 2 vco f ghz hz ? ? ? = + = + ? ? ? ? ? (eq 6) (eq 7)
plls - s mt 5 - 27 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com in this example the output frequency of 2,300,000,002.98hz is achieved by programming the 16 bit binary value of 46d = 002eh = 0000 0000 0010 1110 into dsm_intg. s imilarly the 24 bit binary value of the fractional word is written into dsm_frac, 1d = 000 001h = 0000 0000 0000 0000 0000 0001 example 2: s et the output to 7.650 025 ghz using a 100mhz reference, r=2. here, output is greater than 4ghz, so we enable the internal divide by 2, d = 1. find the nearest integer value n int . n int = 76, 2f int = 7.600 000ghz this leaves the fractional part to be 2f frac =50.025mhz 24 24 6 6 2 2 2 50.025 10 8392802.3 2 2 100 10 frac frac d xtal r f n f ? ? ? ? = = = ? s ince n frac must be an integer number, we round it to 8,392,802, and the actual vco frequency will be 7,650,024,998.19 hz, an error of -1.81hz or about 2 parts in 2-10. here we program the 16 bit n int = reg 04h = 76d = 4ch = 0000 0000 0100 1100 and the 24 bit n frac = 8,392,802d = 801062h = 1000 0000 0001 0000 0110 0010 in addition to the above frequency programming words, the fractional mode must be enabled using the frac register. other d s m confguration registers should be set to the recommended values supplied with the product evaluation board or available from applications support. exact f requency mode the absolute frequency precision of a fractional frequency plls is normally limited by the number of bits in the frac - tional modulator. for example a 24 bit fractional modulator has frequency resolution set by the phase detector (pd ) comparison rate divided by 2 24 . in the case of a 50mhz pd rate, this would be approximately 2.98 hz, or 0.0596 ppm. in some applications it is necessary to have exact frequency steps, and even an error of 3hz cannot be tol erated. in some fractional plls it is necessary to shorten the length of the accumulator (the denominator or the modulus) to ac - commodate the exact period of the step size. the shortened accumula tor often leads to very high spurious levels at multiples of the channel spacing, f step = f pd /modulus. for example 200khz channel steps with a 10mhz pd rate re - quires a modulus of just 50. the hmc method achieves the exact frequency step size while using the full 24 bit modu - lus, thus achiev ing exact frequency steps with very low spurious and a high comparison rate, which maintains excellent phase noise. exact frequency steps can be achieved only when the pd rate and the desired frequency step size are related by an in - teger multiple. more precisely, the greatest common divisor, (gcd) of the pd rate and the desired frequency step size must be an integer, and that integer must be less than 2 14 -1 or 16,383. as an example suppose that we want to achieve: a. exact channel step size of f step = 100khz. b. reference crystal f xtal = 61.44mhz c. phase detector (pd) rate f pd =61.44mhz d. channel 1 frequency, f vco (ch1) = 2000.200 mhz (eq 8)
pll s - s mt 5 - 28 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com proceed as follows: a. calculate the gcd of the pd rate, f pd , and the step size, f step , gcd( 61.44mhz, 100khz) = f gcd = 20khz (same value for all channels) b. s et the exact frequency register value, reg 0ch = f pd /f gcd = 61.44mhz/20khz = 3072d = c00h (same value is used for all channels) c. calculate the integer register setting for the channel, reg 03h =n int = f vco /f pd = foor (2000.2mhz/61.44mhz) = 32d =20h (note: foor = round down to nearest integer). d. calculate the equivalent integer boundary frequency, f int = n int *f pd = 1966.080mhz. e. calculate the fractional register setting for the channel, reg 04h = n frac = 2 24 (f vco -f int )/f pd = ceiling(224*(2000.2-1966.08)/61.44) = 9317035d=8e2aabh. it is important that this parameter be rounded up (hence the ceiling function). the fractional value is programmed for each new channel. the integer value is only programmed initially and then only if the output crosses an integer boundary. seed r egister and a utoseed mode the start phase of the fractional modulator digital phase accumulator (dpa) may be set to one of four pos - sible default values via the seed register reg 06h [1:0]. if autoseed reg 06h[8] is set, then the pll will automatically reload the start phase from reg 06h [1:0] into the dpa every time a new fractional fre quency is selected. if autoseed is not set, then the pll will start new fractional frequencies with the value left in the dpa from the last frequency. hence the start phase will effectively be random. certain zero or binary seed values may cause spurious energy correlation at specifc frequencies. correlated spurs are advantageous only in very special cases where the spurious are known to be far out of band and are removed in the loop flter. for most cases a pseudo-random seed setting ( reg 06h [1:0] =2 or 3) is recom mended. further, since the autoseed always starts the accumulators at the same place, performance is repeatable if autoseed is used. reg 06h [1:0]=2 is recommended. power on r eset the HMC704LP4E features a hardware power on reset (por) on the digital supply dvdd. all chip reg isters will be reset to default states approximately 250us after power up of dvdd. once the supply is fully up, if the power supply then drops below 0.5v the digital portion will reset. power down mode hardware power down chip enable may be controlled from the hardware cen pin 23, or it may be controlled from the serial port. reg 01h [0] =1 assigns control to the cen pin. reg 01h [0] =0 assigns control to the serial port reg 01h [1]. for hardware test reasons or some special applications it is possible to force certain blocks to remain on inside the chip , even if the chip is disabled. s ee the register reg 01h description for more details. c hip i dentifcation version information may be read from the pll by reading the content of chip_id in reg 00h .
plls - s mt 5 - 29 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com general purpose o utput (gp o ) pin the pll features a general purpose output (gpo) on the ld_ s do pin. gpo registers are described in reg 0fh . the gpo is a fexible interface that supports a number of different functions and real time test waveforms. the phase noise performance at this output is poor and uncharacterized. the gpo output should not be toggling during normal operation otherwise spectral performance may degrade. to use the gpo in hmc s pi mode, bit reg 0fh [7] must be set to 1. external v co , 4.2v t uning, passive f ilter the HMC704LP4E is targeted for high performance applications with an external vco. the pll charge pump has been designed to work directly with vcos that can be tuned nominally over 1.0 to 4.0 volts on the varactor tuning port with a +5v charge pump supply voltage. s lightly wider ranges are pos sible with a +5.2v charge pump supply or with slightly degraded performance. hittite hitt-pll design soft ware is available to design passive loop flters driven directly from the pll charge pump. external v co , high voltage t uning, a ctive f ilter optionally an external op-amp may be used to support vcos requiring higher voltage tuning ranges. hittites hitt-pll design software is available to design active loop flters with external op-amps. various flter con fgurations are sup - ported. m ain se ria l p ort serial port modes of o peration the hmc pll-vco serial port interface can operate in two different modes of operation. a. hmc mode (hmc legacy mode) - s ingle slave per hmc s pi bus. b. open mode - up to 8 slaves per hmc s pi bus. the hmc5675alp4e only uses 5 bits of address space. both protocols support 5 bits of register address space. hmc mode can support up to 6 bits of register address but, is restricted to 5 bits when compatibility with open mode is offered. figure 35. synthesizer with active loop filter and conventional external vco
pll s - s mt 5 - 30 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com r egister 0 modes register 0 has a dedicated function in each mode. open mode allows wider compatibility with other manu facturers s pi protocols. t able 8. r egister 0 c omparison - single vs multi-user modes s ingle user hmc mode s ingle or multi-user open mode read chip id 24 bits chip id 24bits write s oft reset, general s trobes read address [4:0] s oft reset [5] general s trobes [24:6] serial port mode decision after power- o n r eset on power up, both types of modes are active and listening. all digital io must be low at power-up. a decision to select the desired s erial port mode (protocol) is made on the frst occurrence of s en or s clk , after which the s erial port mode is fxed and only changeable by a power down. a. if a rising edge on s en is detected frst hmc mode is selected. b. if a rising edge on s clk is detected frst open mode is selected. serial port hm c mode - single pll hmc mode (legacy mode) serial port operation can only address and communicate with a single pll, and is compat - ible with most hmc plls and plls with integrated vcos. the hmc mode protocol for the serial port is designed for a 4 wire interface with a fxed protocol featuring a. 1 read/write bit b. 6 address bits c. 24 data bits serial port o pen mode the s erial port open mode features: a. compatibility with general serial port protocols that use a shift and strobe approach to com - munication. b. compatible with hmc multi-chip solutions, useful to address multiple chips of various types from a single serial port bus. the hmc open mode protocol has the following general features: a. 3 bit chip address, can address up to 8 devices connected to the serial bus b. wide compatibility with multiple protocols from multiple vendors c. s imultaneous write/read during the s pi cycle d. 5 bit register address space e. 3 wire for write only capability, 4 wire for read/write capability.
plls - s mt 5 - 31 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com hmc rf plls with integrated vcos also support hmc open mode. hmc700, hmc701, hmc702 and some genera - tions of microwave plls with integrated vcos do not support open mode. typical hmc open mode serial port operation can be run with s clk at speeds up to 50mhz. serial port hm c mode typical serial port hmc mode operation can be run with s clk at speeds up to 50mhz. hm c mode - serial port w rit e o peration avdd = dvdd = 3.3v +/-10%, agnd = dgnd = 0v t able 9. sp i hm c mode - write t iming c haracteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 s en to s clk setup time s di to s clk setup time s clk to s di hold time s en low duration max s pi clock frequency 8 3 3 20 50 nsec nsec nsec nsec mhz a typical hmc mode write cycle is shown in figure 36 . a. the master (host) both asserts s en ( s erial port enable) and clears s di to indicate a write cycle, followed by a rising edge of s clk. b. the slave (pll) reads s di on the 1st rising edge of s clk after s en. s di low indi cates a write cycle (/wr). c. host places the six address bits on the next six falling edges of s clk, m s b frst. d. s lave registers the address bits in the next six rising edges of s clk (2-7). e. host places the 24 data bits on the next 24 falling edges of s ck, m s b frst. f. s lave registers the data bits on the next 24 rising edges of s ck (8-31). g. s en is cleared on the 32nd falling edge of s clk. h. the 32nd falling edge of s clk completes the cycle. t 1 t 2 t 3 figure 36. serial port timing diagram - hmc mode write sclk sdi sen /wr a4 a3 a2 a1 ao d23 d22 d2 d1 d0 x x d3 1 2 3 4 5 6 7 8 29 30 31 32 33 t 4
pll s - s mt 5 - 32 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com hm c mode - serial port r e a d o peration a typical hmc mode read cycle is shown in figure 37 . a. the master (host) asserts both s en ( s erial port enable) and s di to indicate a read cycle, followed by a rising edge s clk. note: the lock detect (ld) function is usually mul tiplexed onto the ld_ s do pin. it is suggested that ld only be considered valid when s en is low. in fact ld will not toggle until the frst active data bit toggles on ld_ s do, and will be restored immediately after the trailing edge of the l s b of serial data out as shown in figure 37 . b. the slave (pll) reads s di on the 1st rising edge of s clk after s en. s di high ini tiates the read cycle (rd) c. host places the six address bits on the next six falling edges of s clk, m s b frst. d. s lave registers the address bits on the next six rising edges of s clk (2-7). e. s lave switches from lock detect and places the requested 24 data bits on s d_ldo on the next 24 rising edges of s ck (8-31), m s b frst . f. host registers the data bits on the next 24 falling edges of s ck (8-31). g. s lave restores lock detect on the 32nd rising edge of s ck. h. s en is de-asserted on the 32nd falling edge of s clk. i. the 32nd falling edge of s clk completes the read cycle. t able 10. sp i hm c mode - r ead t iming c haracteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 s en to s clk setup time s di setup to s clk time s clk to s di hold time s en low duration s clk to s do delay 8 3 3 20 8.2ns+0.2ns/pf ns ns ns ns ns figure 37. hmc mode serial port timing diagram - read sclk sdi sen rd a5 a4 a3 a2 a1 ao x x ld_sdo d23 d22 d2 d1 d0 d3 2 3 4 5 6 7 8 29 30 31 32 28 ld (lock detect) ld t 1 t 5 t 3 t 2 t 4
plls - s mt 5 - 33 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com o pen mode - serial port w rit e o peration avdd = dvdd = 3.3v +/-10%, agnd = dgnd = 0v t able 11. sp i o pen mode - write t iming c haracteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 s di setup time s di hold time s en low duration s en high duration s clk 32 rising edge to s en rising edge s erial port clock speed 3 1 10 10 10 dc 50 ns ns ns ns ns mhz a typical write cycle is shown in figure 38 . a. the master (host) places 24 bit data, d23:d0, m s b frst, on s di on the frst 24 falling edges of s clk. b. the slave (pll) shifts in data on s di on the frst 24 rising edges of s clk c. master places 5 bit register address to be written to, r4:r0, m s b frst, on the next 5 falling edges of s clk (25-29) d. s lave shifts the register bits on the next 5 rising edges of s clk (25-29). e. master places 3 bit chip address, a2:a0, m s b frst, on the next 3 falling edges of s clk (30-32). hittite reserves chip address a2:a0 = 000 for all rf pll-vcos. f. s lave shifts the chip address bits on the next 3 rising edges of s clk (30-32). g. master asserts s en after the 32nd rising edge of s clk. h. s lave registers the s di data on the rising edge of s en. i. master clears s en to complete the write cycle. t 1 figure 38. open mode - serial port timing diagram - write sclk sdi d22 d2 d1 d0 r4 r3 a2 a1 a0 x r0 2 3 22 23 24 25 26 31 32 x t 2 sen t 4 t 5 t 3
pll s - s mt 5 - 34 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com o pen mode - serial port r e a d o peration a typical read cycle is shown in figure 39 . in general, in open mode the ld_ s do line is always active during the write cycle. during any open mode s pi cycle ld_ s do will contain the data from the current address written in reg 00h [4:0]. if reg 00h [4:0] is not changed then the same data will always be present on ld_ s do when an open mode cycle is in progress. if it is desired to read from a specifc address, it is necessary in the frst s pi cycle to write the desired address to reg 00h [4:0], then in the next s pi cycle the desired data will be available on ld_ s do. an example of the open mode two cycle procedure to read from any random address is as follows: a. the master (host), on the frst 24 falling edges of s clk places 24 bit data, d23:d0, m s b frst, on s di as shown in figure 39 . d23:d5 should be set to zero. d4:d0 = address of the register to be read on the next cycle. b. the slave (pll) shifts in data on s di on the frst 24 rising edges of s clk c. master places 5 bit register address , r4:r0, ( the address the read addre ss register), m s b frst, on the next 5 falling edges of s clk (23-29). r4:r0=00000. d. s lave shifts the register bits on the next 5 rising edges of s clk (23-29). e. master places 3 bit chip address, a2:a0, m s b frst, on the next 3 falling edges of s clk (30-32).chip address is always 000 for rf pll-vcos. f. s lave shifts the chip address bits on the next 3 rising edges of s clk (30-32). g. master asserts s en after the 32nd rising edge of s clk. h. s lave registers the s di data on the rising edge of s en. i. master clears s en to complete the address transfer of the two part read cycle. j. if we do not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on s di to register zero on the read back part of the cycle. k. master places the same s di data as the previous cycle on the next 32 falling edges of s clk. l. s lave (pll) shifts the s di data on the next 32 rising edges of s clk. m. s lave places the desired data (i.e. data from address in reg 00h [4:0 ]) on ld_ s do on the next 32 rising edges of s clk. lock detect is disabled. n. master asserts s en after the 32nd rising edge of s clk to complete the cycle and revert back to lock detect on ld_ s do. note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the ld_ s do output to prevent a pos - sible contention issue. t able 12. sp i o pen mode - r ead t iming c haracteristics parameter conditions min. typ. max. units t 1 t2 t3 t4 t5 s di setup time s di hold time s en low duration s en high duration s clk rising edge to s do time 3 3 10 10 8.2+0.2ns/pf ns ns ns ns ns
plls - s mt 5 - 35 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t 6 t 1 t 2 figure 39. open mode - serial port timing diagram - read operation 2-cycles sclk sdi sen d5 d4 d0 r4 a2 a1 a0 r0 2 19 20 21 24 25 26 31 32 t 5 t 4 ld_sdo x x x x x x x x x x x x sclk 2 19 20 21 24 25 26 31 32 30 ld_ s do chip address =000 register address =00000 read address ld ld sdi d5 d4 d0 r4 a2 a1 a0 x r0 d23 x d30 d10 d9 d8 d7 d6 d2 d1 d0 d3 d31 ld ld** x first cycle second cycle **note: read-back on ld_ s do can function without s en, however s en rising edge is required to return the ld_ s do to the ld state sen t 3 30 29
pll s - s mt 5 - 36 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a ux se ria l p ort the pll also features a general purpose 16 bit aux s erial port (aux s pi). the auxiliary serial port may be used to con - trol other chips if available, via the open mode protocol. the aux s pi outputs the contents of reg 05h upon receipt of a frequency change command. the aux s pi data is out - put at the aux s pi clock rate which is fpd ( reg 05h [6]). a single aux s pi transfer requires 16 aux s pi cycles plus 4 overhead cycles. r eg i s t er m a p t able 13. r eg 00h i d r egister ( r ead o nly) bit type name w deflt description [23:0] ro chip_id 24 a7975h pll s ubsystem id, 94075 t able 13. r eg 00h o pen mode and hm c mode r eset strobe r egister (write o nly) (continued) bit type name w deflt description [5] wo rst_swrst 1 - s trobe (write only) generates soft reset. resets all digital and registers to default states t able 13. r eg 00h o pen mode r ead a ddress r egister (write o nly) (continued ) bit type name w deflt description [4:0] wo open mode read address 5 - s pecifes address to read when in open mode 2 cycle read t able 14. r eg 01h p o we r d n r egister bit type name w deflt description [0] r/w chipen_pin_select 1 0 1 = chip enable via cen pin, reg01[0]=1 and cen pin low puts pll in power down mode, see power down mode description 0 = pll s ubsystem chip enable via s pi (rst_chipen_from_spi) reg01[1] [1] r/w chipen_from_spi 1 1 controls pll s ubsystem chip enable (power down) if rst_chipen_ pin_select reg01[0]=0 and reg01[1]=1 = chip enabled, cen dont care reg01[0]=0 and reg01[1]=0 = chip disabled, cen dont care see power down mode description and csp_enable [2] r/w keep_bias on 1 0 keeps internal bias generators on, ignores chip enable con trol [3] r/w keep_pfd_on 1 0 keeps pfd circuit on, ignores chip enable control [4] r/w keep_cp_on 1 0 keeps charge pump on, ignores chip enable control [5] r/w keep_ref_buf on 1 0 keeps reference buffer block on, ignores chip enable con trol [6] r/w keep_vco_on 1 0 keeps vco divider buffer on, ignores chip enable control [7] r/w keep_gpo_driver on 1 0 keeps gpo output driver on, ignores chip enable control [8] r/w reserved 1 0 reserved
plls - s mt 5 - 37 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 15. r eg 02h r e f d i v r egister bit type name w deflt description [13:0] r/w rdiv 14 1 reference divider r value (eq 8) divider use also requires refbufen reg08[3]=1 min 0d max 16383d t able 16. r eg 03h f requency r egister - i nteger part bit type name w deflt description [18:0] r/w intg 19 200d c8h vco divider integer part, used in all modes, see (eq 10) fractional mode min 20d max 2 19 -4 = 7fffch = 524,284d integer mode min 16d max 2 19 -1 = 7ffffh = 524,287d t able 17. r eg 04h f requency r egister - f ractional part bit type name w deflt description [23:0] r/w frac 24 0 vco divider fractional part (24 bit unsigned) see fractional fre - quency tuning fractional division value = reg4[23:0]/2^24 used in fractional mode only min 0d max 2^24-1 = ffffffh = 16,777,215d t able 18. r eg 05h a ux sp i r egister bit type name w deflt description [15:0] r/w aux data 16 0 data to be output on a s d pin
pll s - s mt 5 - 38 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 19. r eg 06h sd cf g r egister bit type name w deflt description [1:0] r/w seed select 2 2 s elects the s eed in fractional mode 00: 0 seed 01: lsb seed 02: b29d08h seed 03: 50f1cdh seed note; writes to this register are stored in the pll and are only loaded into the modulator when a frequency change is executed and if autoseed reg06h[13] =1 [3:2] r/w modulator order 2 2 s elect the delta s igma modulator type 0: reserved 1: reserved 2: mode b offers better out of band spectral performance. mode b required for exact frequency mode. 3: mode a offers better in band spectral performance [6:4] r/w reserved 3 7 [7] r/w frac_bypass 1 0 0: use modulator, required for fractional mode, 1: bypass modulator, required for integer mode note: in bypass fractional modulator output is ignored, but frac - tional modulator continues to be clocked if frac_rstb =1, can be used to test the isolation of the digital fractional mod ulator from the vco output in integer mode [8] r/w autoseed 1 1 1: loads the modulator seed (start phase) whenever the frac regis - ter is written 0: when frac register write changes frequency, modulator starts with previous contents [9] r/w clkrq_refdiv_sel 1 1 selects the modulator core clock source- for test only 1: vco divider clock 0: ref divider clock ignored if bits [10] or [21] are set [10] r/w modulator core clk s elect 1 0 0 - modulator auxclk, 1- modulator vco clock delay [11] r/w frac_rstb 1 1 0: disable modulator, use for integer mode or integer mode with c s p 1: enable modulator core, required for fractional mode, or integer isolation testing [12] r/w reserved 1 0 [13] r/w reserved 1 0 [15:14] r/w reserved 2 0 reserved [17:16] r/w reserved 2 0 program to 3 decimal 11 binary [18] r/w bi s t enable 1 0 enable built in s elf test [20:19] r/w rdiv bi s t cycles 2 0 0:1023 1:2047 2:3071 3:4095 [21] r/w reserved 1 0 reserved [22] r/w reserved 1 0 reserved
plls - s mt 5 - 39 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 20. r eg 07h lock detect r egister bit type name w deflt description [2:0] r/w lkd_wincnt_max 3 5 lock detect window sets the number of consecutive counts of divided vco that must land inside the lock detect window to declare lock 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 [3] r/w enable internal lock detect 1 1 enable internal lock detect [5:4] r/w reserved 2 0 reserved [6] r/w lock detect window type 1 0 lock detection window timer s election 1: digital programmable timer 0: analog one shot, nominal +/-10nsec window [9:7] r/w ld digital window duration 3 0 lock detection - digital window duration 0: 1/2 cycle 1: 1 cycle 2: 2 cycles 3: 4 cycles 4: 8 cycles 5: 16 cycles 6: 32 cycles 7: 64 cycles [11:10] r/w ld digital timer freq con trol 2 0 lock detect digital timer frequency control 00 fastest 11 slowest [12] r/w ld timer test mode 1 0 1: force timer on continuously - for test only 0: normal timer operation - one shot [13] r/w auto relock - one try 1 0 1: attempts to relock if lock detect fails for any reason only tries once.
pll s - s mt 5 - 40 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 21. r eg 08h a nalog e n r egister bit type name w deflt description 0 r/w bias_en 1 1 enables main chip bias reference 1 r/w cp_en 1 1 charge pump enable 2 r/w pd_en 1 1 pd enable 3 r/w refbuf_en 1 reference path buffer enable 4 r/w vcobuf_en 1 1 vco path rf buffer enable 5 r/w gpo/ldo/ s do_pad_en 1 1 0 - pin ld_ s do disabled 6 r/w spare 1 1 spare 7 r/w vco_div_clk_to_dig_en 1 1 vco divider clock to digital enable 8 r/w reserved 1 0 reserved 9 r/w prescaler clock enable 1 1 prescaler clock enable [10] r/w vco buffer and prescaler bias enable 1 1 vco buffer and prescaler bias enable [11] r/w charge pump internal opamp enable 1 1 charge pump internal opamp enable [14:12] r/w rf buffer en/bias 3 3 0: disabled, 1: low bias,...7: high bias [17:15] r/w div resync en/bias 3 3 0: disabled, 1: low bias,...7: high bias [18] r/w reserved 1 0 reserved program 0 [19] r/w 8ghz divide by 2 en 1 0 8ghz divide by 2 enable [20] r/w reserved 1 0 reserved program 0 [21] r/w hi frequency reference 1 0 program 1 for xtal > 200 mhz [22] r/w reserved 1 1 reserved [23] r/w reserved 1 1 reserved
plls - s mt 5 - 41 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 22. r eg 09h c harge pump r egister bit type name w deflt description [6:0] r/w cp dn gain 7 10d charge pump dn gain control 20ua/step affects fractional phase noise and lock detect settings 0d = 0ua 1d = 20ua 2d = 40ua ... 127d = 2.54ma [13:7] r/w cp up gain 7 10d charge pump up gain control 20ua/step affects fractional phase noise and lock detect settings 0d = 0ua 1d = 20ua 2d = 40ua ... 127d = 2.54ma [20:14] r/w offset current 7 0 charge pump offset control 5ua/step affects fractional phase noise and spursand lock detect settings 0d = 0ua 1d = 5ua 2d = 110ua ... 127d = 635ua [21] r/w offset current up 1 0 1 - s ets direction of reg[20:14] up, 0- up offset off [22] r/w offset current dn 1 1 1 - s ets direction of reg[20:14] down, 0- dn offset off [23] r/w hik charge pump mode 1 0 hi kcp charge pump - very low noise, narrow compliance range, requires opamp
pll s - s mt 5 - 42 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 23. r eg 0 a h a uxsp i t rigger r egister bit type name w deflt description [11:0] r/w reserved 12 0 reserved [12] r/w no aux s pi trigger 1 0 no aux s pi trigger on reg5 write [15:13] r/w reserved 3 0 reserved [16] r/w force rdivider bypass 1 0 force the r divider bypass, ignore reg03 t able 24. r eg 0bh pd r egister bit type name w deflt description [2:0] r/w pd_del_sel 3 1 s ets pd reset path delay [3] r/w s hort pd inputs 1 0 s horts the inputs to the phase detector - test only [4] r/w pd_invert 1 0 inverts the pd polarity 0 - use with a positive tuning slope vco and passive loop flter (default). 1 - use with a negative slope vco or with an inverting active loop flter with a positive slope vco. [5] r/w pd_up_en 1 1 enables the pd up output, see also reg0b[9] [6] r/w pd_dn_en 1 1 enables the pd dn output, see also reg0b[9] [8:7] r/w c s p mode 2 0 cycle s lip prevention mode 0: c s p disabled 1: cp gain increased if phase error > 2 nsec 2: cp gain increased if phase error > 4 nsec 3: cp gain increased if phase error > 6 nsec [9] r/w force cp up 1 0 forces cp up output on - use for test only [10] r/w force cp dn 1 0 forces cp dn output on - use for test only [11] r/w force cp mid rail 1 0 force cp mid rail - use for test only [14:12] r/w p s bias 3 0 prescaler bias 0: nominal 1: +20% rf buffer 2: +25% rsync 3: +50% [16:15] r/w cp internal opamp bias 2 3 cp internal opamp bias [18:17] r/w mcounter clock gating 2 3 mcounter clock gating 0: mcounter off for n<32 1: n<128 2: n< 1023 3: all clocks on [19] r/w reserved 1 1 [21:20] r/w divider pulse width 2 0 0: shortest, ... 3: longest [23:22] r/w reserved 2 0
plls - s mt 5 - 43 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 25. r eg 0 c h exact f requency r egister bit type name w deflt description [13:0] r/w number of channels per fpd 14 0 comparison frequency divided by the channel spacing. must be an integer. frequencies at multiples of the channel spacing will have zero frequency error. only works in modulator mode b. must be 0 otherwise 0: disabled 1: disabled 2 to16383d (3fffh) allowed t able 26. r eg 0 f h gp o r egister bit type name w deflt description [4:0] r/w gpo_select 5 1 s ignal selected here is output to s do pin when enabled 0: data from reg0f[5] 1: lock detect output 2. lock detect trigger 3: lock detect window output 4: ring osc test 5. pullup hard from c s p 6. pulldn hard from c s p 7. reserved 8: reference buffer output 9: ref divider output 10: vco divider output 11. modulator clock from vco divider 12. auxiliary clock 13. aux s pi clock 14. aux s pi enable 15. aux s pi data out 16. pd dn 17. pd up 18. s d3 clock delay 19. s d3 core clock 20. auto s trobe integer write 21. autostrobe frac write 22. autostrobe aux s pi 23. s pi latch enable 24. vco divider s ync reset 25. s eed load s trobe 26.-29 not used 30. s pi output buffer en 31. s oft r s tb [5] r/w gpo test data 1 0 1 - gpo test data when gpo_ s elect = 0 [6] r/w prevent automux s do 1 0 1- inhibits automux of the s pi s do line with lock detect [7] r/w prevent driver disable 1 0 1- prevents s pi from disabling s do. s hould be 1 if using hmc s pi mode. [8] r/w disable pfet 1 0 disable pfet [9] r/w disable nfet 1 0 disable nfet
pll s - s mt 5 - 44 HMC704LP4E v02.0411 8 gh z fractiona l - n pll for price, delivery, and to place orders: hittite microwave corporation,20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com t able 27. r eg 10h r eserve r egister ( r ead o nly) bit type name w deflt description [8:0] ro reserved 9 0 reserved t able 28. r eg 11h r eserve r egister ( r ead o nly) bit type name w deflt description [18:0] ro reserved 19 0 reserved t able 29. r eg 12h gp o 2 r egister ( r ead o nly) bit type name w deflt description [0] ro gpo 1 0 gpo [1] ro lock detect 1 0 lock detect t able 30. r eg 13h b i s t r egister bit type name w deflt description [15:0] ro bi s t s ignature 16 0 digital built-in s elf test s ignature [16] ro bi s t busy 1 0 bi s t busy

▲Up To Search▲

Price & Availability of HMC704LP4E

	To Download HMC704LP4E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .